clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL

CLK_SET_RATE_GATE means that the clock must be gated when being
reclocked. This is not the case for the PLLs in Ingenic SoCs.

Signed-off-by: Paul C

clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL

CLK_SET_RATE_GATE means that the clock must be gated when being
reclocked. This is not the case for the PLLs in Ingenic SoCs.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-3-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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clk: ingenic: Use readl_poll_timeout instead of custom loop

Use the readl_poll_timeout() function instead of rolling our own
busy-wait loops. This makes the code simpler.

Signed-off-by: Paul Cercue

clk: ingenic: Use readl_poll_timeout instead of custom loop

Use the readl_poll_timeout() function instead of rolling our own
busy-wait loops. This makes the code simpler.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-2-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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clk: ingenic: Use to_clk_info() macro for all clocks

The to_clk_info() previously had a BUG_ON() to check that it was only
called for PLL clocks. Yet, all the other clocks were doing the exact
same

clk: ingenic: Use to_clk_info() macro for all clocks

The to_clk_info() previously had a BUG_ON() to check that it was only
called for PLL clocks. Yet, all the other clocks were doing the exact
same thing the macro does, in-line.

Move the to_clk_info() macro to the top of the file, remove the
hardcoded BUG_ON(), and use it everywhere it makes sense.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20200903015048.3091523-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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