1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013-2014 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014,2017 The Linux Foundation. All rights reserved. 7 */ 8 9 #include "adreno_gpu.h" 10 11 #define ANY_ID 0xff 12 13 bool hang_debug = false; 14 MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)"); 15 module_param_named(hang_debug, hang_debug, bool, 0600); 16 17 static const struct adreno_info gpulist[] = { 18 { 19 .rev = ADRENO_REV(2, 0, 0, 0), 20 .revn = 200, 21 .name = "A200", 22 .fw = { 23 [ADRENO_FW_PM4] = "yamato_pm4.fw", 24 [ADRENO_FW_PFP] = "yamato_pfp.fw", 25 }, 26 .gmem = SZ_256K, 27 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 28 .init = a2xx_gpu_init, 29 }, { /* a200 on i.mx51 has only 128kib gmem */ 30 .rev = ADRENO_REV(2, 0, 0, 1), 31 .revn = 201, 32 .name = "A200", 33 .fw = { 34 [ADRENO_FW_PM4] = "yamato_pm4.fw", 35 [ADRENO_FW_PFP] = "yamato_pfp.fw", 36 }, 37 .gmem = SZ_128K, 38 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 39 .init = a2xx_gpu_init, 40 }, { 41 .rev = ADRENO_REV(2, 2, 0, ANY_ID), 42 .revn = 220, 43 .name = "A220", 44 .fw = { 45 [ADRENO_FW_PM4] = "leia_pm4_470.fw", 46 [ADRENO_FW_PFP] = "leia_pfp_470.fw", 47 }, 48 .gmem = SZ_512K, 49 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 50 .init = a2xx_gpu_init, 51 }, { 52 .rev = ADRENO_REV(3, 0, 5, ANY_ID), 53 .revn = 305, 54 .name = "A305", 55 .fw = { 56 [ADRENO_FW_PM4] = "a300_pm4.fw", 57 [ADRENO_FW_PFP] = "a300_pfp.fw", 58 }, 59 .gmem = SZ_256K, 60 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 61 .init = a3xx_gpu_init, 62 }, { 63 .rev = ADRENO_REV(3, 0, 6, 0), 64 .revn = 307, /* because a305c is revn==306 */ 65 .name = "A306", 66 .fw = { 67 [ADRENO_FW_PM4] = "a300_pm4.fw", 68 [ADRENO_FW_PFP] = "a300_pfp.fw", 69 }, 70 .gmem = SZ_128K, 71 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 72 .init = a3xx_gpu_init, 73 }, { 74 .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), 75 .revn = 320, 76 .name = "A320", 77 .fw = { 78 [ADRENO_FW_PM4] = "a300_pm4.fw", 79 [ADRENO_FW_PFP] = "a300_pfp.fw", 80 }, 81 .gmem = SZ_512K, 82 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 83 .init = a3xx_gpu_init, 84 }, { 85 .rev = ADRENO_REV(3, 3, 0, ANY_ID), 86 .revn = 330, 87 .name = "A330", 88 .fw = { 89 [ADRENO_FW_PM4] = "a330_pm4.fw", 90 [ADRENO_FW_PFP] = "a330_pfp.fw", 91 }, 92 .gmem = SZ_1M, 93 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 94 .init = a3xx_gpu_init, 95 }, { 96 .rev = ADRENO_REV(4, 0, 5, ANY_ID), 97 .revn = 405, 98 .name = "A405", 99 .fw = { 100 [ADRENO_FW_PM4] = "a420_pm4.fw", 101 [ADRENO_FW_PFP] = "a420_pfp.fw", 102 }, 103 .gmem = SZ_256K, 104 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 105 .init = a4xx_gpu_init, 106 }, { 107 .rev = ADRENO_REV(4, 2, 0, ANY_ID), 108 .revn = 420, 109 .name = "A420", 110 .fw = { 111 [ADRENO_FW_PM4] = "a420_pm4.fw", 112 [ADRENO_FW_PFP] = "a420_pfp.fw", 113 }, 114 .gmem = (SZ_1M + SZ_512K), 115 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 116 .init = a4xx_gpu_init, 117 }, { 118 .rev = ADRENO_REV(4, 3, 0, ANY_ID), 119 .revn = 430, 120 .name = "A430", 121 .fw = { 122 [ADRENO_FW_PM4] = "a420_pm4.fw", 123 [ADRENO_FW_PFP] = "a420_pfp.fw", 124 }, 125 .gmem = (SZ_1M + SZ_512K), 126 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 127 .init = a4xx_gpu_init, 128 }, { 129 .rev = ADRENO_REV(5, 1, 0, ANY_ID), 130 .revn = 510, 131 .name = "A510", 132 .fw = { 133 [ADRENO_FW_PM4] = "a530_pm4.fw", 134 [ADRENO_FW_PFP] = "a530_pfp.fw", 135 }, 136 .gmem = SZ_256K, 137 /* 138 * Increase inactive period to 250 to avoid bouncing 139 * the GDSC which appears to make it grumpy 140 */ 141 .inactive_period = 250, 142 .init = a5xx_gpu_init, 143 }, { 144 .rev = ADRENO_REV(5, 3, 0, 2), 145 .revn = 530, 146 .name = "A530", 147 .fw = { 148 [ADRENO_FW_PM4] = "a530_pm4.fw", 149 [ADRENO_FW_PFP] = "a530_pfp.fw", 150 [ADRENO_FW_GPMU] = "a530v3_gpmu.fw2", 151 }, 152 .gmem = SZ_1M, 153 /* 154 * Increase inactive period to 250 to avoid bouncing 155 * the GDSC which appears to make it grumpy 156 */ 157 .inactive_period = 250, 158 .quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI | 159 ADRENO_QUIRK_FAULT_DETECT_MASK, 160 .init = a5xx_gpu_init, 161 .zapfw = "a530_zap.mdt", 162 }, { 163 .rev = ADRENO_REV(5, 4, 0, 2), 164 .revn = 540, 165 .name = "A540", 166 .fw = { 167 [ADRENO_FW_PM4] = "a530_pm4.fw", 168 [ADRENO_FW_PFP] = "a530_pfp.fw", 169 [ADRENO_FW_GPMU] = "a540_gpmu.fw2", 170 }, 171 .gmem = SZ_1M, 172 /* 173 * Increase inactive period to 250 to avoid bouncing 174 * the GDSC which appears to make it grumpy 175 */ 176 .inactive_period = 250, 177 .quirks = ADRENO_QUIRK_LMLOADKILL_DISABLE, 178 .init = a5xx_gpu_init, 179 .zapfw = "a540_zap.mdt", 180 }, { 181 .rev = ADRENO_REV(6, 1, 8, ANY_ID), 182 .revn = 618, 183 .name = "A618", 184 .fw = { 185 [ADRENO_FW_SQE] = "a630_sqe.fw", 186 [ADRENO_FW_GMU] = "a630_gmu.bin", 187 }, 188 .gmem = SZ_512K, 189 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 190 .init = a6xx_gpu_init, 191 }, { 192 .rev = ADRENO_REV(6, 3, 0, ANY_ID), 193 .revn = 630, 194 .name = "A630", 195 .fw = { 196 [ADRENO_FW_SQE] = "a630_sqe.fw", 197 [ADRENO_FW_GMU] = "a630_gmu.bin", 198 }, 199 .gmem = SZ_1M, 200 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 201 .init = a6xx_gpu_init, 202 .zapfw = "a630_zap.mdt", 203 .hwcg = a630_hwcg, 204 }, { 205 .rev = ADRENO_REV(6, 4, 0, ANY_ID), 206 .revn = 640, 207 .name = "A640", 208 .fw = { 209 [ADRENO_FW_SQE] = "a630_sqe.fw", 210 [ADRENO_FW_GMU] = "a640_gmu.bin", 211 }, 212 .gmem = SZ_1M, 213 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 214 .init = a6xx_gpu_init, 215 .zapfw = "a640_zap.mdt", 216 .hwcg = a640_hwcg, 217 }, { 218 .rev = ADRENO_REV(6, 5, 0, ANY_ID), 219 .revn = 650, 220 .name = "A650", 221 .fw = { 222 [ADRENO_FW_SQE] = "a650_sqe.fw", 223 [ADRENO_FW_GMU] = "a650_gmu.bin", 224 }, 225 .gmem = SZ_1M + SZ_128K, 226 .inactive_period = DRM_MSM_INACTIVE_PERIOD, 227 .init = a6xx_gpu_init, 228 .zapfw = "a650_zap.mdt", 229 .hwcg = a650_hwcg, 230 }, 231 }; 232 233 MODULE_FIRMWARE("qcom/a300_pm4.fw"); 234 MODULE_FIRMWARE("qcom/a300_pfp.fw"); 235 MODULE_FIRMWARE("qcom/a330_pm4.fw"); 236 MODULE_FIRMWARE("qcom/a330_pfp.fw"); 237 MODULE_FIRMWARE("qcom/a420_pm4.fw"); 238 MODULE_FIRMWARE("qcom/a420_pfp.fw"); 239 MODULE_FIRMWARE("qcom/a530_pm4.fw"); 240 MODULE_FIRMWARE("qcom/a530_pfp.fw"); 241 MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2"); 242 MODULE_FIRMWARE("qcom/a530_zap.mdt"); 243 MODULE_FIRMWARE("qcom/a530_zap.b00"); 244 MODULE_FIRMWARE("qcom/a530_zap.b01"); 245 MODULE_FIRMWARE("qcom/a530_zap.b02"); 246 MODULE_FIRMWARE("qcom/a630_sqe.fw"); 247 MODULE_FIRMWARE("qcom/a630_gmu.bin"); 248 MODULE_FIRMWARE("qcom/a630_zap.mbn"); 249 250 static inline bool _rev_match(uint8_t entry, uint8_t id) 251 { 252 return (entry == ANY_ID) || (entry == id); 253 } 254 255 const struct adreno_info *adreno_info(struct adreno_rev rev) 256 { 257 int i; 258 259 /* identify gpu: */ 260 for (i = 0; i < ARRAY_SIZE(gpulist); i++) { 261 const struct adreno_info *info = &gpulist[i]; 262 if (_rev_match(info->rev.core, rev.core) && 263 _rev_match(info->rev.major, rev.major) && 264 _rev_match(info->rev.minor, rev.minor) && 265 _rev_match(info->rev.patchid, rev.patchid)) 266 return info; 267 } 268 269 return NULL; 270 } 271 272 struct msm_gpu *adreno_load_gpu(struct drm_device *dev) 273 { 274 struct msm_drm_private *priv = dev->dev_private; 275 struct platform_device *pdev = priv->gpu_pdev; 276 struct msm_gpu *gpu = NULL; 277 struct adreno_gpu *adreno_gpu; 278 int ret; 279 280 if (pdev) 281 gpu = platform_get_drvdata(pdev); 282 283 if (!gpu) { 284 dev_err_once(dev->dev, "no GPU device was found\n"); 285 return NULL; 286 } 287 288 adreno_gpu = to_adreno_gpu(gpu); 289 290 /* 291 * The number one reason for HW init to fail is if the firmware isn't 292 * loaded yet. Try that first and don't bother continuing on 293 * otherwise 294 */ 295 296 ret = adreno_load_fw(adreno_gpu); 297 if (ret) 298 return NULL; 299 300 /* Make sure pm runtime is active and reset any previous errors */ 301 pm_runtime_set_active(&pdev->dev); 302 303 ret = pm_runtime_get_sync(&pdev->dev); 304 if (ret < 0) { 305 pm_runtime_put_sync(&pdev->dev); 306 DRM_DEV_ERROR(dev->dev, "Couldn't power up the GPU: %d\n", ret); 307 return NULL; 308 } 309 310 mutex_lock(&dev->struct_mutex); 311 ret = msm_gpu_hw_init(gpu); 312 mutex_unlock(&dev->struct_mutex); 313 pm_runtime_put_autosuspend(&pdev->dev); 314 if (ret) { 315 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 316 return NULL; 317 } 318 319 #ifdef CONFIG_DEBUG_FS 320 if (gpu->funcs->debugfs_init) { 321 gpu->funcs->debugfs_init(gpu, dev->primary); 322 gpu->funcs->debugfs_init(gpu, dev->render); 323 } 324 #endif 325 326 return gpu; 327 } 328 329 static void set_gpu_pdev(struct drm_device *dev, 330 struct platform_device *pdev) 331 { 332 struct msm_drm_private *priv = dev->dev_private; 333 priv->gpu_pdev = pdev; 334 } 335 336 static int find_chipid(struct device *dev, struct adreno_rev *rev) 337 { 338 struct device_node *node = dev->of_node; 339 const char *compat; 340 int ret; 341 u32 chipid; 342 343 /* first search the compat strings for qcom,adreno-XYZ.W: */ 344 ret = of_property_read_string_index(node, "compatible", 0, &compat); 345 if (ret == 0) { 346 unsigned int r, patch; 347 348 if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 || 349 sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) { 350 rev->core = r / 100; 351 r %= 100; 352 rev->major = r / 10; 353 r %= 10; 354 rev->minor = r; 355 rev->patchid = patch; 356 357 return 0; 358 } 359 } 360 361 /* and if that fails, fall back to legacy "qcom,chipid" property: */ 362 ret = of_property_read_u32(node, "qcom,chipid", &chipid); 363 if (ret) { 364 DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret); 365 return ret; 366 } 367 368 rev->core = (chipid >> 24) & 0xff; 369 rev->major = (chipid >> 16) & 0xff; 370 rev->minor = (chipid >> 8) & 0xff; 371 rev->patchid = (chipid & 0xff); 372 373 dev_warn(dev, "Using legacy qcom,chipid binding!\n"); 374 dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", 375 rev->core, rev->major, rev->minor, rev->patchid); 376 377 return 0; 378 } 379 380 static int adreno_bind(struct device *dev, struct device *master, void *data) 381 { 382 static struct adreno_platform_config config = {}; 383 const struct adreno_info *info; 384 struct drm_device *drm = dev_get_drvdata(master); 385 struct msm_drm_private *priv = drm->dev_private; 386 struct msm_gpu *gpu; 387 int ret; 388 389 ret = find_chipid(dev, &config.rev); 390 if (ret) 391 return ret; 392 393 dev->platform_data = &config; 394 set_gpu_pdev(drm, to_platform_device(dev)); 395 396 info = adreno_info(config.rev); 397 398 if (!info) { 399 dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", 400 config.rev.core, config.rev.major, 401 config.rev.minor, config.rev.patchid); 402 return -ENXIO; 403 } 404 405 DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, 406 config.rev.minor, config.rev.patchid); 407 408 priv->is_a2xx = config.rev.core == 2; 409 410 gpu = info->init(drm); 411 if (IS_ERR(gpu)) { 412 dev_warn(drm->dev, "failed to load adreno gpu\n"); 413 return PTR_ERR(gpu); 414 } 415 416 dev_set_drvdata(dev, gpu); 417 418 return 0; 419 } 420 421 static void adreno_unbind(struct device *dev, struct device *master, 422 void *data) 423 { 424 struct msm_gpu *gpu = dev_get_drvdata(dev); 425 426 pm_runtime_force_suspend(dev); 427 gpu->funcs->destroy(gpu); 428 429 set_gpu_pdev(dev_get_drvdata(master), NULL); 430 } 431 432 static const struct component_ops a3xx_ops = { 433 .bind = adreno_bind, 434 .unbind = adreno_unbind, 435 }; 436 437 static void adreno_device_register_headless(void) 438 { 439 /* on imx5, we don't have a top-level mdp/dpu node 440 * this creates a dummy node for the driver for that case 441 */ 442 struct platform_device_info dummy_info = { 443 .parent = NULL, 444 .name = "msm", 445 .id = -1, 446 .res = NULL, 447 .num_res = 0, 448 .data = NULL, 449 .size_data = 0, 450 .dma_mask = ~0, 451 }; 452 platform_device_register_full(&dummy_info); 453 } 454 455 static int adreno_probe(struct platform_device *pdev) 456 { 457 458 int ret; 459 460 ret = component_add(&pdev->dev, &a3xx_ops); 461 if (ret) 462 return ret; 463 464 if (of_device_is_compatible(pdev->dev.of_node, "amd,imageon")) 465 adreno_device_register_headless(); 466 467 return 0; 468 } 469 470 static int adreno_remove(struct platform_device *pdev) 471 { 472 component_del(&pdev->dev, &a3xx_ops); 473 return 0; 474 } 475 476 static const struct of_device_id dt_match[] = { 477 { .compatible = "qcom,adreno" }, 478 { .compatible = "qcom,adreno-3xx" }, 479 /* for compatibility with imx5 gpu: */ 480 { .compatible = "amd,imageon" }, 481 /* for backwards compat w/ downstream kgsl DT files: */ 482 { .compatible = "qcom,kgsl-3d0" }, 483 {} 484 }; 485 486 #ifdef CONFIG_PM 487 static int adreno_resume(struct device *dev) 488 { 489 struct platform_device *pdev = to_platform_device(dev); 490 struct msm_gpu *gpu = platform_get_drvdata(pdev); 491 492 return gpu->funcs->pm_resume(gpu); 493 } 494 495 static int adreno_suspend(struct device *dev) 496 { 497 struct platform_device *pdev = to_platform_device(dev); 498 struct msm_gpu *gpu = platform_get_drvdata(pdev); 499 500 return gpu->funcs->pm_suspend(gpu); 501 } 502 #endif 503 504 static const struct dev_pm_ops adreno_pm_ops = { 505 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 506 SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL) 507 }; 508 509 static struct platform_driver adreno_driver = { 510 .probe = adreno_probe, 511 .remove = adreno_remove, 512 .driver = { 513 .name = "adreno", 514 .of_match_table = dt_match, 515 .pm = &adreno_pm_ops, 516 }, 517 }; 518 519 void __init adreno_register(void) 520 { 521 platform_driver_register(&adreno_driver); 522 } 523 524 void __exit adreno_unregister(void) 525 { 526 platform_driver_unregister(&adreno_driver); 527 } 528