1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 * 5 */ 6 7 #include <linux/bitmap.h> 8 #include <linux/bitops.h> 9 #include <linux/device.h> 10 #include <linux/io.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/regmap.h> 17 #include <linux/sizes.h> 18 #include <linux/slab.h> 19 #include <linux/soc/qcom/llcc-qcom.h> 20 21 #define ACTIVATE BIT(0) 22 #define DEACTIVATE BIT(1) 23 #define ACT_CTRL_OPCODE_ACTIVATE BIT(0) 24 #define ACT_CTRL_OPCODE_DEACTIVATE BIT(1) 25 #define ACT_CTRL_ACT_TRIG BIT(0) 26 #define ACT_CTRL_OPCODE_SHIFT 0x01 27 #define ATTR1_PROBE_TARGET_WAYS_SHIFT 0x02 28 #define ATTR1_FIXED_SIZE_SHIFT 0x03 29 #define ATTR1_PRIORITY_SHIFT 0x04 30 #define ATTR1_MAX_CAP_SHIFT 0x10 31 #define ATTR0_RES_WAYS_MASK GENMASK(11, 0) 32 #define ATTR0_BONUS_WAYS_MASK GENMASK(27, 16) 33 #define ATTR0_BONUS_WAYS_SHIFT 0x10 34 #define LLCC_STATUS_READ_DELAY 100 35 36 #define CACHE_LINE_SIZE_SHIFT 6 37 38 #define LLCC_COMMON_STATUS0 0x0003000c 39 #define LLCC_LB_CNT_MASK GENMASK(31, 28) 40 #define LLCC_LB_CNT_SHIFT 28 41 42 #define MAX_CAP_TO_BYTES(n) (n * SZ_1K) 43 #define LLCC_TRP_ACT_CTRLn(n) (n * SZ_4K) 44 #define LLCC_TRP_STATUSn(n) (4 + n * SZ_4K) 45 #define LLCC_TRP_ATTR0_CFGn(n) (0x21000 + SZ_8 * n) 46 #define LLCC_TRP_ATTR1_CFGn(n) (0x21004 + SZ_8 * n) 47 48 #define BANK_OFFSET_STRIDE 0x80000 49 50 /** 51 * llcc_slice_config - Data associated with the llcc slice 52 * @usecase_id: Unique id for the client's use case 53 * @slice_id: llcc slice id for each client 54 * @max_cap: The maximum capacity of the cache slice provided in KB 55 * @priority: Priority of the client used to select victim line for replacement 56 * @fixed_size: Boolean indicating if the slice has a fixed capacity 57 * @bonus_ways: Bonus ways are additional ways to be used for any slice, 58 * if client ends up using more than reserved cache ways. Bonus 59 * ways are allocated only if they are not reserved for some 60 * other client. 61 * @res_ways: Reserved ways for the cache slice, the reserved ways cannot 62 * be used by any other client than the one its assigned to. 63 * @cache_mode: Each slice operates as a cache, this controls the mode of the 64 * slice: normal or TCM(Tightly Coupled Memory) 65 * @probe_target_ways: Determines what ways to probe for access hit. When 66 * configured to 1 only bonus and reserved ways are probed. 67 * When configured to 0 all ways in llcc are probed. 68 * @dis_cap_alloc: Disable capacity based allocation for a client 69 * @retain_on_pc: If this bit is set and client has maintained active vote 70 * then the ways assigned to this client are not flushed on power 71 * collapse. 72 * @activate_on_init: Activate the slice immediately after it is programmed 73 */ 74 struct llcc_slice_config { 75 u32 usecase_id; 76 u32 slice_id; 77 u32 max_cap; 78 u32 priority; 79 bool fixed_size; 80 u32 bonus_ways; 81 u32 res_ways; 82 u32 cache_mode; 83 u32 probe_target_ways; 84 bool dis_cap_alloc; 85 bool retain_on_pc; 86 bool activate_on_init; 87 }; 88 89 struct qcom_llcc_config { 90 const struct llcc_slice_config *sct_data; 91 int size; 92 }; 93 94 static const struct llcc_slice_config sc7180_data[] = { 95 { LLCC_CPUSS, 1, 256, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 1 }, 96 { LLCC_MDM, 8, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 97 { LLCC_GPUHTW, 11, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 98 { LLCC_GPU, 12, 128, 1, 0, 0xf, 0x0, 0, 0, 0, 1, 0 }, 99 }; 100 101 static const struct llcc_slice_config sdm845_data[] = { 102 { LLCC_CPUSS, 1, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 1 }, 103 { LLCC_VIDSC0, 2, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 104 { LLCC_VIDSC1, 3, 512, 2, 1, 0x0, 0x0f0, 0, 0, 1, 1, 0 }, 105 { LLCC_ROTATOR, 4, 563, 2, 1, 0x0, 0x00e, 2, 0, 1, 1, 0 }, 106 { LLCC_VOICE, 5, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 107 { LLCC_AUDIO, 6, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 108 { LLCC_MDMHPGRW, 7, 1024, 2, 0, 0xfc, 0xf00, 0, 0, 1, 1, 0 }, 109 { LLCC_MDM, 8, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 110 { LLCC_CMPT, 10, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 111 { LLCC_GPUHTW, 11, 512, 1, 1, 0xc, 0x0, 0, 0, 1, 1, 0 }, 112 { LLCC_GPU, 12, 2304, 1, 0, 0xff0, 0x2, 0, 0, 1, 1, 0 }, 113 { LLCC_MMUHWT, 13, 256, 2, 0, 0x0, 0x1, 0, 0, 1, 0, 1 }, 114 { LLCC_CMPTDMA, 15, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 115 { LLCC_DISP, 16, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 116 { LLCC_VIDFW, 17, 2816, 1, 0, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 117 { LLCC_MDMHPFX, 20, 1024, 2, 1, 0x0, 0xf00, 0, 0, 1, 1, 0 }, 118 { LLCC_MDMPNG, 21, 1024, 0, 1, 0x1e, 0x0, 0, 0, 1, 1, 0 }, 119 { LLCC_AUDHW, 22, 1024, 1, 1, 0xffc, 0x2, 0, 0, 1, 1, 0 }, 120 }; 121 122 static const struct qcom_llcc_config sc7180_cfg = { 123 .sct_data = sc7180_data, 124 .size = ARRAY_SIZE(sc7180_data), 125 }; 126 127 static const struct qcom_llcc_config sdm845_cfg = { 128 .sct_data = sdm845_data, 129 .size = ARRAY_SIZE(sdm845_data), 130 }; 131 132 static struct llcc_drv_data *drv_data = (void *) -EPROBE_DEFER; 133 134 /** 135 * llcc_slice_getd - get llcc slice descriptor 136 * @uid: usecase_id for the client 137 * 138 * A pointer to llcc slice descriptor will be returned on success and 139 * and error pointer is returned on failure 140 */ 141 struct llcc_slice_desc *llcc_slice_getd(u32 uid) 142 { 143 const struct llcc_slice_config *cfg; 144 struct llcc_slice_desc *desc; 145 u32 sz, count; 146 147 if (IS_ERR(drv_data)) 148 return ERR_CAST(drv_data); 149 150 cfg = drv_data->cfg; 151 sz = drv_data->cfg_size; 152 153 for (count = 0; cfg && count < sz; count++, cfg++) 154 if (cfg->usecase_id == uid) 155 break; 156 157 if (count == sz || !cfg) 158 return ERR_PTR(-ENODEV); 159 160 desc = kzalloc(sizeof(*desc), GFP_KERNEL); 161 if (!desc) 162 return ERR_PTR(-ENOMEM); 163 164 desc->slice_id = cfg->slice_id; 165 desc->slice_size = cfg->max_cap; 166 167 return desc; 168 } 169 EXPORT_SYMBOL_GPL(llcc_slice_getd); 170 171 /** 172 * llcc_slice_putd - llcc slice descritpor 173 * @desc: Pointer to llcc slice descriptor 174 */ 175 void llcc_slice_putd(struct llcc_slice_desc *desc) 176 { 177 if (!IS_ERR_OR_NULL(desc)) 178 kfree(desc); 179 } 180 EXPORT_SYMBOL_GPL(llcc_slice_putd); 181 182 static int llcc_update_act_ctrl(u32 sid, 183 u32 act_ctrl_reg_val, u32 status) 184 { 185 u32 act_ctrl_reg; 186 u32 status_reg; 187 u32 slice_status; 188 int ret; 189 190 if (IS_ERR(drv_data)) 191 return PTR_ERR(drv_data); 192 193 act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid); 194 status_reg = LLCC_TRP_STATUSn(sid); 195 196 /* Set the ACTIVE trigger */ 197 act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG; 198 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 199 act_ctrl_reg_val); 200 if (ret) 201 return ret; 202 203 /* Clear the ACTIVE trigger */ 204 act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG; 205 ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg, 206 act_ctrl_reg_val); 207 if (ret) 208 return ret; 209 210 ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg, 211 slice_status, !(slice_status & status), 212 0, LLCC_STATUS_READ_DELAY); 213 return ret; 214 } 215 216 /** 217 * llcc_slice_activate - Activate the llcc slice 218 * @desc: Pointer to llcc slice descriptor 219 * 220 * A value of zero will be returned on success and a negative errno will 221 * be returned in error cases 222 */ 223 int llcc_slice_activate(struct llcc_slice_desc *desc) 224 { 225 int ret; 226 u32 act_ctrl_val; 227 228 if (IS_ERR(drv_data)) 229 return PTR_ERR(drv_data); 230 231 if (IS_ERR_OR_NULL(desc)) 232 return -EINVAL; 233 234 mutex_lock(&drv_data->lock); 235 if (test_bit(desc->slice_id, drv_data->bitmap)) { 236 mutex_unlock(&drv_data->lock); 237 return 0; 238 } 239 240 act_ctrl_val = ACT_CTRL_OPCODE_ACTIVATE << ACT_CTRL_OPCODE_SHIFT; 241 242 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 243 DEACTIVATE); 244 if (ret) { 245 mutex_unlock(&drv_data->lock); 246 return ret; 247 } 248 249 __set_bit(desc->slice_id, drv_data->bitmap); 250 mutex_unlock(&drv_data->lock); 251 252 return ret; 253 } 254 EXPORT_SYMBOL_GPL(llcc_slice_activate); 255 256 /** 257 * llcc_slice_deactivate - Deactivate the llcc slice 258 * @desc: Pointer to llcc slice descriptor 259 * 260 * A value of zero will be returned on success and a negative errno will 261 * be returned in error cases 262 */ 263 int llcc_slice_deactivate(struct llcc_slice_desc *desc) 264 { 265 u32 act_ctrl_val; 266 int ret; 267 268 if (IS_ERR(drv_data)) 269 return PTR_ERR(drv_data); 270 271 if (IS_ERR_OR_NULL(desc)) 272 return -EINVAL; 273 274 mutex_lock(&drv_data->lock); 275 if (!test_bit(desc->slice_id, drv_data->bitmap)) { 276 mutex_unlock(&drv_data->lock); 277 return 0; 278 } 279 act_ctrl_val = ACT_CTRL_OPCODE_DEACTIVATE << ACT_CTRL_OPCODE_SHIFT; 280 281 ret = llcc_update_act_ctrl(desc->slice_id, act_ctrl_val, 282 ACTIVATE); 283 if (ret) { 284 mutex_unlock(&drv_data->lock); 285 return ret; 286 } 287 288 __clear_bit(desc->slice_id, drv_data->bitmap); 289 mutex_unlock(&drv_data->lock); 290 291 return ret; 292 } 293 EXPORT_SYMBOL_GPL(llcc_slice_deactivate); 294 295 /** 296 * llcc_get_slice_id - return the slice id 297 * @desc: Pointer to llcc slice descriptor 298 */ 299 int llcc_get_slice_id(struct llcc_slice_desc *desc) 300 { 301 if (IS_ERR_OR_NULL(desc)) 302 return -EINVAL; 303 304 return desc->slice_id; 305 } 306 EXPORT_SYMBOL_GPL(llcc_get_slice_id); 307 308 /** 309 * llcc_get_slice_size - return the slice id 310 * @desc: Pointer to llcc slice descriptor 311 */ 312 size_t llcc_get_slice_size(struct llcc_slice_desc *desc) 313 { 314 if (IS_ERR_OR_NULL(desc)) 315 return 0; 316 317 return desc->slice_size; 318 } 319 EXPORT_SYMBOL_GPL(llcc_get_slice_size); 320 321 static int qcom_llcc_cfg_program(struct platform_device *pdev) 322 { 323 int i; 324 u32 attr1_cfg; 325 u32 attr0_cfg; 326 u32 attr1_val; 327 u32 attr0_val; 328 u32 max_cap_cacheline; 329 u32 sz; 330 int ret = 0; 331 const struct llcc_slice_config *llcc_table; 332 struct llcc_slice_desc desc; 333 334 sz = drv_data->cfg_size; 335 llcc_table = drv_data->cfg; 336 337 for (i = 0; i < sz; i++) { 338 attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id); 339 attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id); 340 341 attr1_val = llcc_table[i].cache_mode; 342 attr1_val |= llcc_table[i].probe_target_ways << 343 ATTR1_PROBE_TARGET_WAYS_SHIFT; 344 attr1_val |= llcc_table[i].fixed_size << 345 ATTR1_FIXED_SIZE_SHIFT; 346 attr1_val |= llcc_table[i].priority << 347 ATTR1_PRIORITY_SHIFT; 348 349 max_cap_cacheline = MAX_CAP_TO_BYTES(llcc_table[i].max_cap); 350 351 /* LLCC instances can vary for each target. 352 * The SW writes to broadcast register which gets propagated 353 * to each llcc instace (llcc0,.. llccN). 354 * Since the size of the memory is divided equally amongst the 355 * llcc instances, we need to configure the max cap accordingly. 356 */ 357 max_cap_cacheline = max_cap_cacheline / drv_data->num_banks; 358 max_cap_cacheline >>= CACHE_LINE_SIZE_SHIFT; 359 attr1_val |= max_cap_cacheline << ATTR1_MAX_CAP_SHIFT; 360 361 attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK; 362 attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT; 363 364 ret = regmap_write(drv_data->bcast_regmap, attr1_cfg, 365 attr1_val); 366 if (ret) 367 return ret; 368 ret = regmap_write(drv_data->bcast_regmap, attr0_cfg, 369 attr0_val); 370 if (ret) 371 return ret; 372 if (llcc_table[i].activate_on_init) { 373 desc.slice_id = llcc_table[i].slice_id; 374 ret = llcc_slice_activate(&desc); 375 } 376 } 377 return ret; 378 } 379 380 static int qcom_llcc_remove(struct platform_device *pdev) 381 { 382 /* Set the global pointer to a error code to avoid referencing it */ 383 drv_data = ERR_PTR(-ENODEV); 384 return 0; 385 } 386 387 static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, 388 const char *name) 389 { 390 struct resource *res; 391 void __iomem *base; 392 struct regmap_config llcc_regmap_config = { 393 .reg_bits = 32, 394 .reg_stride = 4, 395 .val_bits = 32, 396 .fast_io = true, 397 }; 398 399 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 400 if (!res) 401 return ERR_PTR(-ENODEV); 402 403 base = devm_ioremap_resource(&pdev->dev, res); 404 if (IS_ERR(base)) 405 return ERR_CAST(base); 406 407 llcc_regmap_config.name = name; 408 return devm_regmap_init_mmio(&pdev->dev, base, &llcc_regmap_config); 409 } 410 411 static int qcom_llcc_probe(struct platform_device *pdev) 412 { 413 u32 num_banks; 414 struct device *dev = &pdev->dev; 415 int ret, i; 416 struct platform_device *llcc_edac; 417 const struct qcom_llcc_config *cfg; 418 const struct llcc_slice_config *llcc_cfg; 419 u32 sz; 420 421 drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); 422 if (!drv_data) { 423 ret = -ENOMEM; 424 goto err; 425 } 426 427 drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); 428 if (IS_ERR(drv_data->regmap)) { 429 ret = PTR_ERR(drv_data->regmap); 430 goto err; 431 } 432 433 drv_data->bcast_regmap = 434 qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); 435 if (IS_ERR(drv_data->bcast_regmap)) { 436 ret = PTR_ERR(drv_data->bcast_regmap); 437 goto err; 438 } 439 440 ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0, 441 &num_banks); 442 if (ret) 443 goto err; 444 445 num_banks &= LLCC_LB_CNT_MASK; 446 num_banks >>= LLCC_LB_CNT_SHIFT; 447 drv_data->num_banks = num_banks; 448 449 cfg = of_device_get_match_data(&pdev->dev); 450 llcc_cfg = cfg->sct_data; 451 sz = cfg->size; 452 453 for (i = 0; i < sz; i++) 454 if (llcc_cfg[i].slice_id > drv_data->max_slices) 455 drv_data->max_slices = llcc_cfg[i].slice_id; 456 457 drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), 458 GFP_KERNEL); 459 if (!drv_data->offsets) { 460 ret = -ENOMEM; 461 goto err; 462 } 463 464 for (i = 0; i < num_banks; i++) 465 drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; 466 467 drv_data->bitmap = devm_kcalloc(dev, 468 BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long), 469 GFP_KERNEL); 470 if (!drv_data->bitmap) { 471 ret = -ENOMEM; 472 goto err; 473 } 474 475 drv_data->cfg = llcc_cfg; 476 drv_data->cfg_size = sz; 477 mutex_init(&drv_data->lock); 478 platform_set_drvdata(pdev, drv_data); 479 480 ret = qcom_llcc_cfg_program(pdev); 481 if (ret) 482 goto err; 483 484 drv_data->ecc_irq = platform_get_irq(pdev, 0); 485 if (drv_data->ecc_irq >= 0) { 486 llcc_edac = platform_device_register_data(&pdev->dev, 487 "qcom_llcc_edac", -1, drv_data, 488 sizeof(*drv_data)); 489 if (IS_ERR(llcc_edac)) 490 dev_err(dev, "Failed to register llcc edac driver\n"); 491 } 492 493 return 0; 494 err: 495 drv_data = ERR_PTR(-ENODEV); 496 return ret; 497 } 498 499 static const struct of_device_id qcom_llcc_of_match[] = { 500 { .compatible = "qcom,sc7180-llcc", .data = &sc7180_cfg }, 501 { .compatible = "qcom,sdm845-llcc", .data = &sdm845_cfg }, 502 { } 503 }; 504 505 static struct platform_driver qcom_llcc_driver = { 506 .driver = { 507 .name = "qcom-llcc", 508 .of_match_table = qcom_llcc_of_match, 509 }, 510 .probe = qcom_llcc_probe, 511 .remove = qcom_llcc_remove, 512 }; 513 module_platform_driver(qcom_llcc_driver); 514 515 MODULE_DESCRIPTION("Qualcomm Last Level Cache Controller"); 516 MODULE_LICENSE("GPL v2"); 517