1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2018-2019 HiSilicon Limited. */ 3 #include <linux/acpi.h> 4 #include <linux/aer.h> 5 #include <linux/bitops.h> 6 #include <linux/debugfs.h> 7 #include <linux/init.h> 8 #include <linux/io.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/topology.h> 13 #include "hpre.h" 14 15 #define HPRE_VF_NUM 63 16 #define HPRE_QUEUE_NUM_V2 1024 17 #define HPRE_QM_ABNML_INT_MASK 0x100004 18 #define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0) 19 #define HPRE_COMM_CNT_CLR_CE 0x0 20 #define HPRE_CTRL_CNT_CLR_CE 0x301000 21 #define HPRE_FSM_MAX_CNT 0x301008 22 #define HPRE_VFG_AXQOS 0x30100c 23 #define HPRE_VFG_AXCACHE 0x301010 24 #define HPRE_RDCHN_INI_CFG 0x301014 25 #define HPRE_AWUSR_FP_CFG 0x301018 26 #define HPRE_BD_ENDIAN 0x301020 27 #define HPRE_ECC_BYPASS 0x301024 28 #define HPRE_RAS_WIDTH_CFG 0x301028 29 #define HPRE_POISON_BYPASS 0x30102c 30 #define HPRE_BD_ARUSR_CFG 0x301030 31 #define HPRE_BD_AWUSR_CFG 0x301034 32 #define HPRE_TYPES_ENB 0x301038 33 #define HPRE_DATA_RUSER_CFG 0x30103c 34 #define HPRE_DATA_WUSER_CFG 0x301040 35 #define HPRE_INT_MASK 0x301400 36 #define HPRE_INT_STATUS 0x301800 37 #define HPRE_CORE_INT_ENABLE 0 38 #define HPRE_CORE_INT_DISABLE 0x003fffff 39 #define HPRE_RAS_ECC_1BIT_TH 0x30140c 40 #define HPRE_RDCHN_INI_ST 0x301a00 41 #define HPRE_CLSTR_BASE 0x302000 42 #define HPRE_CORE_EN_OFFSET 0x04 43 #define HPRE_CORE_INI_CFG_OFFSET 0x20 44 #define HPRE_CORE_INI_STATUS_OFFSET 0x80 45 #define HPRE_CORE_HTBT_WARN_OFFSET 0x8c 46 #define HPRE_CORE_IS_SCHD_OFFSET 0x90 47 48 #define HPRE_RAS_CE_ENB 0x301410 49 #define HPRE_HAC_RAS_CE_ENABLE 0x3f 50 #define HPRE_RAS_NFE_ENB 0x301414 51 #define HPRE_HAC_RAS_NFE_ENABLE 0x3fffc0 52 #define HPRE_RAS_FE_ENB 0x301418 53 #define HPRE_HAC_RAS_FE_ENABLE 0 54 55 #define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET) 56 #define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET) 57 #define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET) 58 #define HPRE_HAC_ECC1_CNT 0x301a04 59 #define HPRE_HAC_ECC2_CNT 0x301a08 60 #define HPRE_HAC_INT_STATUS 0x301800 61 #define HPRE_HAC_SOURCE_INT 0x301600 62 #define MASTER_GLOBAL_CTRL_SHUTDOWN 1 63 #define MASTER_TRANS_RETURN_RW 3 64 #define HPRE_MASTER_TRANS_RETURN 0x300150 65 #define HPRE_MASTER_GLOBAL_CTRL 0x300000 66 #define HPRE_CLSTR_ADDR_INTRVL 0x1000 67 #define HPRE_CLUSTER_INQURY 0x100 68 #define HPRE_CLSTR_ADDR_INQRY_RSLT 0x104 69 #define HPRE_TIMEOUT_ABNML_BIT 6 70 #define HPRE_PASID_EN_BIT 9 71 #define HPRE_REG_RD_INTVRL_US 10 72 #define HPRE_REG_RD_TMOUT_US 1000 73 #define HPRE_DBGFS_VAL_MAX_LEN 20 74 #define HPRE_PCI_DEVICE_ID 0xa258 75 #define HPRE_PCI_VF_DEVICE_ID 0xa259 76 #define HPRE_ADDR(qm, offset) ((qm)->io_base + (offset)) 77 #define HPRE_QM_USR_CFG_MASK 0xfffffffe 78 #define HPRE_QM_AXI_CFG_MASK 0xffff 79 #define HPRE_QM_VFG_AX_MASK 0xff 80 #define HPRE_BD_USR_MASK 0x3 81 #define HPRE_CLUSTER_CORE_MASK 0xf 82 83 #define HPRE_VIA_MSI_DSM 1 84 85 static struct hisi_qm_list hpre_devices; 86 static const char hpre_name[] = "hisi_hpre"; 87 static struct dentry *hpre_debugfs_root; 88 static const struct pci_device_id hpre_dev_ids[] = { 89 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_DEVICE_ID) }, 90 { PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_VF_DEVICE_ID) }, 91 { 0, } 92 }; 93 94 MODULE_DEVICE_TABLE(pci, hpre_dev_ids); 95 96 struct hpre_hw_error { 97 u32 int_msk; 98 const char *msg; 99 }; 100 101 static const char * const hpre_debug_file_name[] = { 102 [HPRE_CURRENT_QM] = "current_qm", 103 [HPRE_CLEAR_ENABLE] = "rdclr_en", 104 [HPRE_CLUSTER_CTRL] = "cluster_ctrl", 105 }; 106 107 static const struct hpre_hw_error hpre_hw_errors[] = { 108 { .int_msk = BIT(0), .msg = "core_ecc_1bit_err_int_set" }, 109 { .int_msk = BIT(1), .msg = "core_ecc_2bit_err_int_set" }, 110 { .int_msk = BIT(2), .msg = "dat_wb_poison_int_set" }, 111 { .int_msk = BIT(3), .msg = "dat_rd_poison_int_set" }, 112 { .int_msk = BIT(4), .msg = "bd_rd_poison_int_set" }, 113 { .int_msk = BIT(5), .msg = "ooo_ecc_2bit_err_int_set" }, 114 { .int_msk = BIT(6), .msg = "cluster1_shb_timeout_int_set" }, 115 { .int_msk = BIT(7), .msg = "cluster2_shb_timeout_int_set" }, 116 { .int_msk = BIT(8), .msg = "cluster3_shb_timeout_int_set" }, 117 { .int_msk = BIT(9), .msg = "cluster4_shb_timeout_int_set" }, 118 { .int_msk = GENMASK(15, 10), .msg = "ooo_rdrsp_err_int_set" }, 119 { .int_msk = GENMASK(21, 16), .msg = "ooo_wrrsp_err_int_set" }, 120 { /* sentinel */ } 121 }; 122 123 static const u64 hpre_cluster_offsets[] = { 124 [HPRE_CLUSTER0] = 125 HPRE_CLSTR_BASE + HPRE_CLUSTER0 * HPRE_CLSTR_ADDR_INTRVL, 126 [HPRE_CLUSTER1] = 127 HPRE_CLSTR_BASE + HPRE_CLUSTER1 * HPRE_CLSTR_ADDR_INTRVL, 128 [HPRE_CLUSTER2] = 129 HPRE_CLSTR_BASE + HPRE_CLUSTER2 * HPRE_CLSTR_ADDR_INTRVL, 130 [HPRE_CLUSTER3] = 131 HPRE_CLSTR_BASE + HPRE_CLUSTER3 * HPRE_CLSTR_ADDR_INTRVL, 132 }; 133 134 static struct debugfs_reg32 hpre_cluster_dfx_regs[] = { 135 {"CORES_EN_STATUS ", HPRE_CORE_EN_OFFSET}, 136 {"CORES_INI_CFG ", HPRE_CORE_INI_CFG_OFFSET}, 137 {"CORES_INI_STATUS ", HPRE_CORE_INI_STATUS_OFFSET}, 138 {"CORES_HTBT_WARN ", HPRE_CORE_HTBT_WARN_OFFSET}, 139 {"CORES_IS_SCHD ", HPRE_CORE_IS_SCHD_OFFSET}, 140 }; 141 142 static struct debugfs_reg32 hpre_com_dfx_regs[] = { 143 {"READ_CLR_EN ", HPRE_CTRL_CNT_CLR_CE}, 144 {"AXQOS ", HPRE_VFG_AXQOS}, 145 {"AWUSR_CFG ", HPRE_AWUSR_FP_CFG}, 146 {"QM_ARUSR_MCFG1 ", QM_ARUSER_M_CFG_1}, 147 {"QM_AWUSR_MCFG1 ", QM_AWUSER_M_CFG_1}, 148 {"BD_ENDIAN ", HPRE_BD_ENDIAN}, 149 {"ECC_CHECK_CTRL ", HPRE_ECC_BYPASS}, 150 {"RAS_INT_WIDTH ", HPRE_RAS_WIDTH_CFG}, 151 {"POISON_BYPASS ", HPRE_POISON_BYPASS}, 152 {"BD_ARUSER ", HPRE_BD_ARUSR_CFG}, 153 {"BD_AWUSER ", HPRE_BD_AWUSR_CFG}, 154 {"DATA_ARUSER ", HPRE_DATA_RUSER_CFG}, 155 {"DATA_AWUSER ", HPRE_DATA_WUSER_CFG}, 156 {"INT_STATUS ", HPRE_INT_STATUS}, 157 }; 158 159 static int hpre_pf_q_num_set(const char *val, const struct kernel_param *kp) 160 { 161 struct pci_dev *pdev; 162 u32 n, q_num; 163 u8 rev_id; 164 int ret; 165 166 if (!val) 167 return -EINVAL; 168 169 pdev = pci_get_device(PCI_VENDOR_ID_HUAWEI, HPRE_PCI_DEVICE_ID, NULL); 170 if (!pdev) { 171 q_num = HPRE_QUEUE_NUM_V2; 172 pr_info("No device found currently, suppose queue number is %d\n", 173 q_num); 174 } else { 175 rev_id = pdev->revision; 176 if (rev_id != QM_HW_V2) 177 return -EINVAL; 178 179 q_num = HPRE_QUEUE_NUM_V2; 180 } 181 182 ret = kstrtou32(val, 10, &n); 183 if (ret != 0 || n == 0 || n > q_num) 184 return -EINVAL; 185 186 return param_set_int(val, kp); 187 } 188 189 static const struct kernel_param_ops hpre_pf_q_num_ops = { 190 .set = hpre_pf_q_num_set, 191 .get = param_get_int, 192 }; 193 194 static u32 hpre_pf_q_num = HPRE_PF_DEF_Q_NUM; 195 module_param_cb(hpre_pf_q_num, &hpre_pf_q_num_ops, &hpre_pf_q_num, 0444); 196 MODULE_PARM_DESC(hpre_pf_q_num, "Number of queues in PF of CS(1-1024)"); 197 198 struct hisi_qp *hpre_create_qp(void) 199 { 200 int node = cpu_to_node(smp_processor_id()); 201 struct hisi_qp *qp = NULL; 202 int ret; 203 204 ret = hisi_qm_alloc_qps_node(&hpre_devices, 1, 0, node, &qp); 205 if (!ret) 206 return qp; 207 208 return NULL; 209 } 210 211 static int hpre_cfg_by_dsm(struct hisi_qm *qm) 212 { 213 struct device *dev = &qm->pdev->dev; 214 union acpi_object *obj; 215 guid_t guid; 216 217 if (guid_parse("b06b81ab-0134-4a45-9b0c-483447b95fa7", &guid)) { 218 dev_err(dev, "Hpre GUID failed\n"); 219 return -EINVAL; 220 } 221 222 /* Switch over to MSI handling due to non-standard PCI implementation */ 223 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 224 0, HPRE_VIA_MSI_DSM, NULL); 225 if (!obj) { 226 dev_err(dev, "ACPI handle failed!\n"); 227 return -EIO; 228 } 229 230 ACPI_FREE(obj); 231 232 return 0; 233 } 234 235 static int hpre_set_user_domain_and_cache(struct hpre *hpre) 236 { 237 struct hisi_qm *qm = &hpre->qm; 238 struct device *dev = &qm->pdev->dev; 239 unsigned long offset; 240 int ret, i; 241 u32 val; 242 243 writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_ARUSER_M_CFG_ENABLE)); 244 writel(HPRE_QM_USR_CFG_MASK, HPRE_ADDR(qm, QM_AWUSER_M_CFG_ENABLE)); 245 writel_relaxed(HPRE_QM_AXI_CFG_MASK, HPRE_ADDR(qm, QM_AXI_M_CFG)); 246 247 /* disable FLR triggered by BME(bus master enable) */ 248 writel(PEH_AXUSER_CFG, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG)); 249 writel(PEH_AXUSER_CFG_ENABLE, HPRE_ADDR(qm, QM_PEH_AXUSER_CFG_ENABLE)); 250 251 /* HPRE need more time, we close this interrupt */ 252 val = readl_relaxed(HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK)); 253 val |= BIT(HPRE_TIMEOUT_ABNML_BIT); 254 writel_relaxed(val, HPRE_ADDR(qm, HPRE_QM_ABNML_INT_MASK)); 255 256 writel(0x1, HPRE_ADDR(qm, HPRE_TYPES_ENB)); 257 writel(HPRE_QM_VFG_AX_MASK, HPRE_ADDR(qm, HPRE_VFG_AXCACHE)); 258 writel(0x0, HPRE_ADDR(qm, HPRE_BD_ENDIAN)); 259 writel(0x0, HPRE_ADDR(qm, HPRE_INT_MASK)); 260 writel(0x0, HPRE_ADDR(qm, HPRE_RAS_ECC_1BIT_TH)); 261 writel(0x0, HPRE_ADDR(qm, HPRE_POISON_BYPASS)); 262 writel(0x0, HPRE_ADDR(qm, HPRE_COMM_CNT_CLR_CE)); 263 writel(0x0, HPRE_ADDR(qm, HPRE_ECC_BYPASS)); 264 265 writel(HPRE_BD_USR_MASK, HPRE_ADDR(qm, HPRE_BD_ARUSR_CFG)); 266 writel(HPRE_BD_USR_MASK, HPRE_ADDR(qm, HPRE_BD_AWUSR_CFG)); 267 writel(0x1, HPRE_ADDR(qm, HPRE_RDCHN_INI_CFG)); 268 ret = readl_relaxed_poll_timeout(HPRE_ADDR(qm, HPRE_RDCHN_INI_ST), val, 269 val & BIT(0), 270 HPRE_REG_RD_INTVRL_US, 271 HPRE_REG_RD_TMOUT_US); 272 if (ret) { 273 dev_err(dev, "read rd channel timeout fail!\n"); 274 return -ETIMEDOUT; 275 } 276 277 for (i = 0; i < HPRE_CLUSTERS_NUM; i++) { 278 offset = i * HPRE_CLSTR_ADDR_INTRVL; 279 280 /* clusters initiating */ 281 writel(HPRE_CLUSTER_CORE_MASK, 282 HPRE_ADDR(qm, offset + HPRE_CORE_ENB)); 283 writel(0x1, HPRE_ADDR(qm, offset + HPRE_CORE_INI_CFG)); 284 ret = readl_relaxed_poll_timeout(HPRE_ADDR(qm, offset + 285 HPRE_CORE_INI_STATUS), val, 286 ((val & HPRE_CLUSTER_CORE_MASK) == 287 HPRE_CLUSTER_CORE_MASK), 288 HPRE_REG_RD_INTVRL_US, 289 HPRE_REG_RD_TMOUT_US); 290 if (ret) { 291 dev_err(dev, 292 "cluster %d int st status timeout!\n", i); 293 return -ETIMEDOUT; 294 } 295 } 296 297 ret = hpre_cfg_by_dsm(qm); 298 if (ret) 299 dev_err(dev, "acpi_evaluate_dsm err.\n"); 300 301 return ret; 302 } 303 304 static void hpre_cnt_regs_clear(struct hisi_qm *qm) 305 { 306 unsigned long offset; 307 int i; 308 309 /* clear current_qm */ 310 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF); 311 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF); 312 313 /* clear clusterX/cluster_ctrl */ 314 for (i = 0; i < HPRE_CLUSTERS_NUM; i++) { 315 offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL; 316 writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY); 317 } 318 319 /* clear rdclr_en */ 320 writel(0x0, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 321 322 hisi_qm_debug_regs_clear(qm); 323 } 324 325 static void hpre_hw_error_disable(struct hisi_qm *qm) 326 { 327 /* disable hpre hw error interrupts */ 328 writel(HPRE_CORE_INT_DISABLE, qm->io_base + HPRE_INT_MASK); 329 } 330 331 static void hpre_hw_error_enable(struct hisi_qm *qm) 332 { 333 /* enable hpre hw error interrupts */ 334 writel(HPRE_CORE_INT_ENABLE, qm->io_base + HPRE_INT_MASK); 335 writel(HPRE_HAC_RAS_CE_ENABLE, qm->io_base + HPRE_RAS_CE_ENB); 336 writel(HPRE_HAC_RAS_NFE_ENABLE, qm->io_base + HPRE_RAS_NFE_ENB); 337 writel(HPRE_HAC_RAS_FE_ENABLE, qm->io_base + HPRE_RAS_FE_ENB); 338 } 339 340 static inline struct hisi_qm *hpre_file_to_qm(struct hpre_debugfs_file *file) 341 { 342 struct hpre *hpre = container_of(file->debug, struct hpre, debug); 343 344 return &hpre->qm; 345 } 346 347 static u32 hpre_current_qm_read(struct hpre_debugfs_file *file) 348 { 349 struct hisi_qm *qm = hpre_file_to_qm(file); 350 351 return readl(qm->io_base + QM_DFX_MB_CNT_VF); 352 } 353 354 static int hpre_current_qm_write(struct hpre_debugfs_file *file, u32 val) 355 { 356 struct hisi_qm *qm = hpre_file_to_qm(file); 357 struct hpre_debug *debug = file->debug; 358 struct hpre *hpre = container_of(debug, struct hpre, debug); 359 u32 num_vfs = hpre->num_vfs; 360 u32 vfq_num, tmp; 361 362 363 if (val > num_vfs) 364 return -EINVAL; 365 366 /* According PF or VF Dev ID to calculation curr_qm_qp_num and store */ 367 if (val == 0) { 368 qm->debug.curr_qm_qp_num = qm->qp_num; 369 } else { 370 vfq_num = (qm->ctrl_qp_num - qm->qp_num) / num_vfs; 371 if (val == num_vfs) { 372 qm->debug.curr_qm_qp_num = 373 qm->ctrl_qp_num - qm->qp_num - (num_vfs - 1) * vfq_num; 374 } else { 375 qm->debug.curr_qm_qp_num = vfq_num; 376 } 377 } 378 379 writel(val, qm->io_base + QM_DFX_MB_CNT_VF); 380 writel(val, qm->io_base + QM_DFX_DB_CNT_VF); 381 382 tmp = val | 383 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK); 384 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN); 385 386 tmp = val | 387 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK); 388 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN); 389 390 return 0; 391 } 392 393 static u32 hpre_clear_enable_read(struct hpre_debugfs_file *file) 394 { 395 struct hisi_qm *qm = hpre_file_to_qm(file); 396 397 return readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 398 HPRE_CTRL_CNT_CLR_CE_BIT; 399 } 400 401 static int hpre_clear_enable_write(struct hpre_debugfs_file *file, u32 val) 402 { 403 struct hisi_qm *qm = hpre_file_to_qm(file); 404 u32 tmp; 405 406 if (val != 1 && val != 0) 407 return -EINVAL; 408 409 tmp = (readl(qm->io_base + HPRE_CTRL_CNT_CLR_CE) & 410 ~HPRE_CTRL_CNT_CLR_CE_BIT) | val; 411 writel(tmp, qm->io_base + HPRE_CTRL_CNT_CLR_CE); 412 413 return 0; 414 } 415 416 static u32 hpre_cluster_inqry_read(struct hpre_debugfs_file *file) 417 { 418 struct hisi_qm *qm = hpre_file_to_qm(file); 419 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 420 unsigned long offset = HPRE_CLSTR_BASE + 421 cluster_index * HPRE_CLSTR_ADDR_INTRVL; 422 423 return readl(qm->io_base + offset + HPRE_CLSTR_ADDR_INQRY_RSLT); 424 } 425 426 static int hpre_cluster_inqry_write(struct hpre_debugfs_file *file, u32 val) 427 { 428 struct hisi_qm *qm = hpre_file_to_qm(file); 429 int cluster_index = file->index - HPRE_CLUSTER_CTRL; 430 unsigned long offset = HPRE_CLSTR_BASE + cluster_index * 431 HPRE_CLSTR_ADDR_INTRVL; 432 433 writel(val, qm->io_base + offset + HPRE_CLUSTER_INQURY); 434 435 return 0; 436 } 437 438 static ssize_t hpre_ctrl_debug_read(struct file *filp, char __user *buf, 439 size_t count, loff_t *pos) 440 { 441 struct hpre_debugfs_file *file = filp->private_data; 442 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 443 u32 val; 444 int ret; 445 446 spin_lock_irq(&file->lock); 447 switch (file->type) { 448 case HPRE_CURRENT_QM: 449 val = hpre_current_qm_read(file); 450 break; 451 case HPRE_CLEAR_ENABLE: 452 val = hpre_clear_enable_read(file); 453 break; 454 case HPRE_CLUSTER_CTRL: 455 val = hpre_cluster_inqry_read(file); 456 break; 457 default: 458 spin_unlock_irq(&file->lock); 459 return -EINVAL; 460 } 461 spin_unlock_irq(&file->lock); 462 ret = snprintf(tbuf, HPRE_DBGFS_VAL_MAX_LEN, "%u\n", val); 463 return simple_read_from_buffer(buf, count, pos, tbuf, ret); 464 } 465 466 static ssize_t hpre_ctrl_debug_write(struct file *filp, const char __user *buf, 467 size_t count, loff_t *pos) 468 { 469 struct hpre_debugfs_file *file = filp->private_data; 470 char tbuf[HPRE_DBGFS_VAL_MAX_LEN]; 471 unsigned long val; 472 int len, ret; 473 474 if (*pos != 0) 475 return 0; 476 477 if (count >= HPRE_DBGFS_VAL_MAX_LEN) 478 return -ENOSPC; 479 480 len = simple_write_to_buffer(tbuf, HPRE_DBGFS_VAL_MAX_LEN - 1, 481 pos, buf, count); 482 if (len < 0) 483 return len; 484 485 tbuf[len] = '\0'; 486 if (kstrtoul(tbuf, 0, &val)) 487 return -EFAULT; 488 489 spin_lock_irq(&file->lock); 490 switch (file->type) { 491 case HPRE_CURRENT_QM: 492 ret = hpre_current_qm_write(file, val); 493 if (ret) 494 goto err_input; 495 break; 496 case HPRE_CLEAR_ENABLE: 497 ret = hpre_clear_enable_write(file, val); 498 if (ret) 499 goto err_input; 500 break; 501 case HPRE_CLUSTER_CTRL: 502 ret = hpre_cluster_inqry_write(file, val); 503 if (ret) 504 goto err_input; 505 break; 506 default: 507 ret = -EINVAL; 508 goto err_input; 509 } 510 spin_unlock_irq(&file->lock); 511 512 return count; 513 514 err_input: 515 spin_unlock_irq(&file->lock); 516 return ret; 517 } 518 519 static const struct file_operations hpre_ctrl_debug_fops = { 520 .owner = THIS_MODULE, 521 .open = simple_open, 522 .read = hpre_ctrl_debug_read, 523 .write = hpre_ctrl_debug_write, 524 }; 525 526 static int hpre_create_debugfs_file(struct hpre_debug *dbg, struct dentry *dir, 527 enum hpre_ctrl_dbgfs_file type, int indx) 528 { 529 struct dentry *file_dir; 530 531 if (dir) 532 file_dir = dir; 533 else 534 file_dir = dbg->debug_root; 535 536 if (type >= HPRE_DEBUG_FILE_NUM) 537 return -EINVAL; 538 539 spin_lock_init(&dbg->files[indx].lock); 540 dbg->files[indx].debug = dbg; 541 dbg->files[indx].type = type; 542 dbg->files[indx].index = indx; 543 debugfs_create_file(hpre_debug_file_name[type], 0600, file_dir, 544 dbg->files + indx, &hpre_ctrl_debug_fops); 545 546 return 0; 547 } 548 549 static int hpre_pf_comm_regs_debugfs_init(struct hpre_debug *debug) 550 { 551 struct hpre *hpre = container_of(debug, struct hpre, debug); 552 struct hisi_qm *qm = &hpre->qm; 553 struct device *dev = &qm->pdev->dev; 554 struct debugfs_regset32 *regset; 555 556 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 557 if (!regset) 558 return -ENOMEM; 559 560 regset->regs = hpre_com_dfx_regs; 561 regset->nregs = ARRAY_SIZE(hpre_com_dfx_regs); 562 regset->base = qm->io_base; 563 564 debugfs_create_regset32("regs", 0444, debug->debug_root, regset); 565 return 0; 566 } 567 568 static int hpre_cluster_debugfs_init(struct hpre_debug *debug) 569 { 570 struct hpre *hpre = container_of(debug, struct hpre, debug); 571 struct hisi_qm *qm = &hpre->qm; 572 struct device *dev = &qm->pdev->dev; 573 char buf[HPRE_DBGFS_VAL_MAX_LEN]; 574 struct debugfs_regset32 *regset; 575 struct dentry *tmp_d; 576 int i, ret; 577 578 for (i = 0; i < HPRE_CLUSTERS_NUM; i++) { 579 ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i); 580 if (ret < 0) 581 return -EINVAL; 582 tmp_d = debugfs_create_dir(buf, debug->debug_root); 583 584 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 585 if (!regset) 586 return -ENOMEM; 587 588 regset->regs = hpre_cluster_dfx_regs; 589 regset->nregs = ARRAY_SIZE(hpre_cluster_dfx_regs); 590 regset->base = qm->io_base + hpre_cluster_offsets[i]; 591 592 debugfs_create_regset32("regs", 0444, tmp_d, regset); 593 ret = hpre_create_debugfs_file(debug, tmp_d, HPRE_CLUSTER_CTRL, 594 i + HPRE_CLUSTER_CTRL); 595 if (ret) 596 return ret; 597 } 598 599 return 0; 600 } 601 602 static int hpre_ctrl_debug_init(struct hpre_debug *debug) 603 { 604 int ret; 605 606 ret = hpre_create_debugfs_file(debug, NULL, HPRE_CURRENT_QM, 607 HPRE_CURRENT_QM); 608 if (ret) 609 return ret; 610 611 ret = hpre_create_debugfs_file(debug, NULL, HPRE_CLEAR_ENABLE, 612 HPRE_CLEAR_ENABLE); 613 if (ret) 614 return ret; 615 616 ret = hpre_pf_comm_regs_debugfs_init(debug); 617 if (ret) 618 return ret; 619 620 return hpre_cluster_debugfs_init(debug); 621 } 622 623 static int hpre_debugfs_init(struct hpre *hpre) 624 { 625 struct hisi_qm *qm = &hpre->qm; 626 struct device *dev = &qm->pdev->dev; 627 struct dentry *dir; 628 int ret; 629 630 dir = debugfs_create_dir(dev_name(dev), hpre_debugfs_root); 631 qm->debug.debug_root = dir; 632 633 ret = hisi_qm_debug_init(qm); 634 if (ret) 635 goto failed_to_create; 636 637 if (qm->pdev->device == HPRE_PCI_DEVICE_ID) { 638 hpre->debug.debug_root = dir; 639 ret = hpre_ctrl_debug_init(&hpre->debug); 640 if (ret) 641 goto failed_to_create; 642 } 643 return 0; 644 645 failed_to_create: 646 debugfs_remove_recursive(qm->debug.debug_root); 647 return ret; 648 } 649 650 static void hpre_debugfs_exit(struct hpre *hpre) 651 { 652 struct hisi_qm *qm = &hpre->qm; 653 654 debugfs_remove_recursive(qm->debug.debug_root); 655 } 656 657 static int hpre_qm_pre_init(struct hisi_qm *qm, struct pci_dev *pdev) 658 { 659 enum qm_hw_ver rev_id; 660 661 rev_id = hisi_qm_get_hw_version(pdev); 662 if (rev_id < 0) 663 return -ENODEV; 664 665 if (rev_id == QM_HW_V1) { 666 pci_warn(pdev, "HPRE version 1 is not supported!\n"); 667 return -EINVAL; 668 } 669 670 qm->pdev = pdev; 671 qm->ver = rev_id; 672 qm->sqe_size = HPRE_SQE_SIZE; 673 qm->dev_name = hpre_name; 674 qm->fun_type = (pdev->device == HPRE_PCI_DEVICE_ID) ? 675 QM_HW_PF : QM_HW_VF; 676 if (pdev->is_physfn) { 677 qm->qp_base = HPRE_PF_DEF_Q_BASE; 678 qm->qp_num = hpre_pf_q_num; 679 } 680 qm->use_dma_api = true; 681 682 return 0; 683 } 684 685 static void hpre_log_hw_error(struct hisi_qm *qm, u32 err_sts) 686 { 687 const struct hpre_hw_error *err = hpre_hw_errors; 688 struct device *dev = &qm->pdev->dev; 689 690 while (err->msg) { 691 if (err->int_msk & err_sts) 692 dev_warn(dev, "%s [error status=0x%x] found\n", 693 err->msg, err->int_msk); 694 err++; 695 } 696 697 writel(err_sts, qm->io_base + HPRE_HAC_SOURCE_INT); 698 } 699 700 static u32 hpre_get_hw_err_status(struct hisi_qm *qm) 701 { 702 return readl(qm->io_base + HPRE_HAC_INT_STATUS); 703 } 704 705 static const struct hisi_qm_err_ini hpre_err_ini = { 706 .hw_err_enable = hpre_hw_error_enable, 707 .hw_err_disable = hpre_hw_error_disable, 708 .get_dev_hw_err_status = hpre_get_hw_err_status, 709 .log_dev_hw_err = hpre_log_hw_error, 710 .err_info = { 711 .ce = QM_BASE_CE, 712 .nfe = QM_BASE_NFE | QM_ACC_DO_TASK_TIMEOUT, 713 .fe = 0, 714 .msi = QM_DB_RANDOM_INVALID, 715 } 716 }; 717 718 static int hpre_pf_probe_init(struct hpre *hpre) 719 { 720 struct hisi_qm *qm = &hpre->qm; 721 int ret; 722 723 qm->ctrl_qp_num = HPRE_QUEUE_NUM_V2; 724 725 ret = hpre_set_user_domain_and_cache(hpre); 726 if (ret) 727 return ret; 728 729 qm->err_ini = &hpre_err_ini; 730 hisi_qm_dev_err_init(qm); 731 732 return 0; 733 } 734 735 static int hpre_probe(struct pci_dev *pdev, const struct pci_device_id *id) 736 { 737 struct hisi_qm *qm; 738 struct hpre *hpre; 739 int ret; 740 741 hpre = devm_kzalloc(&pdev->dev, sizeof(*hpre), GFP_KERNEL); 742 if (!hpre) 743 return -ENOMEM; 744 745 pci_set_drvdata(pdev, hpre); 746 747 qm = &hpre->qm; 748 ret = hpre_qm_pre_init(qm, pdev); 749 if (ret) 750 return ret; 751 752 ret = hisi_qm_init(qm); 753 if (ret) 754 return ret; 755 756 if (pdev->is_physfn) { 757 ret = hpre_pf_probe_init(hpre); 758 if (ret) 759 goto err_with_qm_init; 760 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V2) { 761 /* v2 starts to support get vft by mailbox */ 762 ret = hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num); 763 if (ret) 764 goto err_with_qm_init; 765 } 766 767 ret = hisi_qm_start(qm); 768 if (ret) 769 goto err_with_err_init; 770 771 ret = hpre_debugfs_init(hpre); 772 if (ret) 773 dev_warn(&pdev->dev, "init debugfs fail!\n"); 774 775 hisi_qm_add_to_list(qm, &hpre_devices); 776 777 ret = hpre_algs_register(); 778 if (ret < 0) { 779 pci_err(pdev, "fail to register algs to crypto!\n"); 780 goto err_with_qm_start; 781 } 782 return 0; 783 784 err_with_qm_start: 785 hisi_qm_del_from_list(qm, &hpre_devices); 786 hisi_qm_stop(qm); 787 788 err_with_err_init: 789 hisi_qm_dev_err_uninit(qm); 790 791 err_with_qm_init: 792 hisi_qm_uninit(qm); 793 794 return ret; 795 } 796 797 static int hpre_vf_q_assign(struct hpre *hpre, int num_vfs) 798 { 799 struct hisi_qm *qm = &hpre->qm; 800 u32 qp_num = qm->qp_num; 801 int q_num, remain_q_num, i; 802 u32 q_base = qp_num; 803 int ret; 804 805 if (!num_vfs) 806 return -EINVAL; 807 808 remain_q_num = qm->ctrl_qp_num - qp_num; 809 810 /* If remaining queues are not enough, return error. */ 811 if (remain_q_num < num_vfs) 812 return -EINVAL; 813 814 q_num = remain_q_num / num_vfs; 815 for (i = 1; i <= num_vfs; i++) { 816 if (i == num_vfs) 817 q_num += remain_q_num % num_vfs; 818 ret = hisi_qm_set_vft(qm, i, q_base, (u32)q_num); 819 if (ret) 820 return ret; 821 q_base += q_num; 822 } 823 824 return 0; 825 } 826 827 static int hpre_clear_vft_config(struct hpre *hpre) 828 { 829 struct hisi_qm *qm = &hpre->qm; 830 u32 num_vfs = hpre->num_vfs; 831 int ret; 832 u32 i; 833 834 for (i = 1; i <= num_vfs; i++) { 835 ret = hisi_qm_set_vft(qm, i, 0, 0); 836 if (ret) 837 return ret; 838 } 839 hpre->num_vfs = 0; 840 841 return 0; 842 } 843 844 static int hpre_sriov_enable(struct pci_dev *pdev, int max_vfs) 845 { 846 struct hpre *hpre = pci_get_drvdata(pdev); 847 int pre_existing_vfs, num_vfs, ret; 848 849 pre_existing_vfs = pci_num_vf(pdev); 850 if (pre_existing_vfs) { 851 pci_err(pdev, 852 "Can't enable VF. Please disable pre-enabled VFs!\n"); 853 return 0; 854 } 855 856 num_vfs = min_t(int, max_vfs, HPRE_VF_NUM); 857 ret = hpre_vf_q_assign(hpre, num_vfs); 858 if (ret) { 859 pci_err(pdev, "Can't assign queues for VF!\n"); 860 return ret; 861 } 862 863 hpre->num_vfs = num_vfs; 864 865 ret = pci_enable_sriov(pdev, num_vfs); 866 if (ret) { 867 pci_err(pdev, "Can't enable VF!\n"); 868 hpre_clear_vft_config(hpre); 869 return ret; 870 } 871 872 return num_vfs; 873 } 874 875 static int hpre_sriov_disable(struct pci_dev *pdev) 876 { 877 struct hpre *hpre = pci_get_drvdata(pdev); 878 879 if (pci_vfs_assigned(pdev)) { 880 pci_err(pdev, "Failed to disable VFs while VFs are assigned!\n"); 881 return -EPERM; 882 } 883 884 /* remove in hpre_pci_driver will be called to free VF resources */ 885 pci_disable_sriov(pdev); 886 887 return hpre_clear_vft_config(hpre); 888 } 889 890 static int hpre_sriov_configure(struct pci_dev *pdev, int num_vfs) 891 { 892 if (num_vfs) 893 return hpre_sriov_enable(pdev, num_vfs); 894 else 895 return hpre_sriov_disable(pdev); 896 } 897 898 static void hpre_remove(struct pci_dev *pdev) 899 { 900 struct hpre *hpre = pci_get_drvdata(pdev); 901 struct hisi_qm *qm = &hpre->qm; 902 int ret; 903 904 hpre_algs_unregister(); 905 hisi_qm_del_from_list(qm, &hpre_devices); 906 if (qm->fun_type == QM_HW_PF && hpre->num_vfs != 0) { 907 ret = hpre_sriov_disable(pdev); 908 if (ret) { 909 pci_err(pdev, "Disable SRIOV fail!\n"); 910 return; 911 } 912 } 913 if (qm->fun_type == QM_HW_PF) { 914 hpre_cnt_regs_clear(qm); 915 qm->debug.curr_qm_qp_num = 0; 916 } 917 918 hpre_debugfs_exit(hpre); 919 hisi_qm_stop(qm); 920 hisi_qm_dev_err_uninit(qm); 921 hisi_qm_uninit(qm); 922 } 923 924 925 static const struct pci_error_handlers hpre_err_handler = { 926 .error_detected = hisi_qm_dev_err_detected, 927 }; 928 929 static struct pci_driver hpre_pci_driver = { 930 .name = hpre_name, 931 .id_table = hpre_dev_ids, 932 .probe = hpre_probe, 933 .remove = hpre_remove, 934 .sriov_configure = hpre_sriov_configure, 935 .err_handler = &hpre_err_handler, 936 }; 937 938 static void hpre_register_debugfs(void) 939 { 940 if (!debugfs_initialized()) 941 return; 942 943 hpre_debugfs_root = debugfs_create_dir(hpre_name, NULL); 944 } 945 946 static void hpre_unregister_debugfs(void) 947 { 948 debugfs_remove_recursive(hpre_debugfs_root); 949 } 950 951 static int __init hpre_init(void) 952 { 953 int ret; 954 955 hisi_qm_init_list(&hpre_devices); 956 hpre_register_debugfs(); 957 958 ret = pci_register_driver(&hpre_pci_driver); 959 if (ret) { 960 hpre_unregister_debugfs(); 961 pr_err("hpre: can't register hisi hpre driver.\n"); 962 } 963 964 return ret; 965 } 966 967 static void __exit hpre_exit(void) 968 { 969 pci_unregister_driver(&hpre_pci_driver); 970 hpre_unregister_debugfs(); 971 } 972 973 module_init(hpre_init); 974 module_exit(hpre_exit); 975 976 MODULE_LICENSE("GPL v2"); 977 MODULE_AUTHOR("Zaibo Xu <xuzaibo@huawei.com>"); 978 MODULE_DESCRIPTION("Driver for HiSilicon HPRE accelerator"); 979