1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "global1.h" 36 #include "global2.h" 37 #include "hwtstamp.h" 38 #include "phy.h" 39 #include "port.h" 40 #include "ptp.h" 41 #include "serdes.h" 42 #include "smi.h" 43 44 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 45 { 46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 47 dev_err(chip->dev, "Switch registers lock not held!\n"); 48 dump_stack(); 49 } 50 } 51 52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 53 { 54 int err; 55 56 assert_reg_lock(chip); 57 58 err = mv88e6xxx_smi_read(chip, addr, reg, val); 59 if (err) 60 return err; 61 62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 63 addr, reg, *val); 64 65 return 0; 66 } 67 68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 69 { 70 int err; 71 72 assert_reg_lock(chip); 73 74 err = mv88e6xxx_smi_write(chip, addr, reg, val); 75 if (err) 76 return err; 77 78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 79 addr, reg, val); 80 81 return 0; 82 } 83 84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 85 u16 mask, u16 val) 86 { 87 u16 data; 88 int err; 89 int i; 90 91 /* There's no bus specific operation to wait for a mask */ 92 for (i = 0; i < 16; i++) { 93 err = mv88e6xxx_read(chip, addr, reg, &data); 94 if (err) 95 return err; 96 97 if ((data & mask) == val) 98 return 0; 99 100 usleep_range(1000, 2000); 101 } 102 103 dev_err(chip->dev, "Timeout while waiting for switch\n"); 104 return -ETIMEDOUT; 105 } 106 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 108 int bit, int val) 109 { 110 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 111 val ? BIT(bit) : 0x0000); 112 } 113 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 115 { 116 struct mv88e6xxx_mdio_bus *mdio_bus; 117 118 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 119 list); 120 if (!mdio_bus) 121 return NULL; 122 123 return mdio_bus->bus; 124 } 125 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 127 { 128 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 129 unsigned int n = d->hwirq; 130 131 chip->g1_irq.masked |= (1 << n); 132 } 133 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 135 { 136 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 137 unsigned int n = d->hwirq; 138 139 chip->g1_irq.masked &= ~(1 << n); 140 } 141 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 143 { 144 unsigned int nhandled = 0; 145 unsigned int sub_irq; 146 unsigned int n; 147 u16 reg; 148 u16 ctl1; 149 int err; 150 151 mv88e6xxx_reg_lock(chip); 152 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 153 mv88e6xxx_reg_unlock(chip); 154 155 if (err) 156 goto out; 157 158 do { 159 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 160 if (reg & (1 << n)) { 161 sub_irq = irq_find_mapping(chip->g1_irq.domain, 162 n); 163 handle_nested_irq(sub_irq); 164 ++nhandled; 165 } 166 } 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 170 if (err) 171 goto unlock; 172 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 173 unlock: 174 mv88e6xxx_reg_unlock(chip); 175 if (err) 176 goto out; 177 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 178 } while (reg & ctl1); 179 180 out: 181 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 182 } 183 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 185 { 186 struct mv88e6xxx_chip *chip = dev_id; 187 188 return mv88e6xxx_g1_irq_thread_work(chip); 189 } 190 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 192 { 193 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 194 195 mv88e6xxx_reg_lock(chip); 196 } 197 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 199 { 200 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 201 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 202 u16 reg; 203 int err; 204 205 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 206 if (err) 207 goto out; 208 209 reg &= ~mask; 210 reg |= (~chip->g1_irq.masked & mask); 211 212 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 213 if (err) 214 goto out; 215 216 out: 217 mv88e6xxx_reg_unlock(chip); 218 } 219 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 221 .name = "mv88e6xxx-g1", 222 .irq_mask = mv88e6xxx_g1_irq_mask, 223 .irq_unmask = mv88e6xxx_g1_irq_unmask, 224 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 225 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 226 }; 227 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 229 unsigned int irq, 230 irq_hw_number_t hwirq) 231 { 232 struct mv88e6xxx_chip *chip = d->host_data; 233 234 irq_set_chip_data(irq, d->host_data); 235 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 236 irq_set_noprobe(irq); 237 238 return 0; 239 } 240 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 242 .map = mv88e6xxx_g1_irq_domain_map, 243 .xlate = irq_domain_xlate_twocell, 244 }; 245 246 /* To be called with reg_lock held */ 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 248 { 249 int irq, virq; 250 u16 mask; 251 252 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 253 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 254 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 255 256 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 257 virq = irq_find_mapping(chip->g1_irq.domain, irq); 258 irq_dispose_mapping(virq); 259 } 260 261 irq_domain_remove(chip->g1_irq.domain); 262 } 263 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 265 { 266 /* 267 * free_irq must be called without reg_lock taken because the irq 268 * handler takes this lock, too. 269 */ 270 free_irq(chip->irq, chip); 271 272 mv88e6xxx_reg_lock(chip); 273 mv88e6xxx_g1_irq_free_common(chip); 274 mv88e6xxx_reg_unlock(chip); 275 } 276 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 278 { 279 int err, irq, virq; 280 u16 reg, mask; 281 282 chip->g1_irq.nirqs = chip->info->g1_irqs; 283 chip->g1_irq.domain = irq_domain_add_simple( 284 NULL, chip->g1_irq.nirqs, 0, 285 &mv88e6xxx_g1_irq_domain_ops, chip); 286 if (!chip->g1_irq.domain) 287 return -ENOMEM; 288 289 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 290 irq_create_mapping(chip->g1_irq.domain, irq); 291 292 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 293 chip->g1_irq.masked = ~0; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 296 if (err) 297 goto out_mapping; 298 299 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 300 301 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 302 if (err) 303 goto out_disable; 304 305 /* Reading the interrupt status clears (most of) them */ 306 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 307 if (err) 308 goto out_disable; 309 310 return 0; 311 312 out_disable: 313 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 314 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 315 316 out_mapping: 317 for (irq = 0; irq < 16; irq++) { 318 virq = irq_find_mapping(chip->g1_irq.domain, irq); 319 irq_dispose_mapping(virq); 320 } 321 322 irq_domain_remove(chip->g1_irq.domain); 323 324 return err; 325 } 326 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 328 { 329 static struct lock_class_key lock_key; 330 static struct lock_class_key request_key; 331 int err; 332 333 err = mv88e6xxx_g1_irq_setup_common(chip); 334 if (err) 335 return err; 336 337 /* These lock classes tells lockdep that global 1 irqs are in 338 * a different category than their parent GPIO, so it won't 339 * report false recursion. 340 */ 341 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 342 343 snprintf(chip->irq_name, sizeof(chip->irq_name), 344 "mv88e6xxx-%s", dev_name(chip->dev)); 345 346 mv88e6xxx_reg_unlock(chip); 347 err = request_threaded_irq(chip->irq, NULL, 348 mv88e6xxx_g1_irq_thread_fn, 349 IRQF_ONESHOT | IRQF_SHARED, 350 chip->irq_name, chip); 351 mv88e6xxx_reg_lock(chip); 352 if (err) 353 mv88e6xxx_g1_irq_free_common(chip); 354 355 return err; 356 } 357 358 static void mv88e6xxx_irq_poll(struct kthread_work *work) 359 { 360 struct mv88e6xxx_chip *chip = container_of(work, 361 struct mv88e6xxx_chip, 362 irq_poll_work.work); 363 mv88e6xxx_g1_irq_thread_work(chip); 364 365 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 366 msecs_to_jiffies(100)); 367 } 368 369 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 370 { 371 int err; 372 373 err = mv88e6xxx_g1_irq_setup_common(chip); 374 if (err) 375 return err; 376 377 kthread_init_delayed_work(&chip->irq_poll_work, 378 mv88e6xxx_irq_poll); 379 380 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 381 if (IS_ERR(chip->kworker)) 382 return PTR_ERR(chip->kworker); 383 384 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 385 msecs_to_jiffies(100)); 386 387 return 0; 388 } 389 390 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 391 { 392 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 393 kthread_destroy_worker(chip->kworker); 394 395 mv88e6xxx_reg_lock(chip); 396 mv88e6xxx_g1_irq_free_common(chip); 397 mv88e6xxx_reg_unlock(chip); 398 } 399 400 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 401 int port, phy_interface_t interface) 402 { 403 int err; 404 405 if (chip->info->ops->port_set_rgmii_delay) { 406 err = chip->info->ops->port_set_rgmii_delay(chip, port, 407 interface); 408 if (err && err != -EOPNOTSUPP) 409 return err; 410 } 411 412 if (chip->info->ops->port_set_cmode) { 413 err = chip->info->ops->port_set_cmode(chip, port, 414 interface); 415 if (err && err != -EOPNOTSUPP) 416 return err; 417 } 418 419 return 0; 420 } 421 422 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 423 int link, int speed, int duplex, int pause, 424 phy_interface_t mode) 425 { 426 int err; 427 428 if (!chip->info->ops->port_set_link) 429 return 0; 430 431 /* Port's MAC control must not be changed unless the link is down */ 432 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 433 if (err) 434 return err; 435 436 if (chip->info->ops->port_set_speed_duplex) { 437 err = chip->info->ops->port_set_speed_duplex(chip, port, 438 speed, duplex); 439 if (err && err != -EOPNOTSUPP) 440 goto restore_link; 441 } 442 443 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 444 mode = chip->info->ops->port_max_speed_mode(port); 445 446 if (chip->info->ops->port_set_pause) { 447 err = chip->info->ops->port_set_pause(chip, port, pause); 448 if (err) 449 goto restore_link; 450 } 451 452 err = mv88e6xxx_port_config_interface(chip, port, mode); 453 restore_link: 454 if (chip->info->ops->port_set_link(chip, port, link)) 455 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 456 457 return err; 458 } 459 460 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 461 { 462 struct mv88e6xxx_chip *chip = ds->priv; 463 464 return port < chip->info->num_internal_phys; 465 } 466 467 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 468 { 469 u16 reg; 470 int err; 471 472 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 473 if (err) { 474 dev_err(chip->dev, 475 "p%d: %s: failed to read port status\n", 476 port, __func__); 477 return err; 478 } 479 480 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 481 } 482 483 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 484 struct phylink_link_state *state) 485 { 486 struct mv88e6xxx_chip *chip = ds->priv; 487 u8 lane; 488 int err; 489 490 mv88e6xxx_reg_lock(chip); 491 lane = mv88e6xxx_serdes_get_lane(chip, port); 492 if (lane && chip->info->ops->serdes_pcs_get_state) 493 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 494 state); 495 else 496 err = -EOPNOTSUPP; 497 mv88e6xxx_reg_unlock(chip); 498 499 return err; 500 } 501 502 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 503 unsigned int mode, 504 phy_interface_t interface, 505 const unsigned long *advertise) 506 { 507 const struct mv88e6xxx_ops *ops = chip->info->ops; 508 u8 lane; 509 510 if (ops->serdes_pcs_config) { 511 lane = mv88e6xxx_serdes_get_lane(chip, port); 512 if (lane) 513 return ops->serdes_pcs_config(chip, port, lane, mode, 514 interface, advertise); 515 } 516 517 return 0; 518 } 519 520 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 521 { 522 struct mv88e6xxx_chip *chip = ds->priv; 523 const struct mv88e6xxx_ops *ops; 524 int err = 0; 525 u8 lane; 526 527 ops = chip->info->ops; 528 529 if (ops->serdes_pcs_an_restart) { 530 mv88e6xxx_reg_lock(chip); 531 lane = mv88e6xxx_serdes_get_lane(chip, port); 532 if (lane) 533 err = ops->serdes_pcs_an_restart(chip, port, lane); 534 mv88e6xxx_reg_unlock(chip); 535 536 if (err) 537 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 538 } 539 } 540 541 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 542 unsigned int mode, 543 int speed, int duplex) 544 { 545 const struct mv88e6xxx_ops *ops = chip->info->ops; 546 u8 lane; 547 548 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 549 lane = mv88e6xxx_serdes_get_lane(chip, port); 550 if (lane) 551 return ops->serdes_pcs_link_up(chip, port, lane, 552 speed, duplex); 553 } 554 555 return 0; 556 } 557 558 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 559 unsigned long *mask, 560 struct phylink_link_state *state) 561 { 562 if (!phy_interface_mode_is_8023z(state->interface)) { 563 /* 10M and 100M are only supported in non-802.3z mode */ 564 phylink_set(mask, 10baseT_Half); 565 phylink_set(mask, 10baseT_Full); 566 phylink_set(mask, 100baseT_Half); 567 phylink_set(mask, 100baseT_Full); 568 } 569 } 570 571 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 572 unsigned long *mask, 573 struct phylink_link_state *state) 574 { 575 /* FIXME: if the port is in 1000Base-X mode, then it only supports 576 * 1000M FD speeds. In this case, CMODE will indicate 5. 577 */ 578 phylink_set(mask, 1000baseT_Full); 579 phylink_set(mask, 1000baseX_Full); 580 581 mv88e6065_phylink_validate(chip, port, mask, state); 582 } 583 584 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 585 unsigned long *mask, 586 struct phylink_link_state *state) 587 { 588 if (port >= 5) 589 phylink_set(mask, 2500baseX_Full); 590 591 /* No ethtool bits for 200Mbps */ 592 phylink_set(mask, 1000baseT_Full); 593 phylink_set(mask, 1000baseX_Full); 594 595 mv88e6065_phylink_validate(chip, port, mask, state); 596 } 597 598 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 599 unsigned long *mask, 600 struct phylink_link_state *state) 601 { 602 /* No ethtool bits for 200Mbps */ 603 phylink_set(mask, 1000baseT_Full); 604 phylink_set(mask, 1000baseX_Full); 605 606 mv88e6065_phylink_validate(chip, port, mask, state); 607 } 608 609 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 610 unsigned long *mask, 611 struct phylink_link_state *state) 612 { 613 if (port >= 9) { 614 phylink_set(mask, 2500baseX_Full); 615 phylink_set(mask, 2500baseT_Full); 616 } 617 618 /* No ethtool bits for 200Mbps */ 619 phylink_set(mask, 1000baseT_Full); 620 phylink_set(mask, 1000baseX_Full); 621 622 mv88e6065_phylink_validate(chip, port, mask, state); 623 } 624 625 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 626 unsigned long *mask, 627 struct phylink_link_state *state) 628 { 629 if (port >= 9) { 630 phylink_set(mask, 10000baseT_Full); 631 phylink_set(mask, 10000baseKR_Full); 632 } 633 634 mv88e6390_phylink_validate(chip, port, mask, state); 635 } 636 637 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 638 unsigned long *supported, 639 struct phylink_link_state *state) 640 { 641 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 642 struct mv88e6xxx_chip *chip = ds->priv; 643 644 /* Allow all the expected bits */ 645 phylink_set(mask, Autoneg); 646 phylink_set(mask, Pause); 647 phylink_set_port_modes(mask); 648 649 if (chip->info->ops->phylink_validate) 650 chip->info->ops->phylink_validate(chip, port, mask, state); 651 652 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 653 bitmap_and(state->advertising, state->advertising, mask, 654 __ETHTOOL_LINK_MODE_MASK_NBITS); 655 656 /* We can only operate at 2500BaseX or 1000BaseX. If requested 657 * to advertise both, only report advertising at 2500BaseX. 658 */ 659 phylink_helper_basex_speed(state); 660 } 661 662 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 663 unsigned int mode, 664 const struct phylink_link_state *state) 665 { 666 struct mv88e6xxx_chip *chip = ds->priv; 667 int err; 668 669 /* FIXME: is this the correct test? If we're in fixed mode on an 670 * internal port, why should we process this any different from 671 * PHY mode? On the other hand, the port may be automedia between 672 * an internal PHY and the serdes... 673 */ 674 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 675 return; 676 677 mv88e6xxx_reg_lock(chip); 678 /* FIXME: should we force the link down here - but if we do, how 679 * do we restore the link force/unforce state? The driver layering 680 * gets in the way. 681 */ 682 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 683 if (err && err != -EOPNOTSUPP) 684 goto err_unlock; 685 686 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 687 state->advertising); 688 /* FIXME: we should restart negotiation if something changed - which 689 * is something we get if we convert to using phylinks PCS operations. 690 */ 691 if (err > 0) 692 err = 0; 693 694 err_unlock: 695 mv88e6xxx_reg_unlock(chip); 696 697 if (err && err != -EOPNOTSUPP) 698 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 699 } 700 701 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 702 unsigned int mode, 703 phy_interface_t interface) 704 { 705 struct mv88e6xxx_chip *chip = ds->priv; 706 const struct mv88e6xxx_ops *ops; 707 int err = 0; 708 709 ops = chip->info->ops; 710 711 mv88e6xxx_reg_lock(chip); 712 if (!mv88e6xxx_port_ppu_updates(chip, port) && ops->port_set_link) 713 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN); 714 mv88e6xxx_reg_unlock(chip); 715 716 if (err) 717 dev_err(chip->dev, 718 "p%d: failed to force MAC link down\n", port); 719 } 720 721 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 722 unsigned int mode, phy_interface_t interface, 723 struct phy_device *phydev, 724 int speed, int duplex, 725 bool tx_pause, bool rx_pause) 726 { 727 struct mv88e6xxx_chip *chip = ds->priv; 728 const struct mv88e6xxx_ops *ops; 729 int err = 0; 730 731 ops = chip->info->ops; 732 733 mv88e6xxx_reg_lock(chip); 734 if (!mv88e6xxx_port_ppu_updates(chip, port)) { 735 /* FIXME: for an automedia port, should we force the link 736 * down here - what if the link comes up due to "other" media 737 * while we're bringing the port up, how is the exclusivity 738 * handled in the Marvell hardware? E.g. port 2 on 88E6390 739 * shared between internal PHY and Serdes. 740 */ 741 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 742 duplex); 743 if (err) 744 goto error; 745 746 if (ops->port_set_speed_duplex) { 747 err = ops->port_set_speed_duplex(chip, port, 748 speed, duplex); 749 if (err && err != -EOPNOTSUPP) 750 goto error; 751 } 752 753 if (ops->port_set_link) 754 err = ops->port_set_link(chip, port, LINK_FORCED_UP); 755 } 756 error: 757 mv88e6xxx_reg_unlock(chip); 758 759 if (err && err != -EOPNOTSUPP) 760 dev_err(ds->dev, 761 "p%d: failed to configure MAC link up\n", port); 762 } 763 764 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 765 { 766 if (!chip->info->ops->stats_snapshot) 767 return -EOPNOTSUPP; 768 769 return chip->info->ops->stats_snapshot(chip, port); 770 } 771 772 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 773 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 774 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 775 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 776 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 777 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 778 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 779 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 780 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 781 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 782 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 783 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 784 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 785 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 786 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 787 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 788 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 789 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 790 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 791 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 792 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 793 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 794 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 795 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 796 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 797 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 798 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 799 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 800 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 801 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 802 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 803 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 804 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 805 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 806 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 807 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 808 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 809 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 810 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 811 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 812 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 813 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 814 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 815 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 816 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 817 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 818 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 819 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 820 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 821 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 822 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 823 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 824 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 825 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 826 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 827 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 828 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 829 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 830 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 831 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 832 }; 833 834 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 835 struct mv88e6xxx_hw_stat *s, 836 int port, u16 bank1_select, 837 u16 histogram) 838 { 839 u32 low; 840 u32 high = 0; 841 u16 reg = 0; 842 int err; 843 u64 value; 844 845 switch (s->type) { 846 case STATS_TYPE_PORT: 847 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 848 if (err) 849 return U64_MAX; 850 851 low = reg; 852 if (s->size == 4) { 853 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 854 if (err) 855 return U64_MAX; 856 low |= ((u32)reg) << 16; 857 } 858 break; 859 case STATS_TYPE_BANK1: 860 reg = bank1_select; 861 /* fall through */ 862 case STATS_TYPE_BANK0: 863 reg |= s->reg | histogram; 864 mv88e6xxx_g1_stats_read(chip, reg, &low); 865 if (s->size == 8) 866 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 867 break; 868 default: 869 return U64_MAX; 870 } 871 value = (((u64)high) << 32) | low; 872 return value; 873 } 874 875 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 876 uint8_t *data, int types) 877 { 878 struct mv88e6xxx_hw_stat *stat; 879 int i, j; 880 881 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 882 stat = &mv88e6xxx_hw_stats[i]; 883 if (stat->type & types) { 884 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 885 ETH_GSTRING_LEN); 886 j++; 887 } 888 } 889 890 return j; 891 } 892 893 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 894 uint8_t *data) 895 { 896 return mv88e6xxx_stats_get_strings(chip, data, 897 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 898 } 899 900 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 901 uint8_t *data) 902 { 903 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 904 } 905 906 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 907 uint8_t *data) 908 { 909 return mv88e6xxx_stats_get_strings(chip, data, 910 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 911 } 912 913 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 914 "atu_member_violation", 915 "atu_miss_violation", 916 "atu_full_violation", 917 "vtu_member_violation", 918 "vtu_miss_violation", 919 }; 920 921 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 922 { 923 unsigned int i; 924 925 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 926 strlcpy(data + i * ETH_GSTRING_LEN, 927 mv88e6xxx_atu_vtu_stats_strings[i], 928 ETH_GSTRING_LEN); 929 } 930 931 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 932 u32 stringset, uint8_t *data) 933 { 934 struct mv88e6xxx_chip *chip = ds->priv; 935 int count = 0; 936 937 if (stringset != ETH_SS_STATS) 938 return; 939 940 mv88e6xxx_reg_lock(chip); 941 942 if (chip->info->ops->stats_get_strings) 943 count = chip->info->ops->stats_get_strings(chip, data); 944 945 if (chip->info->ops->serdes_get_strings) { 946 data += count * ETH_GSTRING_LEN; 947 count = chip->info->ops->serdes_get_strings(chip, port, data); 948 } 949 950 data += count * ETH_GSTRING_LEN; 951 mv88e6xxx_atu_vtu_get_strings(data); 952 953 mv88e6xxx_reg_unlock(chip); 954 } 955 956 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 957 int types) 958 { 959 struct mv88e6xxx_hw_stat *stat; 960 int i, j; 961 962 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 963 stat = &mv88e6xxx_hw_stats[i]; 964 if (stat->type & types) 965 j++; 966 } 967 return j; 968 } 969 970 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 971 { 972 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 973 STATS_TYPE_PORT); 974 } 975 976 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 977 { 978 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 979 } 980 981 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 982 { 983 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 984 STATS_TYPE_BANK1); 985 } 986 987 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 988 { 989 struct mv88e6xxx_chip *chip = ds->priv; 990 int serdes_count = 0; 991 int count = 0; 992 993 if (sset != ETH_SS_STATS) 994 return 0; 995 996 mv88e6xxx_reg_lock(chip); 997 if (chip->info->ops->stats_get_sset_count) 998 count = chip->info->ops->stats_get_sset_count(chip); 999 if (count < 0) 1000 goto out; 1001 1002 if (chip->info->ops->serdes_get_sset_count) 1003 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1004 port); 1005 if (serdes_count < 0) { 1006 count = serdes_count; 1007 goto out; 1008 } 1009 count += serdes_count; 1010 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1011 1012 out: 1013 mv88e6xxx_reg_unlock(chip); 1014 1015 return count; 1016 } 1017 1018 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1019 uint64_t *data, int types, 1020 u16 bank1_select, u16 histogram) 1021 { 1022 struct mv88e6xxx_hw_stat *stat; 1023 int i, j; 1024 1025 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1026 stat = &mv88e6xxx_hw_stats[i]; 1027 if (stat->type & types) { 1028 mv88e6xxx_reg_lock(chip); 1029 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1030 bank1_select, 1031 histogram); 1032 mv88e6xxx_reg_unlock(chip); 1033 1034 j++; 1035 } 1036 } 1037 return j; 1038 } 1039 1040 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1041 uint64_t *data) 1042 { 1043 return mv88e6xxx_stats_get_stats(chip, port, data, 1044 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1045 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1046 } 1047 1048 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1049 uint64_t *data) 1050 { 1051 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1052 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1053 } 1054 1055 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1056 uint64_t *data) 1057 { 1058 return mv88e6xxx_stats_get_stats(chip, port, data, 1059 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1060 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1061 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1062 } 1063 1064 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1065 uint64_t *data) 1066 { 1067 return mv88e6xxx_stats_get_stats(chip, port, data, 1068 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1069 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1070 0); 1071 } 1072 1073 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1074 uint64_t *data) 1075 { 1076 *data++ = chip->ports[port].atu_member_violation; 1077 *data++ = chip->ports[port].atu_miss_violation; 1078 *data++ = chip->ports[port].atu_full_violation; 1079 *data++ = chip->ports[port].vtu_member_violation; 1080 *data++ = chip->ports[port].vtu_miss_violation; 1081 } 1082 1083 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1084 uint64_t *data) 1085 { 1086 int count = 0; 1087 1088 if (chip->info->ops->stats_get_stats) 1089 count = chip->info->ops->stats_get_stats(chip, port, data); 1090 1091 mv88e6xxx_reg_lock(chip); 1092 if (chip->info->ops->serdes_get_stats) { 1093 data += count; 1094 count = chip->info->ops->serdes_get_stats(chip, port, data); 1095 } 1096 data += count; 1097 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1098 mv88e6xxx_reg_unlock(chip); 1099 } 1100 1101 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1102 uint64_t *data) 1103 { 1104 struct mv88e6xxx_chip *chip = ds->priv; 1105 int ret; 1106 1107 mv88e6xxx_reg_lock(chip); 1108 1109 ret = mv88e6xxx_stats_snapshot(chip, port); 1110 mv88e6xxx_reg_unlock(chip); 1111 1112 if (ret < 0) 1113 return; 1114 1115 mv88e6xxx_get_stats(chip, port, data); 1116 1117 } 1118 1119 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1120 { 1121 struct mv88e6xxx_chip *chip = ds->priv; 1122 int len; 1123 1124 len = 32 * sizeof(u16); 1125 if (chip->info->ops->serdes_get_regs_len) 1126 len += chip->info->ops->serdes_get_regs_len(chip, port); 1127 1128 return len; 1129 } 1130 1131 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1132 struct ethtool_regs *regs, void *_p) 1133 { 1134 struct mv88e6xxx_chip *chip = ds->priv; 1135 int err; 1136 u16 reg; 1137 u16 *p = _p; 1138 int i; 1139 1140 regs->version = chip->info->prod_num; 1141 1142 memset(p, 0xff, 32 * sizeof(u16)); 1143 1144 mv88e6xxx_reg_lock(chip); 1145 1146 for (i = 0; i < 32; i++) { 1147 1148 err = mv88e6xxx_port_read(chip, port, i, ®); 1149 if (!err) 1150 p[i] = reg; 1151 } 1152 1153 if (chip->info->ops->serdes_get_regs) 1154 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1155 1156 mv88e6xxx_reg_unlock(chip); 1157 } 1158 1159 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1160 struct ethtool_eee *e) 1161 { 1162 /* Nothing to do on the port's MAC */ 1163 return 0; 1164 } 1165 1166 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1167 struct ethtool_eee *e) 1168 { 1169 /* Nothing to do on the port's MAC */ 1170 return 0; 1171 } 1172 1173 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1174 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1175 { 1176 struct dsa_switch *ds = chip->ds; 1177 struct dsa_switch_tree *dst = ds->dst; 1178 struct net_device *br; 1179 struct dsa_port *dp; 1180 bool found = false; 1181 u16 pvlan; 1182 1183 list_for_each_entry(dp, &dst->ports, list) { 1184 if (dp->ds->index == dev && dp->index == port) { 1185 found = true; 1186 break; 1187 } 1188 } 1189 1190 /* Prevent frames from unknown switch or port */ 1191 if (!found) 1192 return 0; 1193 1194 /* Frames from DSA links and CPU ports can egress any local port */ 1195 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1196 return mv88e6xxx_port_mask(chip); 1197 1198 br = dp->bridge_dev; 1199 pvlan = 0; 1200 1201 /* Frames from user ports can egress any local DSA links and CPU ports, 1202 * as well as any local member of their bridge group. 1203 */ 1204 list_for_each_entry(dp, &dst->ports, list) 1205 if (dp->ds == ds && 1206 (dp->type == DSA_PORT_TYPE_CPU || 1207 dp->type == DSA_PORT_TYPE_DSA || 1208 (br && dp->bridge_dev == br))) 1209 pvlan |= BIT(dp->index); 1210 1211 return pvlan; 1212 } 1213 1214 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1215 { 1216 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1217 1218 /* prevent frames from going back out of the port they came in on */ 1219 output_ports &= ~BIT(port); 1220 1221 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1222 } 1223 1224 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1225 u8 state) 1226 { 1227 struct mv88e6xxx_chip *chip = ds->priv; 1228 int err; 1229 1230 mv88e6xxx_reg_lock(chip); 1231 err = mv88e6xxx_port_set_state(chip, port, state); 1232 mv88e6xxx_reg_unlock(chip); 1233 1234 if (err) 1235 dev_err(ds->dev, "p%d: failed to update state\n", port); 1236 } 1237 1238 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1239 { 1240 int err; 1241 1242 if (chip->info->ops->ieee_pri_map) { 1243 err = chip->info->ops->ieee_pri_map(chip); 1244 if (err) 1245 return err; 1246 } 1247 1248 if (chip->info->ops->ip_pri_map) { 1249 err = chip->info->ops->ip_pri_map(chip); 1250 if (err) 1251 return err; 1252 } 1253 1254 return 0; 1255 } 1256 1257 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1258 { 1259 struct dsa_switch *ds = chip->ds; 1260 int target, port; 1261 int err; 1262 1263 if (!chip->info->global2_addr) 1264 return 0; 1265 1266 /* Initialize the routing port to the 32 possible target devices */ 1267 for (target = 0; target < 32; target++) { 1268 port = dsa_routing_port(ds, target); 1269 if (port == ds->num_ports) 1270 port = 0x1f; 1271 1272 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1273 if (err) 1274 return err; 1275 } 1276 1277 if (chip->info->ops->set_cascade_port) { 1278 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1279 err = chip->info->ops->set_cascade_port(chip, port); 1280 if (err) 1281 return err; 1282 } 1283 1284 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1285 if (err) 1286 return err; 1287 1288 return 0; 1289 } 1290 1291 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1292 { 1293 /* Clear all trunk masks and mapping */ 1294 if (chip->info->global2_addr) 1295 return mv88e6xxx_g2_trunk_clear(chip); 1296 1297 return 0; 1298 } 1299 1300 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1301 { 1302 if (chip->info->ops->rmu_disable) 1303 return chip->info->ops->rmu_disable(chip); 1304 1305 return 0; 1306 } 1307 1308 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1309 { 1310 if (chip->info->ops->pot_clear) 1311 return chip->info->ops->pot_clear(chip); 1312 1313 return 0; 1314 } 1315 1316 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1317 { 1318 if (chip->info->ops->mgmt_rsvd2cpu) 1319 return chip->info->ops->mgmt_rsvd2cpu(chip); 1320 1321 return 0; 1322 } 1323 1324 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1325 { 1326 int err; 1327 1328 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1329 if (err) 1330 return err; 1331 1332 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1333 if (err) 1334 return err; 1335 1336 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1337 } 1338 1339 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1340 { 1341 int port; 1342 int err; 1343 1344 if (!chip->info->ops->irl_init_all) 1345 return 0; 1346 1347 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1348 /* Disable ingress rate limiting by resetting all per port 1349 * ingress rate limit resources to their initial state. 1350 */ 1351 err = chip->info->ops->irl_init_all(chip, port); 1352 if (err) 1353 return err; 1354 } 1355 1356 return 0; 1357 } 1358 1359 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1360 { 1361 if (chip->info->ops->set_switch_mac) { 1362 u8 addr[ETH_ALEN]; 1363 1364 eth_random_addr(addr); 1365 1366 return chip->info->ops->set_switch_mac(chip, addr); 1367 } 1368 1369 return 0; 1370 } 1371 1372 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1373 { 1374 u16 pvlan = 0; 1375 1376 if (!mv88e6xxx_has_pvt(chip)) 1377 return 0; 1378 1379 /* Skip the local source device, which uses in-chip port VLAN */ 1380 if (dev != chip->ds->index) 1381 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1382 1383 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1384 } 1385 1386 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1387 { 1388 int dev, port; 1389 int err; 1390 1391 if (!mv88e6xxx_has_pvt(chip)) 1392 return 0; 1393 1394 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1395 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1396 */ 1397 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1398 if (err) 1399 return err; 1400 1401 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1402 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1403 err = mv88e6xxx_pvt_map(chip, dev, port); 1404 if (err) 1405 return err; 1406 } 1407 } 1408 1409 return 0; 1410 } 1411 1412 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1413 { 1414 struct mv88e6xxx_chip *chip = ds->priv; 1415 int err; 1416 1417 mv88e6xxx_reg_lock(chip); 1418 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1419 mv88e6xxx_reg_unlock(chip); 1420 1421 if (err) 1422 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1423 } 1424 1425 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1426 { 1427 if (!chip->info->max_vid) 1428 return 0; 1429 1430 return mv88e6xxx_g1_vtu_flush(chip); 1431 } 1432 1433 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1434 struct mv88e6xxx_vtu_entry *entry) 1435 { 1436 if (!chip->info->ops->vtu_getnext) 1437 return -EOPNOTSUPP; 1438 1439 return chip->info->ops->vtu_getnext(chip, entry); 1440 } 1441 1442 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1443 struct mv88e6xxx_vtu_entry *entry) 1444 { 1445 if (!chip->info->ops->vtu_loadpurge) 1446 return -EOPNOTSUPP; 1447 1448 return chip->info->ops->vtu_loadpurge(chip, entry); 1449 } 1450 1451 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1452 { 1453 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1454 struct mv88e6xxx_vtu_entry vlan; 1455 int i, err; 1456 1457 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1458 1459 /* Set every FID bit used by the (un)bridged ports */ 1460 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1461 err = mv88e6xxx_port_get_fid(chip, i, fid); 1462 if (err) 1463 return err; 1464 1465 set_bit(*fid, fid_bitmap); 1466 } 1467 1468 /* Set every FID bit used by the VLAN entries */ 1469 vlan.vid = chip->info->max_vid; 1470 vlan.valid = false; 1471 1472 do { 1473 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1474 if (err) 1475 return err; 1476 1477 if (!vlan.valid) 1478 break; 1479 1480 set_bit(vlan.fid, fid_bitmap); 1481 } while (vlan.vid < chip->info->max_vid); 1482 1483 /* The reset value 0x000 is used to indicate that multiple address 1484 * databases are not needed. Return the next positive available. 1485 */ 1486 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1487 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1488 return -ENOSPC; 1489 1490 /* Clear the database */ 1491 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1492 } 1493 1494 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash) 1495 { 1496 if (chip->info->ops->atu_get_hash) 1497 return chip->info->ops->atu_get_hash(chip, hash); 1498 1499 return -EOPNOTSUPP; 1500 } 1501 1502 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash) 1503 { 1504 if (chip->info->ops->atu_set_hash) 1505 return chip->info->ops->atu_set_hash(chip, hash); 1506 1507 return -EOPNOTSUPP; 1508 } 1509 1510 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1511 u16 vid_begin, u16 vid_end) 1512 { 1513 struct mv88e6xxx_chip *chip = ds->priv; 1514 struct mv88e6xxx_vtu_entry vlan; 1515 int i, err; 1516 1517 /* DSA and CPU ports have to be members of multiple vlans */ 1518 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1519 return 0; 1520 1521 if (!vid_begin) 1522 return -EOPNOTSUPP; 1523 1524 vlan.vid = vid_begin - 1; 1525 vlan.valid = false; 1526 1527 do { 1528 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1529 if (err) 1530 return err; 1531 1532 if (!vlan.valid) 1533 break; 1534 1535 if (vlan.vid > vid_end) 1536 break; 1537 1538 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1539 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1540 continue; 1541 1542 if (!dsa_to_port(ds, i)->slave) 1543 continue; 1544 1545 if (vlan.member[i] == 1546 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1547 continue; 1548 1549 if (dsa_to_port(ds, i)->bridge_dev == 1550 dsa_to_port(ds, port)->bridge_dev) 1551 break; /* same bridge, check next VLAN */ 1552 1553 if (!dsa_to_port(ds, i)->bridge_dev) 1554 continue; 1555 1556 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1557 port, vlan.vid, i, 1558 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1559 return -EOPNOTSUPP; 1560 } 1561 } while (vlan.vid < vid_end); 1562 1563 return 0; 1564 } 1565 1566 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1567 bool vlan_filtering) 1568 { 1569 struct mv88e6xxx_chip *chip = ds->priv; 1570 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1571 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1572 int err; 1573 1574 if (!chip->info->max_vid) 1575 return -EOPNOTSUPP; 1576 1577 mv88e6xxx_reg_lock(chip); 1578 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1579 mv88e6xxx_reg_unlock(chip); 1580 1581 return err; 1582 } 1583 1584 static int 1585 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1586 const struct switchdev_obj_port_vlan *vlan) 1587 { 1588 struct mv88e6xxx_chip *chip = ds->priv; 1589 int err; 1590 1591 if (!chip->info->max_vid) 1592 return -EOPNOTSUPP; 1593 1594 /* If the requested port doesn't belong to the same bridge as the VLAN 1595 * members, do not support it (yet) and fallback to software VLAN. 1596 */ 1597 mv88e6xxx_reg_lock(chip); 1598 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1599 vlan->vid_end); 1600 mv88e6xxx_reg_unlock(chip); 1601 1602 /* We don't need any dynamic resource from the kernel (yet), 1603 * so skip the prepare phase. 1604 */ 1605 return err; 1606 } 1607 1608 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1609 const unsigned char *addr, u16 vid, 1610 u8 state) 1611 { 1612 struct mv88e6xxx_atu_entry entry; 1613 struct mv88e6xxx_vtu_entry vlan; 1614 u16 fid; 1615 int err; 1616 1617 /* Null VLAN ID corresponds to the port private database */ 1618 if (vid == 0) { 1619 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1620 if (err) 1621 return err; 1622 } else { 1623 vlan.vid = vid - 1; 1624 vlan.valid = false; 1625 1626 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1627 if (err) 1628 return err; 1629 1630 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1631 if (vlan.vid != vid || !vlan.valid) 1632 return -EOPNOTSUPP; 1633 1634 fid = vlan.fid; 1635 } 1636 1637 entry.state = 0; 1638 ether_addr_copy(entry.mac, addr); 1639 eth_addr_dec(entry.mac); 1640 1641 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1642 if (err) 1643 return err; 1644 1645 /* Initialize a fresh ATU entry if it isn't found */ 1646 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1647 memset(&entry, 0, sizeof(entry)); 1648 ether_addr_copy(entry.mac, addr); 1649 } 1650 1651 /* Purge the ATU entry only if no port is using it anymore */ 1652 if (!state) { 1653 entry.portvec &= ~BIT(port); 1654 if (!entry.portvec) 1655 entry.state = 0; 1656 } else { 1657 entry.portvec |= BIT(port); 1658 entry.state = state; 1659 } 1660 1661 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1662 } 1663 1664 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1665 const struct mv88e6xxx_policy *policy) 1666 { 1667 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1668 enum mv88e6xxx_policy_action action = policy->action; 1669 const u8 *addr = policy->addr; 1670 u16 vid = policy->vid; 1671 u8 state; 1672 int err; 1673 int id; 1674 1675 if (!chip->info->ops->port_set_policy) 1676 return -EOPNOTSUPP; 1677 1678 switch (mapping) { 1679 case MV88E6XXX_POLICY_MAPPING_DA: 1680 case MV88E6XXX_POLICY_MAPPING_SA: 1681 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1682 state = 0; /* Dissociate the port and address */ 1683 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1684 is_multicast_ether_addr(addr)) 1685 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1686 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1687 is_unicast_ether_addr(addr)) 1688 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1689 else 1690 return -EOPNOTSUPP; 1691 1692 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1693 state); 1694 if (err) 1695 return err; 1696 break; 1697 default: 1698 return -EOPNOTSUPP; 1699 } 1700 1701 /* Skip the port's policy clearing if the mapping is still in use */ 1702 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1703 idr_for_each_entry(&chip->policies, policy, id) 1704 if (policy->port == port && 1705 policy->mapping == mapping && 1706 policy->action != action) 1707 return 0; 1708 1709 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1710 } 1711 1712 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1713 struct ethtool_rx_flow_spec *fs) 1714 { 1715 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1716 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1717 enum mv88e6xxx_policy_mapping mapping; 1718 enum mv88e6xxx_policy_action action; 1719 struct mv88e6xxx_policy *policy; 1720 u16 vid = 0; 1721 u8 *addr; 1722 int err; 1723 int id; 1724 1725 if (fs->location != RX_CLS_LOC_ANY) 1726 return -EINVAL; 1727 1728 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1729 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1730 else 1731 return -EOPNOTSUPP; 1732 1733 switch (fs->flow_type & ~FLOW_EXT) { 1734 case ETHER_FLOW: 1735 if (!is_zero_ether_addr(mac_mask->h_dest) && 1736 is_zero_ether_addr(mac_mask->h_source)) { 1737 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1738 addr = mac_entry->h_dest; 1739 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1740 !is_zero_ether_addr(mac_mask->h_source)) { 1741 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1742 addr = mac_entry->h_source; 1743 } else { 1744 /* Cannot support DA and SA mapping in the same rule */ 1745 return -EOPNOTSUPP; 1746 } 1747 break; 1748 default: 1749 return -EOPNOTSUPP; 1750 } 1751 1752 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1753 if (fs->m_ext.vlan_tci != 0xffff) 1754 return -EOPNOTSUPP; 1755 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1756 } 1757 1758 idr_for_each_entry(&chip->policies, policy, id) { 1759 if (policy->port == port && policy->mapping == mapping && 1760 policy->action == action && policy->vid == vid && 1761 ether_addr_equal(policy->addr, addr)) 1762 return -EEXIST; 1763 } 1764 1765 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1766 if (!policy) 1767 return -ENOMEM; 1768 1769 fs->location = 0; 1770 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1771 GFP_KERNEL); 1772 if (err) { 1773 devm_kfree(chip->dev, policy); 1774 return err; 1775 } 1776 1777 memcpy(&policy->fs, fs, sizeof(*fs)); 1778 ether_addr_copy(policy->addr, addr); 1779 policy->mapping = mapping; 1780 policy->action = action; 1781 policy->port = port; 1782 policy->vid = vid; 1783 1784 err = mv88e6xxx_policy_apply(chip, port, policy); 1785 if (err) { 1786 idr_remove(&chip->policies, fs->location); 1787 devm_kfree(chip->dev, policy); 1788 return err; 1789 } 1790 1791 return 0; 1792 } 1793 1794 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1795 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1796 { 1797 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1798 struct mv88e6xxx_chip *chip = ds->priv; 1799 struct mv88e6xxx_policy *policy; 1800 int err; 1801 int id; 1802 1803 mv88e6xxx_reg_lock(chip); 1804 1805 switch (rxnfc->cmd) { 1806 case ETHTOOL_GRXCLSRLCNT: 1807 rxnfc->data = 0; 1808 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1809 rxnfc->rule_cnt = 0; 1810 idr_for_each_entry(&chip->policies, policy, id) 1811 if (policy->port == port) 1812 rxnfc->rule_cnt++; 1813 err = 0; 1814 break; 1815 case ETHTOOL_GRXCLSRULE: 1816 err = -ENOENT; 1817 policy = idr_find(&chip->policies, fs->location); 1818 if (policy) { 1819 memcpy(fs, &policy->fs, sizeof(*fs)); 1820 err = 0; 1821 } 1822 break; 1823 case ETHTOOL_GRXCLSRLALL: 1824 rxnfc->data = 0; 1825 rxnfc->rule_cnt = 0; 1826 idr_for_each_entry(&chip->policies, policy, id) 1827 if (policy->port == port) 1828 rule_locs[rxnfc->rule_cnt++] = id; 1829 err = 0; 1830 break; 1831 default: 1832 err = -EOPNOTSUPP; 1833 break; 1834 } 1835 1836 mv88e6xxx_reg_unlock(chip); 1837 1838 return err; 1839 } 1840 1841 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1842 struct ethtool_rxnfc *rxnfc) 1843 { 1844 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1845 struct mv88e6xxx_chip *chip = ds->priv; 1846 struct mv88e6xxx_policy *policy; 1847 int err; 1848 1849 mv88e6xxx_reg_lock(chip); 1850 1851 switch (rxnfc->cmd) { 1852 case ETHTOOL_SRXCLSRLINS: 1853 err = mv88e6xxx_policy_insert(chip, port, fs); 1854 break; 1855 case ETHTOOL_SRXCLSRLDEL: 1856 err = -ENOENT; 1857 policy = idr_remove(&chip->policies, fs->location); 1858 if (policy) { 1859 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1860 err = mv88e6xxx_policy_apply(chip, port, policy); 1861 devm_kfree(chip->dev, policy); 1862 } 1863 break; 1864 default: 1865 err = -EOPNOTSUPP; 1866 break; 1867 } 1868 1869 mv88e6xxx_reg_unlock(chip); 1870 1871 return err; 1872 } 1873 1874 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1875 u16 vid) 1876 { 1877 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1878 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1879 1880 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1881 } 1882 1883 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1884 { 1885 int port; 1886 int err; 1887 1888 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1889 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1890 if (err) 1891 return err; 1892 } 1893 1894 return 0; 1895 } 1896 1897 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1898 u16 vid, u8 member, bool warn) 1899 { 1900 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1901 struct mv88e6xxx_vtu_entry vlan; 1902 int i, err; 1903 1904 if (!vid) 1905 return -EOPNOTSUPP; 1906 1907 vlan.vid = vid - 1; 1908 vlan.valid = false; 1909 1910 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1911 if (err) 1912 return err; 1913 1914 if (vlan.vid != vid || !vlan.valid) { 1915 memset(&vlan, 0, sizeof(vlan)); 1916 1917 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1918 if (err) 1919 return err; 1920 1921 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1922 if (i == port) 1923 vlan.member[i] = member; 1924 else 1925 vlan.member[i] = non_member; 1926 1927 vlan.vid = vid; 1928 vlan.valid = true; 1929 1930 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1931 if (err) 1932 return err; 1933 1934 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1935 if (err) 1936 return err; 1937 } else if (vlan.member[port] != member) { 1938 vlan.member[port] = member; 1939 1940 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1941 if (err) 1942 return err; 1943 } else if (warn) { 1944 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1945 port, vid); 1946 } 1947 1948 return 0; 1949 } 1950 1951 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1952 const struct switchdev_obj_port_vlan *vlan) 1953 { 1954 struct mv88e6xxx_chip *chip = ds->priv; 1955 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1956 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1957 bool warn; 1958 u8 member; 1959 u16 vid; 1960 1961 if (!chip->info->max_vid) 1962 return; 1963 1964 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1965 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1966 else if (untagged) 1967 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1968 else 1969 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1970 1971 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 1972 * and then the CPU port. Do not warn for duplicates for the CPU port. 1973 */ 1974 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 1975 1976 mv88e6xxx_reg_lock(chip); 1977 1978 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1979 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn)) 1980 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1981 vid, untagged ? 'u' : 't'); 1982 1983 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1984 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1985 vlan->vid_end); 1986 1987 mv88e6xxx_reg_unlock(chip); 1988 } 1989 1990 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 1991 int port, u16 vid) 1992 { 1993 struct mv88e6xxx_vtu_entry vlan; 1994 int i, err; 1995 1996 if (!vid) 1997 return -EOPNOTSUPP; 1998 1999 vlan.vid = vid - 1; 2000 vlan.valid = false; 2001 2002 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2003 if (err) 2004 return err; 2005 2006 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2007 * tell switchdev that this VLAN is likely handled in software. 2008 */ 2009 if (vlan.vid != vid || !vlan.valid || 2010 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2011 return -EOPNOTSUPP; 2012 2013 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2014 2015 /* keep the VLAN unless all ports are excluded */ 2016 vlan.valid = false; 2017 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2018 if (vlan.member[i] != 2019 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2020 vlan.valid = true; 2021 break; 2022 } 2023 } 2024 2025 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2026 if (err) 2027 return err; 2028 2029 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2030 } 2031 2032 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2033 const struct switchdev_obj_port_vlan *vlan) 2034 { 2035 struct mv88e6xxx_chip *chip = ds->priv; 2036 u16 pvid, vid; 2037 int err = 0; 2038 2039 if (!chip->info->max_vid) 2040 return -EOPNOTSUPP; 2041 2042 mv88e6xxx_reg_lock(chip); 2043 2044 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2045 if (err) 2046 goto unlock; 2047 2048 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 2049 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 2050 if (err) 2051 goto unlock; 2052 2053 if (vid == pvid) { 2054 err = mv88e6xxx_port_set_pvid(chip, port, 0); 2055 if (err) 2056 goto unlock; 2057 } 2058 } 2059 2060 unlock: 2061 mv88e6xxx_reg_unlock(chip); 2062 2063 return err; 2064 } 2065 2066 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2067 const unsigned char *addr, u16 vid) 2068 { 2069 struct mv88e6xxx_chip *chip = ds->priv; 2070 int err; 2071 2072 mv88e6xxx_reg_lock(chip); 2073 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2074 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2075 mv88e6xxx_reg_unlock(chip); 2076 2077 return err; 2078 } 2079 2080 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2081 const unsigned char *addr, u16 vid) 2082 { 2083 struct mv88e6xxx_chip *chip = ds->priv; 2084 int err; 2085 2086 mv88e6xxx_reg_lock(chip); 2087 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2088 mv88e6xxx_reg_unlock(chip); 2089 2090 return err; 2091 } 2092 2093 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2094 u16 fid, u16 vid, int port, 2095 dsa_fdb_dump_cb_t *cb, void *data) 2096 { 2097 struct mv88e6xxx_atu_entry addr; 2098 bool is_static; 2099 int err; 2100 2101 addr.state = 0; 2102 eth_broadcast_addr(addr.mac); 2103 2104 do { 2105 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2106 if (err) 2107 return err; 2108 2109 if (!addr.state) 2110 break; 2111 2112 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2113 continue; 2114 2115 if (!is_unicast_ether_addr(addr.mac)) 2116 continue; 2117 2118 is_static = (addr.state == 2119 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2120 err = cb(addr.mac, vid, is_static, data); 2121 if (err) 2122 return err; 2123 } while (!is_broadcast_ether_addr(addr.mac)); 2124 2125 return err; 2126 } 2127 2128 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2129 dsa_fdb_dump_cb_t *cb, void *data) 2130 { 2131 struct mv88e6xxx_vtu_entry vlan; 2132 u16 fid; 2133 int err; 2134 2135 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2136 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2137 if (err) 2138 return err; 2139 2140 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2141 if (err) 2142 return err; 2143 2144 /* Dump VLANs' Filtering Information Databases */ 2145 vlan.vid = chip->info->max_vid; 2146 vlan.valid = false; 2147 2148 do { 2149 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2150 if (err) 2151 return err; 2152 2153 if (!vlan.valid) 2154 break; 2155 2156 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2157 cb, data); 2158 if (err) 2159 return err; 2160 } while (vlan.vid < chip->info->max_vid); 2161 2162 return err; 2163 } 2164 2165 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2166 dsa_fdb_dump_cb_t *cb, void *data) 2167 { 2168 struct mv88e6xxx_chip *chip = ds->priv; 2169 int err; 2170 2171 mv88e6xxx_reg_lock(chip); 2172 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2173 mv88e6xxx_reg_unlock(chip); 2174 2175 return err; 2176 } 2177 2178 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2179 struct net_device *br) 2180 { 2181 struct dsa_switch *ds = chip->ds; 2182 struct dsa_switch_tree *dst = ds->dst; 2183 struct dsa_port *dp; 2184 int err; 2185 2186 list_for_each_entry(dp, &dst->ports, list) { 2187 if (dp->bridge_dev == br) { 2188 if (dp->ds == ds) { 2189 /* This is a local bridge group member, 2190 * remap its Port VLAN Map. 2191 */ 2192 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2193 if (err) 2194 return err; 2195 } else { 2196 /* This is an external bridge group member, 2197 * remap its cross-chip Port VLAN Table entry. 2198 */ 2199 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2200 dp->index); 2201 if (err) 2202 return err; 2203 } 2204 } 2205 } 2206 2207 return 0; 2208 } 2209 2210 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2211 struct net_device *br) 2212 { 2213 struct mv88e6xxx_chip *chip = ds->priv; 2214 int err; 2215 2216 mv88e6xxx_reg_lock(chip); 2217 err = mv88e6xxx_bridge_map(chip, br); 2218 mv88e6xxx_reg_unlock(chip); 2219 2220 return err; 2221 } 2222 2223 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2224 struct net_device *br) 2225 { 2226 struct mv88e6xxx_chip *chip = ds->priv; 2227 2228 mv88e6xxx_reg_lock(chip); 2229 if (mv88e6xxx_bridge_map(chip, br) || 2230 mv88e6xxx_port_vlan_map(chip, port)) 2231 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2232 mv88e6xxx_reg_unlock(chip); 2233 } 2234 2235 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 2236 int port, struct net_device *br) 2237 { 2238 struct mv88e6xxx_chip *chip = ds->priv; 2239 int err; 2240 2241 mv88e6xxx_reg_lock(chip); 2242 err = mv88e6xxx_pvt_map(chip, dev, port); 2243 mv88e6xxx_reg_unlock(chip); 2244 2245 return err; 2246 } 2247 2248 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 2249 int port, struct net_device *br) 2250 { 2251 struct mv88e6xxx_chip *chip = ds->priv; 2252 2253 mv88e6xxx_reg_lock(chip); 2254 if (mv88e6xxx_pvt_map(chip, dev, port)) 2255 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2256 mv88e6xxx_reg_unlock(chip); 2257 } 2258 2259 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2260 { 2261 if (chip->info->ops->reset) 2262 return chip->info->ops->reset(chip); 2263 2264 return 0; 2265 } 2266 2267 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2268 { 2269 struct gpio_desc *gpiod = chip->reset; 2270 2271 /* If there is a GPIO connected to the reset pin, toggle it */ 2272 if (gpiod) { 2273 gpiod_set_value_cansleep(gpiod, 1); 2274 usleep_range(10000, 20000); 2275 gpiod_set_value_cansleep(gpiod, 0); 2276 usleep_range(10000, 20000); 2277 } 2278 } 2279 2280 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2281 { 2282 int i, err; 2283 2284 /* Set all ports to the Disabled state */ 2285 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2286 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2287 if (err) 2288 return err; 2289 } 2290 2291 /* Wait for transmit queues to drain, 2292 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2293 */ 2294 usleep_range(2000, 4000); 2295 2296 return 0; 2297 } 2298 2299 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2300 { 2301 int err; 2302 2303 err = mv88e6xxx_disable_ports(chip); 2304 if (err) 2305 return err; 2306 2307 mv88e6xxx_hardware_reset(chip); 2308 2309 return mv88e6xxx_software_reset(chip); 2310 } 2311 2312 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2313 enum mv88e6xxx_frame_mode frame, 2314 enum mv88e6xxx_egress_mode egress, u16 etype) 2315 { 2316 int err; 2317 2318 if (!chip->info->ops->port_set_frame_mode) 2319 return -EOPNOTSUPP; 2320 2321 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2322 if (err) 2323 return err; 2324 2325 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2326 if (err) 2327 return err; 2328 2329 if (chip->info->ops->port_set_ether_type) 2330 return chip->info->ops->port_set_ether_type(chip, port, etype); 2331 2332 return 0; 2333 } 2334 2335 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2336 { 2337 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2338 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2339 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2340 } 2341 2342 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2343 { 2344 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2345 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2346 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2347 } 2348 2349 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2350 { 2351 return mv88e6xxx_set_port_mode(chip, port, 2352 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2353 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2354 ETH_P_EDSA); 2355 } 2356 2357 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2358 { 2359 if (dsa_is_dsa_port(chip->ds, port)) 2360 return mv88e6xxx_set_port_mode_dsa(chip, port); 2361 2362 if (dsa_is_user_port(chip->ds, port)) 2363 return mv88e6xxx_set_port_mode_normal(chip, port); 2364 2365 /* Setup CPU port mode depending on its supported tag format */ 2366 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2367 return mv88e6xxx_set_port_mode_dsa(chip, port); 2368 2369 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2370 return mv88e6xxx_set_port_mode_edsa(chip, port); 2371 2372 return -EINVAL; 2373 } 2374 2375 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2376 { 2377 bool message = dsa_is_dsa_port(chip->ds, port); 2378 2379 return mv88e6xxx_port_set_message_port(chip, port, message); 2380 } 2381 2382 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2383 { 2384 struct dsa_switch *ds = chip->ds; 2385 bool flood; 2386 2387 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2388 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2389 if (chip->info->ops->port_set_egress_floods) 2390 return chip->info->ops->port_set_egress_floods(chip, port, 2391 flood, flood); 2392 2393 return 0; 2394 } 2395 2396 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2397 { 2398 struct mv88e6xxx_port *mvp = dev_id; 2399 struct mv88e6xxx_chip *chip = mvp->chip; 2400 irqreturn_t ret = IRQ_NONE; 2401 int port = mvp->port; 2402 u8 lane; 2403 2404 mv88e6xxx_reg_lock(chip); 2405 lane = mv88e6xxx_serdes_get_lane(chip, port); 2406 if (lane) 2407 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2408 mv88e6xxx_reg_unlock(chip); 2409 2410 return ret; 2411 } 2412 2413 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2414 u8 lane) 2415 { 2416 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2417 unsigned int irq; 2418 int err; 2419 2420 /* Nothing to request if this SERDES port has no IRQ */ 2421 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2422 if (!irq) 2423 return 0; 2424 2425 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2426 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2427 2428 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2429 mv88e6xxx_reg_unlock(chip); 2430 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2431 IRQF_ONESHOT, dev_id->serdes_irq_name, 2432 dev_id); 2433 mv88e6xxx_reg_lock(chip); 2434 if (err) 2435 return err; 2436 2437 dev_id->serdes_irq = irq; 2438 2439 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2440 } 2441 2442 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2443 u8 lane) 2444 { 2445 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2446 unsigned int irq = dev_id->serdes_irq; 2447 int err; 2448 2449 /* Nothing to free if no IRQ has been requested */ 2450 if (!irq) 2451 return 0; 2452 2453 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2454 2455 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2456 mv88e6xxx_reg_unlock(chip); 2457 free_irq(irq, dev_id); 2458 mv88e6xxx_reg_lock(chip); 2459 2460 dev_id->serdes_irq = 0; 2461 2462 return err; 2463 } 2464 2465 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2466 bool on) 2467 { 2468 u8 lane; 2469 int err; 2470 2471 lane = mv88e6xxx_serdes_get_lane(chip, port); 2472 if (!lane) 2473 return 0; 2474 2475 if (on) { 2476 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2477 if (err) 2478 return err; 2479 2480 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2481 } else { 2482 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2483 if (err) 2484 return err; 2485 2486 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2487 } 2488 2489 return err; 2490 } 2491 2492 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2493 { 2494 struct dsa_switch *ds = chip->ds; 2495 int upstream_port; 2496 int err; 2497 2498 upstream_port = dsa_upstream_port(ds, port); 2499 if (chip->info->ops->port_set_upstream_port) { 2500 err = chip->info->ops->port_set_upstream_port(chip, port, 2501 upstream_port); 2502 if (err) 2503 return err; 2504 } 2505 2506 if (port == upstream_port) { 2507 if (chip->info->ops->set_cpu_port) { 2508 err = chip->info->ops->set_cpu_port(chip, 2509 upstream_port); 2510 if (err) 2511 return err; 2512 } 2513 2514 if (chip->info->ops->set_egress_port) { 2515 err = chip->info->ops->set_egress_port(chip, 2516 MV88E6XXX_EGRESS_DIR_INGRESS, 2517 upstream_port); 2518 if (err) 2519 return err; 2520 2521 err = chip->info->ops->set_egress_port(chip, 2522 MV88E6XXX_EGRESS_DIR_EGRESS, 2523 upstream_port); 2524 if (err) 2525 return err; 2526 } 2527 } 2528 2529 return 0; 2530 } 2531 2532 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2533 { 2534 struct dsa_switch *ds = chip->ds; 2535 int err; 2536 u16 reg; 2537 2538 chip->ports[port].chip = chip; 2539 chip->ports[port].port = port; 2540 2541 /* MAC Forcing register: don't force link, speed, duplex or flow control 2542 * state to any particular values on physical ports, but force the CPU 2543 * port and all DSA ports to their maximum bandwidth and full duplex. 2544 */ 2545 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2546 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2547 SPEED_MAX, DUPLEX_FULL, 2548 PAUSE_OFF, 2549 PHY_INTERFACE_MODE_NA); 2550 else 2551 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2552 SPEED_UNFORCED, DUPLEX_UNFORCED, 2553 PAUSE_ON, 2554 PHY_INTERFACE_MODE_NA); 2555 if (err) 2556 return err; 2557 2558 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2559 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2560 * tunneling, determine priority by looking at 802.1p and IP 2561 * priority fields (IP prio has precedence), and set STP state 2562 * to Forwarding. 2563 * 2564 * If this is the CPU link, use DSA or EDSA tagging depending 2565 * on which tagging mode was configured. 2566 * 2567 * If this is a link to another switch, use DSA tagging mode. 2568 * 2569 * If this is the upstream port for this switch, enable 2570 * forwarding of unknown unicasts and multicasts. 2571 */ 2572 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2573 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2574 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2575 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2576 if (err) 2577 return err; 2578 2579 err = mv88e6xxx_setup_port_mode(chip, port); 2580 if (err) 2581 return err; 2582 2583 err = mv88e6xxx_setup_egress_floods(chip, port); 2584 if (err) 2585 return err; 2586 2587 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2588 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2589 * untagged frames on this port, do a destination address lookup on all 2590 * received packets as usual, disable ARP mirroring and don't send a 2591 * copy of all transmitted/received frames on this port to the CPU. 2592 */ 2593 err = mv88e6xxx_port_set_map_da(chip, port); 2594 if (err) 2595 return err; 2596 2597 err = mv88e6xxx_setup_upstream_port(chip, port); 2598 if (err) 2599 return err; 2600 2601 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2602 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2603 if (err) 2604 return err; 2605 2606 if (chip->info->ops->port_set_jumbo_size) { 2607 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2608 if (err) 2609 return err; 2610 } 2611 2612 /* Port Association Vector: when learning source addresses 2613 * of packets, add the address to the address database using 2614 * a port bitmap that has only the bit for this port set and 2615 * the other bits clear. 2616 */ 2617 reg = 1 << port; 2618 /* Disable learning for CPU port */ 2619 if (dsa_is_cpu_port(ds, port)) 2620 reg = 0; 2621 2622 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2623 reg); 2624 if (err) 2625 return err; 2626 2627 /* Egress rate control 2: disable egress rate control. */ 2628 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2629 0x0000); 2630 if (err) 2631 return err; 2632 2633 if (chip->info->ops->port_pause_limit) { 2634 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2635 if (err) 2636 return err; 2637 } 2638 2639 if (chip->info->ops->port_disable_learn_limit) { 2640 err = chip->info->ops->port_disable_learn_limit(chip, port); 2641 if (err) 2642 return err; 2643 } 2644 2645 if (chip->info->ops->port_disable_pri_override) { 2646 err = chip->info->ops->port_disable_pri_override(chip, port); 2647 if (err) 2648 return err; 2649 } 2650 2651 if (chip->info->ops->port_tag_remap) { 2652 err = chip->info->ops->port_tag_remap(chip, port); 2653 if (err) 2654 return err; 2655 } 2656 2657 if (chip->info->ops->port_egress_rate_limiting) { 2658 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2659 if (err) 2660 return err; 2661 } 2662 2663 if (chip->info->ops->port_setup_message_port) { 2664 err = chip->info->ops->port_setup_message_port(chip, port); 2665 if (err) 2666 return err; 2667 } 2668 2669 /* Port based VLAN map: give each port the same default address 2670 * database, and allow bidirectional communication between the 2671 * CPU and DSA port(s), and the other ports. 2672 */ 2673 err = mv88e6xxx_port_set_fid(chip, port, 0); 2674 if (err) 2675 return err; 2676 2677 err = mv88e6xxx_port_vlan_map(chip, port); 2678 if (err) 2679 return err; 2680 2681 /* Default VLAN ID and priority: don't set a default VLAN 2682 * ID, and set the default packet priority to zero. 2683 */ 2684 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2685 } 2686 2687 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2688 struct phy_device *phydev) 2689 { 2690 struct mv88e6xxx_chip *chip = ds->priv; 2691 int err; 2692 2693 mv88e6xxx_reg_lock(chip); 2694 err = mv88e6xxx_serdes_power(chip, port, true); 2695 mv88e6xxx_reg_unlock(chip); 2696 2697 return err; 2698 } 2699 2700 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2701 { 2702 struct mv88e6xxx_chip *chip = ds->priv; 2703 2704 mv88e6xxx_reg_lock(chip); 2705 if (mv88e6xxx_serdes_power(chip, port, false)) 2706 dev_err(chip->dev, "failed to power off SERDES\n"); 2707 mv88e6xxx_reg_unlock(chip); 2708 } 2709 2710 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2711 unsigned int ageing_time) 2712 { 2713 struct mv88e6xxx_chip *chip = ds->priv; 2714 int err; 2715 2716 mv88e6xxx_reg_lock(chip); 2717 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2718 mv88e6xxx_reg_unlock(chip); 2719 2720 return err; 2721 } 2722 2723 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2724 { 2725 int err; 2726 2727 /* Initialize the statistics unit */ 2728 if (chip->info->ops->stats_set_histogram) { 2729 err = chip->info->ops->stats_set_histogram(chip); 2730 if (err) 2731 return err; 2732 } 2733 2734 return mv88e6xxx_g1_stats_clear(chip); 2735 } 2736 2737 /* Check if the errata has already been applied. */ 2738 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2739 { 2740 int port; 2741 int err; 2742 u16 val; 2743 2744 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2745 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2746 if (err) { 2747 dev_err(chip->dev, 2748 "Error reading hidden register: %d\n", err); 2749 return false; 2750 } 2751 if (val != 0x01c0) 2752 return false; 2753 } 2754 2755 return true; 2756 } 2757 2758 /* The 6390 copper ports have an errata which require poking magic 2759 * values into undocumented hidden registers and then performing a 2760 * software reset. 2761 */ 2762 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2763 { 2764 int port; 2765 int err; 2766 2767 if (mv88e6390_setup_errata_applied(chip)) 2768 return 0; 2769 2770 /* Set the ports into blocking mode */ 2771 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2772 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2773 if (err) 2774 return err; 2775 } 2776 2777 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2778 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2779 if (err) 2780 return err; 2781 } 2782 2783 return mv88e6xxx_software_reset(chip); 2784 } 2785 2786 enum mv88e6xxx_devlink_param_id { 2787 MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 2788 MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2789 }; 2790 2791 static int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id, 2792 struct devlink_param_gset_ctx *ctx) 2793 { 2794 struct mv88e6xxx_chip *chip = ds->priv; 2795 int err; 2796 2797 mv88e6xxx_reg_lock(chip); 2798 2799 switch (id) { 2800 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2801 err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8); 2802 break; 2803 default: 2804 err = -EOPNOTSUPP; 2805 break; 2806 } 2807 2808 mv88e6xxx_reg_unlock(chip); 2809 2810 return err; 2811 } 2812 2813 static int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id, 2814 struct devlink_param_gset_ctx *ctx) 2815 { 2816 struct mv88e6xxx_chip *chip = ds->priv; 2817 int err; 2818 2819 mv88e6xxx_reg_lock(chip); 2820 2821 switch (id) { 2822 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2823 err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8); 2824 break; 2825 default: 2826 err = -EOPNOTSUPP; 2827 break; 2828 } 2829 2830 mv88e6xxx_reg_unlock(chip); 2831 2832 return err; 2833 } 2834 2835 static const struct devlink_param mv88e6xxx_devlink_params[] = { 2836 DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2837 "ATU_hash", DEVLINK_PARAM_TYPE_U8, 2838 BIT(DEVLINK_PARAM_CMODE_RUNTIME)), 2839 }; 2840 2841 static int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds) 2842 { 2843 return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params, 2844 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2845 } 2846 2847 static void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds) 2848 { 2849 dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params, 2850 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2851 } 2852 2853 enum mv88e6xxx_devlink_resource_id { 2854 MV88E6XXX_RESOURCE_ID_ATU, 2855 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2856 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2857 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2858 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2859 }; 2860 2861 static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip, 2862 u16 bin) 2863 { 2864 u16 occupancy = 0; 2865 int err; 2866 2867 mv88e6xxx_reg_lock(chip); 2868 2869 err = mv88e6xxx_g2_atu_stats_set(chip, MV88E6XXX_G2_ATU_STATS_MODE_ALL, 2870 bin); 2871 if (err) { 2872 dev_err(chip->dev, "failed to set ATU stats kind/bin\n"); 2873 goto unlock; 2874 } 2875 2876 err = mv88e6xxx_g1_atu_get_next(chip, 0); 2877 if (err) { 2878 dev_err(chip->dev, "failed to perform ATU get next\n"); 2879 goto unlock; 2880 } 2881 2882 err = mv88e6xxx_g2_atu_stats_get(chip, &occupancy); 2883 if (err) { 2884 dev_err(chip->dev, "failed to get ATU stats\n"); 2885 goto unlock; 2886 } 2887 2888 occupancy &= MV88E6XXX_G2_ATU_STATS_MASK; 2889 2890 unlock: 2891 mv88e6xxx_reg_unlock(chip); 2892 2893 return occupancy; 2894 } 2895 2896 static u64 mv88e6xxx_devlink_atu_bin_0_get(void *priv) 2897 { 2898 struct mv88e6xxx_chip *chip = priv; 2899 2900 return mv88e6xxx_devlink_atu_bin_get(chip, 2901 MV88E6XXX_G2_ATU_STATS_BIN_0); 2902 } 2903 2904 static u64 mv88e6xxx_devlink_atu_bin_1_get(void *priv) 2905 { 2906 struct mv88e6xxx_chip *chip = priv; 2907 2908 return mv88e6xxx_devlink_atu_bin_get(chip, 2909 MV88E6XXX_G2_ATU_STATS_BIN_1); 2910 } 2911 2912 static u64 mv88e6xxx_devlink_atu_bin_2_get(void *priv) 2913 { 2914 struct mv88e6xxx_chip *chip = priv; 2915 2916 return mv88e6xxx_devlink_atu_bin_get(chip, 2917 MV88E6XXX_G2_ATU_STATS_BIN_2); 2918 } 2919 2920 static u64 mv88e6xxx_devlink_atu_bin_3_get(void *priv) 2921 { 2922 struct mv88e6xxx_chip *chip = priv; 2923 2924 return mv88e6xxx_devlink_atu_bin_get(chip, 2925 MV88E6XXX_G2_ATU_STATS_BIN_3); 2926 } 2927 2928 static u64 mv88e6xxx_devlink_atu_get(void *priv) 2929 { 2930 return mv88e6xxx_devlink_atu_bin_0_get(priv) + 2931 mv88e6xxx_devlink_atu_bin_1_get(priv) + 2932 mv88e6xxx_devlink_atu_bin_2_get(priv) + 2933 mv88e6xxx_devlink_atu_bin_3_get(priv); 2934 } 2935 2936 static int mv88e6xxx_setup_devlink_resources(struct dsa_switch *ds) 2937 { 2938 struct devlink_resource_size_params size_params; 2939 struct mv88e6xxx_chip *chip = ds->priv; 2940 int err; 2941 2942 devlink_resource_size_params_init(&size_params, 2943 mv88e6xxx_num_macs(chip), 2944 mv88e6xxx_num_macs(chip), 2945 1, DEVLINK_RESOURCE_UNIT_ENTRY); 2946 2947 err = dsa_devlink_resource_register(ds, "ATU", 2948 mv88e6xxx_num_macs(chip), 2949 MV88E6XXX_RESOURCE_ID_ATU, 2950 DEVLINK_RESOURCE_ID_PARENT_TOP, 2951 &size_params); 2952 if (err) 2953 goto out; 2954 2955 devlink_resource_size_params_init(&size_params, 2956 mv88e6xxx_num_macs(chip) / 4, 2957 mv88e6xxx_num_macs(chip) / 4, 2958 1, DEVLINK_RESOURCE_UNIT_ENTRY); 2959 2960 err = dsa_devlink_resource_register(ds, "ATU_bin_0", 2961 mv88e6xxx_num_macs(chip) / 4, 2962 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2963 MV88E6XXX_RESOURCE_ID_ATU, 2964 &size_params); 2965 if (err) 2966 goto out; 2967 2968 err = dsa_devlink_resource_register(ds, "ATU_bin_1", 2969 mv88e6xxx_num_macs(chip) / 4, 2970 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2971 MV88E6XXX_RESOURCE_ID_ATU, 2972 &size_params); 2973 if (err) 2974 goto out; 2975 2976 err = dsa_devlink_resource_register(ds, "ATU_bin_2", 2977 mv88e6xxx_num_macs(chip) / 4, 2978 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2979 MV88E6XXX_RESOURCE_ID_ATU, 2980 &size_params); 2981 if (err) 2982 goto out; 2983 2984 err = dsa_devlink_resource_register(ds, "ATU_bin_3", 2985 mv88e6xxx_num_macs(chip) / 4, 2986 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2987 MV88E6XXX_RESOURCE_ID_ATU, 2988 &size_params); 2989 if (err) 2990 goto out; 2991 2992 dsa_devlink_resource_occ_get_register(ds, 2993 MV88E6XXX_RESOURCE_ID_ATU, 2994 mv88e6xxx_devlink_atu_get, 2995 chip); 2996 2997 dsa_devlink_resource_occ_get_register(ds, 2998 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2999 mv88e6xxx_devlink_atu_bin_0_get, 3000 chip); 3001 3002 dsa_devlink_resource_occ_get_register(ds, 3003 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 3004 mv88e6xxx_devlink_atu_bin_1_get, 3005 chip); 3006 3007 dsa_devlink_resource_occ_get_register(ds, 3008 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 3009 mv88e6xxx_devlink_atu_bin_2_get, 3010 chip); 3011 3012 dsa_devlink_resource_occ_get_register(ds, 3013 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 3014 mv88e6xxx_devlink_atu_bin_3_get, 3015 chip); 3016 3017 return 0; 3018 3019 out: 3020 dsa_devlink_resources_unregister(ds); 3021 return err; 3022 } 3023 3024 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3025 { 3026 mv88e6xxx_teardown_devlink_params(ds); 3027 dsa_devlink_resources_unregister(ds); 3028 } 3029 3030 static int mv88e6xxx_setup(struct dsa_switch *ds) 3031 { 3032 struct mv88e6xxx_chip *chip = ds->priv; 3033 u8 cmode; 3034 int err; 3035 int i; 3036 3037 chip->ds = ds; 3038 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3039 3040 mv88e6xxx_reg_lock(chip); 3041 3042 if (chip->info->ops->setup_errata) { 3043 err = chip->info->ops->setup_errata(chip); 3044 if (err) 3045 goto unlock; 3046 } 3047 3048 /* Cache the cmode of each port. */ 3049 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3050 if (chip->info->ops->port_get_cmode) { 3051 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3052 if (err) 3053 goto unlock; 3054 3055 chip->ports[i].cmode = cmode; 3056 } 3057 } 3058 3059 /* Setup Switch Port Registers */ 3060 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3061 if (dsa_is_unused_port(ds, i)) 3062 continue; 3063 3064 /* Prevent the use of an invalid port. */ 3065 if (mv88e6xxx_is_invalid_port(chip, i)) { 3066 dev_err(chip->dev, "port %d is invalid\n", i); 3067 err = -EINVAL; 3068 goto unlock; 3069 } 3070 3071 err = mv88e6xxx_setup_port(chip, i); 3072 if (err) 3073 goto unlock; 3074 } 3075 3076 err = mv88e6xxx_irl_setup(chip); 3077 if (err) 3078 goto unlock; 3079 3080 err = mv88e6xxx_mac_setup(chip); 3081 if (err) 3082 goto unlock; 3083 3084 err = mv88e6xxx_phy_setup(chip); 3085 if (err) 3086 goto unlock; 3087 3088 err = mv88e6xxx_vtu_setup(chip); 3089 if (err) 3090 goto unlock; 3091 3092 err = mv88e6xxx_pvt_setup(chip); 3093 if (err) 3094 goto unlock; 3095 3096 err = mv88e6xxx_atu_setup(chip); 3097 if (err) 3098 goto unlock; 3099 3100 err = mv88e6xxx_broadcast_setup(chip, 0); 3101 if (err) 3102 goto unlock; 3103 3104 err = mv88e6xxx_pot_setup(chip); 3105 if (err) 3106 goto unlock; 3107 3108 err = mv88e6xxx_rmu_setup(chip); 3109 if (err) 3110 goto unlock; 3111 3112 err = mv88e6xxx_rsvd2cpu_setup(chip); 3113 if (err) 3114 goto unlock; 3115 3116 err = mv88e6xxx_trunk_setup(chip); 3117 if (err) 3118 goto unlock; 3119 3120 err = mv88e6xxx_devmap_setup(chip); 3121 if (err) 3122 goto unlock; 3123 3124 err = mv88e6xxx_pri_setup(chip); 3125 if (err) 3126 goto unlock; 3127 3128 /* Setup PTP Hardware Clock and timestamping */ 3129 if (chip->info->ptp_support) { 3130 err = mv88e6xxx_ptp_setup(chip); 3131 if (err) 3132 goto unlock; 3133 3134 err = mv88e6xxx_hwtstamp_setup(chip); 3135 if (err) 3136 goto unlock; 3137 } 3138 3139 err = mv88e6xxx_stats_setup(chip); 3140 if (err) 3141 goto unlock; 3142 3143 unlock: 3144 mv88e6xxx_reg_unlock(chip); 3145 3146 if (err) 3147 return err; 3148 3149 /* Have to be called without holding the register lock, since 3150 * they take the devlink lock, and we later take the locks in 3151 * the reverse order when getting/setting parameters or 3152 * resource occupancy. 3153 */ 3154 err = mv88e6xxx_setup_devlink_resources(ds); 3155 if (err) 3156 return err; 3157 3158 err = mv88e6xxx_setup_devlink_params(ds); 3159 if (err) 3160 dsa_devlink_resources_unregister(ds); 3161 3162 return err; 3163 } 3164 3165 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3166 { 3167 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3168 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3169 u16 val; 3170 int err; 3171 3172 if (!chip->info->ops->phy_read) 3173 return -EOPNOTSUPP; 3174 3175 mv88e6xxx_reg_lock(chip); 3176 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3177 mv88e6xxx_reg_unlock(chip); 3178 3179 if (reg == MII_PHYSID2) { 3180 /* Some internal PHYs don't have a model number. */ 3181 if (chip->info->family != MV88E6XXX_FAMILY_6165) 3182 /* Then there is the 6165 family. It gets is 3183 * PHYs correct. But it can also have two 3184 * SERDES interfaces in the PHY address 3185 * space. And these don't have a model 3186 * number. But they are not PHYs, so we don't 3187 * want to give them something a PHY driver 3188 * will recognise. 3189 * 3190 * Use the mv88e6390 family model number 3191 * instead, for anything which really could be 3192 * a PHY, 3193 */ 3194 if (!(val & 0x3f0)) 3195 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 3196 } 3197 3198 return err ? err : val; 3199 } 3200 3201 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3202 { 3203 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3204 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3205 int err; 3206 3207 if (!chip->info->ops->phy_write) 3208 return -EOPNOTSUPP; 3209 3210 mv88e6xxx_reg_lock(chip); 3211 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3212 mv88e6xxx_reg_unlock(chip); 3213 3214 return err; 3215 } 3216 3217 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3218 struct device_node *np, 3219 bool external) 3220 { 3221 static int index; 3222 struct mv88e6xxx_mdio_bus *mdio_bus; 3223 struct mii_bus *bus; 3224 int err; 3225 3226 if (external) { 3227 mv88e6xxx_reg_lock(chip); 3228 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3229 mv88e6xxx_reg_unlock(chip); 3230 3231 if (err) 3232 return err; 3233 } 3234 3235 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3236 if (!bus) 3237 return -ENOMEM; 3238 3239 mdio_bus = bus->priv; 3240 mdio_bus->bus = bus; 3241 mdio_bus->chip = chip; 3242 INIT_LIST_HEAD(&mdio_bus->list); 3243 mdio_bus->external = external; 3244 3245 if (np) { 3246 bus->name = np->full_name; 3247 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3248 } else { 3249 bus->name = "mv88e6xxx SMI"; 3250 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3251 } 3252 3253 bus->read = mv88e6xxx_mdio_read; 3254 bus->write = mv88e6xxx_mdio_write; 3255 bus->parent = chip->dev; 3256 3257 if (!external) { 3258 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3259 if (err) 3260 return err; 3261 } 3262 3263 err = of_mdiobus_register(bus, np); 3264 if (err) { 3265 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3266 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3267 return err; 3268 } 3269 3270 if (external) 3271 list_add_tail(&mdio_bus->list, &chip->mdios); 3272 else 3273 list_add(&mdio_bus->list, &chip->mdios); 3274 3275 return 0; 3276 } 3277 3278 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 3279 { .compatible = "marvell,mv88e6xxx-mdio-external", 3280 .data = (void *)true }, 3281 { }, 3282 }; 3283 3284 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3285 3286 { 3287 struct mv88e6xxx_mdio_bus *mdio_bus; 3288 struct mii_bus *bus; 3289 3290 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3291 bus = mdio_bus->bus; 3292 3293 if (!mdio_bus->external) 3294 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3295 3296 mdiobus_unregister(bus); 3297 } 3298 } 3299 3300 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3301 struct device_node *np) 3302 { 3303 const struct of_device_id *match; 3304 struct device_node *child; 3305 int err; 3306 3307 /* Always register one mdio bus for the internal/default mdio 3308 * bus. This maybe represented in the device tree, but is 3309 * optional. 3310 */ 3311 child = of_get_child_by_name(np, "mdio"); 3312 err = mv88e6xxx_mdio_register(chip, child, false); 3313 if (err) 3314 return err; 3315 3316 /* Walk the device tree, and see if there are any other nodes 3317 * which say they are compatible with the external mdio 3318 * bus. 3319 */ 3320 for_each_available_child_of_node(np, child) { 3321 match = of_match_node(mv88e6xxx_mdio_external_match, child); 3322 if (match) { 3323 err = mv88e6xxx_mdio_register(chip, child, true); 3324 if (err) { 3325 mv88e6xxx_mdios_unregister(chip); 3326 of_node_put(child); 3327 return err; 3328 } 3329 } 3330 } 3331 3332 return 0; 3333 } 3334 3335 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3336 { 3337 struct mv88e6xxx_chip *chip = ds->priv; 3338 3339 return chip->eeprom_len; 3340 } 3341 3342 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3343 struct ethtool_eeprom *eeprom, u8 *data) 3344 { 3345 struct mv88e6xxx_chip *chip = ds->priv; 3346 int err; 3347 3348 if (!chip->info->ops->get_eeprom) 3349 return -EOPNOTSUPP; 3350 3351 mv88e6xxx_reg_lock(chip); 3352 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3353 mv88e6xxx_reg_unlock(chip); 3354 3355 if (err) 3356 return err; 3357 3358 eeprom->magic = 0xc3ec4951; 3359 3360 return 0; 3361 } 3362 3363 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3364 struct ethtool_eeprom *eeprom, u8 *data) 3365 { 3366 struct mv88e6xxx_chip *chip = ds->priv; 3367 int err; 3368 3369 if (!chip->info->ops->set_eeprom) 3370 return -EOPNOTSUPP; 3371 3372 if (eeprom->magic != 0xc3ec4951) 3373 return -EINVAL; 3374 3375 mv88e6xxx_reg_lock(chip); 3376 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3377 mv88e6xxx_reg_unlock(chip); 3378 3379 return err; 3380 } 3381 3382 static const struct mv88e6xxx_ops mv88e6085_ops = { 3383 /* MV88E6XXX_FAMILY_6097 */ 3384 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3385 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3386 .irl_init_all = mv88e6352_g2_irl_init_all, 3387 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3388 .phy_read = mv88e6185_phy_ppu_read, 3389 .phy_write = mv88e6185_phy_ppu_write, 3390 .port_set_link = mv88e6xxx_port_set_link, 3391 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3392 .port_tag_remap = mv88e6095_port_tag_remap, 3393 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3394 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3395 .port_set_ether_type = mv88e6351_port_set_ether_type, 3396 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3397 .port_pause_limit = mv88e6097_port_pause_limit, 3398 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3399 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3400 .port_get_cmode = mv88e6185_port_get_cmode, 3401 .port_setup_message_port = mv88e6xxx_setup_message_port, 3402 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3403 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3404 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3405 .stats_get_strings = mv88e6095_stats_get_strings, 3406 .stats_get_stats = mv88e6095_stats_get_stats, 3407 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3408 .set_egress_port = mv88e6095_g1_set_egress_port, 3409 .watchdog_ops = &mv88e6097_watchdog_ops, 3410 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3411 .pot_clear = mv88e6xxx_g2_pot_clear, 3412 .ppu_enable = mv88e6185_g1_ppu_enable, 3413 .ppu_disable = mv88e6185_g1_ppu_disable, 3414 .reset = mv88e6185_g1_reset, 3415 .rmu_disable = mv88e6085_g1_rmu_disable, 3416 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3417 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3418 .phylink_validate = mv88e6185_phylink_validate, 3419 }; 3420 3421 static const struct mv88e6xxx_ops mv88e6095_ops = { 3422 /* MV88E6XXX_FAMILY_6095 */ 3423 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3424 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3425 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3426 .phy_read = mv88e6185_phy_ppu_read, 3427 .phy_write = mv88e6185_phy_ppu_write, 3428 .port_set_link = mv88e6xxx_port_set_link, 3429 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3430 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3431 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3432 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3433 .port_get_cmode = mv88e6185_port_get_cmode, 3434 .port_setup_message_port = mv88e6xxx_setup_message_port, 3435 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3436 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3437 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3438 .stats_get_strings = mv88e6095_stats_get_strings, 3439 .stats_get_stats = mv88e6095_stats_get_stats, 3440 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3441 .ppu_enable = mv88e6185_g1_ppu_enable, 3442 .ppu_disable = mv88e6185_g1_ppu_disable, 3443 .reset = mv88e6185_g1_reset, 3444 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3445 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3446 .phylink_validate = mv88e6185_phylink_validate, 3447 }; 3448 3449 static const struct mv88e6xxx_ops mv88e6097_ops = { 3450 /* MV88E6XXX_FAMILY_6097 */ 3451 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3452 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3453 .irl_init_all = mv88e6352_g2_irl_init_all, 3454 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3455 .phy_read = mv88e6xxx_g2_smi_phy_read, 3456 .phy_write = mv88e6xxx_g2_smi_phy_write, 3457 .port_set_link = mv88e6xxx_port_set_link, 3458 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3459 .port_tag_remap = mv88e6095_port_tag_remap, 3460 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3461 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3462 .port_set_ether_type = mv88e6351_port_set_ether_type, 3463 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3464 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3465 .port_pause_limit = mv88e6097_port_pause_limit, 3466 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3467 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3468 .port_get_cmode = mv88e6185_port_get_cmode, 3469 .port_setup_message_port = mv88e6xxx_setup_message_port, 3470 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3471 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3472 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3473 .stats_get_strings = mv88e6095_stats_get_strings, 3474 .stats_get_stats = mv88e6095_stats_get_stats, 3475 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3476 .set_egress_port = mv88e6095_g1_set_egress_port, 3477 .watchdog_ops = &mv88e6097_watchdog_ops, 3478 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3479 .pot_clear = mv88e6xxx_g2_pot_clear, 3480 .reset = mv88e6352_g1_reset, 3481 .rmu_disable = mv88e6085_g1_rmu_disable, 3482 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3483 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3484 .phylink_validate = mv88e6185_phylink_validate, 3485 }; 3486 3487 static const struct mv88e6xxx_ops mv88e6123_ops = { 3488 /* MV88E6XXX_FAMILY_6165 */ 3489 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3490 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3491 .irl_init_all = mv88e6352_g2_irl_init_all, 3492 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3493 .phy_read = mv88e6xxx_g2_smi_phy_read, 3494 .phy_write = mv88e6xxx_g2_smi_phy_write, 3495 .port_set_link = mv88e6xxx_port_set_link, 3496 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3497 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3498 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3499 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3500 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3501 .port_get_cmode = mv88e6185_port_get_cmode, 3502 .port_setup_message_port = mv88e6xxx_setup_message_port, 3503 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3504 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3505 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3506 .stats_get_strings = mv88e6095_stats_get_strings, 3507 .stats_get_stats = mv88e6095_stats_get_stats, 3508 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3509 .set_egress_port = mv88e6095_g1_set_egress_port, 3510 .watchdog_ops = &mv88e6097_watchdog_ops, 3511 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3512 .pot_clear = mv88e6xxx_g2_pot_clear, 3513 .reset = mv88e6352_g1_reset, 3514 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3515 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3516 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3517 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3518 .phylink_validate = mv88e6185_phylink_validate, 3519 }; 3520 3521 static const struct mv88e6xxx_ops mv88e6131_ops = { 3522 /* MV88E6XXX_FAMILY_6185 */ 3523 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3524 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3525 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3526 .phy_read = mv88e6185_phy_ppu_read, 3527 .phy_write = mv88e6185_phy_ppu_write, 3528 .port_set_link = mv88e6xxx_port_set_link, 3529 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3530 .port_tag_remap = mv88e6095_port_tag_remap, 3531 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3532 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3533 .port_set_ether_type = mv88e6351_port_set_ether_type, 3534 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3535 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3536 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3537 .port_pause_limit = mv88e6097_port_pause_limit, 3538 .port_set_pause = mv88e6185_port_set_pause, 3539 .port_get_cmode = mv88e6185_port_get_cmode, 3540 .port_setup_message_port = mv88e6xxx_setup_message_port, 3541 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3542 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3543 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3544 .stats_get_strings = mv88e6095_stats_get_strings, 3545 .stats_get_stats = mv88e6095_stats_get_stats, 3546 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3547 .set_egress_port = mv88e6095_g1_set_egress_port, 3548 .watchdog_ops = &mv88e6097_watchdog_ops, 3549 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3550 .ppu_enable = mv88e6185_g1_ppu_enable, 3551 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3552 .ppu_disable = mv88e6185_g1_ppu_disable, 3553 .reset = mv88e6185_g1_reset, 3554 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3555 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3556 .phylink_validate = mv88e6185_phylink_validate, 3557 }; 3558 3559 static const struct mv88e6xxx_ops mv88e6141_ops = { 3560 /* MV88E6XXX_FAMILY_6341 */ 3561 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3562 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3563 .irl_init_all = mv88e6352_g2_irl_init_all, 3564 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3565 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3566 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3567 .phy_read = mv88e6xxx_g2_smi_phy_read, 3568 .phy_write = mv88e6xxx_g2_smi_phy_write, 3569 .port_set_link = mv88e6xxx_port_set_link, 3570 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3571 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3572 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3573 .port_tag_remap = mv88e6095_port_tag_remap, 3574 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3575 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3576 .port_set_ether_type = mv88e6351_port_set_ether_type, 3577 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3578 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3579 .port_pause_limit = mv88e6097_port_pause_limit, 3580 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3581 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3582 .port_get_cmode = mv88e6352_port_get_cmode, 3583 .port_set_cmode = mv88e6341_port_set_cmode, 3584 .port_setup_message_port = mv88e6xxx_setup_message_port, 3585 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3586 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3587 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3588 .stats_get_strings = mv88e6320_stats_get_strings, 3589 .stats_get_stats = mv88e6390_stats_get_stats, 3590 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3591 .set_egress_port = mv88e6390_g1_set_egress_port, 3592 .watchdog_ops = &mv88e6390_watchdog_ops, 3593 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3594 .pot_clear = mv88e6xxx_g2_pot_clear, 3595 .reset = mv88e6352_g1_reset, 3596 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3597 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3598 .serdes_power = mv88e6390_serdes_power, 3599 .serdes_get_lane = mv88e6341_serdes_get_lane, 3600 /* Check status register pause & lpa register */ 3601 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3602 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3603 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3604 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3605 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3606 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3607 .serdes_irq_status = mv88e6390_serdes_irq_status, 3608 .gpio_ops = &mv88e6352_gpio_ops, 3609 .phylink_validate = mv88e6341_phylink_validate, 3610 }; 3611 3612 static const struct mv88e6xxx_ops mv88e6161_ops = { 3613 /* MV88E6XXX_FAMILY_6165 */ 3614 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3615 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3616 .irl_init_all = mv88e6352_g2_irl_init_all, 3617 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3618 .phy_read = mv88e6xxx_g2_smi_phy_read, 3619 .phy_write = mv88e6xxx_g2_smi_phy_write, 3620 .port_set_link = mv88e6xxx_port_set_link, 3621 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3622 .port_tag_remap = mv88e6095_port_tag_remap, 3623 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3624 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3625 .port_set_ether_type = mv88e6351_port_set_ether_type, 3626 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3627 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3628 .port_pause_limit = mv88e6097_port_pause_limit, 3629 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3630 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3631 .port_get_cmode = mv88e6185_port_get_cmode, 3632 .port_setup_message_port = mv88e6xxx_setup_message_port, 3633 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3634 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3635 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3636 .stats_get_strings = mv88e6095_stats_get_strings, 3637 .stats_get_stats = mv88e6095_stats_get_stats, 3638 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3639 .set_egress_port = mv88e6095_g1_set_egress_port, 3640 .watchdog_ops = &mv88e6097_watchdog_ops, 3641 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3642 .pot_clear = mv88e6xxx_g2_pot_clear, 3643 .reset = mv88e6352_g1_reset, 3644 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3645 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3646 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3647 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3648 .avb_ops = &mv88e6165_avb_ops, 3649 .ptp_ops = &mv88e6165_ptp_ops, 3650 .phylink_validate = mv88e6185_phylink_validate, 3651 }; 3652 3653 static const struct mv88e6xxx_ops mv88e6165_ops = { 3654 /* MV88E6XXX_FAMILY_6165 */ 3655 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3656 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3657 .irl_init_all = mv88e6352_g2_irl_init_all, 3658 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3659 .phy_read = mv88e6165_phy_read, 3660 .phy_write = mv88e6165_phy_write, 3661 .port_set_link = mv88e6xxx_port_set_link, 3662 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3663 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3664 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3665 .port_get_cmode = mv88e6185_port_get_cmode, 3666 .port_setup_message_port = mv88e6xxx_setup_message_port, 3667 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3668 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3669 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3670 .stats_get_strings = mv88e6095_stats_get_strings, 3671 .stats_get_stats = mv88e6095_stats_get_stats, 3672 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3673 .set_egress_port = mv88e6095_g1_set_egress_port, 3674 .watchdog_ops = &mv88e6097_watchdog_ops, 3675 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3676 .pot_clear = mv88e6xxx_g2_pot_clear, 3677 .reset = mv88e6352_g1_reset, 3678 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3679 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3680 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3681 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3682 .avb_ops = &mv88e6165_avb_ops, 3683 .ptp_ops = &mv88e6165_ptp_ops, 3684 .phylink_validate = mv88e6185_phylink_validate, 3685 }; 3686 3687 static const struct mv88e6xxx_ops mv88e6171_ops = { 3688 /* MV88E6XXX_FAMILY_6351 */ 3689 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3690 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3691 .irl_init_all = mv88e6352_g2_irl_init_all, 3692 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3693 .phy_read = mv88e6xxx_g2_smi_phy_read, 3694 .phy_write = mv88e6xxx_g2_smi_phy_write, 3695 .port_set_link = mv88e6xxx_port_set_link, 3696 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3697 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3698 .port_tag_remap = mv88e6095_port_tag_remap, 3699 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3700 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3701 .port_set_ether_type = mv88e6351_port_set_ether_type, 3702 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3703 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3704 .port_pause_limit = mv88e6097_port_pause_limit, 3705 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3706 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3707 .port_get_cmode = mv88e6352_port_get_cmode, 3708 .port_setup_message_port = mv88e6xxx_setup_message_port, 3709 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3710 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3711 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3712 .stats_get_strings = mv88e6095_stats_get_strings, 3713 .stats_get_stats = mv88e6095_stats_get_stats, 3714 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3715 .set_egress_port = mv88e6095_g1_set_egress_port, 3716 .watchdog_ops = &mv88e6097_watchdog_ops, 3717 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3718 .pot_clear = mv88e6xxx_g2_pot_clear, 3719 .reset = mv88e6352_g1_reset, 3720 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3721 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3722 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3723 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3724 .phylink_validate = mv88e6185_phylink_validate, 3725 }; 3726 3727 static const struct mv88e6xxx_ops mv88e6172_ops = { 3728 /* MV88E6XXX_FAMILY_6352 */ 3729 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3730 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3731 .irl_init_all = mv88e6352_g2_irl_init_all, 3732 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3733 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3734 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3735 .phy_read = mv88e6xxx_g2_smi_phy_read, 3736 .phy_write = mv88e6xxx_g2_smi_phy_write, 3737 .port_set_link = mv88e6xxx_port_set_link, 3738 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3739 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3740 .port_tag_remap = mv88e6095_port_tag_remap, 3741 .port_set_policy = mv88e6352_port_set_policy, 3742 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3743 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3744 .port_set_ether_type = mv88e6351_port_set_ether_type, 3745 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3746 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3747 .port_pause_limit = mv88e6097_port_pause_limit, 3748 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3749 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3750 .port_get_cmode = mv88e6352_port_get_cmode, 3751 .port_setup_message_port = mv88e6xxx_setup_message_port, 3752 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3753 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3754 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3755 .stats_get_strings = mv88e6095_stats_get_strings, 3756 .stats_get_stats = mv88e6095_stats_get_stats, 3757 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3758 .set_egress_port = mv88e6095_g1_set_egress_port, 3759 .watchdog_ops = &mv88e6097_watchdog_ops, 3760 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3761 .pot_clear = mv88e6xxx_g2_pot_clear, 3762 .reset = mv88e6352_g1_reset, 3763 .rmu_disable = mv88e6352_g1_rmu_disable, 3764 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3765 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3766 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3767 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3768 .serdes_get_lane = mv88e6352_serdes_get_lane, 3769 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3770 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3771 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3772 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3773 .serdes_power = mv88e6352_serdes_power, 3774 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3775 .serdes_get_regs = mv88e6352_serdes_get_regs, 3776 .gpio_ops = &mv88e6352_gpio_ops, 3777 .phylink_validate = mv88e6352_phylink_validate, 3778 }; 3779 3780 static const struct mv88e6xxx_ops mv88e6175_ops = { 3781 /* MV88E6XXX_FAMILY_6351 */ 3782 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3783 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3784 .irl_init_all = mv88e6352_g2_irl_init_all, 3785 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3786 .phy_read = mv88e6xxx_g2_smi_phy_read, 3787 .phy_write = mv88e6xxx_g2_smi_phy_write, 3788 .port_set_link = mv88e6xxx_port_set_link, 3789 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3790 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3791 .port_tag_remap = mv88e6095_port_tag_remap, 3792 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3793 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3794 .port_set_ether_type = mv88e6351_port_set_ether_type, 3795 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3796 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3797 .port_pause_limit = mv88e6097_port_pause_limit, 3798 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3799 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3800 .port_get_cmode = mv88e6352_port_get_cmode, 3801 .port_setup_message_port = mv88e6xxx_setup_message_port, 3802 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3803 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3804 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3805 .stats_get_strings = mv88e6095_stats_get_strings, 3806 .stats_get_stats = mv88e6095_stats_get_stats, 3807 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3808 .set_egress_port = mv88e6095_g1_set_egress_port, 3809 .watchdog_ops = &mv88e6097_watchdog_ops, 3810 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3811 .pot_clear = mv88e6xxx_g2_pot_clear, 3812 .reset = mv88e6352_g1_reset, 3813 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3814 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3815 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3816 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3817 .phylink_validate = mv88e6185_phylink_validate, 3818 }; 3819 3820 static const struct mv88e6xxx_ops mv88e6176_ops = { 3821 /* MV88E6XXX_FAMILY_6352 */ 3822 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3823 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3824 .irl_init_all = mv88e6352_g2_irl_init_all, 3825 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3826 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3827 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3828 .phy_read = mv88e6xxx_g2_smi_phy_read, 3829 .phy_write = mv88e6xxx_g2_smi_phy_write, 3830 .port_set_link = mv88e6xxx_port_set_link, 3831 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3832 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3833 .port_tag_remap = mv88e6095_port_tag_remap, 3834 .port_set_policy = mv88e6352_port_set_policy, 3835 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3836 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3837 .port_set_ether_type = mv88e6351_port_set_ether_type, 3838 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3839 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3840 .port_pause_limit = mv88e6097_port_pause_limit, 3841 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3842 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3843 .port_get_cmode = mv88e6352_port_get_cmode, 3844 .port_setup_message_port = mv88e6xxx_setup_message_port, 3845 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3846 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3847 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3848 .stats_get_strings = mv88e6095_stats_get_strings, 3849 .stats_get_stats = mv88e6095_stats_get_stats, 3850 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3851 .set_egress_port = mv88e6095_g1_set_egress_port, 3852 .watchdog_ops = &mv88e6097_watchdog_ops, 3853 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3854 .pot_clear = mv88e6xxx_g2_pot_clear, 3855 .reset = mv88e6352_g1_reset, 3856 .rmu_disable = mv88e6352_g1_rmu_disable, 3857 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3858 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3859 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3860 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3861 .serdes_get_lane = mv88e6352_serdes_get_lane, 3862 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3863 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3864 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3865 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3866 .serdes_power = mv88e6352_serdes_power, 3867 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3868 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3869 .serdes_irq_status = mv88e6352_serdes_irq_status, 3870 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3871 .serdes_get_regs = mv88e6352_serdes_get_regs, 3872 .gpio_ops = &mv88e6352_gpio_ops, 3873 .phylink_validate = mv88e6352_phylink_validate, 3874 }; 3875 3876 static const struct mv88e6xxx_ops mv88e6185_ops = { 3877 /* MV88E6XXX_FAMILY_6185 */ 3878 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3879 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3880 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3881 .phy_read = mv88e6185_phy_ppu_read, 3882 .phy_write = mv88e6185_phy_ppu_write, 3883 .port_set_link = mv88e6xxx_port_set_link, 3884 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3885 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3886 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3887 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3888 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3889 .port_set_pause = mv88e6185_port_set_pause, 3890 .port_get_cmode = mv88e6185_port_get_cmode, 3891 .port_setup_message_port = mv88e6xxx_setup_message_port, 3892 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3893 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3894 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3895 .stats_get_strings = mv88e6095_stats_get_strings, 3896 .stats_get_stats = mv88e6095_stats_get_stats, 3897 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3898 .set_egress_port = mv88e6095_g1_set_egress_port, 3899 .watchdog_ops = &mv88e6097_watchdog_ops, 3900 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3901 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3902 .ppu_enable = mv88e6185_g1_ppu_enable, 3903 .ppu_disable = mv88e6185_g1_ppu_disable, 3904 .reset = mv88e6185_g1_reset, 3905 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3906 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3907 .phylink_validate = mv88e6185_phylink_validate, 3908 }; 3909 3910 static const struct mv88e6xxx_ops mv88e6190_ops = { 3911 /* MV88E6XXX_FAMILY_6390 */ 3912 .setup_errata = mv88e6390_setup_errata, 3913 .irl_init_all = mv88e6390_g2_irl_init_all, 3914 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3915 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3916 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3917 .phy_read = mv88e6xxx_g2_smi_phy_read, 3918 .phy_write = mv88e6xxx_g2_smi_phy_write, 3919 .port_set_link = mv88e6xxx_port_set_link, 3920 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3921 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3922 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3923 .port_tag_remap = mv88e6390_port_tag_remap, 3924 .port_set_policy = mv88e6352_port_set_policy, 3925 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3926 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3927 .port_set_ether_type = mv88e6351_port_set_ether_type, 3928 .port_pause_limit = mv88e6390_port_pause_limit, 3929 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3930 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3931 .port_get_cmode = mv88e6352_port_get_cmode, 3932 .port_set_cmode = mv88e6390_port_set_cmode, 3933 .port_setup_message_port = mv88e6xxx_setup_message_port, 3934 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3935 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3936 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3937 .stats_get_strings = mv88e6320_stats_get_strings, 3938 .stats_get_stats = mv88e6390_stats_get_stats, 3939 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3940 .set_egress_port = mv88e6390_g1_set_egress_port, 3941 .watchdog_ops = &mv88e6390_watchdog_ops, 3942 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3943 .pot_clear = mv88e6xxx_g2_pot_clear, 3944 .reset = mv88e6352_g1_reset, 3945 .rmu_disable = mv88e6390_g1_rmu_disable, 3946 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3947 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3948 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3949 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3950 .serdes_power = mv88e6390_serdes_power, 3951 .serdes_get_lane = mv88e6390_serdes_get_lane, 3952 /* Check status register pause & lpa register */ 3953 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3954 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3955 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3956 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3957 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3958 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3959 .serdes_irq_status = mv88e6390_serdes_irq_status, 3960 .serdes_get_strings = mv88e6390_serdes_get_strings, 3961 .serdes_get_stats = mv88e6390_serdes_get_stats, 3962 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3963 .serdes_get_regs = mv88e6390_serdes_get_regs, 3964 .phylink_validate = mv88e6390_phylink_validate, 3965 .gpio_ops = &mv88e6352_gpio_ops, 3966 .phylink_validate = mv88e6390_phylink_validate, 3967 }; 3968 3969 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3970 /* MV88E6XXX_FAMILY_6390 */ 3971 .setup_errata = mv88e6390_setup_errata, 3972 .irl_init_all = mv88e6390_g2_irl_init_all, 3973 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3974 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3975 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3976 .phy_read = mv88e6xxx_g2_smi_phy_read, 3977 .phy_write = mv88e6xxx_g2_smi_phy_write, 3978 .port_set_link = mv88e6xxx_port_set_link, 3979 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3980 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 3981 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3982 .port_tag_remap = mv88e6390_port_tag_remap, 3983 .port_set_policy = mv88e6352_port_set_policy, 3984 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3985 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3986 .port_set_ether_type = mv88e6351_port_set_ether_type, 3987 .port_pause_limit = mv88e6390_port_pause_limit, 3988 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3989 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3990 .port_get_cmode = mv88e6352_port_get_cmode, 3991 .port_set_cmode = mv88e6390x_port_set_cmode, 3992 .port_setup_message_port = mv88e6xxx_setup_message_port, 3993 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3994 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3995 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3996 .stats_get_strings = mv88e6320_stats_get_strings, 3997 .stats_get_stats = mv88e6390_stats_get_stats, 3998 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3999 .set_egress_port = mv88e6390_g1_set_egress_port, 4000 .watchdog_ops = &mv88e6390_watchdog_ops, 4001 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4002 .pot_clear = mv88e6xxx_g2_pot_clear, 4003 .reset = mv88e6352_g1_reset, 4004 .rmu_disable = mv88e6390_g1_rmu_disable, 4005 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4006 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4007 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4008 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4009 .serdes_power = mv88e6390_serdes_power, 4010 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4011 /* Check status register pause & lpa register */ 4012 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4013 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4014 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4015 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4016 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4017 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4018 .serdes_irq_status = mv88e6390_serdes_irq_status, 4019 .serdes_get_strings = mv88e6390_serdes_get_strings, 4020 .serdes_get_stats = mv88e6390_serdes_get_stats, 4021 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4022 .serdes_get_regs = mv88e6390_serdes_get_regs, 4023 .phylink_validate = mv88e6390_phylink_validate, 4024 .gpio_ops = &mv88e6352_gpio_ops, 4025 .phylink_validate = mv88e6390x_phylink_validate, 4026 }; 4027 4028 static const struct mv88e6xxx_ops mv88e6191_ops = { 4029 /* MV88E6XXX_FAMILY_6390 */ 4030 .setup_errata = mv88e6390_setup_errata, 4031 .irl_init_all = mv88e6390_g2_irl_init_all, 4032 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4033 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4034 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4035 .phy_read = mv88e6xxx_g2_smi_phy_read, 4036 .phy_write = mv88e6xxx_g2_smi_phy_write, 4037 .port_set_link = mv88e6xxx_port_set_link, 4038 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4039 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4040 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4041 .port_tag_remap = mv88e6390_port_tag_remap, 4042 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4043 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4044 .port_set_ether_type = mv88e6351_port_set_ether_type, 4045 .port_pause_limit = mv88e6390_port_pause_limit, 4046 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4047 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4048 .port_get_cmode = mv88e6352_port_get_cmode, 4049 .port_set_cmode = mv88e6390_port_set_cmode, 4050 .port_setup_message_port = mv88e6xxx_setup_message_port, 4051 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4052 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4053 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4054 .stats_get_strings = mv88e6320_stats_get_strings, 4055 .stats_get_stats = mv88e6390_stats_get_stats, 4056 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4057 .set_egress_port = mv88e6390_g1_set_egress_port, 4058 .watchdog_ops = &mv88e6390_watchdog_ops, 4059 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4060 .pot_clear = mv88e6xxx_g2_pot_clear, 4061 .reset = mv88e6352_g1_reset, 4062 .rmu_disable = mv88e6390_g1_rmu_disable, 4063 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4064 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4065 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4066 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4067 .serdes_power = mv88e6390_serdes_power, 4068 .serdes_get_lane = mv88e6390_serdes_get_lane, 4069 /* Check status register pause & lpa register */ 4070 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4071 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4072 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4073 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4074 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4075 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4076 .serdes_irq_status = mv88e6390_serdes_irq_status, 4077 .serdes_get_strings = mv88e6390_serdes_get_strings, 4078 .serdes_get_stats = mv88e6390_serdes_get_stats, 4079 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4080 .serdes_get_regs = mv88e6390_serdes_get_regs, 4081 .phylink_validate = mv88e6390_phylink_validate, 4082 .avb_ops = &mv88e6390_avb_ops, 4083 .ptp_ops = &mv88e6352_ptp_ops, 4084 .phylink_validate = mv88e6390_phylink_validate, 4085 }; 4086 4087 static const struct mv88e6xxx_ops mv88e6240_ops = { 4088 /* MV88E6XXX_FAMILY_6352 */ 4089 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4090 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4091 .irl_init_all = mv88e6352_g2_irl_init_all, 4092 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4093 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4094 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4095 .phy_read = mv88e6xxx_g2_smi_phy_read, 4096 .phy_write = mv88e6xxx_g2_smi_phy_write, 4097 .port_set_link = mv88e6xxx_port_set_link, 4098 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4099 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4100 .port_tag_remap = mv88e6095_port_tag_remap, 4101 .port_set_policy = mv88e6352_port_set_policy, 4102 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4103 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4104 .port_set_ether_type = mv88e6351_port_set_ether_type, 4105 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4106 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4107 .port_pause_limit = mv88e6097_port_pause_limit, 4108 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4109 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4110 .port_get_cmode = mv88e6352_port_get_cmode, 4111 .port_setup_message_port = mv88e6xxx_setup_message_port, 4112 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4113 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4114 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4115 .stats_get_strings = mv88e6095_stats_get_strings, 4116 .stats_get_stats = mv88e6095_stats_get_stats, 4117 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4118 .set_egress_port = mv88e6095_g1_set_egress_port, 4119 .watchdog_ops = &mv88e6097_watchdog_ops, 4120 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4121 .pot_clear = mv88e6xxx_g2_pot_clear, 4122 .reset = mv88e6352_g1_reset, 4123 .rmu_disable = mv88e6352_g1_rmu_disable, 4124 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4125 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4126 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4127 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4128 .serdes_get_lane = mv88e6352_serdes_get_lane, 4129 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4130 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4131 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4132 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4133 .serdes_power = mv88e6352_serdes_power, 4134 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4135 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4136 .serdes_irq_status = mv88e6352_serdes_irq_status, 4137 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4138 .serdes_get_regs = mv88e6352_serdes_get_regs, 4139 .gpio_ops = &mv88e6352_gpio_ops, 4140 .avb_ops = &mv88e6352_avb_ops, 4141 .ptp_ops = &mv88e6352_ptp_ops, 4142 .phylink_validate = mv88e6352_phylink_validate, 4143 }; 4144 4145 static const struct mv88e6xxx_ops mv88e6250_ops = { 4146 /* MV88E6XXX_FAMILY_6250 */ 4147 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4148 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4149 .irl_init_all = mv88e6352_g2_irl_init_all, 4150 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4151 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4152 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4153 .phy_read = mv88e6xxx_g2_smi_phy_read, 4154 .phy_write = mv88e6xxx_g2_smi_phy_write, 4155 .port_set_link = mv88e6xxx_port_set_link, 4156 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4157 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4158 .port_tag_remap = mv88e6095_port_tag_remap, 4159 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4160 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4161 .port_set_ether_type = mv88e6351_port_set_ether_type, 4162 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4163 .port_pause_limit = mv88e6097_port_pause_limit, 4164 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4165 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4166 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4167 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4168 .stats_get_strings = mv88e6250_stats_get_strings, 4169 .stats_get_stats = mv88e6250_stats_get_stats, 4170 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4171 .set_egress_port = mv88e6095_g1_set_egress_port, 4172 .watchdog_ops = &mv88e6250_watchdog_ops, 4173 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4174 .pot_clear = mv88e6xxx_g2_pot_clear, 4175 .reset = mv88e6250_g1_reset, 4176 .vtu_getnext = mv88e6250_g1_vtu_getnext, 4177 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 4178 .avb_ops = &mv88e6352_avb_ops, 4179 .ptp_ops = &mv88e6250_ptp_ops, 4180 .phylink_validate = mv88e6065_phylink_validate, 4181 }; 4182 4183 static const struct mv88e6xxx_ops mv88e6290_ops = { 4184 /* MV88E6XXX_FAMILY_6390 */ 4185 .setup_errata = mv88e6390_setup_errata, 4186 .irl_init_all = mv88e6390_g2_irl_init_all, 4187 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4188 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4189 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4190 .phy_read = mv88e6xxx_g2_smi_phy_read, 4191 .phy_write = mv88e6xxx_g2_smi_phy_write, 4192 .port_set_link = mv88e6xxx_port_set_link, 4193 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4194 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4195 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4196 .port_tag_remap = mv88e6390_port_tag_remap, 4197 .port_set_policy = mv88e6352_port_set_policy, 4198 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4199 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4200 .port_set_ether_type = mv88e6351_port_set_ether_type, 4201 .port_pause_limit = mv88e6390_port_pause_limit, 4202 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4203 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4204 .port_get_cmode = mv88e6352_port_get_cmode, 4205 .port_set_cmode = mv88e6390_port_set_cmode, 4206 .port_setup_message_port = mv88e6xxx_setup_message_port, 4207 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4208 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4209 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4210 .stats_get_strings = mv88e6320_stats_get_strings, 4211 .stats_get_stats = mv88e6390_stats_get_stats, 4212 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4213 .set_egress_port = mv88e6390_g1_set_egress_port, 4214 .watchdog_ops = &mv88e6390_watchdog_ops, 4215 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4216 .pot_clear = mv88e6xxx_g2_pot_clear, 4217 .reset = mv88e6352_g1_reset, 4218 .rmu_disable = mv88e6390_g1_rmu_disable, 4219 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4220 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4221 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4222 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4223 .serdes_power = mv88e6390_serdes_power, 4224 .serdes_get_lane = mv88e6390_serdes_get_lane, 4225 /* Check status register pause & lpa register */ 4226 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4227 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4228 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4229 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4230 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4231 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4232 .serdes_irq_status = mv88e6390_serdes_irq_status, 4233 .serdes_get_strings = mv88e6390_serdes_get_strings, 4234 .serdes_get_stats = mv88e6390_serdes_get_stats, 4235 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4236 .serdes_get_regs = mv88e6390_serdes_get_regs, 4237 .phylink_validate = mv88e6390_phylink_validate, 4238 .gpio_ops = &mv88e6352_gpio_ops, 4239 .avb_ops = &mv88e6390_avb_ops, 4240 .ptp_ops = &mv88e6352_ptp_ops, 4241 .phylink_validate = mv88e6390_phylink_validate, 4242 }; 4243 4244 static const struct mv88e6xxx_ops mv88e6320_ops = { 4245 /* MV88E6XXX_FAMILY_6320 */ 4246 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4247 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4248 .irl_init_all = mv88e6352_g2_irl_init_all, 4249 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4250 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4251 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4252 .phy_read = mv88e6xxx_g2_smi_phy_read, 4253 .phy_write = mv88e6xxx_g2_smi_phy_write, 4254 .port_set_link = mv88e6xxx_port_set_link, 4255 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4256 .port_tag_remap = mv88e6095_port_tag_remap, 4257 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4258 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4259 .port_set_ether_type = mv88e6351_port_set_ether_type, 4260 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4261 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4262 .port_pause_limit = mv88e6097_port_pause_limit, 4263 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4264 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4265 .port_get_cmode = mv88e6352_port_get_cmode, 4266 .port_setup_message_port = mv88e6xxx_setup_message_port, 4267 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4268 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4269 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4270 .stats_get_strings = mv88e6320_stats_get_strings, 4271 .stats_get_stats = mv88e6320_stats_get_stats, 4272 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4273 .set_egress_port = mv88e6095_g1_set_egress_port, 4274 .watchdog_ops = &mv88e6390_watchdog_ops, 4275 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4276 .pot_clear = mv88e6xxx_g2_pot_clear, 4277 .reset = mv88e6352_g1_reset, 4278 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4279 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4280 .gpio_ops = &mv88e6352_gpio_ops, 4281 .avb_ops = &mv88e6352_avb_ops, 4282 .ptp_ops = &mv88e6352_ptp_ops, 4283 .phylink_validate = mv88e6185_phylink_validate, 4284 }; 4285 4286 static const struct mv88e6xxx_ops mv88e6321_ops = { 4287 /* MV88E6XXX_FAMILY_6320 */ 4288 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4289 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4290 .irl_init_all = mv88e6352_g2_irl_init_all, 4291 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4292 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4293 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4294 .phy_read = mv88e6xxx_g2_smi_phy_read, 4295 .phy_write = mv88e6xxx_g2_smi_phy_write, 4296 .port_set_link = mv88e6xxx_port_set_link, 4297 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4298 .port_tag_remap = mv88e6095_port_tag_remap, 4299 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4300 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4301 .port_set_ether_type = mv88e6351_port_set_ether_type, 4302 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4303 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4304 .port_pause_limit = mv88e6097_port_pause_limit, 4305 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4306 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4307 .port_get_cmode = mv88e6352_port_get_cmode, 4308 .port_setup_message_port = mv88e6xxx_setup_message_port, 4309 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4310 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4311 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4312 .stats_get_strings = mv88e6320_stats_get_strings, 4313 .stats_get_stats = mv88e6320_stats_get_stats, 4314 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4315 .set_egress_port = mv88e6095_g1_set_egress_port, 4316 .watchdog_ops = &mv88e6390_watchdog_ops, 4317 .reset = mv88e6352_g1_reset, 4318 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4319 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4320 .gpio_ops = &mv88e6352_gpio_ops, 4321 .avb_ops = &mv88e6352_avb_ops, 4322 .ptp_ops = &mv88e6352_ptp_ops, 4323 .phylink_validate = mv88e6185_phylink_validate, 4324 }; 4325 4326 static const struct mv88e6xxx_ops mv88e6341_ops = { 4327 /* MV88E6XXX_FAMILY_6341 */ 4328 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4329 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4330 .irl_init_all = mv88e6352_g2_irl_init_all, 4331 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4332 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4333 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4334 .phy_read = mv88e6xxx_g2_smi_phy_read, 4335 .phy_write = mv88e6xxx_g2_smi_phy_write, 4336 .port_set_link = mv88e6xxx_port_set_link, 4337 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4338 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4339 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4340 .port_tag_remap = mv88e6095_port_tag_remap, 4341 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4342 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4343 .port_set_ether_type = mv88e6351_port_set_ether_type, 4344 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4345 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4346 .port_pause_limit = mv88e6097_port_pause_limit, 4347 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4348 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4349 .port_get_cmode = mv88e6352_port_get_cmode, 4350 .port_set_cmode = mv88e6341_port_set_cmode, 4351 .port_setup_message_port = mv88e6xxx_setup_message_port, 4352 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4353 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4354 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4355 .stats_get_strings = mv88e6320_stats_get_strings, 4356 .stats_get_stats = mv88e6390_stats_get_stats, 4357 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4358 .set_egress_port = mv88e6390_g1_set_egress_port, 4359 .watchdog_ops = &mv88e6390_watchdog_ops, 4360 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4361 .pot_clear = mv88e6xxx_g2_pot_clear, 4362 .reset = mv88e6352_g1_reset, 4363 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4364 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4365 .serdes_power = mv88e6390_serdes_power, 4366 .serdes_get_lane = mv88e6341_serdes_get_lane, 4367 /* Check status register pause & lpa register */ 4368 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4369 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4370 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4371 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4372 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4373 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4374 .serdes_irq_status = mv88e6390_serdes_irq_status, 4375 .gpio_ops = &mv88e6352_gpio_ops, 4376 .avb_ops = &mv88e6390_avb_ops, 4377 .ptp_ops = &mv88e6352_ptp_ops, 4378 .phylink_validate = mv88e6341_phylink_validate, 4379 }; 4380 4381 static const struct mv88e6xxx_ops mv88e6350_ops = { 4382 /* MV88E6XXX_FAMILY_6351 */ 4383 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4384 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4385 .irl_init_all = mv88e6352_g2_irl_init_all, 4386 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4387 .phy_read = mv88e6xxx_g2_smi_phy_read, 4388 .phy_write = mv88e6xxx_g2_smi_phy_write, 4389 .port_set_link = mv88e6xxx_port_set_link, 4390 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4391 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4392 .port_tag_remap = mv88e6095_port_tag_remap, 4393 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4394 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4395 .port_set_ether_type = mv88e6351_port_set_ether_type, 4396 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4397 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4398 .port_pause_limit = mv88e6097_port_pause_limit, 4399 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4400 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4401 .port_get_cmode = mv88e6352_port_get_cmode, 4402 .port_setup_message_port = mv88e6xxx_setup_message_port, 4403 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4404 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4405 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4406 .stats_get_strings = mv88e6095_stats_get_strings, 4407 .stats_get_stats = mv88e6095_stats_get_stats, 4408 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4409 .set_egress_port = mv88e6095_g1_set_egress_port, 4410 .watchdog_ops = &mv88e6097_watchdog_ops, 4411 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4412 .pot_clear = mv88e6xxx_g2_pot_clear, 4413 .reset = mv88e6352_g1_reset, 4414 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4415 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4416 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4417 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4418 .phylink_validate = mv88e6185_phylink_validate, 4419 }; 4420 4421 static const struct mv88e6xxx_ops mv88e6351_ops = { 4422 /* MV88E6XXX_FAMILY_6351 */ 4423 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4424 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4425 .irl_init_all = mv88e6352_g2_irl_init_all, 4426 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4427 .phy_read = mv88e6xxx_g2_smi_phy_read, 4428 .phy_write = mv88e6xxx_g2_smi_phy_write, 4429 .port_set_link = mv88e6xxx_port_set_link, 4430 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4431 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4432 .port_tag_remap = mv88e6095_port_tag_remap, 4433 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4434 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4435 .port_set_ether_type = mv88e6351_port_set_ether_type, 4436 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4437 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4438 .port_pause_limit = mv88e6097_port_pause_limit, 4439 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4440 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4441 .port_get_cmode = mv88e6352_port_get_cmode, 4442 .port_setup_message_port = mv88e6xxx_setup_message_port, 4443 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4444 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4445 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4446 .stats_get_strings = mv88e6095_stats_get_strings, 4447 .stats_get_stats = mv88e6095_stats_get_stats, 4448 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4449 .set_egress_port = mv88e6095_g1_set_egress_port, 4450 .watchdog_ops = &mv88e6097_watchdog_ops, 4451 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4452 .pot_clear = mv88e6xxx_g2_pot_clear, 4453 .reset = mv88e6352_g1_reset, 4454 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4455 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4456 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4457 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4458 .avb_ops = &mv88e6352_avb_ops, 4459 .ptp_ops = &mv88e6352_ptp_ops, 4460 .phylink_validate = mv88e6185_phylink_validate, 4461 }; 4462 4463 static const struct mv88e6xxx_ops mv88e6352_ops = { 4464 /* MV88E6XXX_FAMILY_6352 */ 4465 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4466 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4467 .irl_init_all = mv88e6352_g2_irl_init_all, 4468 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4469 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4470 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4471 .phy_read = mv88e6xxx_g2_smi_phy_read, 4472 .phy_write = mv88e6xxx_g2_smi_phy_write, 4473 .port_set_link = mv88e6xxx_port_set_link, 4474 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4475 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4476 .port_tag_remap = mv88e6095_port_tag_remap, 4477 .port_set_policy = mv88e6352_port_set_policy, 4478 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4479 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4480 .port_set_ether_type = mv88e6351_port_set_ether_type, 4481 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4482 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4483 .port_pause_limit = mv88e6097_port_pause_limit, 4484 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4485 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4486 .port_get_cmode = mv88e6352_port_get_cmode, 4487 .port_setup_message_port = mv88e6xxx_setup_message_port, 4488 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4489 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4490 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4491 .stats_get_strings = mv88e6095_stats_get_strings, 4492 .stats_get_stats = mv88e6095_stats_get_stats, 4493 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4494 .set_egress_port = mv88e6095_g1_set_egress_port, 4495 .watchdog_ops = &mv88e6097_watchdog_ops, 4496 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4497 .pot_clear = mv88e6xxx_g2_pot_clear, 4498 .reset = mv88e6352_g1_reset, 4499 .rmu_disable = mv88e6352_g1_rmu_disable, 4500 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4501 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4502 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4503 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4504 .serdes_get_lane = mv88e6352_serdes_get_lane, 4505 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4506 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4507 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4508 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4509 .serdes_power = mv88e6352_serdes_power, 4510 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4511 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4512 .serdes_irq_status = mv88e6352_serdes_irq_status, 4513 .gpio_ops = &mv88e6352_gpio_ops, 4514 .avb_ops = &mv88e6352_avb_ops, 4515 .ptp_ops = &mv88e6352_ptp_ops, 4516 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4517 .serdes_get_strings = mv88e6352_serdes_get_strings, 4518 .serdes_get_stats = mv88e6352_serdes_get_stats, 4519 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4520 .serdes_get_regs = mv88e6352_serdes_get_regs, 4521 .phylink_validate = mv88e6352_phylink_validate, 4522 }; 4523 4524 static const struct mv88e6xxx_ops mv88e6390_ops = { 4525 /* MV88E6XXX_FAMILY_6390 */ 4526 .setup_errata = mv88e6390_setup_errata, 4527 .irl_init_all = mv88e6390_g2_irl_init_all, 4528 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4529 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4530 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4531 .phy_read = mv88e6xxx_g2_smi_phy_read, 4532 .phy_write = mv88e6xxx_g2_smi_phy_write, 4533 .port_set_link = mv88e6xxx_port_set_link, 4534 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4535 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4536 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4537 .port_tag_remap = mv88e6390_port_tag_remap, 4538 .port_set_policy = mv88e6352_port_set_policy, 4539 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4540 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4541 .port_set_ether_type = mv88e6351_port_set_ether_type, 4542 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4543 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4544 .port_pause_limit = mv88e6390_port_pause_limit, 4545 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4546 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4547 .port_get_cmode = mv88e6352_port_get_cmode, 4548 .port_set_cmode = mv88e6390_port_set_cmode, 4549 .port_setup_message_port = mv88e6xxx_setup_message_port, 4550 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4551 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4552 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4553 .stats_get_strings = mv88e6320_stats_get_strings, 4554 .stats_get_stats = mv88e6390_stats_get_stats, 4555 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4556 .set_egress_port = mv88e6390_g1_set_egress_port, 4557 .watchdog_ops = &mv88e6390_watchdog_ops, 4558 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4559 .pot_clear = mv88e6xxx_g2_pot_clear, 4560 .reset = mv88e6352_g1_reset, 4561 .rmu_disable = mv88e6390_g1_rmu_disable, 4562 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4563 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4564 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4565 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4566 .serdes_power = mv88e6390_serdes_power, 4567 .serdes_get_lane = mv88e6390_serdes_get_lane, 4568 /* Check status register pause & lpa register */ 4569 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4570 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4571 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4572 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4573 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4574 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4575 .serdes_irq_status = mv88e6390_serdes_irq_status, 4576 .gpio_ops = &mv88e6352_gpio_ops, 4577 .avb_ops = &mv88e6390_avb_ops, 4578 .ptp_ops = &mv88e6352_ptp_ops, 4579 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4580 .serdes_get_strings = mv88e6390_serdes_get_strings, 4581 .serdes_get_stats = mv88e6390_serdes_get_stats, 4582 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4583 .serdes_get_regs = mv88e6390_serdes_get_regs, 4584 .phylink_validate = mv88e6390_phylink_validate, 4585 }; 4586 4587 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4588 /* MV88E6XXX_FAMILY_6390 */ 4589 .setup_errata = mv88e6390_setup_errata, 4590 .irl_init_all = mv88e6390_g2_irl_init_all, 4591 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4592 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4593 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4594 .phy_read = mv88e6xxx_g2_smi_phy_read, 4595 .phy_write = mv88e6xxx_g2_smi_phy_write, 4596 .port_set_link = mv88e6xxx_port_set_link, 4597 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4598 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4599 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4600 .port_tag_remap = mv88e6390_port_tag_remap, 4601 .port_set_policy = mv88e6352_port_set_policy, 4602 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4603 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4604 .port_set_ether_type = mv88e6351_port_set_ether_type, 4605 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4606 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4607 .port_pause_limit = mv88e6390_port_pause_limit, 4608 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4609 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4610 .port_get_cmode = mv88e6352_port_get_cmode, 4611 .port_set_cmode = mv88e6390x_port_set_cmode, 4612 .port_setup_message_port = mv88e6xxx_setup_message_port, 4613 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4614 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4615 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4616 .stats_get_strings = mv88e6320_stats_get_strings, 4617 .stats_get_stats = mv88e6390_stats_get_stats, 4618 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4619 .set_egress_port = mv88e6390_g1_set_egress_port, 4620 .watchdog_ops = &mv88e6390_watchdog_ops, 4621 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4622 .pot_clear = mv88e6xxx_g2_pot_clear, 4623 .reset = mv88e6352_g1_reset, 4624 .rmu_disable = mv88e6390_g1_rmu_disable, 4625 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4626 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4627 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4628 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4629 .serdes_power = mv88e6390_serdes_power, 4630 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4631 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4632 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4633 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4634 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4635 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4636 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4637 .serdes_irq_status = mv88e6390_serdes_irq_status, 4638 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4639 .serdes_get_strings = mv88e6390_serdes_get_strings, 4640 .serdes_get_stats = mv88e6390_serdes_get_stats, 4641 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4642 .serdes_get_regs = mv88e6390_serdes_get_regs, 4643 .gpio_ops = &mv88e6352_gpio_ops, 4644 .avb_ops = &mv88e6390_avb_ops, 4645 .ptp_ops = &mv88e6352_ptp_ops, 4646 .phylink_validate = mv88e6390x_phylink_validate, 4647 }; 4648 4649 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4650 [MV88E6085] = { 4651 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4652 .family = MV88E6XXX_FAMILY_6097, 4653 .name = "Marvell 88E6085", 4654 .num_databases = 4096, 4655 .num_macs = 8192, 4656 .num_ports = 10, 4657 .num_internal_phys = 5, 4658 .max_vid = 4095, 4659 .port_base_addr = 0x10, 4660 .phy_base_addr = 0x0, 4661 .global1_addr = 0x1b, 4662 .global2_addr = 0x1c, 4663 .age_time_coeff = 15000, 4664 .g1_irqs = 8, 4665 .g2_irqs = 10, 4666 .atu_move_port_mask = 0xf, 4667 .pvt = true, 4668 .multi_chip = true, 4669 .tag_protocol = DSA_TAG_PROTO_DSA, 4670 .ops = &mv88e6085_ops, 4671 }, 4672 4673 [MV88E6095] = { 4674 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4675 .family = MV88E6XXX_FAMILY_6095, 4676 .name = "Marvell 88E6095/88E6095F", 4677 .num_databases = 256, 4678 .num_macs = 8192, 4679 .num_ports = 11, 4680 .num_internal_phys = 0, 4681 .max_vid = 4095, 4682 .port_base_addr = 0x10, 4683 .phy_base_addr = 0x0, 4684 .global1_addr = 0x1b, 4685 .global2_addr = 0x1c, 4686 .age_time_coeff = 15000, 4687 .g1_irqs = 8, 4688 .atu_move_port_mask = 0xf, 4689 .multi_chip = true, 4690 .tag_protocol = DSA_TAG_PROTO_DSA, 4691 .ops = &mv88e6095_ops, 4692 }, 4693 4694 [MV88E6097] = { 4695 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4696 .family = MV88E6XXX_FAMILY_6097, 4697 .name = "Marvell 88E6097/88E6097F", 4698 .num_databases = 4096, 4699 .num_macs = 8192, 4700 .num_ports = 11, 4701 .num_internal_phys = 8, 4702 .max_vid = 4095, 4703 .port_base_addr = 0x10, 4704 .phy_base_addr = 0x0, 4705 .global1_addr = 0x1b, 4706 .global2_addr = 0x1c, 4707 .age_time_coeff = 15000, 4708 .g1_irqs = 8, 4709 .g2_irqs = 10, 4710 .atu_move_port_mask = 0xf, 4711 .pvt = true, 4712 .multi_chip = true, 4713 .tag_protocol = DSA_TAG_PROTO_EDSA, 4714 .ops = &mv88e6097_ops, 4715 }, 4716 4717 [MV88E6123] = { 4718 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4719 .family = MV88E6XXX_FAMILY_6165, 4720 .name = "Marvell 88E6123", 4721 .num_databases = 4096, 4722 .num_macs = 1024, 4723 .num_ports = 3, 4724 .num_internal_phys = 5, 4725 .max_vid = 4095, 4726 .port_base_addr = 0x10, 4727 .phy_base_addr = 0x0, 4728 .global1_addr = 0x1b, 4729 .global2_addr = 0x1c, 4730 .age_time_coeff = 15000, 4731 .g1_irqs = 9, 4732 .g2_irqs = 10, 4733 .atu_move_port_mask = 0xf, 4734 .pvt = true, 4735 .multi_chip = true, 4736 .tag_protocol = DSA_TAG_PROTO_EDSA, 4737 .ops = &mv88e6123_ops, 4738 }, 4739 4740 [MV88E6131] = { 4741 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4742 .family = MV88E6XXX_FAMILY_6185, 4743 .name = "Marvell 88E6131", 4744 .num_databases = 256, 4745 .num_macs = 8192, 4746 .num_ports = 8, 4747 .num_internal_phys = 0, 4748 .max_vid = 4095, 4749 .port_base_addr = 0x10, 4750 .phy_base_addr = 0x0, 4751 .global1_addr = 0x1b, 4752 .global2_addr = 0x1c, 4753 .age_time_coeff = 15000, 4754 .g1_irqs = 9, 4755 .atu_move_port_mask = 0xf, 4756 .multi_chip = true, 4757 .tag_protocol = DSA_TAG_PROTO_DSA, 4758 .ops = &mv88e6131_ops, 4759 }, 4760 4761 [MV88E6141] = { 4762 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4763 .family = MV88E6XXX_FAMILY_6341, 4764 .name = "Marvell 88E6141", 4765 .num_databases = 4096, 4766 .num_macs = 2048, 4767 .num_ports = 6, 4768 .num_internal_phys = 5, 4769 .num_gpio = 11, 4770 .max_vid = 4095, 4771 .port_base_addr = 0x10, 4772 .phy_base_addr = 0x10, 4773 .global1_addr = 0x1b, 4774 .global2_addr = 0x1c, 4775 .age_time_coeff = 3750, 4776 .atu_move_port_mask = 0x1f, 4777 .g1_irqs = 9, 4778 .g2_irqs = 10, 4779 .pvt = true, 4780 .multi_chip = true, 4781 .tag_protocol = DSA_TAG_PROTO_EDSA, 4782 .ops = &mv88e6141_ops, 4783 }, 4784 4785 [MV88E6161] = { 4786 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4787 .family = MV88E6XXX_FAMILY_6165, 4788 .name = "Marvell 88E6161", 4789 .num_databases = 4096, 4790 .num_macs = 1024, 4791 .num_ports = 6, 4792 .num_internal_phys = 5, 4793 .max_vid = 4095, 4794 .port_base_addr = 0x10, 4795 .phy_base_addr = 0x0, 4796 .global1_addr = 0x1b, 4797 .global2_addr = 0x1c, 4798 .age_time_coeff = 15000, 4799 .g1_irqs = 9, 4800 .g2_irqs = 10, 4801 .atu_move_port_mask = 0xf, 4802 .pvt = true, 4803 .multi_chip = true, 4804 .tag_protocol = DSA_TAG_PROTO_EDSA, 4805 .ptp_support = true, 4806 .ops = &mv88e6161_ops, 4807 }, 4808 4809 [MV88E6165] = { 4810 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4811 .family = MV88E6XXX_FAMILY_6165, 4812 .name = "Marvell 88E6165", 4813 .num_databases = 4096, 4814 .num_macs = 8192, 4815 .num_ports = 6, 4816 .num_internal_phys = 0, 4817 .max_vid = 4095, 4818 .port_base_addr = 0x10, 4819 .phy_base_addr = 0x0, 4820 .global1_addr = 0x1b, 4821 .global2_addr = 0x1c, 4822 .age_time_coeff = 15000, 4823 .g1_irqs = 9, 4824 .g2_irqs = 10, 4825 .atu_move_port_mask = 0xf, 4826 .pvt = true, 4827 .multi_chip = true, 4828 .tag_protocol = DSA_TAG_PROTO_DSA, 4829 .ptp_support = true, 4830 .ops = &mv88e6165_ops, 4831 }, 4832 4833 [MV88E6171] = { 4834 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4835 .family = MV88E6XXX_FAMILY_6351, 4836 .name = "Marvell 88E6171", 4837 .num_databases = 4096, 4838 .num_macs = 8192, 4839 .num_ports = 7, 4840 .num_internal_phys = 5, 4841 .max_vid = 4095, 4842 .port_base_addr = 0x10, 4843 .phy_base_addr = 0x0, 4844 .global1_addr = 0x1b, 4845 .global2_addr = 0x1c, 4846 .age_time_coeff = 15000, 4847 .g1_irqs = 9, 4848 .g2_irqs = 10, 4849 .atu_move_port_mask = 0xf, 4850 .pvt = true, 4851 .multi_chip = true, 4852 .tag_protocol = DSA_TAG_PROTO_EDSA, 4853 .ops = &mv88e6171_ops, 4854 }, 4855 4856 [MV88E6172] = { 4857 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4858 .family = MV88E6XXX_FAMILY_6352, 4859 .name = "Marvell 88E6172", 4860 .num_databases = 4096, 4861 .num_macs = 8192, 4862 .num_ports = 7, 4863 .num_internal_phys = 5, 4864 .num_gpio = 15, 4865 .max_vid = 4095, 4866 .port_base_addr = 0x10, 4867 .phy_base_addr = 0x0, 4868 .global1_addr = 0x1b, 4869 .global2_addr = 0x1c, 4870 .age_time_coeff = 15000, 4871 .g1_irqs = 9, 4872 .g2_irqs = 10, 4873 .atu_move_port_mask = 0xf, 4874 .pvt = true, 4875 .multi_chip = true, 4876 .tag_protocol = DSA_TAG_PROTO_EDSA, 4877 .ops = &mv88e6172_ops, 4878 }, 4879 4880 [MV88E6175] = { 4881 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4882 .family = MV88E6XXX_FAMILY_6351, 4883 .name = "Marvell 88E6175", 4884 .num_databases = 4096, 4885 .num_macs = 8192, 4886 .num_ports = 7, 4887 .num_internal_phys = 5, 4888 .max_vid = 4095, 4889 .port_base_addr = 0x10, 4890 .phy_base_addr = 0x0, 4891 .global1_addr = 0x1b, 4892 .global2_addr = 0x1c, 4893 .age_time_coeff = 15000, 4894 .g1_irqs = 9, 4895 .g2_irqs = 10, 4896 .atu_move_port_mask = 0xf, 4897 .pvt = true, 4898 .multi_chip = true, 4899 .tag_protocol = DSA_TAG_PROTO_EDSA, 4900 .ops = &mv88e6175_ops, 4901 }, 4902 4903 [MV88E6176] = { 4904 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4905 .family = MV88E6XXX_FAMILY_6352, 4906 .name = "Marvell 88E6176", 4907 .num_databases = 4096, 4908 .num_macs = 8192, 4909 .num_ports = 7, 4910 .num_internal_phys = 5, 4911 .num_gpio = 15, 4912 .max_vid = 4095, 4913 .port_base_addr = 0x10, 4914 .phy_base_addr = 0x0, 4915 .global1_addr = 0x1b, 4916 .global2_addr = 0x1c, 4917 .age_time_coeff = 15000, 4918 .g1_irqs = 9, 4919 .g2_irqs = 10, 4920 .atu_move_port_mask = 0xf, 4921 .pvt = true, 4922 .multi_chip = true, 4923 .tag_protocol = DSA_TAG_PROTO_EDSA, 4924 .ops = &mv88e6176_ops, 4925 }, 4926 4927 [MV88E6185] = { 4928 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4929 .family = MV88E6XXX_FAMILY_6185, 4930 .name = "Marvell 88E6185", 4931 .num_databases = 256, 4932 .num_macs = 8192, 4933 .num_ports = 10, 4934 .num_internal_phys = 0, 4935 .max_vid = 4095, 4936 .port_base_addr = 0x10, 4937 .phy_base_addr = 0x0, 4938 .global1_addr = 0x1b, 4939 .global2_addr = 0x1c, 4940 .age_time_coeff = 15000, 4941 .g1_irqs = 8, 4942 .atu_move_port_mask = 0xf, 4943 .multi_chip = true, 4944 .tag_protocol = DSA_TAG_PROTO_EDSA, 4945 .ops = &mv88e6185_ops, 4946 }, 4947 4948 [MV88E6190] = { 4949 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4950 .family = MV88E6XXX_FAMILY_6390, 4951 .name = "Marvell 88E6190", 4952 .num_databases = 4096, 4953 .num_macs = 16384, 4954 .num_ports = 11, /* 10 + Z80 */ 4955 .num_internal_phys = 9, 4956 .num_gpio = 16, 4957 .max_vid = 8191, 4958 .port_base_addr = 0x0, 4959 .phy_base_addr = 0x0, 4960 .global1_addr = 0x1b, 4961 .global2_addr = 0x1c, 4962 .tag_protocol = DSA_TAG_PROTO_DSA, 4963 .age_time_coeff = 3750, 4964 .g1_irqs = 9, 4965 .g2_irqs = 14, 4966 .pvt = true, 4967 .multi_chip = true, 4968 .atu_move_port_mask = 0x1f, 4969 .ops = &mv88e6190_ops, 4970 }, 4971 4972 [MV88E6190X] = { 4973 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4974 .family = MV88E6XXX_FAMILY_6390, 4975 .name = "Marvell 88E6190X", 4976 .num_databases = 4096, 4977 .num_macs = 16384, 4978 .num_ports = 11, /* 10 + Z80 */ 4979 .num_internal_phys = 9, 4980 .num_gpio = 16, 4981 .max_vid = 8191, 4982 .port_base_addr = 0x0, 4983 .phy_base_addr = 0x0, 4984 .global1_addr = 0x1b, 4985 .global2_addr = 0x1c, 4986 .age_time_coeff = 3750, 4987 .g1_irqs = 9, 4988 .g2_irqs = 14, 4989 .atu_move_port_mask = 0x1f, 4990 .pvt = true, 4991 .multi_chip = true, 4992 .tag_protocol = DSA_TAG_PROTO_DSA, 4993 .ops = &mv88e6190x_ops, 4994 }, 4995 4996 [MV88E6191] = { 4997 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4998 .family = MV88E6XXX_FAMILY_6390, 4999 .name = "Marvell 88E6191", 5000 .num_databases = 4096, 5001 .num_macs = 16384, 5002 .num_ports = 11, /* 10 + Z80 */ 5003 .num_internal_phys = 9, 5004 .max_vid = 8191, 5005 .port_base_addr = 0x0, 5006 .phy_base_addr = 0x0, 5007 .global1_addr = 0x1b, 5008 .global2_addr = 0x1c, 5009 .age_time_coeff = 3750, 5010 .g1_irqs = 9, 5011 .g2_irqs = 14, 5012 .atu_move_port_mask = 0x1f, 5013 .pvt = true, 5014 .multi_chip = true, 5015 .tag_protocol = DSA_TAG_PROTO_DSA, 5016 .ptp_support = true, 5017 .ops = &mv88e6191_ops, 5018 }, 5019 5020 [MV88E6220] = { 5021 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5022 .family = MV88E6XXX_FAMILY_6250, 5023 .name = "Marvell 88E6220", 5024 .num_databases = 64, 5025 5026 /* Ports 2-4 are not routed to pins 5027 * => usable ports 0, 1, 5, 6 5028 */ 5029 .num_ports = 7, 5030 .num_internal_phys = 2, 5031 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5032 .max_vid = 4095, 5033 .port_base_addr = 0x08, 5034 .phy_base_addr = 0x00, 5035 .global1_addr = 0x0f, 5036 .global2_addr = 0x07, 5037 .age_time_coeff = 15000, 5038 .g1_irqs = 9, 5039 .g2_irqs = 10, 5040 .atu_move_port_mask = 0xf, 5041 .dual_chip = true, 5042 .tag_protocol = DSA_TAG_PROTO_DSA, 5043 .ptp_support = true, 5044 .ops = &mv88e6250_ops, 5045 }, 5046 5047 [MV88E6240] = { 5048 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5049 .family = MV88E6XXX_FAMILY_6352, 5050 .name = "Marvell 88E6240", 5051 .num_databases = 4096, 5052 .num_macs = 8192, 5053 .num_ports = 7, 5054 .num_internal_phys = 5, 5055 .num_gpio = 15, 5056 .max_vid = 4095, 5057 .port_base_addr = 0x10, 5058 .phy_base_addr = 0x0, 5059 .global1_addr = 0x1b, 5060 .global2_addr = 0x1c, 5061 .age_time_coeff = 15000, 5062 .g1_irqs = 9, 5063 .g2_irqs = 10, 5064 .atu_move_port_mask = 0xf, 5065 .pvt = true, 5066 .multi_chip = true, 5067 .tag_protocol = DSA_TAG_PROTO_EDSA, 5068 .ptp_support = true, 5069 .ops = &mv88e6240_ops, 5070 }, 5071 5072 [MV88E6250] = { 5073 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5074 .family = MV88E6XXX_FAMILY_6250, 5075 .name = "Marvell 88E6250", 5076 .num_databases = 64, 5077 .num_ports = 7, 5078 .num_internal_phys = 5, 5079 .max_vid = 4095, 5080 .port_base_addr = 0x08, 5081 .phy_base_addr = 0x00, 5082 .global1_addr = 0x0f, 5083 .global2_addr = 0x07, 5084 .age_time_coeff = 15000, 5085 .g1_irqs = 9, 5086 .g2_irqs = 10, 5087 .atu_move_port_mask = 0xf, 5088 .dual_chip = true, 5089 .tag_protocol = DSA_TAG_PROTO_DSA, 5090 .ptp_support = true, 5091 .ops = &mv88e6250_ops, 5092 }, 5093 5094 [MV88E6290] = { 5095 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5096 .family = MV88E6XXX_FAMILY_6390, 5097 .name = "Marvell 88E6290", 5098 .num_databases = 4096, 5099 .num_ports = 11, /* 10 + Z80 */ 5100 .num_internal_phys = 9, 5101 .num_gpio = 16, 5102 .max_vid = 8191, 5103 .port_base_addr = 0x0, 5104 .phy_base_addr = 0x0, 5105 .global1_addr = 0x1b, 5106 .global2_addr = 0x1c, 5107 .age_time_coeff = 3750, 5108 .g1_irqs = 9, 5109 .g2_irqs = 14, 5110 .atu_move_port_mask = 0x1f, 5111 .pvt = true, 5112 .multi_chip = true, 5113 .tag_protocol = DSA_TAG_PROTO_DSA, 5114 .ptp_support = true, 5115 .ops = &mv88e6290_ops, 5116 }, 5117 5118 [MV88E6320] = { 5119 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5120 .family = MV88E6XXX_FAMILY_6320, 5121 .name = "Marvell 88E6320", 5122 .num_databases = 4096, 5123 .num_macs = 8192, 5124 .num_ports = 7, 5125 .num_internal_phys = 5, 5126 .num_gpio = 15, 5127 .max_vid = 4095, 5128 .port_base_addr = 0x10, 5129 .phy_base_addr = 0x0, 5130 .global1_addr = 0x1b, 5131 .global2_addr = 0x1c, 5132 .age_time_coeff = 15000, 5133 .g1_irqs = 8, 5134 .g2_irqs = 10, 5135 .atu_move_port_mask = 0xf, 5136 .pvt = true, 5137 .multi_chip = true, 5138 .tag_protocol = DSA_TAG_PROTO_EDSA, 5139 .ptp_support = true, 5140 .ops = &mv88e6320_ops, 5141 }, 5142 5143 [MV88E6321] = { 5144 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5145 .family = MV88E6XXX_FAMILY_6320, 5146 .name = "Marvell 88E6321", 5147 .num_databases = 4096, 5148 .num_macs = 8192, 5149 .num_ports = 7, 5150 .num_internal_phys = 5, 5151 .num_gpio = 15, 5152 .max_vid = 4095, 5153 .port_base_addr = 0x10, 5154 .phy_base_addr = 0x0, 5155 .global1_addr = 0x1b, 5156 .global2_addr = 0x1c, 5157 .age_time_coeff = 15000, 5158 .g1_irqs = 8, 5159 .g2_irqs = 10, 5160 .atu_move_port_mask = 0xf, 5161 .multi_chip = true, 5162 .tag_protocol = DSA_TAG_PROTO_EDSA, 5163 .ptp_support = true, 5164 .ops = &mv88e6321_ops, 5165 }, 5166 5167 [MV88E6341] = { 5168 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5169 .family = MV88E6XXX_FAMILY_6341, 5170 .name = "Marvell 88E6341", 5171 .num_databases = 4096, 5172 .num_macs = 2048, 5173 .num_internal_phys = 5, 5174 .num_ports = 6, 5175 .num_gpio = 11, 5176 .max_vid = 4095, 5177 .port_base_addr = 0x10, 5178 .phy_base_addr = 0x10, 5179 .global1_addr = 0x1b, 5180 .global2_addr = 0x1c, 5181 .age_time_coeff = 3750, 5182 .atu_move_port_mask = 0x1f, 5183 .g1_irqs = 9, 5184 .g2_irqs = 10, 5185 .pvt = true, 5186 .multi_chip = true, 5187 .tag_protocol = DSA_TAG_PROTO_EDSA, 5188 .ptp_support = true, 5189 .ops = &mv88e6341_ops, 5190 }, 5191 5192 [MV88E6350] = { 5193 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5194 .family = MV88E6XXX_FAMILY_6351, 5195 .name = "Marvell 88E6350", 5196 .num_databases = 4096, 5197 .num_macs = 8192, 5198 .num_ports = 7, 5199 .num_internal_phys = 5, 5200 .max_vid = 4095, 5201 .port_base_addr = 0x10, 5202 .phy_base_addr = 0x0, 5203 .global1_addr = 0x1b, 5204 .global2_addr = 0x1c, 5205 .age_time_coeff = 15000, 5206 .g1_irqs = 9, 5207 .g2_irqs = 10, 5208 .atu_move_port_mask = 0xf, 5209 .pvt = true, 5210 .multi_chip = true, 5211 .tag_protocol = DSA_TAG_PROTO_EDSA, 5212 .ops = &mv88e6350_ops, 5213 }, 5214 5215 [MV88E6351] = { 5216 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5217 .family = MV88E6XXX_FAMILY_6351, 5218 .name = "Marvell 88E6351", 5219 .num_databases = 4096, 5220 .num_macs = 8192, 5221 .num_ports = 7, 5222 .num_internal_phys = 5, 5223 .max_vid = 4095, 5224 .port_base_addr = 0x10, 5225 .phy_base_addr = 0x0, 5226 .global1_addr = 0x1b, 5227 .global2_addr = 0x1c, 5228 .age_time_coeff = 15000, 5229 .g1_irqs = 9, 5230 .g2_irqs = 10, 5231 .atu_move_port_mask = 0xf, 5232 .pvt = true, 5233 .multi_chip = true, 5234 .tag_protocol = DSA_TAG_PROTO_EDSA, 5235 .ops = &mv88e6351_ops, 5236 }, 5237 5238 [MV88E6352] = { 5239 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5240 .family = MV88E6XXX_FAMILY_6352, 5241 .name = "Marvell 88E6352", 5242 .num_databases = 4096, 5243 .num_macs = 8192, 5244 .num_ports = 7, 5245 .num_internal_phys = 5, 5246 .num_gpio = 15, 5247 .max_vid = 4095, 5248 .port_base_addr = 0x10, 5249 .phy_base_addr = 0x0, 5250 .global1_addr = 0x1b, 5251 .global2_addr = 0x1c, 5252 .age_time_coeff = 15000, 5253 .g1_irqs = 9, 5254 .g2_irqs = 10, 5255 .atu_move_port_mask = 0xf, 5256 .pvt = true, 5257 .multi_chip = true, 5258 .tag_protocol = DSA_TAG_PROTO_EDSA, 5259 .ptp_support = true, 5260 .ops = &mv88e6352_ops, 5261 }, 5262 [MV88E6390] = { 5263 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5264 .family = MV88E6XXX_FAMILY_6390, 5265 .name = "Marvell 88E6390", 5266 .num_databases = 4096, 5267 .num_macs = 16384, 5268 .num_ports = 11, /* 10 + Z80 */ 5269 .num_internal_phys = 9, 5270 .num_gpio = 16, 5271 .max_vid = 8191, 5272 .port_base_addr = 0x0, 5273 .phy_base_addr = 0x0, 5274 .global1_addr = 0x1b, 5275 .global2_addr = 0x1c, 5276 .age_time_coeff = 3750, 5277 .g1_irqs = 9, 5278 .g2_irqs = 14, 5279 .atu_move_port_mask = 0x1f, 5280 .pvt = true, 5281 .multi_chip = true, 5282 .tag_protocol = DSA_TAG_PROTO_DSA, 5283 .ptp_support = true, 5284 .ops = &mv88e6390_ops, 5285 }, 5286 [MV88E6390X] = { 5287 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5288 .family = MV88E6XXX_FAMILY_6390, 5289 .name = "Marvell 88E6390X", 5290 .num_databases = 4096, 5291 .num_macs = 16384, 5292 .num_ports = 11, /* 10 + Z80 */ 5293 .num_internal_phys = 9, 5294 .num_gpio = 16, 5295 .max_vid = 8191, 5296 .port_base_addr = 0x0, 5297 .phy_base_addr = 0x0, 5298 .global1_addr = 0x1b, 5299 .global2_addr = 0x1c, 5300 .age_time_coeff = 3750, 5301 .g1_irqs = 9, 5302 .g2_irqs = 14, 5303 .atu_move_port_mask = 0x1f, 5304 .pvt = true, 5305 .multi_chip = true, 5306 .tag_protocol = DSA_TAG_PROTO_DSA, 5307 .ptp_support = true, 5308 .ops = &mv88e6390x_ops, 5309 }, 5310 }; 5311 5312 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5313 { 5314 int i; 5315 5316 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5317 if (mv88e6xxx_table[i].prod_num == prod_num) 5318 return &mv88e6xxx_table[i]; 5319 5320 return NULL; 5321 } 5322 5323 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5324 { 5325 const struct mv88e6xxx_info *info; 5326 unsigned int prod_num, rev; 5327 u16 id; 5328 int err; 5329 5330 mv88e6xxx_reg_lock(chip); 5331 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5332 mv88e6xxx_reg_unlock(chip); 5333 if (err) 5334 return err; 5335 5336 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5337 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5338 5339 info = mv88e6xxx_lookup_info(prod_num); 5340 if (!info) 5341 return -ENODEV; 5342 5343 /* Update the compatible info with the probed one */ 5344 chip->info = info; 5345 5346 err = mv88e6xxx_g2_require(chip); 5347 if (err) 5348 return err; 5349 5350 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5351 chip->info->prod_num, chip->info->name, rev); 5352 5353 return 0; 5354 } 5355 5356 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5357 { 5358 struct mv88e6xxx_chip *chip; 5359 5360 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5361 if (!chip) 5362 return NULL; 5363 5364 chip->dev = dev; 5365 5366 mutex_init(&chip->reg_lock); 5367 INIT_LIST_HEAD(&chip->mdios); 5368 idr_init(&chip->policies); 5369 5370 return chip; 5371 } 5372 5373 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5374 int port, 5375 enum dsa_tag_protocol m) 5376 { 5377 struct mv88e6xxx_chip *chip = ds->priv; 5378 5379 return chip->info->tag_protocol; 5380 } 5381 5382 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 5383 const struct switchdev_obj_port_mdb *mdb) 5384 { 5385 /* We don't need any dynamic resource from the kernel (yet), 5386 * so skip the prepare phase. 5387 */ 5388 5389 return 0; 5390 } 5391 5392 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5393 const struct switchdev_obj_port_mdb *mdb) 5394 { 5395 struct mv88e6xxx_chip *chip = ds->priv; 5396 5397 mv88e6xxx_reg_lock(chip); 5398 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5399 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 5400 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 5401 port); 5402 mv88e6xxx_reg_unlock(chip); 5403 } 5404 5405 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5406 const struct switchdev_obj_port_mdb *mdb) 5407 { 5408 struct mv88e6xxx_chip *chip = ds->priv; 5409 int err; 5410 5411 mv88e6xxx_reg_lock(chip); 5412 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5413 mv88e6xxx_reg_unlock(chip); 5414 5415 return err; 5416 } 5417 5418 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5419 struct dsa_mall_mirror_tc_entry *mirror, 5420 bool ingress) 5421 { 5422 enum mv88e6xxx_egress_direction direction = ingress ? 5423 MV88E6XXX_EGRESS_DIR_INGRESS : 5424 MV88E6XXX_EGRESS_DIR_EGRESS; 5425 struct mv88e6xxx_chip *chip = ds->priv; 5426 bool other_mirrors = false; 5427 int i; 5428 int err; 5429 5430 if (!chip->info->ops->set_egress_port) 5431 return -EOPNOTSUPP; 5432 5433 mutex_lock(&chip->reg_lock); 5434 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5435 mirror->to_local_port) { 5436 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5437 other_mirrors |= ingress ? 5438 chip->ports[i].mirror_ingress : 5439 chip->ports[i].mirror_egress; 5440 5441 /* Can't change egress port when other mirror is active */ 5442 if (other_mirrors) { 5443 err = -EBUSY; 5444 goto out; 5445 } 5446 5447 err = chip->info->ops->set_egress_port(chip, 5448 direction, 5449 mirror->to_local_port); 5450 if (err) 5451 goto out; 5452 } 5453 5454 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5455 out: 5456 mutex_unlock(&chip->reg_lock); 5457 5458 return err; 5459 } 5460 5461 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5462 struct dsa_mall_mirror_tc_entry *mirror) 5463 { 5464 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5465 MV88E6XXX_EGRESS_DIR_INGRESS : 5466 MV88E6XXX_EGRESS_DIR_EGRESS; 5467 struct mv88e6xxx_chip *chip = ds->priv; 5468 bool other_mirrors = false; 5469 int i; 5470 5471 mutex_lock(&chip->reg_lock); 5472 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5473 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5474 5475 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5476 other_mirrors |= mirror->ingress ? 5477 chip->ports[i].mirror_ingress : 5478 chip->ports[i].mirror_egress; 5479 5480 /* Reset egress port when no other mirror is active */ 5481 if (!other_mirrors) { 5482 if (chip->info->ops->set_egress_port(chip, 5483 direction, 5484 dsa_upstream_port(ds, 5485 port))) 5486 dev_err(ds->dev, "failed to set egress port\n"); 5487 } 5488 5489 mutex_unlock(&chip->reg_lock); 5490 } 5491 5492 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 5493 bool unicast, bool multicast) 5494 { 5495 struct mv88e6xxx_chip *chip = ds->priv; 5496 int err = -EOPNOTSUPP; 5497 5498 mv88e6xxx_reg_lock(chip); 5499 if (chip->info->ops->port_set_egress_floods) 5500 err = chip->info->ops->port_set_egress_floods(chip, port, 5501 unicast, 5502 multicast); 5503 mv88e6xxx_reg_unlock(chip); 5504 5505 return err; 5506 } 5507 5508 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 5509 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 5510 .setup = mv88e6xxx_setup, 5511 .teardown = mv88e6xxx_teardown, 5512 .phylink_validate = mv88e6xxx_validate, 5513 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 5514 .phylink_mac_config = mv88e6xxx_mac_config, 5515 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 5516 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 5517 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 5518 .get_strings = mv88e6xxx_get_strings, 5519 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 5520 .get_sset_count = mv88e6xxx_get_sset_count, 5521 .port_enable = mv88e6xxx_port_enable, 5522 .port_disable = mv88e6xxx_port_disable, 5523 .get_mac_eee = mv88e6xxx_get_mac_eee, 5524 .set_mac_eee = mv88e6xxx_set_mac_eee, 5525 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 5526 .get_eeprom = mv88e6xxx_get_eeprom, 5527 .set_eeprom = mv88e6xxx_set_eeprom, 5528 .get_regs_len = mv88e6xxx_get_regs_len, 5529 .get_regs = mv88e6xxx_get_regs, 5530 .get_rxnfc = mv88e6xxx_get_rxnfc, 5531 .set_rxnfc = mv88e6xxx_set_rxnfc, 5532 .set_ageing_time = mv88e6xxx_set_ageing_time, 5533 .port_bridge_join = mv88e6xxx_port_bridge_join, 5534 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 5535 .port_egress_floods = mv88e6xxx_port_egress_floods, 5536 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 5537 .port_fast_age = mv88e6xxx_port_fast_age, 5538 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 5539 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 5540 .port_vlan_add = mv88e6xxx_port_vlan_add, 5541 .port_vlan_del = mv88e6xxx_port_vlan_del, 5542 .port_fdb_add = mv88e6xxx_port_fdb_add, 5543 .port_fdb_del = mv88e6xxx_port_fdb_del, 5544 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 5545 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 5546 .port_mdb_add = mv88e6xxx_port_mdb_add, 5547 .port_mdb_del = mv88e6xxx_port_mdb_del, 5548 .port_mirror_add = mv88e6xxx_port_mirror_add, 5549 .port_mirror_del = mv88e6xxx_port_mirror_del, 5550 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 5551 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 5552 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 5553 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 5554 .port_txtstamp = mv88e6xxx_port_txtstamp, 5555 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 5556 .get_ts_info = mv88e6xxx_get_ts_info, 5557 .devlink_param_get = mv88e6xxx_devlink_param_get, 5558 .devlink_param_set = mv88e6xxx_devlink_param_set, 5559 }; 5560 5561 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 5562 { 5563 struct device *dev = chip->dev; 5564 struct dsa_switch *ds; 5565 5566 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 5567 if (!ds) 5568 return -ENOMEM; 5569 5570 ds->dev = dev; 5571 ds->num_ports = mv88e6xxx_num_ports(chip); 5572 ds->priv = chip; 5573 ds->dev = dev; 5574 ds->ops = &mv88e6xxx_switch_ops; 5575 ds->ageing_time_min = chip->info->age_time_coeff; 5576 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 5577 5578 dev_set_drvdata(dev, ds); 5579 5580 return dsa_register_switch(ds); 5581 } 5582 5583 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 5584 { 5585 dsa_unregister_switch(chip->ds); 5586 } 5587 5588 static const void *pdata_device_get_match_data(struct device *dev) 5589 { 5590 const struct of_device_id *matches = dev->driver->of_match_table; 5591 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 5592 5593 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 5594 matches++) { 5595 if (!strcmp(pdata->compatible, matches->compatible)) 5596 return matches->data; 5597 } 5598 return NULL; 5599 } 5600 5601 /* There is no suspend to RAM support at DSA level yet, the switch configuration 5602 * would be lost after a power cycle so prevent it to be suspended. 5603 */ 5604 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 5605 { 5606 return -EOPNOTSUPP; 5607 } 5608 5609 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 5610 { 5611 return 0; 5612 } 5613 5614 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 5615 5616 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 5617 { 5618 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 5619 const struct mv88e6xxx_info *compat_info = NULL; 5620 struct device *dev = &mdiodev->dev; 5621 struct device_node *np = dev->of_node; 5622 struct mv88e6xxx_chip *chip; 5623 int port; 5624 int err; 5625 5626 if (!np && !pdata) 5627 return -EINVAL; 5628 5629 if (np) 5630 compat_info = of_device_get_match_data(dev); 5631 5632 if (pdata) { 5633 compat_info = pdata_device_get_match_data(dev); 5634 5635 if (!pdata->netdev) 5636 return -EINVAL; 5637 5638 for (port = 0; port < DSA_MAX_PORTS; port++) { 5639 if (!(pdata->enabled_ports & (1 << port))) 5640 continue; 5641 if (strcmp(pdata->cd.port_names[port], "cpu")) 5642 continue; 5643 pdata->cd.netdev[port] = &pdata->netdev->dev; 5644 break; 5645 } 5646 } 5647 5648 if (!compat_info) 5649 return -EINVAL; 5650 5651 chip = mv88e6xxx_alloc_chip(dev); 5652 if (!chip) { 5653 err = -ENOMEM; 5654 goto out; 5655 } 5656 5657 chip->info = compat_info; 5658 5659 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 5660 if (err) 5661 goto out; 5662 5663 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 5664 if (IS_ERR(chip->reset)) { 5665 err = PTR_ERR(chip->reset); 5666 goto out; 5667 } 5668 if (chip->reset) 5669 usleep_range(1000, 2000); 5670 5671 err = mv88e6xxx_detect(chip); 5672 if (err) 5673 goto out; 5674 5675 mv88e6xxx_phy_init(chip); 5676 5677 if (chip->info->ops->get_eeprom) { 5678 if (np) 5679 of_property_read_u32(np, "eeprom-length", 5680 &chip->eeprom_len); 5681 else 5682 chip->eeprom_len = pdata->eeprom_len; 5683 } 5684 5685 mv88e6xxx_reg_lock(chip); 5686 err = mv88e6xxx_switch_reset(chip); 5687 mv88e6xxx_reg_unlock(chip); 5688 if (err) 5689 goto out; 5690 5691 if (np) { 5692 chip->irq = of_irq_get(np, 0); 5693 if (chip->irq == -EPROBE_DEFER) { 5694 err = chip->irq; 5695 goto out; 5696 } 5697 } 5698 5699 if (pdata) 5700 chip->irq = pdata->irq; 5701 5702 /* Has to be performed before the MDIO bus is created, because 5703 * the PHYs will link their interrupts to these interrupt 5704 * controllers 5705 */ 5706 mv88e6xxx_reg_lock(chip); 5707 if (chip->irq > 0) 5708 err = mv88e6xxx_g1_irq_setup(chip); 5709 else 5710 err = mv88e6xxx_irq_poll_setup(chip); 5711 mv88e6xxx_reg_unlock(chip); 5712 5713 if (err) 5714 goto out; 5715 5716 if (chip->info->g2_irqs > 0) { 5717 err = mv88e6xxx_g2_irq_setup(chip); 5718 if (err) 5719 goto out_g1_irq; 5720 } 5721 5722 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 5723 if (err) 5724 goto out_g2_irq; 5725 5726 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 5727 if (err) 5728 goto out_g1_atu_prob_irq; 5729 5730 err = mv88e6xxx_mdios_register(chip, np); 5731 if (err) 5732 goto out_g1_vtu_prob_irq; 5733 5734 err = mv88e6xxx_register_switch(chip); 5735 if (err) 5736 goto out_mdio; 5737 5738 return 0; 5739 5740 out_mdio: 5741 mv88e6xxx_mdios_unregister(chip); 5742 out_g1_vtu_prob_irq: 5743 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5744 out_g1_atu_prob_irq: 5745 mv88e6xxx_g1_atu_prob_irq_free(chip); 5746 out_g2_irq: 5747 if (chip->info->g2_irqs > 0) 5748 mv88e6xxx_g2_irq_free(chip); 5749 out_g1_irq: 5750 if (chip->irq > 0) 5751 mv88e6xxx_g1_irq_free(chip); 5752 else 5753 mv88e6xxx_irq_poll_free(chip); 5754 out: 5755 if (pdata) 5756 dev_put(pdata->netdev); 5757 5758 return err; 5759 } 5760 5761 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5762 { 5763 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5764 struct mv88e6xxx_chip *chip = ds->priv; 5765 5766 if (chip->info->ptp_support) { 5767 mv88e6xxx_hwtstamp_free(chip); 5768 mv88e6xxx_ptp_free(chip); 5769 } 5770 5771 mv88e6xxx_phy_destroy(chip); 5772 mv88e6xxx_unregister_switch(chip); 5773 mv88e6xxx_mdios_unregister(chip); 5774 5775 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5776 mv88e6xxx_g1_atu_prob_irq_free(chip); 5777 5778 if (chip->info->g2_irqs > 0) 5779 mv88e6xxx_g2_irq_free(chip); 5780 5781 if (chip->irq > 0) 5782 mv88e6xxx_g1_irq_free(chip); 5783 else 5784 mv88e6xxx_irq_poll_free(chip); 5785 } 5786 5787 static const struct of_device_id mv88e6xxx_of_match[] = { 5788 { 5789 .compatible = "marvell,mv88e6085", 5790 .data = &mv88e6xxx_table[MV88E6085], 5791 }, 5792 { 5793 .compatible = "marvell,mv88e6190", 5794 .data = &mv88e6xxx_table[MV88E6190], 5795 }, 5796 { 5797 .compatible = "marvell,mv88e6250", 5798 .data = &mv88e6xxx_table[MV88E6250], 5799 }, 5800 { /* sentinel */ }, 5801 }; 5802 5803 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5804 5805 static struct mdio_driver mv88e6xxx_driver = { 5806 .probe = mv88e6xxx_probe, 5807 .remove = mv88e6xxx_remove, 5808 .mdiodrv.driver = { 5809 .name = "mv88e6085", 5810 .of_match_table = mv88e6xxx_of_match, 5811 .pm = &mv88e6xxx_pm_ops, 5812 }, 5813 }; 5814 5815 mdio_module_driver(mv88e6xxx_driver); 5816 5817 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5818 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5819 MODULE_LICENSE("GPL"); 5820