1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 9#include <dt-bindings/clock/qcom,gcc-sdm845.h> 10#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 11#include <dt-bindings/clock/qcom,lpass-sdm845.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/clock/qcom,videocc-sdm845.h> 14#include <dt-bindings/interconnect/qcom,sdm845.h> 15#include <dt-bindings/interrupt-controller/arm-gic.h> 16#include <dt-bindings/phy/phy-qcom-qusb2.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/reset/qcom,sdm845-aoss.h> 19#include <dt-bindings/reset/qcom,sdm845-pdc.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21#include <dt-bindings/clock/qcom,gcc-sdm845.h> 22#include <dt-bindings/thermal/thermal.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 i2c5 = &i2c5; 37 i2c6 = &i2c6; 38 i2c7 = &i2c7; 39 i2c8 = &i2c8; 40 i2c9 = &i2c9; 41 i2c10 = &i2c10; 42 i2c11 = &i2c11; 43 i2c12 = &i2c12; 44 i2c13 = &i2c13; 45 i2c14 = &i2c14; 46 i2c15 = &i2c15; 47 spi0 = &spi0; 48 spi1 = &spi1; 49 spi2 = &spi2; 50 spi3 = &spi3; 51 spi4 = &spi4; 52 spi5 = &spi5; 53 spi6 = &spi6; 54 spi7 = &spi7; 55 spi8 = &spi8; 56 spi9 = &spi9; 57 spi10 = &spi10; 58 spi11 = &spi11; 59 spi12 = &spi12; 60 spi13 = &spi13; 61 spi14 = &spi14; 62 spi15 = &spi15; 63 }; 64 65 chosen { }; 66 67 memory@80000000 { 68 device_type = "memory"; 69 /* We expect the bootloader to fill in the size */ 70 reg = <0 0x80000000 0 0>; 71 }; 72 73 reserved-memory { 74 #address-cells = <2>; 75 #size-cells = <2>; 76 ranges; 77 78 hyp_mem: memory@85700000 { 79 reg = <0 0x85700000 0 0x600000>; 80 no-map; 81 }; 82 83 xbl_mem: memory@85e00000 { 84 reg = <0 0x85e00000 0 0x100000>; 85 no-map; 86 }; 87 88 aop_mem: memory@85fc0000 { 89 reg = <0 0x85fc0000 0 0x20000>; 90 no-map; 91 }; 92 93 aop_cmd_db_mem: memory@85fe0000 { 94 compatible = "qcom,cmd-db"; 95 reg = <0x0 0x85fe0000 0 0x20000>; 96 no-map; 97 }; 98 99 smem_mem: memory@86000000 { 100 reg = <0x0 0x86000000 0 0x200000>; 101 no-map; 102 }; 103 104 tz_mem: memory@86200000 { 105 reg = <0 0x86200000 0 0x2d00000>; 106 no-map; 107 }; 108 109 rmtfs_mem: memory@88f00000 { 110 compatible = "qcom,rmtfs-mem"; 111 reg = <0 0x88f00000 0 0x200000>; 112 no-map; 113 114 qcom,client-id = <1>; 115 qcom,vmid = <15>; 116 }; 117 118 qseecom_mem: memory@8ab00000 { 119 reg = <0 0x8ab00000 0 0x1400000>; 120 no-map; 121 }; 122 123 camera_mem: memory@8bf00000 { 124 reg = <0 0x8bf00000 0 0x500000>; 125 no-map; 126 }; 127 128 ipa_fw_mem: memory@8c400000 { 129 reg = <0 0x8c400000 0 0x10000>; 130 no-map; 131 }; 132 133 ipa_gsi_mem: memory@8c410000 { 134 reg = <0 0x8c410000 0 0x5000>; 135 no-map; 136 }; 137 138 gpu_mem: memory@8c415000 { 139 reg = <0 0x8c415000 0 0x2000>; 140 no-map; 141 }; 142 143 adsp_mem: memory@8c500000 { 144 reg = <0 0x8c500000 0 0x1a00000>; 145 no-map; 146 }; 147 148 wlan_msa_mem: memory@8df00000 { 149 reg = <0 0x8df00000 0 0x100000>; 150 no-map; 151 }; 152 153 mpss_region: memory@8e000000 { 154 reg = <0 0x8e000000 0 0x7800000>; 155 no-map; 156 }; 157 158 venus_mem: memory@95800000 { 159 reg = <0 0x95800000 0 0x500000>; 160 no-map; 161 }; 162 163 cdsp_mem: memory@95d00000 { 164 reg = <0 0x95d00000 0 0x800000>; 165 no-map; 166 }; 167 168 mba_region: memory@96500000 { 169 reg = <0 0x96500000 0 0x200000>; 170 no-map; 171 }; 172 173 slpi_mem: memory@96700000 { 174 reg = <0 0x96700000 0 0x1400000>; 175 no-map; 176 }; 177 178 spss_mem: memory@97b00000 { 179 reg = <0 0x97b00000 0 0x100000>; 180 no-map; 181 }; 182 }; 183 184 cpus { 185 #address-cells = <2>; 186 #size-cells = <0>; 187 188 CPU0: cpu@0 { 189 device_type = "cpu"; 190 compatible = "qcom,kryo385"; 191 reg = <0x0 0x0>; 192 enable-method = "psci"; 193 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 194 &LITTLE_CPU_SLEEP_1 195 &CLUSTER_SLEEP_0>; 196 capacity-dmips-mhz = <607>; 197 dynamic-power-coefficient = <100>; 198 qcom,freq-domain = <&cpufreq_hw 0>; 199 #cooling-cells = <2>; 200 next-level-cache = <&L2_0>; 201 L2_0: l2-cache { 202 compatible = "cache"; 203 next-level-cache = <&L3_0>; 204 L3_0: l3-cache { 205 compatible = "cache"; 206 }; 207 }; 208 }; 209 210 CPU1: cpu@100 { 211 device_type = "cpu"; 212 compatible = "qcom,kryo385"; 213 reg = <0x0 0x100>; 214 enable-method = "psci"; 215 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 216 &LITTLE_CPU_SLEEP_1 217 &CLUSTER_SLEEP_0>; 218 capacity-dmips-mhz = <607>; 219 dynamic-power-coefficient = <100>; 220 qcom,freq-domain = <&cpufreq_hw 0>; 221 #cooling-cells = <2>; 222 next-level-cache = <&L2_100>; 223 L2_100: l2-cache { 224 compatible = "cache"; 225 next-level-cache = <&L3_0>; 226 }; 227 }; 228 229 CPU2: cpu@200 { 230 device_type = "cpu"; 231 compatible = "qcom,kryo385"; 232 reg = <0x0 0x200>; 233 enable-method = "psci"; 234 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 235 &LITTLE_CPU_SLEEP_1 236 &CLUSTER_SLEEP_0>; 237 capacity-dmips-mhz = <607>; 238 dynamic-power-coefficient = <100>; 239 qcom,freq-domain = <&cpufreq_hw 0>; 240 #cooling-cells = <2>; 241 next-level-cache = <&L2_200>; 242 L2_200: l2-cache { 243 compatible = "cache"; 244 next-level-cache = <&L3_0>; 245 }; 246 }; 247 248 CPU3: cpu@300 { 249 device_type = "cpu"; 250 compatible = "qcom,kryo385"; 251 reg = <0x0 0x300>; 252 enable-method = "psci"; 253 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 254 &LITTLE_CPU_SLEEP_1 255 &CLUSTER_SLEEP_0>; 256 capacity-dmips-mhz = <607>; 257 dynamic-power-coefficient = <100>; 258 qcom,freq-domain = <&cpufreq_hw 0>; 259 #cooling-cells = <2>; 260 next-level-cache = <&L2_300>; 261 L2_300: l2-cache { 262 compatible = "cache"; 263 next-level-cache = <&L3_0>; 264 }; 265 }; 266 267 CPU4: cpu@400 { 268 device_type = "cpu"; 269 compatible = "qcom,kryo385"; 270 reg = <0x0 0x400>; 271 enable-method = "psci"; 272 capacity-dmips-mhz = <1024>; 273 cpu-idle-states = <&BIG_CPU_SLEEP_0 274 &BIG_CPU_SLEEP_1 275 &CLUSTER_SLEEP_0>; 276 dynamic-power-coefficient = <396>; 277 qcom,freq-domain = <&cpufreq_hw 1>; 278 #cooling-cells = <2>; 279 next-level-cache = <&L2_400>; 280 L2_400: l2-cache { 281 compatible = "cache"; 282 next-level-cache = <&L3_0>; 283 }; 284 }; 285 286 CPU5: cpu@500 { 287 device_type = "cpu"; 288 compatible = "qcom,kryo385"; 289 reg = <0x0 0x500>; 290 enable-method = "psci"; 291 capacity-dmips-mhz = <1024>; 292 cpu-idle-states = <&BIG_CPU_SLEEP_0 293 &BIG_CPU_SLEEP_1 294 &CLUSTER_SLEEP_0>; 295 dynamic-power-coefficient = <396>; 296 qcom,freq-domain = <&cpufreq_hw 1>; 297 #cooling-cells = <2>; 298 next-level-cache = <&L2_500>; 299 L2_500: l2-cache { 300 compatible = "cache"; 301 next-level-cache = <&L3_0>; 302 }; 303 }; 304 305 CPU6: cpu@600 { 306 device_type = "cpu"; 307 compatible = "qcom,kryo385"; 308 reg = <0x0 0x600>; 309 enable-method = "psci"; 310 capacity-dmips-mhz = <1024>; 311 cpu-idle-states = <&BIG_CPU_SLEEP_0 312 &BIG_CPU_SLEEP_1 313 &CLUSTER_SLEEP_0>; 314 dynamic-power-coefficient = <396>; 315 qcom,freq-domain = <&cpufreq_hw 1>; 316 #cooling-cells = <2>; 317 next-level-cache = <&L2_600>; 318 L2_600: l2-cache { 319 compatible = "cache"; 320 next-level-cache = <&L3_0>; 321 }; 322 }; 323 324 CPU7: cpu@700 { 325 device_type = "cpu"; 326 compatible = "qcom,kryo385"; 327 reg = <0x0 0x700>; 328 enable-method = "psci"; 329 capacity-dmips-mhz = <1024>; 330 cpu-idle-states = <&BIG_CPU_SLEEP_0 331 &BIG_CPU_SLEEP_1 332 &CLUSTER_SLEEP_0>; 333 dynamic-power-coefficient = <396>; 334 qcom,freq-domain = <&cpufreq_hw 1>; 335 #cooling-cells = <2>; 336 next-level-cache = <&L2_700>; 337 L2_700: l2-cache { 338 compatible = "cache"; 339 next-level-cache = <&L3_0>; 340 }; 341 }; 342 343 cpu-map { 344 cluster0 { 345 core0 { 346 cpu = <&CPU0>; 347 }; 348 349 core1 { 350 cpu = <&CPU1>; 351 }; 352 353 core2 { 354 cpu = <&CPU2>; 355 }; 356 357 core3 { 358 cpu = <&CPU3>; 359 }; 360 361 core4 { 362 cpu = <&CPU4>; 363 }; 364 365 core5 { 366 cpu = <&CPU5>; 367 }; 368 369 core6 { 370 cpu = <&CPU6>; 371 }; 372 373 core7 { 374 cpu = <&CPU7>; 375 }; 376 }; 377 }; 378 379 idle-states { 380 entry-method = "psci"; 381 382 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { 383 compatible = "arm,idle-state"; 384 idle-state-name = "little-power-down"; 385 arm,psci-suspend-param = <0x40000003>; 386 entry-latency-us = <350>; 387 exit-latency-us = <461>; 388 min-residency-us = <1890>; 389 local-timer-stop; 390 }; 391 392 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { 393 compatible = "arm,idle-state"; 394 idle-state-name = "little-rail-power-down"; 395 arm,psci-suspend-param = <0x40000004>; 396 entry-latency-us = <360>; 397 exit-latency-us = <531>; 398 min-residency-us = <3934>; 399 local-timer-stop; 400 }; 401 402 BIG_CPU_SLEEP_0: cpu-sleep-1-0 { 403 compatible = "arm,idle-state"; 404 idle-state-name = "big-power-down"; 405 arm,psci-suspend-param = <0x40000003>; 406 entry-latency-us = <264>; 407 exit-latency-us = <621>; 408 min-residency-us = <952>; 409 local-timer-stop; 410 }; 411 412 BIG_CPU_SLEEP_1: cpu-sleep-1-1 { 413 compatible = "arm,idle-state"; 414 idle-state-name = "big-rail-power-down"; 415 arm,psci-suspend-param = <0x40000004>; 416 entry-latency-us = <702>; 417 exit-latency-us = <1061>; 418 min-residency-us = <4488>; 419 local-timer-stop; 420 }; 421 422 CLUSTER_SLEEP_0: cluster-sleep-0 { 423 compatible = "arm,idle-state"; 424 idle-state-name = "cluster-power-down"; 425 arm,psci-suspend-param = <0x400000F4>; 426 entry-latency-us = <3263>; 427 exit-latency-us = <6562>; 428 min-residency-us = <9987>; 429 local-timer-stop; 430 }; 431 }; 432 }; 433 434 pmu { 435 compatible = "arm,armv8-pmuv3"; 436 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 437 }; 438 439 timer { 440 compatible = "arm,armv8-timer"; 441 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 442 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 443 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 444 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 445 }; 446 447 clocks { 448 xo_board: xo-board { 449 compatible = "fixed-clock"; 450 #clock-cells = <0>; 451 clock-frequency = <38400000>; 452 clock-output-names = "xo_board"; 453 }; 454 455 sleep_clk: sleep-clk { 456 compatible = "fixed-clock"; 457 #clock-cells = <0>; 458 clock-frequency = <32764>; 459 }; 460 }; 461 462 firmware { 463 scm { 464 compatible = "qcom,scm-sdm845", "qcom,scm"; 465 }; 466 }; 467 468 adsp_pas: remoteproc-adsp { 469 compatible = "qcom,sdm845-adsp-pas"; 470 471 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 472 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 473 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 474 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 475 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 476 interrupt-names = "wdog", "fatal", "ready", 477 "handover", "stop-ack"; 478 479 clocks = <&rpmhcc RPMH_CXO_CLK>; 480 clock-names = "xo"; 481 482 memory-region = <&adsp_mem>; 483 484 qcom,smem-states = <&adsp_smp2p_out 0>; 485 qcom,smem-state-names = "stop"; 486 487 status = "disabled"; 488 489 glink-edge { 490 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 491 label = "lpass"; 492 qcom,remote-pid = <2>; 493 mboxes = <&apss_shared 8>; 494 fastrpc { 495 compatible = "qcom,fastrpc"; 496 qcom,glink-channels = "fastrpcglink-apps-dsp"; 497 label = "adsp"; 498 #address-cells = <1>; 499 #size-cells = <0>; 500 501 compute-cb@3 { 502 compatible = "qcom,fastrpc-compute-cb"; 503 reg = <3>; 504 iommus = <&apps_smmu 0x1823 0x0>; 505 }; 506 507 compute-cb@4 { 508 compatible = "qcom,fastrpc-compute-cb"; 509 reg = <4>; 510 iommus = <&apps_smmu 0x1824 0x0>; 511 }; 512 }; 513 }; 514 }; 515 516 cdsp_pas: remoteproc-cdsp { 517 compatible = "qcom,sdm845-cdsp-pas"; 518 519 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 520 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 521 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 522 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 523 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 524 interrupt-names = "wdog", "fatal", "ready", 525 "handover", "stop-ack"; 526 527 clocks = <&rpmhcc RPMH_CXO_CLK>; 528 clock-names = "xo"; 529 530 memory-region = <&cdsp_mem>; 531 532 qcom,smem-states = <&cdsp_smp2p_out 0>; 533 qcom,smem-state-names = "stop"; 534 535 status = "disabled"; 536 537 glink-edge { 538 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 539 label = "turing"; 540 qcom,remote-pid = <5>; 541 mboxes = <&apss_shared 4>; 542 fastrpc { 543 compatible = "qcom,fastrpc"; 544 qcom,glink-channels = "fastrpcglink-apps-dsp"; 545 label = "cdsp"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 549 compute-cb@1 { 550 compatible = "qcom,fastrpc-compute-cb"; 551 reg = <1>; 552 iommus = <&apps_smmu 0x1401 0x30>; 553 }; 554 555 compute-cb@2 { 556 compatible = "qcom,fastrpc-compute-cb"; 557 reg = <2>; 558 iommus = <&apps_smmu 0x1402 0x30>; 559 }; 560 561 compute-cb@3 { 562 compatible = "qcom,fastrpc-compute-cb"; 563 reg = <3>; 564 iommus = <&apps_smmu 0x1403 0x30>; 565 }; 566 567 compute-cb@4 { 568 compatible = "qcom,fastrpc-compute-cb"; 569 reg = <4>; 570 iommus = <&apps_smmu 0x1404 0x30>; 571 }; 572 573 compute-cb@5 { 574 compatible = "qcom,fastrpc-compute-cb"; 575 reg = <5>; 576 iommus = <&apps_smmu 0x1405 0x30>; 577 }; 578 579 compute-cb@6 { 580 compatible = "qcom,fastrpc-compute-cb"; 581 reg = <6>; 582 iommus = <&apps_smmu 0x1406 0x30>; 583 }; 584 585 compute-cb@7 { 586 compatible = "qcom,fastrpc-compute-cb"; 587 reg = <7>; 588 iommus = <&apps_smmu 0x1407 0x30>; 589 }; 590 591 compute-cb@8 { 592 compatible = "qcom,fastrpc-compute-cb"; 593 reg = <8>; 594 iommus = <&apps_smmu 0x1408 0x30>; 595 }; 596 }; 597 }; 598 }; 599 600 tcsr_mutex: hwlock { 601 compatible = "qcom,tcsr-mutex"; 602 syscon = <&tcsr_mutex_regs 0 0x1000>; 603 #hwlock-cells = <1>; 604 }; 605 606 smem { 607 compatible = "qcom,smem"; 608 memory-region = <&smem_mem>; 609 hwlocks = <&tcsr_mutex 3>; 610 }; 611 612 smp2p-cdsp { 613 compatible = "qcom,smp2p"; 614 qcom,smem = <94>, <432>; 615 616 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 617 618 mboxes = <&apss_shared 6>; 619 620 qcom,local-pid = <0>; 621 qcom,remote-pid = <5>; 622 623 cdsp_smp2p_out: master-kernel { 624 qcom,entry-name = "master-kernel"; 625 #qcom,smem-state-cells = <1>; 626 }; 627 628 cdsp_smp2p_in: slave-kernel { 629 qcom,entry-name = "slave-kernel"; 630 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 }; 634 }; 635 636 smp2p-lpass { 637 compatible = "qcom,smp2p"; 638 qcom,smem = <443>, <429>; 639 640 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 641 642 mboxes = <&apss_shared 10>; 643 644 qcom,local-pid = <0>; 645 qcom,remote-pid = <2>; 646 647 adsp_smp2p_out: master-kernel { 648 qcom,entry-name = "master-kernel"; 649 #qcom,smem-state-cells = <1>; 650 }; 651 652 adsp_smp2p_in: slave-kernel { 653 qcom,entry-name = "slave-kernel"; 654 655 interrupt-controller; 656 #interrupt-cells = <2>; 657 }; 658 }; 659 660 smp2p-mpss { 661 compatible = "qcom,smp2p"; 662 qcom,smem = <435>, <428>; 663 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 664 mboxes = <&apss_shared 14>; 665 qcom,local-pid = <0>; 666 qcom,remote-pid = <1>; 667 668 modem_smp2p_out: master-kernel { 669 qcom,entry-name = "master-kernel"; 670 #qcom,smem-state-cells = <1>; 671 }; 672 673 modem_smp2p_in: slave-kernel { 674 qcom,entry-name = "slave-kernel"; 675 interrupt-controller; 676 #interrupt-cells = <2>; 677 }; 678 }; 679 680 smp2p-slpi { 681 compatible = "qcom,smp2p"; 682 qcom,smem = <481>, <430>; 683 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 684 mboxes = <&apss_shared 26>; 685 qcom,local-pid = <0>; 686 qcom,remote-pid = <3>; 687 688 slpi_smp2p_out: master-kernel { 689 qcom,entry-name = "master-kernel"; 690 #qcom,smem-state-cells = <1>; 691 }; 692 693 slpi_smp2p_in: slave-kernel { 694 qcom,entry-name = "slave-kernel"; 695 interrupt-controller; 696 #interrupt-cells = <2>; 697 }; 698 }; 699 700 psci { 701 compatible = "arm,psci-1.0"; 702 method = "smc"; 703 }; 704 705 soc: soc@0 { 706 #address-cells = <2>; 707 #size-cells = <2>; 708 ranges = <0 0 0 0 0x10 0>; 709 dma-ranges = <0 0 0 0 0x10 0>; 710 compatible = "simple-bus"; 711 712 gcc: clock-controller@100000 { 713 compatible = "qcom,gcc-sdm845"; 714 reg = <0 0x00100000 0 0x1f0000>; 715 #clock-cells = <1>; 716 #reset-cells = <1>; 717 #power-domain-cells = <1>; 718 }; 719 720 qfprom@784000 { 721 compatible = "qcom,qfprom"; 722 reg = <0 0x00784000 0 0x8ff>; 723 #address-cells = <1>; 724 #size-cells = <1>; 725 726 qusb2p_hstx_trim: hstx-trim-primary@1eb { 727 reg = <0x1eb 0x1>; 728 bits = <1 4>; 729 }; 730 731 qusb2s_hstx_trim: hstx-trim-secondary@1eb { 732 reg = <0x1eb 0x2>; 733 bits = <6 4>; 734 }; 735 }; 736 737 rng: rng@793000 { 738 compatible = "qcom,prng-ee"; 739 reg = <0 0x00793000 0 0x1000>; 740 clocks = <&gcc GCC_PRNG_AHB_CLK>; 741 clock-names = "core"; 742 }; 743 744 qupv3_id_0: geniqup@8c0000 { 745 compatible = "qcom,geni-se-qup"; 746 reg = <0 0x008c0000 0 0x6000>; 747 clock-names = "m-ahb", "s-ahb"; 748 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 749 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 750 #address-cells = <2>; 751 #size-cells = <2>; 752 ranges; 753 status = "disabled"; 754 755 i2c0: i2c@880000 { 756 compatible = "qcom,geni-i2c"; 757 reg = <0 0x00880000 0 0x4000>; 758 clock-names = "se"; 759 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 760 pinctrl-names = "default"; 761 pinctrl-0 = <&qup_i2c0_default>; 762 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 status = "disabled"; 766 }; 767 768 spi0: spi@880000 { 769 compatible = "qcom,geni-spi"; 770 reg = <0 0x00880000 0 0x4000>; 771 clock-names = "se"; 772 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 773 pinctrl-names = "default"; 774 pinctrl-0 = <&qup_spi0_default>; 775 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 776 #address-cells = <1>; 777 #size-cells = <0>; 778 status = "disabled"; 779 }; 780 781 uart0: serial@880000 { 782 compatible = "qcom,geni-uart"; 783 reg = <0 0x00880000 0 0x4000>; 784 clock-names = "se"; 785 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 786 pinctrl-names = "default"; 787 pinctrl-0 = <&qup_uart0_default>; 788 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 789 status = "disabled"; 790 }; 791 792 i2c1: i2c@884000 { 793 compatible = "qcom,geni-i2c"; 794 reg = <0 0x00884000 0 0x4000>; 795 clock-names = "se"; 796 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&qup_i2c1_default>; 799 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 status = "disabled"; 803 }; 804 805 spi1: spi@884000 { 806 compatible = "qcom,geni-spi"; 807 reg = <0 0x00884000 0 0x4000>; 808 clock-names = "se"; 809 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 810 pinctrl-names = "default"; 811 pinctrl-0 = <&qup_spi1_default>; 812 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 813 #address-cells = <1>; 814 #size-cells = <0>; 815 status = "disabled"; 816 }; 817 818 uart1: serial@884000 { 819 compatible = "qcom,geni-uart"; 820 reg = <0 0x00884000 0 0x4000>; 821 clock-names = "se"; 822 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 823 pinctrl-names = "default"; 824 pinctrl-0 = <&qup_uart1_default>; 825 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 826 status = "disabled"; 827 }; 828 829 i2c2: i2c@888000 { 830 compatible = "qcom,geni-i2c"; 831 reg = <0 0x00888000 0 0x4000>; 832 clock-names = "se"; 833 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 834 pinctrl-names = "default"; 835 pinctrl-0 = <&qup_i2c2_default>; 836 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 status = "disabled"; 840 }; 841 842 spi2: spi@888000 { 843 compatible = "qcom,geni-spi"; 844 reg = <0 0x00888000 0 0x4000>; 845 clock-names = "se"; 846 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&qup_spi2_default>; 849 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 status = "disabled"; 853 }; 854 855 uart2: serial@888000 { 856 compatible = "qcom,geni-uart"; 857 reg = <0 0x00888000 0 0x4000>; 858 clock-names = "se"; 859 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&qup_uart2_default>; 862 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 863 status = "disabled"; 864 }; 865 866 i2c3: i2c@88c000 { 867 compatible = "qcom,geni-i2c"; 868 reg = <0 0x0088c000 0 0x4000>; 869 clock-names = "se"; 870 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 871 pinctrl-names = "default"; 872 pinctrl-0 = <&qup_i2c3_default>; 873 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 874 #address-cells = <1>; 875 #size-cells = <0>; 876 status = "disabled"; 877 }; 878 879 spi3: spi@88c000 { 880 compatible = "qcom,geni-spi"; 881 reg = <0 0x0088c000 0 0x4000>; 882 clock-names = "se"; 883 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 884 pinctrl-names = "default"; 885 pinctrl-0 = <&qup_spi3_default>; 886 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 887 #address-cells = <1>; 888 #size-cells = <0>; 889 status = "disabled"; 890 }; 891 892 uart3: serial@88c000 { 893 compatible = "qcom,geni-uart"; 894 reg = <0 0x0088c000 0 0x4000>; 895 clock-names = "se"; 896 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 897 pinctrl-names = "default"; 898 pinctrl-0 = <&qup_uart3_default>; 899 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 900 status = "disabled"; 901 }; 902 903 i2c4: i2c@890000 { 904 compatible = "qcom,geni-i2c"; 905 reg = <0 0x00890000 0 0x4000>; 906 clock-names = "se"; 907 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 908 pinctrl-names = "default"; 909 pinctrl-0 = <&qup_i2c4_default>; 910 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 911 #address-cells = <1>; 912 #size-cells = <0>; 913 status = "disabled"; 914 }; 915 916 spi4: spi@890000 { 917 compatible = "qcom,geni-spi"; 918 reg = <0 0x00890000 0 0x4000>; 919 clock-names = "se"; 920 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 921 pinctrl-names = "default"; 922 pinctrl-0 = <&qup_spi4_default>; 923 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 924 #address-cells = <1>; 925 #size-cells = <0>; 926 status = "disabled"; 927 }; 928 929 uart4: serial@890000 { 930 compatible = "qcom,geni-uart"; 931 reg = <0 0x00890000 0 0x4000>; 932 clock-names = "se"; 933 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 934 pinctrl-names = "default"; 935 pinctrl-0 = <&qup_uart4_default>; 936 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 937 status = "disabled"; 938 }; 939 940 i2c5: i2c@894000 { 941 compatible = "qcom,geni-i2c"; 942 reg = <0 0x00894000 0 0x4000>; 943 clock-names = "se"; 944 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 945 pinctrl-names = "default"; 946 pinctrl-0 = <&qup_i2c5_default>; 947 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 948 #address-cells = <1>; 949 #size-cells = <0>; 950 status = "disabled"; 951 }; 952 953 spi5: spi@894000 { 954 compatible = "qcom,geni-spi"; 955 reg = <0 0x00894000 0 0x4000>; 956 clock-names = "se"; 957 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 958 pinctrl-names = "default"; 959 pinctrl-0 = <&qup_spi5_default>; 960 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 status = "disabled"; 964 }; 965 966 uart5: serial@894000 { 967 compatible = "qcom,geni-uart"; 968 reg = <0 0x00894000 0 0x4000>; 969 clock-names = "se"; 970 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 971 pinctrl-names = "default"; 972 pinctrl-0 = <&qup_uart5_default>; 973 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 974 status = "disabled"; 975 }; 976 977 i2c6: i2c@898000 { 978 compatible = "qcom,geni-i2c"; 979 reg = <0 0x00898000 0 0x4000>; 980 clock-names = "se"; 981 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 982 pinctrl-names = "default"; 983 pinctrl-0 = <&qup_i2c6_default>; 984 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 status = "disabled"; 988 }; 989 990 spi6: spi@898000 { 991 compatible = "qcom,geni-spi"; 992 reg = <0 0x00898000 0 0x4000>; 993 clock-names = "se"; 994 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 995 pinctrl-names = "default"; 996 pinctrl-0 = <&qup_spi6_default>; 997 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 status = "disabled"; 1001 }; 1002 1003 uart6: serial@898000 { 1004 compatible = "qcom,geni-uart"; 1005 reg = <0 0x00898000 0 0x4000>; 1006 clock-names = "se"; 1007 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&qup_uart6_default>; 1010 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1011 status = "disabled"; 1012 }; 1013 1014 i2c7: i2c@89c000 { 1015 compatible = "qcom,geni-i2c"; 1016 reg = <0 0x0089c000 0 0x4000>; 1017 clock-names = "se"; 1018 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1019 pinctrl-names = "default"; 1020 pinctrl-0 = <&qup_i2c7_default>; 1021 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1022 #address-cells = <1>; 1023 #size-cells = <0>; 1024 status = "disabled"; 1025 }; 1026 1027 spi7: spi@89c000 { 1028 compatible = "qcom,geni-spi"; 1029 reg = <0 0x0089c000 0 0x4000>; 1030 clock-names = "se"; 1031 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1032 pinctrl-names = "default"; 1033 pinctrl-0 = <&qup_spi7_default>; 1034 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1035 #address-cells = <1>; 1036 #size-cells = <0>; 1037 status = "disabled"; 1038 }; 1039 1040 uart7: serial@89c000 { 1041 compatible = "qcom,geni-uart"; 1042 reg = <0 0x0089c000 0 0x4000>; 1043 clock-names = "se"; 1044 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1045 pinctrl-names = "default"; 1046 pinctrl-0 = <&qup_uart7_default>; 1047 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1048 status = "disabled"; 1049 }; 1050 }; 1051 1052 qupv3_id_1: geniqup@ac0000 { 1053 compatible = "qcom,geni-se-qup"; 1054 reg = <0 0x00ac0000 0 0x6000>; 1055 clock-names = "m-ahb", "s-ahb"; 1056 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1057 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1058 #address-cells = <2>; 1059 #size-cells = <2>; 1060 ranges; 1061 status = "disabled"; 1062 1063 i2c8: i2c@a80000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0 0x00a80000 0 0x4000>; 1066 clock-names = "se"; 1067 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_i2c8_default>; 1070 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 status = "disabled"; 1074 }; 1075 1076 spi8: spi@a80000 { 1077 compatible = "qcom,geni-spi"; 1078 reg = <0 0x00a80000 0 0x4000>; 1079 clock-names = "se"; 1080 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1081 pinctrl-names = "default"; 1082 pinctrl-0 = <&qup_spi8_default>; 1083 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 status = "disabled"; 1087 }; 1088 1089 uart8: serial@a80000 { 1090 compatible = "qcom,geni-uart"; 1091 reg = <0 0x00a80000 0 0x4000>; 1092 clock-names = "se"; 1093 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1094 pinctrl-names = "default"; 1095 pinctrl-0 = <&qup_uart8_default>; 1096 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1097 status = "disabled"; 1098 }; 1099 1100 i2c9: i2c@a84000 { 1101 compatible = "qcom,geni-i2c"; 1102 reg = <0 0x00a84000 0 0x4000>; 1103 clock-names = "se"; 1104 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1105 pinctrl-names = "default"; 1106 pinctrl-0 = <&qup_i2c9_default>; 1107 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 status = "disabled"; 1111 }; 1112 1113 spi9: spi@a84000 { 1114 compatible = "qcom,geni-spi"; 1115 reg = <0 0x00a84000 0 0x4000>; 1116 clock-names = "se"; 1117 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_spi9_default>; 1120 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 status = "disabled"; 1124 }; 1125 1126 uart9: serial@a84000 { 1127 compatible = "qcom,geni-debug-uart"; 1128 reg = <0 0x00a84000 0 0x4000>; 1129 clock-names = "se"; 1130 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1131 pinctrl-names = "default"; 1132 pinctrl-0 = <&qup_uart9_default>; 1133 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1134 status = "disabled"; 1135 }; 1136 1137 i2c10: i2c@a88000 { 1138 compatible = "qcom,geni-i2c"; 1139 reg = <0 0x00a88000 0 0x4000>; 1140 clock-names = "se"; 1141 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1142 pinctrl-names = "default"; 1143 pinctrl-0 = <&qup_i2c10_default>; 1144 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 status = "disabled"; 1148 }; 1149 1150 spi10: spi@a88000 { 1151 compatible = "qcom,geni-spi"; 1152 reg = <0 0x00a88000 0 0x4000>; 1153 clock-names = "se"; 1154 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1155 pinctrl-names = "default"; 1156 pinctrl-0 = <&qup_spi10_default>; 1157 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1158 #address-cells = <1>; 1159 #size-cells = <0>; 1160 status = "disabled"; 1161 }; 1162 1163 uart10: serial@a88000 { 1164 compatible = "qcom,geni-uart"; 1165 reg = <0 0x00a88000 0 0x4000>; 1166 clock-names = "se"; 1167 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&qup_uart10_default>; 1170 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1171 status = "disabled"; 1172 }; 1173 1174 i2c11: i2c@a8c000 { 1175 compatible = "qcom,geni-i2c"; 1176 reg = <0 0x00a8c000 0 0x4000>; 1177 clock-names = "se"; 1178 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1179 pinctrl-names = "default"; 1180 pinctrl-0 = <&qup_i2c11_default>; 1181 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 status = "disabled"; 1185 }; 1186 1187 spi11: spi@a8c000 { 1188 compatible = "qcom,geni-spi"; 1189 reg = <0 0x00a8c000 0 0x4000>; 1190 clock-names = "se"; 1191 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1192 pinctrl-names = "default"; 1193 pinctrl-0 = <&qup_spi11_default>; 1194 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1195 #address-cells = <1>; 1196 #size-cells = <0>; 1197 status = "disabled"; 1198 }; 1199 1200 uart11: serial@a8c000 { 1201 compatible = "qcom,geni-uart"; 1202 reg = <0 0x00a8c000 0 0x4000>; 1203 clock-names = "se"; 1204 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1205 pinctrl-names = "default"; 1206 pinctrl-0 = <&qup_uart11_default>; 1207 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1208 status = "disabled"; 1209 }; 1210 1211 i2c12: i2c@a90000 { 1212 compatible = "qcom,geni-i2c"; 1213 reg = <0 0x00a90000 0 0x4000>; 1214 clock-names = "se"; 1215 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1216 pinctrl-names = "default"; 1217 pinctrl-0 = <&qup_i2c12_default>; 1218 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 status = "disabled"; 1222 }; 1223 1224 spi12: spi@a90000 { 1225 compatible = "qcom,geni-spi"; 1226 reg = <0 0x00a90000 0 0x4000>; 1227 clock-names = "se"; 1228 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1229 pinctrl-names = "default"; 1230 pinctrl-0 = <&qup_spi12_default>; 1231 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1232 #address-cells = <1>; 1233 #size-cells = <0>; 1234 status = "disabled"; 1235 }; 1236 1237 uart12: serial@a90000 { 1238 compatible = "qcom,geni-uart"; 1239 reg = <0 0x00a90000 0 0x4000>; 1240 clock-names = "se"; 1241 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1242 pinctrl-names = "default"; 1243 pinctrl-0 = <&qup_uart12_default>; 1244 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1245 status = "disabled"; 1246 }; 1247 1248 i2c13: i2c@a94000 { 1249 compatible = "qcom,geni-i2c"; 1250 reg = <0 0x00a94000 0 0x4000>; 1251 clock-names = "se"; 1252 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1253 pinctrl-names = "default"; 1254 pinctrl-0 = <&qup_i2c13_default>; 1255 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 status = "disabled"; 1259 }; 1260 1261 spi13: spi@a94000 { 1262 compatible = "qcom,geni-spi"; 1263 reg = <0 0x00a94000 0 0x4000>; 1264 clock-names = "se"; 1265 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1266 pinctrl-names = "default"; 1267 pinctrl-0 = <&qup_spi13_default>; 1268 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1269 #address-cells = <1>; 1270 #size-cells = <0>; 1271 status = "disabled"; 1272 }; 1273 1274 uart13: serial@a94000 { 1275 compatible = "qcom,geni-uart"; 1276 reg = <0 0x00a94000 0 0x4000>; 1277 clock-names = "se"; 1278 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1279 pinctrl-names = "default"; 1280 pinctrl-0 = <&qup_uart13_default>; 1281 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1282 status = "disabled"; 1283 }; 1284 1285 i2c14: i2c@a98000 { 1286 compatible = "qcom,geni-i2c"; 1287 reg = <0 0x00a98000 0 0x4000>; 1288 clock-names = "se"; 1289 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&qup_i2c14_default>; 1292 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 status = "disabled"; 1296 }; 1297 1298 spi14: spi@a98000 { 1299 compatible = "qcom,geni-spi"; 1300 reg = <0 0x00a98000 0 0x4000>; 1301 clock-names = "se"; 1302 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1303 pinctrl-names = "default"; 1304 pinctrl-0 = <&qup_spi14_default>; 1305 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1306 #address-cells = <1>; 1307 #size-cells = <0>; 1308 status = "disabled"; 1309 }; 1310 1311 uart14: serial@a98000 { 1312 compatible = "qcom,geni-uart"; 1313 reg = <0 0x00a98000 0 0x4000>; 1314 clock-names = "se"; 1315 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1316 pinctrl-names = "default"; 1317 pinctrl-0 = <&qup_uart14_default>; 1318 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1319 status = "disabled"; 1320 }; 1321 1322 i2c15: i2c@a9c000 { 1323 compatible = "qcom,geni-i2c"; 1324 reg = <0 0x00a9c000 0 0x4000>; 1325 clock-names = "se"; 1326 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1327 pinctrl-names = "default"; 1328 pinctrl-0 = <&qup_i2c15_default>; 1329 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1330 #address-cells = <1>; 1331 #size-cells = <0>; 1332 status = "disabled"; 1333 }; 1334 1335 spi15: spi@a9c000 { 1336 compatible = "qcom,geni-spi"; 1337 reg = <0 0x00a9c000 0 0x4000>; 1338 clock-names = "se"; 1339 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1340 pinctrl-names = "default"; 1341 pinctrl-0 = <&qup_spi15_default>; 1342 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 status = "disabled"; 1346 }; 1347 1348 uart15: serial@a9c000 { 1349 compatible = "qcom,geni-uart"; 1350 reg = <0 0x00a9c000 0 0x4000>; 1351 clock-names = "se"; 1352 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1353 pinctrl-names = "default"; 1354 pinctrl-0 = <&qup_uart15_default>; 1355 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1356 status = "disabled"; 1357 }; 1358 }; 1359 1360 system-cache-controller@1100000 { 1361 compatible = "qcom,sdm845-llcc"; 1362 reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>; 1363 reg-names = "llcc_base", "llcc_broadcast_base"; 1364 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 1365 }; 1366 1367 ufs_mem_hc: ufshc@1d84000 { 1368 compatible = "qcom,sdm845-ufshc", "qcom,ufshc", 1369 "jedec,ufs-2.0"; 1370 reg = <0 0x01d84000 0 0x2500>; 1371 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1372 phys = <&ufs_mem_phy_lanes>; 1373 phy-names = "ufsphy"; 1374 lanes-per-direction = <2>; 1375 power-domains = <&gcc UFS_PHY_GDSC>; 1376 #reset-cells = <1>; 1377 resets = <&gcc GCC_UFS_PHY_BCR>; 1378 reset-names = "rst"; 1379 1380 iommus = <&apps_smmu 0x100 0xf>; 1381 1382 clock-names = 1383 "core_clk", 1384 "bus_aggr_clk", 1385 "iface_clk", 1386 "core_clk_unipro", 1387 "ref_clk", 1388 "tx_lane0_sync_clk", 1389 "rx_lane0_sync_clk", 1390 "rx_lane1_sync_clk"; 1391 clocks = 1392 <&gcc GCC_UFS_PHY_AXI_CLK>, 1393 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1394 <&gcc GCC_UFS_PHY_AHB_CLK>, 1395 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1396 <&rpmhcc RPMH_CXO_CLK>, 1397 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1398 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1399 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 1400 freq-table-hz = 1401 <50000000 200000000>, 1402 <0 0>, 1403 <0 0>, 1404 <37500000 150000000>, 1405 <0 0>, 1406 <0 0>, 1407 <0 0>, 1408 <0 0>; 1409 1410 status = "disabled"; 1411 }; 1412 1413 ufs_mem_phy: phy@1d87000 { 1414 compatible = "qcom,sdm845-qmp-ufs-phy"; 1415 reg = <0 0x01d87000 0 0x18c>; 1416 #address-cells = <2>; 1417 #size-cells = <2>; 1418 ranges; 1419 clock-names = "ref", 1420 "ref_aux"; 1421 clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, 1422 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; 1423 1424 resets = <&ufs_mem_hc 0>; 1425 reset-names = "ufsphy"; 1426 status = "disabled"; 1427 1428 ufs_mem_phy_lanes: lanes@1d87400 { 1429 reg = <0 0x01d87400 0 0x108>, 1430 <0 0x01d87600 0 0x1e0>, 1431 <0 0x01d87c00 0 0x1dc>, 1432 <0 0x01d87800 0 0x108>, 1433 <0 0x01d87a00 0 0x1e0>; 1434 #phy-cells = <0>; 1435 }; 1436 }; 1437 1438 tcsr_mutex_regs: syscon@1f40000 { 1439 compatible = "syscon"; 1440 reg = <0 0x01f40000 0 0x40000>; 1441 }; 1442 1443 tlmm: pinctrl@3400000 { 1444 compatible = "qcom,sdm845-pinctrl"; 1445 reg = <0 0x03400000 0 0xc00000>; 1446 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1447 gpio-controller; 1448 #gpio-cells = <2>; 1449 interrupt-controller; 1450 #interrupt-cells = <2>; 1451 gpio-ranges = <&tlmm 0 0 150>; 1452 wakeup-parent = <&pdc_intc>; 1453 1454 qspi_clk: qspi-clk { 1455 pinmux { 1456 pins = "gpio95"; 1457 function = "qspi_clk"; 1458 }; 1459 }; 1460 1461 qspi_cs0: qspi-cs0 { 1462 pinmux { 1463 pins = "gpio90"; 1464 function = "qspi_cs"; 1465 }; 1466 }; 1467 1468 qspi_cs1: qspi-cs1 { 1469 pinmux { 1470 pins = "gpio89"; 1471 function = "qspi_cs"; 1472 }; 1473 }; 1474 1475 qspi_data01: qspi-data01 { 1476 pinmux-data { 1477 pins = "gpio91", "gpio92"; 1478 function = "qspi_data"; 1479 }; 1480 }; 1481 1482 qspi_data12: qspi-data12 { 1483 pinmux-data { 1484 pins = "gpio93", "gpio94"; 1485 function = "qspi_data"; 1486 }; 1487 }; 1488 1489 qup_i2c0_default: qup-i2c0-default { 1490 pinmux { 1491 pins = "gpio0", "gpio1"; 1492 function = "qup0"; 1493 }; 1494 }; 1495 1496 qup_i2c1_default: qup-i2c1-default { 1497 pinmux { 1498 pins = "gpio17", "gpio18"; 1499 function = "qup1"; 1500 }; 1501 }; 1502 1503 qup_i2c2_default: qup-i2c2-default { 1504 pinmux { 1505 pins = "gpio27", "gpio28"; 1506 function = "qup2"; 1507 }; 1508 }; 1509 1510 qup_i2c3_default: qup-i2c3-default { 1511 pinmux { 1512 pins = "gpio41", "gpio42"; 1513 function = "qup3"; 1514 }; 1515 }; 1516 1517 qup_i2c4_default: qup-i2c4-default { 1518 pinmux { 1519 pins = "gpio89", "gpio90"; 1520 function = "qup4"; 1521 }; 1522 }; 1523 1524 qup_i2c5_default: qup-i2c5-default { 1525 pinmux { 1526 pins = "gpio85", "gpio86"; 1527 function = "qup5"; 1528 }; 1529 }; 1530 1531 qup_i2c6_default: qup-i2c6-default { 1532 pinmux { 1533 pins = "gpio45", "gpio46"; 1534 function = "qup6"; 1535 }; 1536 }; 1537 1538 qup_i2c7_default: qup-i2c7-default { 1539 pinmux { 1540 pins = "gpio93", "gpio94"; 1541 function = "qup7"; 1542 }; 1543 }; 1544 1545 qup_i2c8_default: qup-i2c8-default { 1546 pinmux { 1547 pins = "gpio65", "gpio66"; 1548 function = "qup8"; 1549 }; 1550 }; 1551 1552 qup_i2c9_default: qup-i2c9-default { 1553 pinmux { 1554 pins = "gpio6", "gpio7"; 1555 function = "qup9"; 1556 }; 1557 }; 1558 1559 qup_i2c10_default: qup-i2c10-default { 1560 pinmux { 1561 pins = "gpio55", "gpio56"; 1562 function = "qup10"; 1563 }; 1564 }; 1565 1566 qup_i2c11_default: qup-i2c11-default { 1567 pinmux { 1568 pins = "gpio31", "gpio32"; 1569 function = "qup11"; 1570 }; 1571 }; 1572 1573 qup_i2c12_default: qup-i2c12-default { 1574 pinmux { 1575 pins = "gpio49", "gpio50"; 1576 function = "qup12"; 1577 }; 1578 }; 1579 1580 qup_i2c13_default: qup-i2c13-default { 1581 pinmux { 1582 pins = "gpio105", "gpio106"; 1583 function = "qup13"; 1584 }; 1585 }; 1586 1587 qup_i2c14_default: qup-i2c14-default { 1588 pinmux { 1589 pins = "gpio33", "gpio34"; 1590 function = "qup14"; 1591 }; 1592 }; 1593 1594 qup_i2c15_default: qup-i2c15-default { 1595 pinmux { 1596 pins = "gpio81", "gpio82"; 1597 function = "qup15"; 1598 }; 1599 }; 1600 1601 qup_spi0_default: qup-spi0-default { 1602 pinmux { 1603 pins = "gpio0", "gpio1", 1604 "gpio2", "gpio3"; 1605 function = "qup0"; 1606 }; 1607 }; 1608 1609 qup_spi1_default: qup-spi1-default { 1610 pinmux { 1611 pins = "gpio17", "gpio18", 1612 "gpio19", "gpio20"; 1613 function = "qup1"; 1614 }; 1615 }; 1616 1617 qup_spi2_default: qup-spi2-default { 1618 pinmux { 1619 pins = "gpio27", "gpio28", 1620 "gpio29", "gpio30"; 1621 function = "qup2"; 1622 }; 1623 }; 1624 1625 qup_spi3_default: qup-spi3-default { 1626 pinmux { 1627 pins = "gpio41", "gpio42", 1628 "gpio43", "gpio44"; 1629 function = "qup3"; 1630 }; 1631 }; 1632 1633 qup_spi4_default: qup-spi4-default { 1634 pinmux { 1635 pins = "gpio89", "gpio90", 1636 "gpio91", "gpio92"; 1637 function = "qup4"; 1638 }; 1639 }; 1640 1641 qup_spi5_default: qup-spi5-default { 1642 pinmux { 1643 pins = "gpio85", "gpio86", 1644 "gpio87", "gpio88"; 1645 function = "qup5"; 1646 }; 1647 }; 1648 1649 qup_spi6_default: qup-spi6-default { 1650 pinmux { 1651 pins = "gpio45", "gpio46", 1652 "gpio47", "gpio48"; 1653 function = "qup6"; 1654 }; 1655 }; 1656 1657 qup_spi7_default: qup-spi7-default { 1658 pinmux { 1659 pins = "gpio93", "gpio94", 1660 "gpio95", "gpio96"; 1661 function = "qup7"; 1662 }; 1663 }; 1664 1665 qup_spi8_default: qup-spi8-default { 1666 pinmux { 1667 pins = "gpio65", "gpio66", 1668 "gpio67", "gpio68"; 1669 function = "qup8"; 1670 }; 1671 }; 1672 1673 qup_spi9_default: qup-spi9-default { 1674 pinmux { 1675 pins = "gpio6", "gpio7", 1676 "gpio4", "gpio5"; 1677 function = "qup9"; 1678 }; 1679 }; 1680 1681 qup_spi10_default: qup-spi10-default { 1682 pinmux { 1683 pins = "gpio55", "gpio56", 1684 "gpio53", "gpio54"; 1685 function = "qup10"; 1686 }; 1687 }; 1688 1689 qup_spi11_default: qup-spi11-default { 1690 pinmux { 1691 pins = "gpio31", "gpio32", 1692 "gpio33", "gpio34"; 1693 function = "qup11"; 1694 }; 1695 }; 1696 1697 qup_spi12_default: qup-spi12-default { 1698 pinmux { 1699 pins = "gpio49", "gpio50", 1700 "gpio51", "gpio52"; 1701 function = "qup12"; 1702 }; 1703 }; 1704 1705 qup_spi13_default: qup-spi13-default { 1706 pinmux { 1707 pins = "gpio105", "gpio106", 1708 "gpio107", "gpio108"; 1709 function = "qup13"; 1710 }; 1711 }; 1712 1713 qup_spi14_default: qup-spi14-default { 1714 pinmux { 1715 pins = "gpio33", "gpio34", 1716 "gpio31", "gpio32"; 1717 function = "qup14"; 1718 }; 1719 }; 1720 1721 qup_spi15_default: qup-spi15-default { 1722 pinmux { 1723 pins = "gpio81", "gpio82", 1724 "gpio83", "gpio84"; 1725 function = "qup15"; 1726 }; 1727 }; 1728 1729 qup_uart0_default: qup-uart0-default { 1730 pinmux { 1731 pins = "gpio2", "gpio3"; 1732 function = "qup0"; 1733 }; 1734 }; 1735 1736 qup_uart1_default: qup-uart1-default { 1737 pinmux { 1738 pins = "gpio19", "gpio20"; 1739 function = "qup1"; 1740 }; 1741 }; 1742 1743 qup_uart2_default: qup-uart2-default { 1744 pinmux { 1745 pins = "gpio29", "gpio30"; 1746 function = "qup2"; 1747 }; 1748 }; 1749 1750 qup_uart3_default: qup-uart3-default { 1751 pinmux { 1752 pins = "gpio43", "gpio44"; 1753 function = "qup3"; 1754 }; 1755 }; 1756 1757 qup_uart4_default: qup-uart4-default { 1758 pinmux { 1759 pins = "gpio91", "gpio92"; 1760 function = "qup4"; 1761 }; 1762 }; 1763 1764 qup_uart5_default: qup-uart5-default { 1765 pinmux { 1766 pins = "gpio87", "gpio88"; 1767 function = "qup5"; 1768 }; 1769 }; 1770 1771 qup_uart6_default: qup-uart6-default { 1772 pinmux { 1773 pins = "gpio47", "gpio48"; 1774 function = "qup6"; 1775 }; 1776 }; 1777 1778 qup_uart7_default: qup-uart7-default { 1779 pinmux { 1780 pins = "gpio95", "gpio96"; 1781 function = "qup7"; 1782 }; 1783 }; 1784 1785 qup_uart8_default: qup-uart8-default { 1786 pinmux { 1787 pins = "gpio67", "gpio68"; 1788 function = "qup8"; 1789 }; 1790 }; 1791 1792 qup_uart9_default: qup-uart9-default { 1793 pinmux { 1794 pins = "gpio4", "gpio5"; 1795 function = "qup9"; 1796 }; 1797 }; 1798 1799 qup_uart10_default: qup-uart10-default { 1800 pinmux { 1801 pins = "gpio53", "gpio54"; 1802 function = "qup10"; 1803 }; 1804 }; 1805 1806 qup_uart11_default: qup-uart11-default { 1807 pinmux { 1808 pins = "gpio33", "gpio34"; 1809 function = "qup11"; 1810 }; 1811 }; 1812 1813 qup_uart12_default: qup-uart12-default { 1814 pinmux { 1815 pins = "gpio51", "gpio52"; 1816 function = "qup12"; 1817 }; 1818 }; 1819 1820 qup_uart13_default: qup-uart13-default { 1821 pinmux { 1822 pins = "gpio107", "gpio108"; 1823 function = "qup13"; 1824 }; 1825 }; 1826 1827 qup_uart14_default: qup-uart14-default { 1828 pinmux { 1829 pins = "gpio31", "gpio32"; 1830 function = "qup14"; 1831 }; 1832 }; 1833 1834 qup_uart15_default: qup-uart15-default { 1835 pinmux { 1836 pins = "gpio83", "gpio84"; 1837 function = "qup15"; 1838 }; 1839 }; 1840 }; 1841 1842 mss_pil: remoteproc@4080000 { 1843 compatible = "qcom,sdm845-mss-pil"; 1844 reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>; 1845 reg-names = "qdsp6", "rmb"; 1846 1847 interrupts-extended = 1848 <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>, 1849 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1850 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1851 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1852 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1853 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1854 interrupt-names = "wdog", "fatal", "ready", 1855 "handover", "stop-ack", 1856 "shutdown-ack"; 1857 1858 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1859 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>, 1860 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1861 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1862 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1863 <&gcc GCC_MSS_MFAB_AXIS_CLK>, 1864 <&gcc GCC_PRNG_AHB_CLK>, 1865 <&rpmhcc RPMH_CXO_CLK>; 1866 clock-names = "iface", "bus", "mem", "gpll0_mss", 1867 "snoc_axi", "mnoc_axi", "prng", "xo"; 1868 1869 qcom,smem-states = <&modem_smp2p_out 0>; 1870 qcom,smem-state-names = "stop"; 1871 1872 resets = <&aoss_reset AOSS_CC_MSS_RESTART>, 1873 <&pdc_reset PDC_MODEM_SYNC_RESET>; 1874 reset-names = "mss_restart", "pdc_reset"; 1875 1876 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; 1877 1878 power-domains = <&aoss_qmp 2>, 1879 <&rpmhpd SDM845_CX>, 1880 <&rpmhpd SDM845_MX>, 1881 <&rpmhpd SDM845_MSS>; 1882 power-domain-names = "load_state", "cx", "mx", "mss"; 1883 1884 mba { 1885 memory-region = <&mba_region>; 1886 }; 1887 1888 mpss { 1889 memory-region = <&mpss_region>; 1890 }; 1891 1892 glink-edge { 1893 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>; 1894 label = "modem"; 1895 qcom,remote-pid = <1>; 1896 mboxes = <&apss_shared 12>; 1897 }; 1898 }; 1899 1900 gpucc: clock-controller@5090000 { 1901 compatible = "qcom,sdm845-gpucc"; 1902 reg = <0 0x05090000 0 0x9000>; 1903 #clock-cells = <1>; 1904 #reset-cells = <1>; 1905 #power-domain-cells = <1>; 1906 clocks = <&rpmhcc RPMH_CXO_CLK>; 1907 clock-names = "xo"; 1908 }; 1909 1910 stm@6002000 { 1911 compatible = "arm,coresight-stm", "arm,primecell"; 1912 reg = <0 0x06002000 0 0x1000>, 1913 <0 0x16280000 0 0x180000>; 1914 reg-names = "stm-base", "stm-stimulus-base"; 1915 1916 clocks = <&aoss_qmp>; 1917 clock-names = "apb_pclk"; 1918 1919 out-ports { 1920 port { 1921 stm_out: endpoint { 1922 remote-endpoint = 1923 <&funnel0_in7>; 1924 }; 1925 }; 1926 }; 1927 }; 1928 1929 funnel@6041000 { 1930 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1931 reg = <0 0x06041000 0 0x1000>; 1932 1933 clocks = <&aoss_qmp>; 1934 clock-names = "apb_pclk"; 1935 1936 out-ports { 1937 port { 1938 funnel0_out: endpoint { 1939 remote-endpoint = 1940 <&merge_funnel_in0>; 1941 }; 1942 }; 1943 }; 1944 1945 in-ports { 1946 #address-cells = <1>; 1947 #size-cells = <0>; 1948 1949 port@7 { 1950 reg = <7>; 1951 funnel0_in7: endpoint { 1952 remote-endpoint = <&stm_out>; 1953 }; 1954 }; 1955 }; 1956 }; 1957 1958 funnel@6043000 { 1959 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1960 reg = <0 0x06043000 0 0x1000>; 1961 1962 clocks = <&aoss_qmp>; 1963 clock-names = "apb_pclk"; 1964 1965 out-ports { 1966 port { 1967 funnel2_out: endpoint { 1968 remote-endpoint = 1969 <&merge_funnel_in2>; 1970 }; 1971 }; 1972 }; 1973 1974 in-ports { 1975 #address-cells = <1>; 1976 #size-cells = <0>; 1977 1978 port@5 { 1979 reg = <5>; 1980 funnel2_in5: endpoint { 1981 remote-endpoint = 1982 <&apss_merge_funnel_out>; 1983 }; 1984 }; 1985 }; 1986 }; 1987 1988 funnel@6045000 { 1989 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1990 reg = <0 0x06045000 0 0x1000>; 1991 1992 clocks = <&aoss_qmp>; 1993 clock-names = "apb_pclk"; 1994 1995 out-ports { 1996 port { 1997 merge_funnel_out: endpoint { 1998 remote-endpoint = <&etf_in>; 1999 }; 2000 }; 2001 }; 2002 2003 in-ports { 2004 #address-cells = <1>; 2005 #size-cells = <0>; 2006 2007 port@0 { 2008 reg = <0>; 2009 merge_funnel_in0: endpoint { 2010 remote-endpoint = 2011 <&funnel0_out>; 2012 }; 2013 }; 2014 2015 port@2 { 2016 reg = <2>; 2017 merge_funnel_in2: endpoint { 2018 remote-endpoint = 2019 <&funnel2_out>; 2020 }; 2021 }; 2022 }; 2023 }; 2024 2025 replicator@6046000 { 2026 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2027 reg = <0 0x06046000 0 0x1000>; 2028 2029 clocks = <&aoss_qmp>; 2030 clock-names = "apb_pclk"; 2031 2032 out-ports { 2033 port { 2034 replicator_out: endpoint { 2035 remote-endpoint = <&etr_in>; 2036 }; 2037 }; 2038 }; 2039 2040 in-ports { 2041 port { 2042 replicator_in: endpoint { 2043 remote-endpoint = <&etf_out>; 2044 }; 2045 }; 2046 }; 2047 }; 2048 2049 etf@6047000 { 2050 compatible = "arm,coresight-tmc", "arm,primecell"; 2051 reg = <0 0x06047000 0 0x1000>; 2052 2053 clocks = <&aoss_qmp>; 2054 clock-names = "apb_pclk"; 2055 2056 out-ports { 2057 port { 2058 etf_out: endpoint { 2059 remote-endpoint = 2060 <&replicator_in>; 2061 }; 2062 }; 2063 }; 2064 2065 in-ports { 2066 #address-cells = <1>; 2067 #size-cells = <0>; 2068 2069 port@1 { 2070 reg = <1>; 2071 etf_in: endpoint { 2072 remote-endpoint = 2073 <&merge_funnel_out>; 2074 }; 2075 }; 2076 }; 2077 }; 2078 2079 etr@6048000 { 2080 compatible = "arm,coresight-tmc", "arm,primecell"; 2081 reg = <0 0x06048000 0 0x1000>; 2082 2083 clocks = <&aoss_qmp>; 2084 clock-names = "apb_pclk"; 2085 arm,scatter-gather; 2086 2087 in-ports { 2088 port { 2089 etr_in: endpoint { 2090 remote-endpoint = 2091 <&replicator_out>; 2092 }; 2093 }; 2094 }; 2095 }; 2096 2097 etm@7040000 { 2098 compatible = "arm,coresight-etm4x", "arm,primecell"; 2099 reg = <0 0x07040000 0 0x1000>; 2100 2101 cpu = <&CPU0>; 2102 2103 clocks = <&aoss_qmp>; 2104 clock-names = "apb_pclk"; 2105 2106 out-ports { 2107 port { 2108 etm0_out: endpoint { 2109 remote-endpoint = 2110 <&apss_funnel_in0>; 2111 }; 2112 }; 2113 }; 2114 }; 2115 2116 etm@7140000 { 2117 compatible = "arm,coresight-etm4x", "arm,primecell"; 2118 reg = <0 0x07140000 0 0x1000>; 2119 2120 cpu = <&CPU1>; 2121 2122 clocks = <&aoss_qmp>; 2123 clock-names = "apb_pclk"; 2124 2125 out-ports { 2126 port { 2127 etm1_out: endpoint { 2128 remote-endpoint = 2129 <&apss_funnel_in1>; 2130 }; 2131 }; 2132 }; 2133 }; 2134 2135 etm@7240000 { 2136 compatible = "arm,coresight-etm4x", "arm,primecell"; 2137 reg = <0 0x07240000 0 0x1000>; 2138 2139 cpu = <&CPU2>; 2140 2141 clocks = <&aoss_qmp>; 2142 clock-names = "apb_pclk"; 2143 2144 out-ports { 2145 port { 2146 etm2_out: endpoint { 2147 remote-endpoint = 2148 <&apss_funnel_in2>; 2149 }; 2150 }; 2151 }; 2152 }; 2153 2154 etm@7340000 { 2155 compatible = "arm,coresight-etm4x", "arm,primecell"; 2156 reg = <0 0x07340000 0 0x1000>; 2157 2158 cpu = <&CPU3>; 2159 2160 clocks = <&aoss_qmp>; 2161 clock-names = "apb_pclk"; 2162 2163 out-ports { 2164 port { 2165 etm3_out: endpoint { 2166 remote-endpoint = 2167 <&apss_funnel_in3>; 2168 }; 2169 }; 2170 }; 2171 }; 2172 2173 etm@7440000 { 2174 compatible = "arm,coresight-etm4x", "arm,primecell"; 2175 reg = <0 0x07440000 0 0x1000>; 2176 2177 cpu = <&CPU4>; 2178 2179 clocks = <&aoss_qmp>; 2180 clock-names = "apb_pclk"; 2181 2182 out-ports { 2183 port { 2184 etm4_out: endpoint { 2185 remote-endpoint = 2186 <&apss_funnel_in4>; 2187 }; 2188 }; 2189 }; 2190 }; 2191 2192 etm@7540000 { 2193 compatible = "arm,coresight-etm4x", "arm,primecell"; 2194 reg = <0 0x07540000 0 0x1000>; 2195 2196 cpu = <&CPU5>; 2197 2198 clocks = <&aoss_qmp>; 2199 clock-names = "apb_pclk"; 2200 2201 out-ports { 2202 port { 2203 etm5_out: endpoint { 2204 remote-endpoint = 2205 <&apss_funnel_in5>; 2206 }; 2207 }; 2208 }; 2209 }; 2210 2211 etm@7640000 { 2212 compatible = "arm,coresight-etm4x", "arm,primecell"; 2213 reg = <0 0x07640000 0 0x1000>; 2214 2215 cpu = <&CPU6>; 2216 2217 clocks = <&aoss_qmp>; 2218 clock-names = "apb_pclk"; 2219 2220 out-ports { 2221 port { 2222 etm6_out: endpoint { 2223 remote-endpoint = 2224 <&apss_funnel_in6>; 2225 }; 2226 }; 2227 }; 2228 }; 2229 2230 etm@7740000 { 2231 compatible = "arm,coresight-etm4x", "arm,primecell"; 2232 reg = <0 0x07740000 0 0x1000>; 2233 2234 cpu = <&CPU7>; 2235 2236 clocks = <&aoss_qmp>; 2237 clock-names = "apb_pclk"; 2238 2239 out-ports { 2240 port { 2241 etm7_out: endpoint { 2242 remote-endpoint = 2243 <&apss_funnel_in7>; 2244 }; 2245 }; 2246 }; 2247 }; 2248 2249 funnel@7800000 { /* APSS Funnel */ 2250 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2251 reg = <0 0x07800000 0 0x1000>; 2252 2253 clocks = <&aoss_qmp>; 2254 clock-names = "apb_pclk"; 2255 2256 out-ports { 2257 port { 2258 apss_funnel_out: endpoint { 2259 remote-endpoint = 2260 <&apss_merge_funnel_in>; 2261 }; 2262 }; 2263 }; 2264 2265 in-ports { 2266 #address-cells = <1>; 2267 #size-cells = <0>; 2268 2269 port@0 { 2270 reg = <0>; 2271 apss_funnel_in0: endpoint { 2272 remote-endpoint = 2273 <&etm0_out>; 2274 }; 2275 }; 2276 2277 port@1 { 2278 reg = <1>; 2279 apss_funnel_in1: endpoint { 2280 remote-endpoint = 2281 <&etm1_out>; 2282 }; 2283 }; 2284 2285 port@2 { 2286 reg = <2>; 2287 apss_funnel_in2: endpoint { 2288 remote-endpoint = 2289 <&etm2_out>; 2290 }; 2291 }; 2292 2293 port@3 { 2294 reg = <3>; 2295 apss_funnel_in3: endpoint { 2296 remote-endpoint = 2297 <&etm3_out>; 2298 }; 2299 }; 2300 2301 port@4 { 2302 reg = <4>; 2303 apss_funnel_in4: endpoint { 2304 remote-endpoint = 2305 <&etm4_out>; 2306 }; 2307 }; 2308 2309 port@5 { 2310 reg = <5>; 2311 apss_funnel_in5: endpoint { 2312 remote-endpoint = 2313 <&etm5_out>; 2314 }; 2315 }; 2316 2317 port@6 { 2318 reg = <6>; 2319 apss_funnel_in6: endpoint { 2320 remote-endpoint = 2321 <&etm6_out>; 2322 }; 2323 }; 2324 2325 port@7 { 2326 reg = <7>; 2327 apss_funnel_in7: endpoint { 2328 remote-endpoint = 2329 <&etm7_out>; 2330 }; 2331 }; 2332 }; 2333 }; 2334 2335 funnel@7810000 { 2336 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2337 reg = <0 0x07810000 0 0x1000>; 2338 2339 clocks = <&aoss_qmp>; 2340 clock-names = "apb_pclk"; 2341 2342 out-ports { 2343 port { 2344 apss_merge_funnel_out: endpoint { 2345 remote-endpoint = 2346 <&funnel2_in5>; 2347 }; 2348 }; 2349 }; 2350 2351 in-ports { 2352 port { 2353 apss_merge_funnel_in: endpoint { 2354 remote-endpoint = 2355 <&apss_funnel_out>; 2356 }; 2357 }; 2358 }; 2359 }; 2360 2361 sdhc_2: sdhci@8804000 { 2362 compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; 2363 reg = <0 0x08804000 0 0x1000>; 2364 2365 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 2366 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2367 interrupt-names = "hc_irq", "pwr_irq"; 2368 2369 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2370 <&gcc GCC_SDCC2_APPS_CLK>; 2371 clock-names = "iface", "core"; 2372 iommus = <&apps_smmu 0xa0 0xf>; 2373 2374 status = "disabled"; 2375 }; 2376 2377 qspi: spi@88df000 { 2378 compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; 2379 reg = <0 0x088df000 0 0x600>; 2380 #address-cells = <1>; 2381 #size-cells = <0>; 2382 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 2383 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 2384 <&gcc GCC_QSPI_CORE_CLK>; 2385 clock-names = "iface", "core"; 2386 status = "disabled"; 2387 }; 2388 2389 usb_1_hsphy: phy@88e2000 { 2390 compatible = "qcom,sdm845-qusb2-phy"; 2391 reg = <0 0x088e2000 0 0x400>; 2392 status = "disabled"; 2393 #phy-cells = <0>; 2394 2395 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2396 <&rpmhcc RPMH_CXO_CLK>; 2397 clock-names = "cfg_ahb", "ref"; 2398 2399 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2400 2401 nvmem-cells = <&qusb2p_hstx_trim>; 2402 }; 2403 2404 usb_2_hsphy: phy@88e3000 { 2405 compatible = "qcom,sdm845-qusb2-phy"; 2406 reg = <0 0x088e3000 0 0x400>; 2407 status = "disabled"; 2408 #phy-cells = <0>; 2409 2410 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2411 <&rpmhcc RPMH_CXO_CLK>; 2412 clock-names = "cfg_ahb", "ref"; 2413 2414 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 2415 2416 nvmem-cells = <&qusb2s_hstx_trim>; 2417 }; 2418 2419 usb_1_qmpphy: phy@88e9000 { 2420 compatible = "qcom,sdm845-qmp-usb3-phy"; 2421 reg = <0 0x088e9000 0 0x18c>, 2422 <0 0x088e8000 0 0x10>; 2423 reg-names = "reg-base", "dp_com"; 2424 status = "disabled"; 2425 #clock-cells = <1>; 2426 #address-cells = <2>; 2427 #size-cells = <2>; 2428 ranges; 2429 2430 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2431 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2432 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 2433 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; 2434 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2435 2436 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 2437 <&gcc GCC_USB3_PHY_PRIM_BCR>; 2438 reset-names = "phy", "common"; 2439 2440 usb_1_ssphy: lanes@88e9200 { 2441 reg = <0 0x088e9200 0 0x128>, 2442 <0 0x088e9400 0 0x200>, 2443 <0 0x088e9c00 0 0x218>, 2444 <0 0x088e9600 0 0x128>, 2445 <0 0x088e9800 0 0x200>, 2446 <0 0x088e9a00 0 0x100>; 2447 #phy-cells = <0>; 2448 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2449 clock-names = "pipe0"; 2450 clock-output-names = "usb3_phy_pipe_clk_src"; 2451 }; 2452 }; 2453 2454 usb_2_qmpphy: phy@88eb000 { 2455 compatible = "qcom,sdm845-qmp-usb3-uni-phy"; 2456 reg = <0 0x088eb000 0 0x18c>; 2457 status = "disabled"; 2458 #clock-cells = <1>; 2459 #address-cells = <2>; 2460 #size-cells = <2>; 2461 ranges; 2462 2463 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, 2464 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2465 <&gcc GCC_USB3_SEC_CLKREF_CLK>, 2466 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; 2467 clock-names = "aux", "cfg_ahb", "ref", "com_aux"; 2468 2469 resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 2470 <&gcc GCC_USB3_PHY_SEC_BCR>; 2471 reset-names = "phy", "common"; 2472 2473 usb_2_ssphy: lane@88eb200 { 2474 reg = <0 0x088eb200 0 0x128>, 2475 <0 0x088eb400 0 0x1fc>, 2476 <0 0x088eb800 0 0x218>, 2477 <0 0x088eb600 0 0x70>; 2478 #phy-cells = <0>; 2479 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; 2480 clock-names = "pipe0"; 2481 clock-output-names = "usb3_uni_phy_pipe_clk_src"; 2482 }; 2483 }; 2484 2485 usb_1: usb@a6f8800 { 2486 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 2487 reg = <0 0x0a6f8800 0 0x400>; 2488 status = "disabled"; 2489 #address-cells = <2>; 2490 #size-cells = <2>; 2491 ranges; 2492 dma-ranges; 2493 2494 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2495 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2496 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2497 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2498 <&gcc GCC_USB30_PRIM_SLEEP_CLK>; 2499 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2500 "sleep"; 2501 2502 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2503 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2504 assigned-clock-rates = <19200000>, <150000000>; 2505 2506 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2507 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 2508 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 2509 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; 2510 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2511 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2512 2513 power-domains = <&gcc USB30_PRIM_GDSC>; 2514 2515 resets = <&gcc GCC_USB30_PRIM_BCR>; 2516 2517 usb_1_dwc3: dwc3@a600000 { 2518 compatible = "snps,dwc3"; 2519 reg = <0 0x0a600000 0 0xcd00>; 2520 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2521 iommus = <&apps_smmu 0x740 0>; 2522 snps,dis_u2_susphy_quirk; 2523 snps,dis_enblslpm_quirk; 2524 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 2525 phy-names = "usb2-phy", "usb3-phy"; 2526 }; 2527 }; 2528 2529 usb_2: usb@a8f8800 { 2530 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 2531 reg = <0 0x0a8f8800 0 0x400>; 2532 status = "disabled"; 2533 #address-cells = <2>; 2534 #size-cells = <2>; 2535 ranges; 2536 dma-ranges; 2537 2538 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 2539 <&gcc GCC_USB30_SEC_MASTER_CLK>, 2540 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 2541 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2542 <&gcc GCC_USB30_SEC_SLEEP_CLK>; 2543 clock-names = "cfg_noc", "core", "iface", "mock_utmi", 2544 "sleep"; 2545 2546 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 2547 <&gcc GCC_USB30_SEC_MASTER_CLK>; 2548 assigned-clock-rates = <19200000>, <150000000>; 2549 2550 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2551 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 2552 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 2553 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; 2554 interrupt-names = "hs_phy_irq", "ss_phy_irq", 2555 "dm_hs_phy_irq", "dp_hs_phy_irq"; 2556 2557 power-domains = <&gcc USB30_SEC_GDSC>; 2558 2559 resets = <&gcc GCC_USB30_SEC_BCR>; 2560 2561 usb_2_dwc3: dwc3@a800000 { 2562 compatible = "snps,dwc3"; 2563 reg = <0 0x0a800000 0 0xcd00>; 2564 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2565 iommus = <&apps_smmu 0x760 0>; 2566 snps,dis_u2_susphy_quirk; 2567 snps,dis_enblslpm_quirk; 2568 phys = <&usb_2_hsphy>, <&usb_2_ssphy>; 2569 phy-names = "usb2-phy", "usb3-phy"; 2570 }; 2571 }; 2572 2573 video-codec@aa00000 { 2574 compatible = "qcom,sdm845-venus"; 2575 reg = <0 0x0aa00000 0 0xff000>; 2576 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 2577 power-domains = <&videocc VENUS_GDSC>; 2578 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 2579 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 2580 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>; 2581 clock-names = "core", "iface", "bus"; 2582 iommus = <&apps_smmu 0x10a0 0x8>, 2583 <&apps_smmu 0x10b0 0x0>; 2584 memory-region = <&venus_mem>; 2585 2586 video-core0 { 2587 compatible = "venus-decoder"; 2588 clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 2589 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 2590 clock-names = "core", "bus"; 2591 power-domains = <&videocc VCODEC0_GDSC>; 2592 }; 2593 2594 video-core1 { 2595 compatible = "venus-encoder"; 2596 clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>, 2597 <&videocc VIDEO_CC_VCODEC1_AXI_CLK>; 2598 clock-names = "core", "bus"; 2599 power-domains = <&videocc VCODEC1_GDSC>; 2600 }; 2601 }; 2602 2603 videocc: clock-controller@ab00000 { 2604 compatible = "qcom,sdm845-videocc"; 2605 reg = <0 0x0ab00000 0 0x10000>; 2606 #clock-cells = <1>; 2607 #power-domain-cells = <1>; 2608 #reset-cells = <1>; 2609 }; 2610 2611 mdss: mdss@ae00000 { 2612 compatible = "qcom,sdm845-mdss"; 2613 reg = <0 0x0ae00000 0 0x1000>; 2614 reg-names = "mdss"; 2615 2616 power-domains = <&dispcc MDSS_GDSC>; 2617 2618 clocks = <&gcc GCC_DISP_AHB_CLK>, 2619 <&gcc GCC_DISP_AXI_CLK>, 2620 <&dispcc DISP_CC_MDSS_MDP_CLK>; 2621 clock-names = "iface", "bus", "core"; 2622 2623 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; 2624 assigned-clock-rates = <300000000>; 2625 2626 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2627 interrupt-controller; 2628 #interrupt-cells = <1>; 2629 2630 iommus = <&apps_smmu 0x880 0x8>, 2631 <&apps_smmu 0xc80 0x8>; 2632 2633 status = "disabled"; 2634 2635 #address-cells = <2>; 2636 #size-cells = <2>; 2637 ranges; 2638 2639 mdss_mdp: mdp@ae01000 { 2640 compatible = "qcom,sdm845-dpu"; 2641 reg = <0 0x0ae01000 0 0x8f000>, 2642 <0 0x0aeb0000 0 0x2008>; 2643 reg-names = "mdp", "vbif"; 2644 2645 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2646 <&dispcc DISP_CC_MDSS_AXI_CLK>, 2647 <&dispcc DISP_CC_MDSS_MDP_CLK>, 2648 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2649 clock-names = "iface", "bus", "core", "vsync"; 2650 2651 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, 2652 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 2653 assigned-clock-rates = <300000000>, 2654 <19200000>; 2655 2656 interrupt-parent = <&mdss>; 2657 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 2658 2659 status = "disabled"; 2660 2661 ports { 2662 #address-cells = <1>; 2663 #size-cells = <0>; 2664 2665 port@0 { 2666 reg = <0>; 2667 dpu_intf1_out: endpoint { 2668 remote-endpoint = <&dsi0_in>; 2669 }; 2670 }; 2671 2672 port@1 { 2673 reg = <1>; 2674 dpu_intf2_out: endpoint { 2675 remote-endpoint = <&dsi1_in>; 2676 }; 2677 }; 2678 }; 2679 }; 2680 2681 dsi0: dsi@ae94000 { 2682 compatible = "qcom,mdss-dsi-ctrl"; 2683 reg = <0 0x0ae94000 0 0x400>; 2684 reg-names = "dsi_ctrl"; 2685 2686 interrupt-parent = <&mdss>; 2687 interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; 2688 2689 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 2690 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 2691 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 2692 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 2693 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2694 <&dispcc DISP_CC_MDSS_AXI_CLK>; 2695 clock-names = "byte", 2696 "byte_intf", 2697 "pixel", 2698 "core", 2699 "iface", 2700 "bus"; 2701 2702 phys = <&dsi0_phy>; 2703 phy-names = "dsi"; 2704 2705 status = "disabled"; 2706 2707 ports { 2708 #address-cells = <1>; 2709 #size-cells = <0>; 2710 2711 port@0 { 2712 reg = <0>; 2713 dsi0_in: endpoint { 2714 remote-endpoint = <&dpu_intf1_out>; 2715 }; 2716 }; 2717 2718 port@1 { 2719 reg = <1>; 2720 dsi0_out: endpoint { 2721 }; 2722 }; 2723 }; 2724 }; 2725 2726 dsi0_phy: dsi-phy@ae94400 { 2727 compatible = "qcom,dsi-phy-10nm"; 2728 reg = <0 0x0ae94400 0 0x200>, 2729 <0 0x0ae94600 0 0x280>, 2730 <0 0x0ae94a00 0 0x1e0>; 2731 reg-names = "dsi_phy", 2732 "dsi_phy_lane", 2733 "dsi_pll"; 2734 2735 #clock-cells = <1>; 2736 #phy-cells = <0>; 2737 2738 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2739 <&rpmhcc RPMH_CXO_CLK>; 2740 clock-names = "iface", "ref"; 2741 2742 status = "disabled"; 2743 }; 2744 2745 dsi1: dsi@ae96000 { 2746 compatible = "qcom,mdss-dsi-ctrl"; 2747 reg = <0 0x0ae96000 0 0x400>; 2748 reg-names = "dsi_ctrl"; 2749 2750 interrupt-parent = <&mdss>; 2751 interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 2752 2753 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 2754 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 2755 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 2756 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 2757 <&dispcc DISP_CC_MDSS_AHB_CLK>, 2758 <&dispcc DISP_CC_MDSS_AXI_CLK>; 2759 clock-names = "byte", 2760 "byte_intf", 2761 "pixel", 2762 "core", 2763 "iface", 2764 "bus"; 2765 2766 phys = <&dsi1_phy>; 2767 phy-names = "dsi"; 2768 2769 status = "disabled"; 2770 2771 ports { 2772 #address-cells = <1>; 2773 #size-cells = <0>; 2774 2775 port@0 { 2776 reg = <0>; 2777 dsi1_in: endpoint { 2778 remote-endpoint = <&dpu_intf2_out>; 2779 }; 2780 }; 2781 2782 port@1 { 2783 reg = <1>; 2784 dsi1_out: endpoint { 2785 }; 2786 }; 2787 }; 2788 }; 2789 2790 dsi1_phy: dsi-phy@ae96400 { 2791 compatible = "qcom,dsi-phy-10nm"; 2792 reg = <0 0x0ae96400 0 0x200>, 2793 <0 0x0ae96600 0 0x280>, 2794 <0 0x0ae96a00 0 0x10e>; 2795 reg-names = "dsi_phy", 2796 "dsi_phy_lane", 2797 "dsi_pll"; 2798 2799 #clock-cells = <1>; 2800 #phy-cells = <0>; 2801 2802 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2803 <&rpmhcc RPMH_CXO_CLK>; 2804 clock-names = "iface", "ref"; 2805 2806 status = "disabled"; 2807 }; 2808 }; 2809 2810 gpu: gpu@5000000 { 2811 compatible = "qcom,adreno-630.2", "qcom,adreno"; 2812 #stream-id-cells = <16>; 2813 2814 reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>; 2815 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 2816 2817 /* 2818 * Look ma, no clocks! The GPU clocks and power are 2819 * controlled entirely by the GMU 2820 */ 2821 2822 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 2823 2824 iommus = <&adreno_smmu 0>; 2825 2826 operating-points-v2 = <&gpu_opp_table>; 2827 2828 qcom,gmu = <&gmu>; 2829 2830 gpu_opp_table: opp-table { 2831 compatible = "operating-points-v2"; 2832 2833 opp-710000000 { 2834 opp-hz = /bits/ 64 <710000000>; 2835 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2836 }; 2837 2838 opp-675000000 { 2839 opp-hz = /bits/ 64 <675000000>; 2840 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2841 }; 2842 2843 opp-596000000 { 2844 opp-hz = /bits/ 64 <596000000>; 2845 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2846 }; 2847 2848 opp-520000000 { 2849 opp-hz = /bits/ 64 <520000000>; 2850 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2851 }; 2852 2853 opp-414000000 { 2854 opp-hz = /bits/ 64 <414000000>; 2855 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2856 }; 2857 2858 opp-342000000 { 2859 opp-hz = /bits/ 64 <342000000>; 2860 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2861 }; 2862 2863 opp-257000000 { 2864 opp-hz = /bits/ 64 <257000000>; 2865 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2866 }; 2867 }; 2868 }; 2869 2870 adreno_smmu: iommu@5040000 { 2871 compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2"; 2872 reg = <0 0x5040000 0 0x10000>; 2873 #iommu-cells = <1>; 2874 #global-interrupts = <2>; 2875 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 2876 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 2877 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 2878 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 2879 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 2880 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 2881 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 2882 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 2883 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 2884 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 2885 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 2886 <&gcc GCC_GPU_CFG_AHB_CLK>; 2887 clock-names = "bus", "iface"; 2888 2889 power-domains = <&gpucc GPU_CX_GDSC>; 2890 }; 2891 2892 gmu: gmu@506a000 { 2893 compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu"; 2894 2895 reg = <0 0x506a000 0 0x30000>, 2896 <0 0xb280000 0 0x10000>, 2897 <0 0xb480000 0 0x10000>; 2898 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 2899 2900 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 2901 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 2902 interrupt-names = "hfi", "gmu"; 2903 2904 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 2905 <&gpucc GPU_CC_CXO_CLK>, 2906 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 2907 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 2908 clock-names = "gmu", "cxo", "axi", "memnoc"; 2909 2910 power-domains = <&gpucc GPU_CX_GDSC>, 2911 <&gpucc GPU_GX_GDSC>; 2912 power-domain-names = "cx", "gx"; 2913 2914 iommus = <&adreno_smmu 5>; 2915 2916 operating-points-v2 = <&gmu_opp_table>; 2917 2918 gmu_opp_table: opp-table { 2919 compatible = "operating-points-v2"; 2920 2921 opp-400000000 { 2922 opp-hz = /bits/ 64 <400000000>; 2923 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2924 }; 2925 2926 opp-200000000 { 2927 opp-hz = /bits/ 64 <200000000>; 2928 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2929 }; 2930 }; 2931 }; 2932 2933 dispcc: clock-controller@af00000 { 2934 compatible = "qcom,sdm845-dispcc"; 2935 reg = <0 0x0af00000 0 0x10000>; 2936 #clock-cells = <1>; 2937 #reset-cells = <1>; 2938 #power-domain-cells = <1>; 2939 }; 2940 2941 pdc_intc: interrupt-controller@b220000 { 2942 compatible = "qcom,sdm845-pdc", "qcom,pdc"; 2943 reg = <0 0x0b220000 0 0x30000>; 2944 qcom,pdc-ranges = <0 480 94>, <94 609 15>, <115 630 7>; 2945 #interrupt-cells = <2>; 2946 interrupt-parent = <&intc>; 2947 interrupt-controller; 2948 }; 2949 2950 pdc_reset: reset-controller@b2e0000 { 2951 compatible = "qcom,sdm845-pdc-global"; 2952 reg = <0 0x0b2e0000 0 0x20000>; 2953 #reset-cells = <1>; 2954 }; 2955 2956 tsens0: thermal-sensor@c263000 { 2957 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 2958 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 2959 <0 0x0c222000 0 0x1ff>; /* SROT */ 2960 #qcom,sensors = <13>; 2961 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 2962 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 2963 interrupt-names = "uplow", "critical"; 2964 #thermal-sensor-cells = <1>; 2965 }; 2966 2967 tsens1: thermal-sensor@c265000 { 2968 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 2969 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 2970 <0 0x0c223000 0 0x1ff>; /* SROT */ 2971 #qcom,sensors = <8>; 2972 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 2973 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 2974 interrupt-names = "uplow", "critical"; 2975 #thermal-sensor-cells = <1>; 2976 }; 2977 2978 aoss_reset: reset-controller@c2a0000 { 2979 compatible = "qcom,sdm845-aoss-cc"; 2980 reg = <0 0x0c2a0000 0 0x31000>; 2981 #reset-cells = <1>; 2982 }; 2983 2984 aoss_qmp: qmp@c300000 { 2985 compatible = "qcom,sdm845-aoss-qmp"; 2986 reg = <0 0x0c300000 0 0x100000>; 2987 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 2988 mboxes = <&apss_shared 0>; 2989 2990 #clock-cells = <0>; 2991 #power-domain-cells = <1>; 2992 2993 cx_cdev: cx { 2994 #cooling-cells = <2>; 2995 }; 2996 2997 ebi_cdev: ebi { 2998 #cooling-cells = <2>; 2999 }; 3000 }; 3001 3002 spmi_bus: spmi@c440000 { 3003 compatible = "qcom,spmi-pmic-arb"; 3004 reg = <0 0x0c440000 0 0x1100>, 3005 <0 0x0c600000 0 0x2000000>, 3006 <0 0x0e600000 0 0x100000>, 3007 <0 0x0e700000 0 0xa0000>, 3008 <0 0x0c40a000 0 0x26000>; 3009 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 3010 interrupt-names = "periph_irq"; 3011 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 3012 qcom,ee = <0>; 3013 qcom,channel = <0>; 3014 #address-cells = <2>; 3015 #size-cells = <0>; 3016 interrupt-controller; 3017 #interrupt-cells = <4>; 3018 cell-index = <0>; 3019 }; 3020 3021 apps_smmu: iommu@15000000 { 3022 compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; 3023 reg = <0 0x15000000 0 0x80000>; 3024 #iommu-cells = <2>; 3025 #global-interrupts = <1>; 3026 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3027 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 3028 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3029 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3030 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3031 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3032 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3033 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3034 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3035 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3036 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3037 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3038 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3039 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3040 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3041 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3042 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3043 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3044 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3045 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3046 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3047 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3048 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3049 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3050 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3051 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3052 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3053 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3054 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3055 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3056 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3057 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3058 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3059 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3060 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3061 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3062 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3063 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3064 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3065 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3066 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3067 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3068 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3069 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3070 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3071 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3072 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3073 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3074 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3075 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3076 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3077 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3078 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3079 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3080 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3081 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3082 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3083 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3084 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3085 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3086 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3087 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3088 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3089 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3090 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 3091 }; 3092 3093 lpasscc: clock-controller@17014000 { 3094 compatible = "qcom,sdm845-lpasscc"; 3095 reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; 3096 reg-names = "cc", "qdsp6ss"; 3097 #clock-cells = <1>; 3098 status = "disabled"; 3099 }; 3100 3101 watchdog@17980000 { 3102 compatible = "qcom,apss-wdt-sdm845", "qcom,kpss-wdt"; 3103 reg = <0 0x17980000 0 0x1000>; 3104 clocks = <&sleep_clk>; 3105 }; 3106 3107 apss_shared: mailbox@17990000 { 3108 compatible = "qcom,sdm845-apss-shared"; 3109 reg = <0 0x17990000 0 0x1000>; 3110 #mbox-cells = <1>; 3111 }; 3112 3113 apps_rsc: rsc@179c0000 { 3114 label = "apps_rsc"; 3115 compatible = "qcom,rpmh-rsc"; 3116 reg = <0 0x179c0000 0 0x10000>, 3117 <0 0x179d0000 0 0x10000>, 3118 <0 0x179e0000 0 0x10000>; 3119 reg-names = "drv-0", "drv-1", "drv-2"; 3120 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3121 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3122 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3123 qcom,tcs-offset = <0xd00>; 3124 qcom,drv-id = <2>; 3125 qcom,tcs-config = <ACTIVE_TCS 2>, 3126 <SLEEP_TCS 3>, 3127 <WAKE_TCS 3>, 3128 <CONTROL_TCS 1>; 3129 3130 rpmhcc: clock-controller { 3131 compatible = "qcom,sdm845-rpmh-clk"; 3132 #clock-cells = <1>; 3133 clock-names = "xo"; 3134 clocks = <&xo_board>; 3135 }; 3136 3137 rpmhpd: power-controller { 3138 compatible = "qcom,sdm845-rpmhpd"; 3139 #power-domain-cells = <1>; 3140 operating-points-v2 = <&rpmhpd_opp_table>; 3141 3142 rpmhpd_opp_table: opp-table { 3143 compatible = "operating-points-v2"; 3144 3145 rpmhpd_opp_ret: opp1 { 3146 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3147 }; 3148 3149 rpmhpd_opp_min_svs: opp2 { 3150 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3151 }; 3152 3153 rpmhpd_opp_low_svs: opp3 { 3154 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3155 }; 3156 3157 rpmhpd_opp_svs: opp4 { 3158 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3159 }; 3160 3161 rpmhpd_opp_svs_l1: opp5 { 3162 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3163 }; 3164 3165 rpmhpd_opp_nom: opp6 { 3166 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3167 }; 3168 3169 rpmhpd_opp_nom_l1: opp7 { 3170 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3171 }; 3172 3173 rpmhpd_opp_nom_l2: opp8 { 3174 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3175 }; 3176 3177 rpmhpd_opp_turbo: opp9 { 3178 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3179 }; 3180 3181 rpmhpd_opp_turbo_l1: opp10 { 3182 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3183 }; 3184 }; 3185 }; 3186 3187 rsc_hlos: interconnect { 3188 compatible = "qcom,sdm845-rsc-hlos"; 3189 #interconnect-cells = <1>; 3190 }; 3191 }; 3192 3193 intc: interrupt-controller@17a00000 { 3194 compatible = "arm,gic-v3"; 3195 #address-cells = <2>; 3196 #size-cells = <2>; 3197 ranges; 3198 #interrupt-cells = <3>; 3199 interrupt-controller; 3200 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 3201 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 3202 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3203 3204 msi-controller@17a40000 { 3205 compatible = "arm,gic-v3-its"; 3206 msi-controller; 3207 #msi-cells = <1>; 3208 reg = <0 0x17a40000 0 0x20000>; 3209 status = "disabled"; 3210 }; 3211 }; 3212 3213 timer@17c90000 { 3214 #address-cells = <2>; 3215 #size-cells = <2>; 3216 ranges; 3217 compatible = "arm,armv7-timer-mem"; 3218 reg = <0 0x17c90000 0 0x1000>; 3219 3220 frame@17ca0000 { 3221 frame-number = <0>; 3222 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 3223 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3224 reg = <0 0x17ca0000 0 0x1000>, 3225 <0 0x17cb0000 0 0x1000>; 3226 }; 3227 3228 frame@17cc0000 { 3229 frame-number = <1>; 3230 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 3231 reg = <0 0x17cc0000 0 0x1000>; 3232 status = "disabled"; 3233 }; 3234 3235 frame@17cd0000 { 3236 frame-number = <2>; 3237 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3238 reg = <0 0x17cd0000 0 0x1000>; 3239 status = "disabled"; 3240 }; 3241 3242 frame@17ce0000 { 3243 frame-number = <3>; 3244 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3245 reg = <0 0x17ce0000 0 0x1000>; 3246 status = "disabled"; 3247 }; 3248 3249 frame@17cf0000 { 3250 frame-number = <4>; 3251 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3252 reg = <0 0x17cf0000 0 0x1000>; 3253 status = "disabled"; 3254 }; 3255 3256 frame@17d00000 { 3257 frame-number = <5>; 3258 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3259 reg = <0 0x17d00000 0 0x1000>; 3260 status = "disabled"; 3261 }; 3262 3263 frame@17d10000 { 3264 frame-number = <6>; 3265 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3266 reg = <0 0x17d10000 0 0x1000>; 3267 status = "disabled"; 3268 }; 3269 }; 3270 3271 cpufreq_hw: cpufreq@17d43000 { 3272 compatible = "qcom,cpufreq-hw"; 3273 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 3274 reg-names = "freq-domain0", "freq-domain1"; 3275 3276 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 3277 clock-names = "xo", "alternate"; 3278 3279 #freq-domain-cells = <1>; 3280 }; 3281 3282 wifi: wifi@18800000 { 3283 compatible = "qcom,wcn3990-wifi"; 3284 status = "disabled"; 3285 reg = <0 0x18800000 0 0x800000>; 3286 reg-names = "membase"; 3287 memory-region = <&wlan_msa_mem>; 3288 clock-names = "cxo_ref_clk_pin"; 3289 clocks = <&rpmhcc RPMH_RF_CLK2>; 3290 interrupts = 3291 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3292 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3293 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3294 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3295 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3297 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3298 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3299 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3300 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3301 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3302 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3303 iommus = <&apps_smmu 0x0040 0x1>; 3304 }; 3305 }; 3306 3307 thermal-zones { 3308 cpu0-thermal { 3309 polling-delay-passive = <250>; 3310 polling-delay = <1000>; 3311 3312 thermal-sensors = <&tsens0 1>; 3313 3314 trips { 3315 cpu0_alert0: trip-point0 { 3316 temperature = <90000>; 3317 hysteresis = <2000>; 3318 type = "passive"; 3319 }; 3320 3321 cpu0_alert1: trip-point1 { 3322 temperature = <95000>; 3323 hysteresis = <2000>; 3324 type = "passive"; 3325 }; 3326 3327 cpu0_crit: cpu_crit { 3328 temperature = <110000>; 3329 hysteresis = <1000>; 3330 type = "critical"; 3331 }; 3332 }; 3333 3334 cooling-maps { 3335 map0 { 3336 trip = <&cpu0_alert0>; 3337 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3338 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3339 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3340 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3341 }; 3342 map1 { 3343 trip = <&cpu0_alert1>; 3344 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3345 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3346 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3347 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3348 }; 3349 }; 3350 }; 3351 3352 cpu1-thermal { 3353 polling-delay-passive = <250>; 3354 polling-delay = <1000>; 3355 3356 thermal-sensors = <&tsens0 2>; 3357 3358 trips { 3359 cpu1_alert0: trip-point0 { 3360 temperature = <90000>; 3361 hysteresis = <2000>; 3362 type = "passive"; 3363 }; 3364 3365 cpu1_alert1: trip-point1 { 3366 temperature = <95000>; 3367 hysteresis = <2000>; 3368 type = "passive"; 3369 }; 3370 3371 cpu1_crit: cpu_crit { 3372 temperature = <110000>; 3373 hysteresis = <1000>; 3374 type = "critical"; 3375 }; 3376 }; 3377 3378 cooling-maps { 3379 map0 { 3380 trip = <&cpu1_alert0>; 3381 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3382 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3383 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3384 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3385 }; 3386 map1 { 3387 trip = <&cpu1_alert1>; 3388 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3389 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3390 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3391 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3392 }; 3393 }; 3394 }; 3395 3396 cpu2-thermal { 3397 polling-delay-passive = <250>; 3398 polling-delay = <1000>; 3399 3400 thermal-sensors = <&tsens0 3>; 3401 3402 trips { 3403 cpu2_alert0: trip-point0 { 3404 temperature = <90000>; 3405 hysteresis = <2000>; 3406 type = "passive"; 3407 }; 3408 3409 cpu2_alert1: trip-point1 { 3410 temperature = <95000>; 3411 hysteresis = <2000>; 3412 type = "passive"; 3413 }; 3414 3415 cpu2_crit: cpu_crit { 3416 temperature = <110000>; 3417 hysteresis = <1000>; 3418 type = "critical"; 3419 }; 3420 }; 3421 3422 cooling-maps { 3423 map0 { 3424 trip = <&cpu2_alert0>; 3425 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3426 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3427 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3428 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3429 }; 3430 map1 { 3431 trip = <&cpu2_alert1>; 3432 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3433 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3434 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3435 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3436 }; 3437 }; 3438 }; 3439 3440 cpu3-thermal { 3441 polling-delay-passive = <250>; 3442 polling-delay = <1000>; 3443 3444 thermal-sensors = <&tsens0 4>; 3445 3446 trips { 3447 cpu3_alert0: trip-point0 { 3448 temperature = <90000>; 3449 hysteresis = <2000>; 3450 type = "passive"; 3451 }; 3452 3453 cpu3_alert1: trip-point1 { 3454 temperature = <95000>; 3455 hysteresis = <2000>; 3456 type = "passive"; 3457 }; 3458 3459 cpu3_crit: cpu_crit { 3460 temperature = <110000>; 3461 hysteresis = <1000>; 3462 type = "critical"; 3463 }; 3464 }; 3465 3466 cooling-maps { 3467 map0 { 3468 trip = <&cpu3_alert0>; 3469 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3470 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3471 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3472 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3473 }; 3474 map1 { 3475 trip = <&cpu3_alert1>; 3476 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3477 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3478 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3479 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3480 }; 3481 }; 3482 }; 3483 3484 cpu4-thermal { 3485 polling-delay-passive = <250>; 3486 polling-delay = <1000>; 3487 3488 thermal-sensors = <&tsens0 7>; 3489 3490 trips { 3491 cpu4_alert0: trip-point0 { 3492 temperature = <90000>; 3493 hysteresis = <2000>; 3494 type = "passive"; 3495 }; 3496 3497 cpu4_alert1: trip-point1 { 3498 temperature = <95000>; 3499 hysteresis = <2000>; 3500 type = "passive"; 3501 }; 3502 3503 cpu4_crit: cpu_crit { 3504 temperature = <110000>; 3505 hysteresis = <1000>; 3506 type = "critical"; 3507 }; 3508 }; 3509 3510 cooling-maps { 3511 map0 { 3512 trip = <&cpu4_alert0>; 3513 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3514 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3515 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3516 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3517 }; 3518 map1 { 3519 trip = <&cpu4_alert1>; 3520 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3521 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3522 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3523 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3524 }; 3525 }; 3526 }; 3527 3528 cpu5-thermal { 3529 polling-delay-passive = <250>; 3530 polling-delay = <1000>; 3531 3532 thermal-sensors = <&tsens0 8>; 3533 3534 trips { 3535 cpu5_alert0: trip-point0 { 3536 temperature = <90000>; 3537 hysteresis = <2000>; 3538 type = "passive"; 3539 }; 3540 3541 cpu5_alert1: trip-point1 { 3542 temperature = <95000>; 3543 hysteresis = <2000>; 3544 type = "passive"; 3545 }; 3546 3547 cpu5_crit: cpu_crit { 3548 temperature = <110000>; 3549 hysteresis = <1000>; 3550 type = "critical"; 3551 }; 3552 }; 3553 3554 cooling-maps { 3555 map0 { 3556 trip = <&cpu5_alert0>; 3557 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3558 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3559 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3560 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3561 }; 3562 map1 { 3563 trip = <&cpu5_alert1>; 3564 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3565 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3566 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3567 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3568 }; 3569 }; 3570 }; 3571 3572 cpu6-thermal { 3573 polling-delay-passive = <250>; 3574 polling-delay = <1000>; 3575 3576 thermal-sensors = <&tsens0 9>; 3577 3578 trips { 3579 cpu6_alert0: trip-point0 { 3580 temperature = <90000>; 3581 hysteresis = <2000>; 3582 type = "passive"; 3583 }; 3584 3585 cpu6_alert1: trip-point1 { 3586 temperature = <95000>; 3587 hysteresis = <2000>; 3588 type = "passive"; 3589 }; 3590 3591 cpu6_crit: cpu_crit { 3592 temperature = <110000>; 3593 hysteresis = <1000>; 3594 type = "critical"; 3595 }; 3596 }; 3597 3598 cooling-maps { 3599 map0 { 3600 trip = <&cpu6_alert0>; 3601 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3602 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3603 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3604 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3605 }; 3606 map1 { 3607 trip = <&cpu6_alert1>; 3608 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3609 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3610 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3611 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3612 }; 3613 }; 3614 }; 3615 3616 cpu7-thermal { 3617 polling-delay-passive = <250>; 3618 polling-delay = <1000>; 3619 3620 thermal-sensors = <&tsens0 10>; 3621 3622 trips { 3623 cpu7_alert0: trip-point0 { 3624 temperature = <90000>; 3625 hysteresis = <2000>; 3626 type = "passive"; 3627 }; 3628 3629 cpu7_alert1: trip-point1 { 3630 temperature = <95000>; 3631 hysteresis = <2000>; 3632 type = "passive"; 3633 }; 3634 3635 cpu7_crit: cpu_crit { 3636 temperature = <110000>; 3637 hysteresis = <1000>; 3638 type = "critical"; 3639 }; 3640 }; 3641 3642 cooling-maps { 3643 map0 { 3644 trip = <&cpu7_alert0>; 3645 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3646 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3647 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3648 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3649 }; 3650 map1 { 3651 trip = <&cpu7_alert1>; 3652 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3653 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3654 <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3655 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3656 }; 3657 }; 3658 }; 3659 3660 aoss0-thermal { 3661 polling-delay-passive = <250>; 3662 polling-delay = <1000>; 3663 3664 thermal-sensors = <&tsens0 0>; 3665 3666 trips { 3667 aoss0_alert0: trip-point0 { 3668 temperature = <90000>; 3669 hysteresis = <2000>; 3670 type = "hot"; 3671 }; 3672 }; 3673 }; 3674 3675 cluster0-thermal { 3676 polling-delay-passive = <250>; 3677 polling-delay = <1000>; 3678 3679 thermal-sensors = <&tsens0 5>; 3680 3681 trips { 3682 cluster0_alert0: trip-point0 { 3683 temperature = <90000>; 3684 hysteresis = <2000>; 3685 type = "hot"; 3686 }; 3687 cluster0_crit: cluster0_crit { 3688 temperature = <110000>; 3689 hysteresis = <2000>; 3690 type = "critical"; 3691 }; 3692 }; 3693 }; 3694 3695 cluster1-thermal { 3696 polling-delay-passive = <250>; 3697 polling-delay = <1000>; 3698 3699 thermal-sensors = <&tsens0 6>; 3700 3701 trips { 3702 cluster1_alert0: trip-point0 { 3703 temperature = <90000>; 3704 hysteresis = <2000>; 3705 type = "hot"; 3706 }; 3707 cluster1_crit: cluster1_crit { 3708 temperature = <110000>; 3709 hysteresis = <2000>; 3710 type = "critical"; 3711 }; 3712 }; 3713 }; 3714 3715 gpu-thermal-top { 3716 polling-delay-passive = <250>; 3717 polling-delay = <1000>; 3718 3719 thermal-sensors = <&tsens0 11>; 3720 3721 trips { 3722 gpu1_alert0: trip-point0 { 3723 temperature = <90000>; 3724 hysteresis = <2000>; 3725 type = "hot"; 3726 }; 3727 }; 3728 }; 3729 3730 gpu-thermal-bottom { 3731 polling-delay-passive = <250>; 3732 polling-delay = <1000>; 3733 3734 thermal-sensors = <&tsens0 12>; 3735 3736 trips { 3737 gpu2_alert0: trip-point0 { 3738 temperature = <90000>; 3739 hysteresis = <2000>; 3740 type = "hot"; 3741 }; 3742 }; 3743 }; 3744 3745 aoss1-thermal { 3746 polling-delay-passive = <250>; 3747 polling-delay = <1000>; 3748 3749 thermal-sensors = <&tsens1 0>; 3750 3751 trips { 3752 aoss1_alert0: trip-point0 { 3753 temperature = <90000>; 3754 hysteresis = <2000>; 3755 type = "hot"; 3756 }; 3757 }; 3758 }; 3759 3760 q6-modem-thermal { 3761 polling-delay-passive = <250>; 3762 polling-delay = <1000>; 3763 3764 thermal-sensors = <&tsens1 1>; 3765 3766 trips { 3767 q6_modem_alert0: trip-point0 { 3768 temperature = <90000>; 3769 hysteresis = <2000>; 3770 type = "hot"; 3771 }; 3772 }; 3773 }; 3774 3775 mem-thermal { 3776 polling-delay-passive = <250>; 3777 polling-delay = <1000>; 3778 3779 thermal-sensors = <&tsens1 2>; 3780 3781 trips { 3782 mem_alert0: trip-point0 { 3783 temperature = <90000>; 3784 hysteresis = <2000>; 3785 type = "hot"; 3786 }; 3787 }; 3788 }; 3789 3790 wlan-thermal { 3791 polling-delay-passive = <250>; 3792 polling-delay = <1000>; 3793 3794 thermal-sensors = <&tsens1 3>; 3795 3796 trips { 3797 wlan_alert0: trip-point0 { 3798 temperature = <90000>; 3799 hysteresis = <2000>; 3800 type = "hot"; 3801 }; 3802 }; 3803 }; 3804 3805 q6-hvx-thermal { 3806 polling-delay-passive = <250>; 3807 polling-delay = <1000>; 3808 3809 thermal-sensors = <&tsens1 4>; 3810 3811 trips { 3812 q6_hvx_alert0: trip-point0 { 3813 temperature = <90000>; 3814 hysteresis = <2000>; 3815 type = "hot"; 3816 }; 3817 }; 3818 }; 3819 3820 camera-thermal { 3821 polling-delay-passive = <250>; 3822 polling-delay = <1000>; 3823 3824 thermal-sensors = <&tsens1 5>; 3825 3826 trips { 3827 camera_alert0: trip-point0 { 3828 temperature = <90000>; 3829 hysteresis = <2000>; 3830 type = "hot"; 3831 }; 3832 }; 3833 }; 3834 3835 video-thermal { 3836 polling-delay-passive = <250>; 3837 polling-delay = <1000>; 3838 3839 thermal-sensors = <&tsens1 6>; 3840 3841 trips { 3842 video_alert0: trip-point0 { 3843 temperature = <90000>; 3844 hysteresis = <2000>; 3845 type = "hot"; 3846 }; 3847 }; 3848 }; 3849 3850 modem-thermal { 3851 polling-delay-passive = <250>; 3852 polling-delay = <1000>; 3853 3854 thermal-sensors = <&tsens1 7>; 3855 3856 trips { 3857 modem_alert0: trip-point0 { 3858 temperature = <90000>; 3859 hysteresis = <2000>; 3860 type = "hot"; 3861 }; 3862 }; 3863 }; 3864 }; 3865}; 3866