1 // SPDX-License-Identifier: ISC 2 /* 3 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name> 4 */ 5 6 #include <linux/dma-mapping.h> 7 #include "mt76.h" 8 #include "dma.h" 9 10 static int 11 mt76_dma_alloc_queue(struct mt76_dev *dev, struct mt76_queue *q, 12 int idx, int n_desc, int bufsize, 13 u32 ring_base) 14 { 15 int size; 16 int i; 17 18 spin_lock_init(&q->lock); 19 20 q->regs = dev->mmio.regs + ring_base + idx * MT_RING_SIZE; 21 q->ndesc = n_desc; 22 q->buf_size = bufsize; 23 q->hw_idx = idx; 24 25 size = q->ndesc * sizeof(struct mt76_desc); 26 q->desc = dmam_alloc_coherent(dev->dev, size, &q->desc_dma, GFP_KERNEL); 27 if (!q->desc) 28 return -ENOMEM; 29 30 size = q->ndesc * sizeof(*q->entry); 31 q->entry = devm_kzalloc(dev->dev, size, GFP_KERNEL); 32 if (!q->entry) 33 return -ENOMEM; 34 35 /* clear descriptors */ 36 for (i = 0; i < q->ndesc; i++) 37 q->desc[i].ctrl = cpu_to_le32(MT_DMA_CTL_DMA_DONE); 38 39 writel(q->desc_dma, &q->regs->desc_base); 40 writel(0, &q->regs->cpu_idx); 41 writel(0, &q->regs->dma_idx); 42 writel(q->ndesc, &q->regs->ring_size); 43 44 return 0; 45 } 46 47 static int 48 mt76_dma_add_buf(struct mt76_dev *dev, struct mt76_queue *q, 49 struct mt76_queue_buf *buf, int nbufs, u32 info, 50 struct sk_buff *skb, void *txwi) 51 { 52 struct mt76_desc *desc; 53 u32 ctrl; 54 int i, idx = -1; 55 56 if (txwi) { 57 q->entry[q->head].txwi = DMA_DUMMY_DATA; 58 q->entry[q->head].skip_buf0 = true; 59 } 60 61 for (i = 0; i < nbufs; i += 2, buf += 2) { 62 u32 buf0 = buf[0].addr, buf1 = 0; 63 64 ctrl = FIELD_PREP(MT_DMA_CTL_SD_LEN0, buf[0].len); 65 if (i < nbufs - 1) { 66 buf1 = buf[1].addr; 67 ctrl |= FIELD_PREP(MT_DMA_CTL_SD_LEN1, buf[1].len); 68 } 69 70 if (i == nbufs - 1) 71 ctrl |= MT_DMA_CTL_LAST_SEC0; 72 else if (i == nbufs - 2) 73 ctrl |= MT_DMA_CTL_LAST_SEC1; 74 75 idx = q->head; 76 q->head = (q->head + 1) % q->ndesc; 77 78 desc = &q->desc[idx]; 79 80 WRITE_ONCE(desc->buf0, cpu_to_le32(buf0)); 81 WRITE_ONCE(desc->buf1, cpu_to_le32(buf1)); 82 WRITE_ONCE(desc->info, cpu_to_le32(info)); 83 WRITE_ONCE(desc->ctrl, cpu_to_le32(ctrl)); 84 85 q->queued++; 86 } 87 88 q->entry[idx].txwi = txwi; 89 q->entry[idx].skb = skb; 90 91 return idx; 92 } 93 94 static void 95 mt76_dma_tx_cleanup_idx(struct mt76_dev *dev, struct mt76_queue *q, int idx, 96 struct mt76_queue_entry *prev_e) 97 { 98 struct mt76_queue_entry *e = &q->entry[idx]; 99 __le32 __ctrl = READ_ONCE(q->desc[idx].ctrl); 100 u32 ctrl = le32_to_cpu(__ctrl); 101 102 if (!e->skip_buf0) { 103 __le32 addr = READ_ONCE(q->desc[idx].buf0); 104 u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctrl); 105 106 dma_unmap_single(dev->dev, le32_to_cpu(addr), len, 107 DMA_TO_DEVICE); 108 } 109 110 if (!(ctrl & MT_DMA_CTL_LAST_SEC0)) { 111 __le32 addr = READ_ONCE(q->desc[idx].buf1); 112 u32 len = FIELD_GET(MT_DMA_CTL_SD_LEN1, ctrl); 113 114 dma_unmap_single(dev->dev, le32_to_cpu(addr), len, 115 DMA_TO_DEVICE); 116 } 117 118 if (e->txwi == DMA_DUMMY_DATA) 119 e->txwi = NULL; 120 121 if (e->skb == DMA_DUMMY_DATA) 122 e->skb = NULL; 123 124 *prev_e = *e; 125 memset(e, 0, sizeof(*e)); 126 } 127 128 static void 129 mt76_dma_sync_idx(struct mt76_dev *dev, struct mt76_queue *q) 130 { 131 writel(q->desc_dma, &q->regs->desc_base); 132 writel(q->ndesc, &q->regs->ring_size); 133 q->head = readl(&q->regs->dma_idx); 134 q->tail = q->head; 135 writel(q->head, &q->regs->cpu_idx); 136 } 137 138 static void 139 mt76_dma_tx_cleanup(struct mt76_dev *dev, enum mt76_txq_id qid, bool flush) 140 { 141 struct mt76_sw_queue *sq = &dev->q_tx[qid]; 142 struct mt76_queue *q = sq->q; 143 struct mt76_queue_entry entry; 144 unsigned int n_swq_queued[4] = {}; 145 unsigned int n_queued = 0; 146 bool wake = false; 147 int i, last; 148 149 if (!q) 150 return; 151 152 if (flush) 153 last = -1; 154 else 155 last = readl(&q->regs->dma_idx); 156 157 while ((q->queued > n_queued) && q->tail != last) { 158 mt76_dma_tx_cleanup_idx(dev, q, q->tail, &entry); 159 if (entry.schedule) 160 n_swq_queued[entry.qid]++; 161 162 q->tail = (q->tail + 1) % q->ndesc; 163 n_queued++; 164 165 if (entry.skb) 166 dev->drv->tx_complete_skb(dev, qid, &entry); 167 168 if (entry.txwi) { 169 if (!(dev->drv->drv_flags & MT_DRV_TXWI_NO_FREE)) 170 mt76_put_txwi(dev, entry.txwi); 171 wake = !flush; 172 } 173 174 if (!flush && q->tail == last) 175 last = readl(&q->regs->dma_idx); 176 } 177 178 spin_lock_bh(&q->lock); 179 180 q->queued -= n_queued; 181 for (i = 0; i < ARRAY_SIZE(n_swq_queued); i++) { 182 if (!n_swq_queued[i]) 183 continue; 184 185 dev->q_tx[i].swq_queued -= n_swq_queued[i]; 186 } 187 188 if (flush) 189 mt76_dma_sync_idx(dev, q); 190 191 wake = wake && q->stopped && 192 qid < IEEE80211_NUM_ACS && q->queued < q->ndesc - 8; 193 if (wake) 194 q->stopped = false; 195 196 if (!q->queued) 197 wake_up(&dev->tx_wait); 198 199 spin_unlock_bh(&q->lock); 200 201 if (wake) 202 ieee80211_wake_queue(dev->hw, qid); 203 } 204 205 static void * 206 mt76_dma_get_buf(struct mt76_dev *dev, struct mt76_queue *q, int idx, 207 int *len, u32 *info, bool *more) 208 { 209 struct mt76_queue_entry *e = &q->entry[idx]; 210 struct mt76_desc *desc = &q->desc[idx]; 211 dma_addr_t buf_addr; 212 void *buf = e->buf; 213 int buf_len = SKB_WITH_OVERHEAD(q->buf_size); 214 215 buf_addr = le32_to_cpu(READ_ONCE(desc->buf0)); 216 if (len) { 217 u32 ctl = le32_to_cpu(READ_ONCE(desc->ctrl)); 218 *len = FIELD_GET(MT_DMA_CTL_SD_LEN0, ctl); 219 *more = !(ctl & MT_DMA_CTL_LAST_SEC0); 220 } 221 222 if (info) 223 *info = le32_to_cpu(desc->info); 224 225 dma_unmap_single(dev->dev, buf_addr, buf_len, DMA_FROM_DEVICE); 226 e->buf = NULL; 227 228 return buf; 229 } 230 231 static void * 232 mt76_dma_dequeue(struct mt76_dev *dev, struct mt76_queue *q, bool flush, 233 int *len, u32 *info, bool *more) 234 { 235 int idx = q->tail; 236 237 *more = false; 238 if (!q->queued) 239 return NULL; 240 241 if (!flush && !(q->desc[idx].ctrl & cpu_to_le32(MT_DMA_CTL_DMA_DONE))) 242 return NULL; 243 244 q->tail = (q->tail + 1) % q->ndesc; 245 q->queued--; 246 247 return mt76_dma_get_buf(dev, q, idx, len, info, more); 248 } 249 250 static void 251 mt76_dma_kick_queue(struct mt76_dev *dev, struct mt76_queue *q) 252 { 253 writel(q->head, &q->regs->cpu_idx); 254 } 255 256 static int 257 mt76_dma_tx_queue_skb_raw(struct mt76_dev *dev, enum mt76_txq_id qid, 258 struct sk_buff *skb, u32 tx_info) 259 { 260 struct mt76_queue *q = dev->q_tx[qid].q; 261 struct mt76_queue_buf buf; 262 dma_addr_t addr; 263 264 addr = dma_map_single(dev->dev, skb->data, skb->len, 265 DMA_TO_DEVICE); 266 if (unlikely(dma_mapping_error(dev->dev, addr))) 267 return -ENOMEM; 268 269 buf.addr = addr; 270 buf.len = skb->len; 271 272 spin_lock_bh(&q->lock); 273 mt76_dma_add_buf(dev, q, &buf, 1, tx_info, skb, NULL); 274 mt76_dma_kick_queue(dev, q); 275 spin_unlock_bh(&q->lock); 276 277 return 0; 278 } 279 280 static int 281 mt76_dma_tx_queue_skb(struct mt76_dev *dev, enum mt76_txq_id qid, 282 struct sk_buff *skb, struct mt76_wcid *wcid, 283 struct ieee80211_sta *sta) 284 { 285 struct mt76_queue *q = dev->q_tx[qid].q; 286 struct mt76_tx_info tx_info = { 287 .skb = skb, 288 }; 289 int len, n = 0, ret = -ENOMEM; 290 struct mt76_queue_entry e; 291 struct mt76_txwi_cache *t; 292 struct sk_buff *iter; 293 dma_addr_t addr; 294 u8 *txwi; 295 296 t = mt76_get_txwi(dev); 297 if (!t) { 298 ieee80211_free_txskb(dev->hw, skb); 299 return -ENOMEM; 300 } 301 txwi = mt76_get_txwi_ptr(dev, t); 302 303 skb->prev = skb->next = NULL; 304 if (dev->drv->drv_flags & MT_DRV_TX_ALIGNED4_SKBS) 305 mt76_insert_hdr_pad(skb); 306 307 len = skb_headlen(skb); 308 addr = dma_map_single(dev->dev, skb->data, len, DMA_TO_DEVICE); 309 if (unlikely(dma_mapping_error(dev->dev, addr))) 310 goto free; 311 312 tx_info.buf[n].addr = t->dma_addr; 313 tx_info.buf[n++].len = dev->drv->txwi_size; 314 tx_info.buf[n].addr = addr; 315 tx_info.buf[n++].len = len; 316 317 skb_walk_frags(skb, iter) { 318 if (n == ARRAY_SIZE(tx_info.buf)) 319 goto unmap; 320 321 addr = dma_map_single(dev->dev, iter->data, iter->len, 322 DMA_TO_DEVICE); 323 if (unlikely(dma_mapping_error(dev->dev, addr))) 324 goto unmap; 325 326 tx_info.buf[n].addr = addr; 327 tx_info.buf[n++].len = iter->len; 328 } 329 tx_info.nbuf = n; 330 331 dma_sync_single_for_cpu(dev->dev, t->dma_addr, dev->drv->txwi_size, 332 DMA_TO_DEVICE); 333 ret = dev->drv->tx_prepare_skb(dev, txwi, qid, wcid, sta, &tx_info); 334 dma_sync_single_for_device(dev->dev, t->dma_addr, dev->drv->txwi_size, 335 DMA_TO_DEVICE); 336 if (ret < 0) 337 goto unmap; 338 339 if (q->queued + (tx_info.nbuf + 1) / 2 >= q->ndesc - 1) { 340 ret = -ENOMEM; 341 goto unmap; 342 } 343 344 return mt76_dma_add_buf(dev, q, tx_info.buf, tx_info.nbuf, 345 tx_info.info, tx_info.skb, t); 346 347 unmap: 348 for (n--; n > 0; n--) 349 dma_unmap_single(dev->dev, tx_info.buf[n].addr, 350 tx_info.buf[n].len, DMA_TO_DEVICE); 351 352 free: 353 e.skb = tx_info.skb; 354 e.txwi = t; 355 dev->drv->tx_complete_skb(dev, qid, &e); 356 mt76_put_txwi(dev, t); 357 return ret; 358 } 359 360 static int 361 mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q) 362 { 363 dma_addr_t addr; 364 void *buf; 365 int frames = 0; 366 int len = SKB_WITH_OVERHEAD(q->buf_size); 367 int offset = q->buf_offset; 368 369 spin_lock_bh(&q->lock); 370 371 while (q->queued < q->ndesc - 1) { 372 struct mt76_queue_buf qbuf; 373 374 buf = page_frag_alloc(&q->rx_page, q->buf_size, GFP_ATOMIC); 375 if (!buf) 376 break; 377 378 addr = dma_map_single(dev->dev, buf, len, DMA_FROM_DEVICE); 379 if (unlikely(dma_mapping_error(dev->dev, addr))) { 380 skb_free_frag(buf); 381 break; 382 } 383 384 qbuf.addr = addr + offset; 385 qbuf.len = len - offset; 386 mt76_dma_add_buf(dev, q, &qbuf, 1, 0, buf, NULL); 387 frames++; 388 } 389 390 if (frames) 391 mt76_dma_kick_queue(dev, q); 392 393 spin_unlock_bh(&q->lock); 394 395 return frames; 396 } 397 398 static void 399 mt76_dma_rx_cleanup(struct mt76_dev *dev, struct mt76_queue *q) 400 { 401 struct page *page; 402 void *buf; 403 bool more; 404 405 spin_lock_bh(&q->lock); 406 do { 407 buf = mt76_dma_dequeue(dev, q, true, NULL, NULL, &more); 408 if (!buf) 409 break; 410 411 skb_free_frag(buf); 412 } while (1); 413 spin_unlock_bh(&q->lock); 414 415 if (!q->rx_page.va) 416 return; 417 418 page = virt_to_page(q->rx_page.va); 419 __page_frag_cache_drain(page, q->rx_page.pagecnt_bias); 420 memset(&q->rx_page, 0, sizeof(q->rx_page)); 421 } 422 423 static void 424 mt76_dma_rx_reset(struct mt76_dev *dev, enum mt76_rxq_id qid) 425 { 426 struct mt76_queue *q = &dev->q_rx[qid]; 427 int i; 428 429 for (i = 0; i < q->ndesc; i++) 430 q->desc[i].ctrl &= ~cpu_to_le32(MT_DMA_CTL_DMA_DONE); 431 432 mt76_dma_rx_cleanup(dev, q); 433 mt76_dma_sync_idx(dev, q); 434 mt76_dma_rx_fill(dev, q); 435 436 if (!q->rx_head) 437 return; 438 439 dev_kfree_skb(q->rx_head); 440 q->rx_head = NULL; 441 } 442 443 static void 444 mt76_add_fragment(struct mt76_dev *dev, struct mt76_queue *q, void *data, 445 int len, bool more) 446 { 447 struct page *page = virt_to_head_page(data); 448 int offset = data - page_address(page); 449 struct sk_buff *skb = q->rx_head; 450 451 offset += q->buf_offset; 452 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, offset, len, 453 q->buf_size); 454 455 if (more) 456 return; 457 458 q->rx_head = NULL; 459 dev->drv->rx_skb(dev, q - dev->q_rx, skb); 460 } 461 462 static int 463 mt76_dma_rx_process(struct mt76_dev *dev, struct mt76_queue *q, int budget) 464 { 465 int len, data_len, done = 0; 466 struct sk_buff *skb; 467 unsigned char *data; 468 bool more; 469 470 while (done < budget) { 471 u32 info; 472 473 data = mt76_dma_dequeue(dev, q, false, &len, &info, &more); 474 if (!data) 475 break; 476 477 if (q->rx_head) 478 data_len = q->buf_size; 479 else 480 data_len = SKB_WITH_OVERHEAD(q->buf_size); 481 482 if (data_len < len + q->buf_offset) { 483 dev_kfree_skb(q->rx_head); 484 q->rx_head = NULL; 485 486 skb_free_frag(data); 487 continue; 488 } 489 490 if (q->rx_head) { 491 mt76_add_fragment(dev, q, data, len, more); 492 continue; 493 } 494 495 skb = build_skb(data, q->buf_size); 496 if (!skb) { 497 skb_free_frag(data); 498 continue; 499 } 500 skb_reserve(skb, q->buf_offset); 501 502 if (q == &dev->q_rx[MT_RXQ_MCU]) { 503 u32 *rxfce = (u32 *)skb->cb; 504 *rxfce = info; 505 } 506 507 __skb_put(skb, len); 508 done++; 509 510 if (more) { 511 q->rx_head = skb; 512 continue; 513 } 514 515 dev->drv->rx_skb(dev, q - dev->q_rx, skb); 516 } 517 518 mt76_dma_rx_fill(dev, q); 519 return done; 520 } 521 522 static int 523 mt76_dma_rx_poll(struct napi_struct *napi, int budget) 524 { 525 struct mt76_dev *dev; 526 int qid, done = 0, cur; 527 528 dev = container_of(napi->dev, struct mt76_dev, napi_dev); 529 qid = napi - dev->napi; 530 531 rcu_read_lock(); 532 533 do { 534 cur = mt76_dma_rx_process(dev, &dev->q_rx[qid], budget - done); 535 mt76_rx_poll_complete(dev, qid, napi); 536 done += cur; 537 } while (cur && done < budget); 538 539 rcu_read_unlock(); 540 541 if (done < budget && napi_complete(napi)) 542 dev->drv->rx_poll_complete(dev, qid); 543 544 return done; 545 } 546 547 static int 548 mt76_dma_init(struct mt76_dev *dev) 549 { 550 int i; 551 552 init_dummy_netdev(&dev->napi_dev); 553 554 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) { 555 netif_napi_add(&dev->napi_dev, &dev->napi[i], mt76_dma_rx_poll, 556 64); 557 mt76_dma_rx_fill(dev, &dev->q_rx[i]); 558 skb_queue_head_init(&dev->rx_skb[i]); 559 napi_enable(&dev->napi[i]); 560 } 561 562 return 0; 563 } 564 565 static const struct mt76_queue_ops mt76_dma_ops = { 566 .init = mt76_dma_init, 567 .alloc = mt76_dma_alloc_queue, 568 .tx_queue_skb_raw = mt76_dma_tx_queue_skb_raw, 569 .tx_queue_skb = mt76_dma_tx_queue_skb, 570 .tx_cleanup = mt76_dma_tx_cleanup, 571 .rx_reset = mt76_dma_rx_reset, 572 .kick = mt76_dma_kick_queue, 573 }; 574 575 void mt76_dma_attach(struct mt76_dev *dev) 576 { 577 dev->queue_ops = &mt76_dma_ops; 578 } 579 EXPORT_SYMBOL_GPL(mt76_dma_attach); 580 581 void mt76_dma_cleanup(struct mt76_dev *dev) 582 { 583 int i; 584 585 netif_napi_del(&dev->tx_napi); 586 for (i = 0; i < ARRAY_SIZE(dev->q_tx); i++) 587 mt76_dma_tx_cleanup(dev, i, true); 588 589 for (i = 0; i < ARRAY_SIZE(dev->q_rx); i++) { 590 netif_napi_del(&dev->napi[i]); 591 mt76_dma_rx_cleanup(dev, &dev->q_rx[i]); 592 } 593 } 594 EXPORT_SYMBOL_GPL(mt76_dma_cleanup); 595