1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Huawei HiNIC PCI Express Linux driver 4 * Copyright(c) 2017 Huawei Technologies Co., Ltd 5 */ 6 7 #include <linux/pci.h> 8 #include <linux/device.h> 9 #include <linux/errno.h> 10 #include <linux/io.h> 11 #include <linux/types.h> 12 #include <linux/bitops.h> 13 #include <linux/delay.h> 14 15 #include "hinic_hw_csr.h" 16 #include "hinic_hw_if.h" 17 18 #define PCIE_ATTR_ENTRY 0 19 20 #define VALID_MSIX_IDX(attr, msix_index) ((msix_index) < (attr)->num_irqs) 21 22 #define WAIT_HWIF_READY_TIMEOUT 10000 23 24 #define HINIC_SELFTEST_RESULT 0x883C 25 26 /** 27 * hinic_msix_attr_set - set message attribute for msix entry 28 * @hwif: the HW interface of a pci function device 29 * @msix_index: msix_index 30 * @pending_limit: the maximum pending interrupt events (unit 8) 31 * @coalesc_timer: coalesc period for interrupt (unit 8 us) 32 * @lli_timer: replenishing period for low latency credit (unit 8 us) 33 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) 34 * @resend_timer: maximum wait for resending msix (unit coalesc period) 35 * 36 * Return 0 - Success, negative - Failure 37 **/ 38 int hinic_msix_attr_set(struct hinic_hwif *hwif, u16 msix_index, 39 u8 pending_limit, u8 coalesc_timer, 40 u8 lli_timer, u8 lli_credit_limit, 41 u8 resend_timer) 42 { 43 u32 msix_ctrl, addr; 44 45 if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) 46 return -EINVAL; 47 48 msix_ctrl = HINIC_MSIX_ATTR_SET(pending_limit, PENDING_LIMIT) | 49 HINIC_MSIX_ATTR_SET(coalesc_timer, COALESC_TIMER) | 50 HINIC_MSIX_ATTR_SET(lli_timer, LLI_TIMER) | 51 HINIC_MSIX_ATTR_SET(lli_credit_limit, LLI_CREDIT) | 52 HINIC_MSIX_ATTR_SET(resend_timer, RESEND_TIMER); 53 54 addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index); 55 56 hinic_hwif_write_reg(hwif, addr, msix_ctrl); 57 return 0; 58 } 59 60 /** 61 * hinic_msix_attr_get - get message attribute of msix entry 62 * @hwif: the HW interface of a pci function device 63 * @msix_index: msix_index 64 * @pending_limit: the maximum pending interrupt events (unit 8) 65 * @coalesc_timer: coalesc period for interrupt (unit 8 us) 66 * @lli_timer: replenishing period for low latency credit (unit 8 us) 67 * @lli_credit_limit: maximum credits for low latency msix messages (unit 8) 68 * @resend_timer: maximum wait for resending msix (unit coalesc period) 69 * 70 * Return 0 - Success, negative - Failure 71 **/ 72 int hinic_msix_attr_get(struct hinic_hwif *hwif, u16 msix_index, 73 u8 *pending_limit, u8 *coalesc_timer, 74 u8 *lli_timer, u8 *lli_credit_limit, 75 u8 *resend_timer) 76 { 77 u32 addr, val; 78 79 if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) 80 return -EINVAL; 81 82 addr = HINIC_CSR_MSIX_CTRL_ADDR(msix_index); 83 val = hinic_hwif_read_reg(hwif, addr); 84 85 *pending_limit = HINIC_MSIX_ATTR_GET(val, PENDING_LIMIT); 86 *coalesc_timer = HINIC_MSIX_ATTR_GET(val, COALESC_TIMER); 87 *lli_timer = HINIC_MSIX_ATTR_GET(val, LLI_TIMER); 88 *lli_credit_limit = HINIC_MSIX_ATTR_GET(val, LLI_CREDIT); 89 *resend_timer = HINIC_MSIX_ATTR_GET(val, RESEND_TIMER); 90 return 0; 91 } 92 93 /** 94 * hinic_msix_attr_cnt_clear - clear message attribute counters for msix entry 95 * @hwif: the HW interface of a pci function device 96 * @msix_index: msix_index 97 * 98 * Return 0 - Success, negative - Failure 99 **/ 100 int hinic_msix_attr_cnt_clear(struct hinic_hwif *hwif, u16 msix_index) 101 { 102 u32 msix_ctrl, addr; 103 104 if (!VALID_MSIX_IDX(&hwif->attr, msix_index)) 105 return -EINVAL; 106 107 msix_ctrl = HINIC_MSIX_CNT_SET(1, RESEND_TIMER); 108 addr = HINIC_CSR_MSIX_CNT_ADDR(msix_index); 109 110 hinic_hwif_write_reg(hwif, addr, msix_ctrl); 111 return 0; 112 } 113 114 /** 115 * hinic_set_pf_action - set action on pf channel 116 * @hwif: the HW interface of a pci function device 117 * @action: action on pf channel 118 * 119 * Return 0 - Success, negative - Failure 120 **/ 121 void hinic_set_pf_action(struct hinic_hwif *hwif, enum hinic_pf_action action) 122 { 123 u32 attr5; 124 125 if (HINIC_IS_VF(hwif)) 126 return; 127 128 attr5 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR); 129 attr5 = HINIC_FA5_CLEAR(attr5, PF_ACTION); 130 attr5 |= HINIC_FA5_SET(action, PF_ACTION); 131 132 hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR5_ADDR, attr5); 133 } 134 135 enum hinic_outbound_state hinic_outbound_state_get(struct hinic_hwif *hwif) 136 { 137 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 138 139 return HINIC_FA4_GET(attr4, OUTBOUND_STATE); 140 } 141 142 void hinic_outbound_state_set(struct hinic_hwif *hwif, 143 enum hinic_outbound_state outbound_state) 144 { 145 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 146 147 attr4 = HINIC_FA4_CLEAR(attr4, OUTBOUND_STATE); 148 attr4 |= HINIC_FA4_SET(outbound_state, OUTBOUND_STATE); 149 150 hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4); 151 } 152 153 enum hinic_db_state hinic_db_state_get(struct hinic_hwif *hwif) 154 { 155 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 156 157 return HINIC_FA4_GET(attr4, DB_STATE); 158 } 159 160 void hinic_db_state_set(struct hinic_hwif *hwif, 161 enum hinic_db_state db_state) 162 { 163 u32 attr4 = hinic_hwif_read_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR); 164 165 attr4 = HINIC_FA4_CLEAR(attr4, DB_STATE); 166 attr4 |= HINIC_FA4_SET(db_state, DB_STATE); 167 168 hinic_hwif_write_reg(hwif, HINIC_CSR_FUNC_ATTR4_ADDR, attr4); 169 } 170 171 void hinic_set_msix_state(struct hinic_hwif *hwif, u16 msix_idx, 172 enum hinic_msix_state flag) 173 { 174 u32 offset = msix_idx * HINIC_PCI_MSIX_ENTRY_SIZE + 175 HINIC_PCI_MSIX_ENTRY_VECTOR_CTRL; 176 u32 mask_bits; 177 178 mask_bits = readl(hwif->intr_regs_base + offset); 179 mask_bits &= ~HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; 180 181 if (flag) 182 mask_bits |= HINIC_PCI_MSIX_ENTRY_CTRL_MASKBIT; 183 184 writel(mask_bits, hwif->intr_regs_base + offset); 185 } 186 187 /** 188 * hwif_ready - test if the HW is ready for use 189 * @hwif: the HW interface of a pci function device 190 * 191 * Return 0 - Success, negative - Failure 192 **/ 193 static int hwif_ready(struct hinic_hwif *hwif) 194 { 195 u32 addr, attr1; 196 197 addr = HINIC_CSR_FUNC_ATTR1_ADDR; 198 attr1 = hinic_hwif_read_reg(hwif, addr); 199 200 if (!HINIC_FA1_GET(attr1, MGMT_INIT_STATUS)) 201 return -EBUSY; 202 203 if (HINIC_IS_VF(hwif)) { 204 if (!HINIC_FA1_GET(attr1, PF_INIT_STATUS)) 205 return -EBUSY; 206 } 207 208 return 0; 209 } 210 211 static int wait_hwif_ready(struct hinic_hwif *hwif) 212 { 213 unsigned long timeout = 0; 214 215 do { 216 if (!hwif_ready(hwif)) 217 return 0; 218 219 usleep_range(999, 1000); 220 timeout++; 221 } while (timeout <= WAIT_HWIF_READY_TIMEOUT); 222 223 dev_err(&hwif->pdev->dev, "Wait for hwif timeout\n"); 224 225 return -EBUSY; 226 } 227 228 /** 229 * set_hwif_attr - set the attributes in the relevant members in hwif 230 * @hwif: the HW interface of a pci function device 231 * @attr0: the first attribute that was read from the hw 232 * @attr1: the second attribute that was read from the hw 233 **/ 234 static void set_hwif_attr(struct hinic_hwif *hwif, u32 attr0, u32 attr1, 235 u32 attr2) 236 { 237 hwif->attr.func_idx = HINIC_FA0_GET(attr0, FUNC_IDX); 238 hwif->attr.pf_idx = HINIC_FA0_GET(attr0, PF_IDX); 239 hwif->attr.pci_intf_idx = HINIC_FA0_GET(attr0, PCI_INTF_IDX); 240 hwif->attr.func_type = HINIC_FA0_GET(attr0, FUNC_TYPE); 241 242 hwif->attr.num_aeqs = BIT(HINIC_FA1_GET(attr1, AEQS_PER_FUNC)); 243 hwif->attr.num_ceqs = BIT(HINIC_FA1_GET(attr1, CEQS_PER_FUNC)); 244 hwif->attr.num_irqs = BIT(HINIC_FA1_GET(attr1, IRQS_PER_FUNC)); 245 hwif->attr.num_dma_attr = BIT(HINIC_FA1_GET(attr1, DMA_ATTR_PER_FUNC)); 246 hwif->attr.global_vf_id_of_pf = HINIC_FA2_GET(attr2, 247 GLOBAL_VF_ID_OF_PF); 248 } 249 250 /** 251 * read_hwif_attr - read the attributes and set members in hwif 252 * @hwif: the HW interface of a pci function device 253 **/ 254 static void read_hwif_attr(struct hinic_hwif *hwif) 255 { 256 u32 addr, attr0, attr1, attr2; 257 258 addr = HINIC_CSR_FUNC_ATTR0_ADDR; 259 attr0 = hinic_hwif_read_reg(hwif, addr); 260 261 addr = HINIC_CSR_FUNC_ATTR1_ADDR; 262 attr1 = hinic_hwif_read_reg(hwif, addr); 263 264 addr = HINIC_CSR_FUNC_ATTR2_ADDR; 265 attr2 = hinic_hwif_read_reg(hwif, addr); 266 267 set_hwif_attr(hwif, attr0, attr1, attr2); 268 } 269 270 /** 271 * set_ppf - try to set hwif as ppf and set the type of hwif in this case 272 * @hwif: the HW interface of a pci function device 273 **/ 274 static void set_ppf(struct hinic_hwif *hwif) 275 { 276 struct hinic_func_attr *attr = &hwif->attr; 277 u32 addr, val, ppf_election; 278 279 /* Read Modify Write */ 280 addr = HINIC_CSR_PPF_ELECTION_ADDR(HINIC_HWIF_PCI_INTF(hwif)); 281 282 val = hinic_hwif_read_reg(hwif, addr); 283 val = HINIC_PPF_ELECTION_CLEAR(val, IDX); 284 285 ppf_election = HINIC_PPF_ELECTION_SET(HINIC_HWIF_FUNC_IDX(hwif), IDX); 286 287 val |= ppf_election; 288 hinic_hwif_write_reg(hwif, addr, val); 289 290 /* check PPF */ 291 val = hinic_hwif_read_reg(hwif, addr); 292 293 attr->ppf_idx = HINIC_PPF_ELECTION_GET(val, IDX); 294 if (attr->ppf_idx == HINIC_HWIF_FUNC_IDX(hwif)) 295 attr->func_type = HINIC_PPF; 296 } 297 298 /** 299 * set_dma_attr - set the dma attributes in the HW 300 * @hwif: the HW interface of a pci function device 301 * @entry_idx: the entry index in the dma table 302 * @st: PCIE TLP steering tag 303 * @at: PCIE TLP AT field 304 * @ph: PCIE TLP Processing Hint field 305 * @no_snooping: PCIE TLP No snooping 306 * @tph_en: PCIE TLP Processing Hint Enable 307 **/ 308 static void set_dma_attr(struct hinic_hwif *hwif, u32 entry_idx, 309 u8 st, u8 at, u8 ph, 310 enum hinic_pcie_nosnoop no_snooping, 311 enum hinic_pcie_tph tph_en) 312 { 313 u32 addr, val, dma_attr_entry; 314 315 /* Read Modify Write */ 316 addr = HINIC_CSR_DMA_ATTR_ADDR(entry_idx); 317 318 val = hinic_hwif_read_reg(hwif, addr); 319 val = HINIC_DMA_ATTR_CLEAR(val, ST) & 320 HINIC_DMA_ATTR_CLEAR(val, AT) & 321 HINIC_DMA_ATTR_CLEAR(val, PH) & 322 HINIC_DMA_ATTR_CLEAR(val, NO_SNOOPING) & 323 HINIC_DMA_ATTR_CLEAR(val, TPH_EN); 324 325 dma_attr_entry = HINIC_DMA_ATTR_SET(st, ST) | 326 HINIC_DMA_ATTR_SET(at, AT) | 327 HINIC_DMA_ATTR_SET(ph, PH) | 328 HINIC_DMA_ATTR_SET(no_snooping, NO_SNOOPING) | 329 HINIC_DMA_ATTR_SET(tph_en, TPH_EN); 330 331 val |= dma_attr_entry; 332 hinic_hwif_write_reg(hwif, addr, val); 333 } 334 335 /** 336 * dma_attr_table_init - initialize the the default dma attributes 337 * @hwif: the HW interface of a pci function device 338 **/ 339 static void dma_attr_init(struct hinic_hwif *hwif) 340 { 341 set_dma_attr(hwif, PCIE_ATTR_ENTRY, HINIC_PCIE_ST_DISABLE, 342 HINIC_PCIE_AT_DISABLE, HINIC_PCIE_PH_DISABLE, 343 HINIC_PCIE_SNOOP, HINIC_PCIE_TPH_DISABLE); 344 } 345 346 u16 hinic_glb_pf_vf_offset(struct hinic_hwif *hwif) 347 { 348 if (!hwif) 349 return 0; 350 351 return hwif->attr.global_vf_id_of_pf; 352 } 353 354 u16 hinic_global_func_id_hw(struct hinic_hwif *hwif) 355 { 356 u32 addr, attr0; 357 358 addr = HINIC_CSR_FUNC_ATTR0_ADDR; 359 attr0 = hinic_hwif_read_reg(hwif, addr); 360 361 return HINIC_FA0_GET(attr0, FUNC_IDX); 362 } 363 364 u16 hinic_pf_id_of_vf_hw(struct hinic_hwif *hwif) 365 { 366 u32 addr, attr0; 367 368 addr = HINIC_CSR_FUNC_ATTR0_ADDR; 369 attr0 = hinic_hwif_read_reg(hwif, addr); 370 371 return HINIC_FA0_GET(attr0, PF_IDX); 372 } 373 374 static void __print_selftest_reg(struct hinic_hwif *hwif) 375 { 376 u32 addr, attr0, attr1; 377 378 addr = HINIC_CSR_FUNC_ATTR1_ADDR; 379 attr1 = hinic_hwif_read_reg(hwif, addr); 380 381 if (attr1 == HINIC_PCIE_LINK_DOWN) { 382 dev_err(&hwif->pdev->dev, "PCIE is link down\n"); 383 return; 384 } 385 386 addr = HINIC_CSR_FUNC_ATTR0_ADDR; 387 attr0 = hinic_hwif_read_reg(hwif, addr); 388 if (HINIC_FA0_GET(attr0, FUNC_TYPE) != HINIC_VF && 389 !HINIC_FA0_GET(attr0, PCI_INTF_IDX)) 390 dev_err(&hwif->pdev->dev, "Selftest reg: 0x%08x\n", 391 hinic_hwif_read_reg(hwif, HINIC_SELFTEST_RESULT)); 392 } 393 394 /** 395 * hinic_init_hwif - initialize the hw interface 396 * @hwif: the HW interface of a pci function device 397 * @pdev: the pci device for acessing PCI resources 398 * 399 * Return 0 - Success, negative - Failure 400 **/ 401 int hinic_init_hwif(struct hinic_hwif *hwif, struct pci_dev *pdev) 402 { 403 int err; 404 405 hwif->pdev = pdev; 406 407 hwif->cfg_regs_bar = pci_ioremap_bar(pdev, HINIC_PCI_CFG_REGS_BAR); 408 if (!hwif->cfg_regs_bar) { 409 dev_err(&pdev->dev, "Failed to map configuration regs\n"); 410 return -ENOMEM; 411 } 412 413 hwif->intr_regs_base = pci_ioremap_bar(pdev, HINIC_PCI_INTR_REGS_BAR); 414 if (!hwif->intr_regs_base) { 415 dev_err(&pdev->dev, "Failed to map configuration regs\n"); 416 err = -ENOMEM; 417 goto err_map_intr_bar; 418 } 419 420 err = wait_hwif_ready(hwif); 421 if (err) { 422 dev_err(&pdev->dev, "HW interface is not ready\n"); 423 __print_selftest_reg(hwif); 424 goto err_hwif_ready; 425 } 426 427 read_hwif_attr(hwif); 428 429 if (HINIC_IS_PF(hwif)) 430 set_ppf(hwif); 431 432 /* No transactionss before DMA is initialized */ 433 dma_attr_init(hwif); 434 return 0; 435 436 err_hwif_ready: 437 iounmap(hwif->intr_regs_base); 438 439 err_map_intr_bar: 440 iounmap(hwif->cfg_regs_bar); 441 442 return err; 443 } 444 445 /** 446 * hinic_free_hwif - free the HW interface 447 * @hwif: the HW interface of a pci function device 448 **/ 449 void hinic_free_hwif(struct hinic_hwif *hwif) 450 { 451 iounmap(hwif->intr_regs_base); 452 iounmap(hwif->cfg_regs_bar); 453 } 454