1 /* SPDX-License-Identifier: ISC */ 2 /* Copyright (C) 2019 MediaTek Inc. */ 3 4 #ifndef __MT7615_MCU_H 5 #define __MT7615_MCU_H 6 7 struct mt7615_mcu_txd { 8 __le32 txd[8]; 9 10 __le16 len; 11 __le16 pq_id; 12 13 u8 cid; 14 u8 pkt_type; 15 u8 set_query; /* FW don't care */ 16 u8 seq; 17 18 u8 uc_d2b0_rev; 19 u8 ext_cid; 20 u8 s2d_index; 21 u8 ext_cid_ack; 22 23 u32 reserved[5]; 24 } __packed __aligned(4); 25 26 /** 27 * struct mt7615_uni_txd - mcu command descriptor for firmware v3 28 * @txd: hardware descriptor 29 * @len: total length not including txd 30 * @cid: command identifier 31 * @pkt_type: must be 0xa0 (cmd packet by long format) 32 * @frag_n: fragment number 33 * @seq: sequence number 34 * @checksum: 0 mean there is no checksum 35 * @s2d_index: index for command source and destination 36 * Definition | value | note 37 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM 38 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM 39 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA 40 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM 41 * 42 * @option: command option 43 * BIT[0]: UNI_CMD_OPT_BIT_ACK 44 * set to 1 to request a fw reply 45 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY 46 * is set, mcu firmware will send response event EID = 0x01 47 * (UNI_EVENT_ID_CMD_RESULT) to the host. 48 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD 49 * 0: original command 50 * 1: unified command 51 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY 52 * 0: QUERY command 53 * 1: SET command 54 */ 55 struct mt7615_uni_txd { 56 __le32 txd[8]; 57 58 /* DW1 */ 59 __le16 len; 60 __le16 cid; 61 62 /* DW2 */ 63 u8 reserved; 64 u8 pkt_type; 65 u8 frag_n; 66 u8 seq; 67 68 /* DW3 */ 69 __le16 checksum; 70 u8 s2d_index; 71 u8 option; 72 73 /* DW4 */ 74 u8 reserved2[4]; 75 } __packed __aligned(4); 76 77 /* event table */ 78 enum { 79 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01, 80 MCU_EVENT_FW_START = 0x01, 81 MCU_EVENT_GENERIC = 0x01, 82 MCU_EVENT_ACCESS_REG = 0x02, 83 MCU_EVENT_MT_PATCH_SEM = 0x04, 84 MCU_EVENT_CH_PRIVILEGE = 0x18, 85 MCU_EVENT_EXT = 0xed, 86 MCU_EVENT_RESTART_DL = 0xef, 87 }; 88 89 /* ext event table */ 90 enum { 91 MCU_EXT_EVENT_PS_SYNC = 0x5, 92 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13, 93 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22, 94 MCU_EXT_EVENT_ASSERT_DUMP = 0x23, 95 MCU_EXT_EVENT_RDD_REPORT = 0x3a, 96 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f, 97 }; 98 99 enum { 100 MT_SKU_CCK_1_2 = 0, 101 MT_SKU_CCK_55_11, 102 MT_SKU_OFDM_6_9, 103 MT_SKU_OFDM_12_18, 104 MT_SKU_OFDM_24_36, 105 MT_SKU_OFDM_48, 106 MT_SKU_OFDM_54, 107 MT_SKU_HT20_0_8, 108 MT_SKU_HT20_32, 109 MT_SKU_HT20_1_2_9_10, 110 MT_SKU_HT20_3_4_11_12, 111 MT_SKU_HT20_5_13, 112 MT_SKU_HT20_6_14, 113 MT_SKU_HT20_7_15, 114 MT_SKU_HT40_0_8, 115 MT_SKU_HT40_32, 116 MT_SKU_HT40_1_2_9_10, 117 MT_SKU_HT40_3_4_11_12, 118 MT_SKU_HT40_5_13, 119 MT_SKU_HT40_6_14, 120 MT_SKU_HT40_7_15, 121 MT_SKU_VHT20_0, 122 MT_SKU_VHT20_1_2, 123 MT_SKU_VHT20_3_4, 124 MT_SKU_VHT20_5_6, 125 MT_SKU_VHT20_7, 126 MT_SKU_VHT20_8, 127 MT_SKU_VHT20_9, 128 MT_SKU_VHT40_0, 129 MT_SKU_VHT40_1_2, 130 MT_SKU_VHT40_3_4, 131 MT_SKU_VHT40_5_6, 132 MT_SKU_VHT40_7, 133 MT_SKU_VHT40_8, 134 MT_SKU_VHT40_9, 135 MT_SKU_VHT80_0, 136 MT_SKU_VHT80_1_2, 137 MT_SKU_VHT80_3_4, 138 MT_SKU_VHT80_5_6, 139 MT_SKU_VHT80_7, 140 MT_SKU_VHT80_8, 141 MT_SKU_VHT80_9, 142 MT_SKU_VHT160_0, 143 MT_SKU_VHT160_1_2, 144 MT_SKU_VHT160_3_4, 145 MT_SKU_VHT160_5_6, 146 MT_SKU_VHT160_7, 147 MT_SKU_VHT160_8, 148 MT_SKU_VHT160_9, 149 MT_SKU_1SS_DELTA, 150 MT_SKU_2SS_DELTA, 151 MT_SKU_3SS_DELTA, 152 MT_SKU_4SS_DELTA, 153 }; 154 155 struct mt7615_mcu_rxd { 156 __le32 rxd[4]; 157 158 __le16 len; 159 __le16 pkt_type_id; 160 161 u8 eid; 162 u8 seq; 163 __le16 __rsv; 164 165 u8 ext_eid; 166 u8 __rsv1[2]; 167 u8 s2d_index; 168 }; 169 170 struct mt7615_mcu_rdd_report { 171 struct mt7615_mcu_rxd rxd; 172 173 u8 idx; 174 u8 long_detected; 175 u8 constant_prf_detected; 176 u8 staggered_prf_detected; 177 u8 radar_type_idx; 178 u8 periodic_pulse_num; 179 u8 long_pulse_num; 180 u8 hw_pulse_num; 181 182 u8 out_lpn; 183 u8 out_spn; 184 u8 out_crpn; 185 u8 out_crpw; 186 u8 out_crbn; 187 u8 out_stgpn; 188 u8 out_stgpw; 189 190 u8 _rsv[2]; 191 192 __le32 out_pri_const; 193 __le32 out_pri_stg[3]; 194 195 struct { 196 __le32 start; 197 __le16 pulse_width; 198 __le16 pulse_power; 199 } long_pulse[32]; 200 201 struct { 202 __le32 start; 203 __le16 pulse_width; 204 __le16 pulse_power; 205 } periodic_pulse[32]; 206 207 struct { 208 __le32 start; 209 __le16 pulse_width; 210 __le16 pulse_power; 211 u8 sc_pass; 212 u8 sw_reset; 213 } hw_pulse[32]; 214 }; 215 216 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10)) 217 #define MCU_PKT_ID 0xa0 218 219 enum { 220 MCU_Q_QUERY, 221 MCU_Q_SET, 222 MCU_Q_RESERVED, 223 MCU_Q_NA 224 }; 225 226 enum { 227 MCU_S2D_H2N, 228 MCU_S2D_C2N, 229 MCU_S2D_H2C, 230 MCU_S2D_H2CN 231 }; 232 233 #define MCU_FW_PREFIX BIT(31) 234 #define MCU_UNI_PREFIX BIT(30) 235 #define MCU_CMD_MASK ~(MCU_FW_PREFIX | MCU_UNI_PREFIX) 236 237 enum { 238 MCU_CMD_TARGET_ADDRESS_LEN_REQ = MCU_FW_PREFIX | 0x01, 239 MCU_CMD_FW_START_REQ = MCU_FW_PREFIX | 0x02, 240 MCU_CMD_INIT_ACCESS_REG = 0x3, 241 MCU_CMD_PATCH_START_REQ = 0x05, 242 MCU_CMD_PATCH_FINISH_REQ = MCU_FW_PREFIX | 0x07, 243 MCU_CMD_PATCH_SEM_CONTROL = MCU_FW_PREFIX | 0x10, 244 MCU_CMD_EXT_CID = 0xED, 245 MCU_CMD_FW_SCATTER = MCU_FW_PREFIX | 0xEE, 246 MCU_CMD_RESTART_DL_REQ = MCU_FW_PREFIX | 0xEF, 247 }; 248 249 enum { 250 MCU_EXT_CMD_PM_STATE_CTRL = 0x07, 251 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08, 252 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11, 253 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13, 254 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21, 255 MCU_EXT_CMD_STA_REC_UPDATE = 0x25, 256 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26, 257 MCU_EXT_CMD_EDCA_UPDATE = 0x27, 258 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A, 259 MCU_EXT_CMD_GET_TEMP = 0x2c, 260 MCU_EXT_CMD_WTBL_UPDATE = 0x32, 261 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a, 262 MCU_EXT_CMD_PROTECT_CTRL = 0x3e, 263 MCU_EXT_CMD_DBDC_CTRL = 0x45, 264 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46, 265 MCU_EXT_CMD_BCN_OFFLOAD = 0x49, 266 MCU_EXT_CMD_SET_RX_PATH = 0x4e, 267 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58, 268 MCU_EXT_CMD_SET_RDD_TH = 0x7c, 269 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d, 270 }; 271 272 enum { 273 MCU_UNI_CMD_DEV_INFO_UPDATE = MCU_UNI_PREFIX | 0x01, 274 MCU_UNI_CMD_BSS_INFO_UPDATE = MCU_UNI_PREFIX | 0x02, 275 MCU_UNI_CMD_STA_REC_UPDATE = MCU_UNI_PREFIX | 0x03, 276 }; 277 278 #define MCU_CMD_ACK BIT(0) 279 #define MCU_CMD_UNI BIT(1) 280 #define MCU_CMD_QUERY BIT(2) 281 282 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | MCU_CMD_QUERY) 283 284 enum { 285 UNI_BSS_INFO_BASIC = 0, 286 UNI_BSS_INFO_BCN_CONTENT = 7, 287 }; 288 289 enum { 290 PATCH_SEM_RELEASE = 0x0, 291 PATCH_SEM_GET = 0x1 292 }; 293 294 enum { 295 PATCH_NOT_DL_SEM_FAIL = 0x0, 296 PATCH_IS_DL = 0x1, 297 PATCH_NOT_DL_SEM_SUCCESS = 0x2, 298 PATCH_REL_SEM_SUCCESS = 0x3 299 }; 300 301 enum { 302 FW_STATE_INITIAL = 0, 303 FW_STATE_FW_DOWNLOAD = 1, 304 FW_STATE_NORMAL_OPERATION = 2, 305 FW_STATE_NORMAL_TRX = 3, 306 FW_STATE_CR4_RDY = 7 307 }; 308 309 #define STA_TYPE_STA BIT(0) 310 #define STA_TYPE_AP BIT(1) 311 #define STA_TYPE_ADHOC BIT(2) 312 #define STA_TYPE_WDS BIT(4) 313 #define STA_TYPE_BC BIT(5) 314 315 #define NETWORK_INFRA BIT(16) 316 #define NETWORK_P2P BIT(17) 317 #define NETWORK_IBSS BIT(18) 318 #define NETWORK_WDS BIT(21) 319 320 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA) 321 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA) 322 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P) 323 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P) 324 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS) 325 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS) 326 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA) 327 328 #define CONN_STATE_DISCONNECT 0 329 #define CONN_STATE_CONNECT 1 330 #define CONN_STATE_PORT_SECURE 2 331 332 enum { 333 DEV_INFO_ACTIVE, 334 DEV_INFO_MAX_NUM 335 }; 336 337 enum { 338 DBDC_TYPE_WMM, 339 DBDC_TYPE_MGMT, 340 DBDC_TYPE_BSS, 341 DBDC_TYPE_MBSS, 342 DBDC_TYPE_REPEATER, 343 DBDC_TYPE_MU, 344 DBDC_TYPE_BF, 345 DBDC_TYPE_PTA, 346 __DBDC_TYPE_MAX, 347 }; 348 349 struct tlv { 350 __le16 tag; 351 __le16 len; 352 } __packed; 353 354 struct bss_info_omac { 355 __le16 tag; 356 __le16 len; 357 u8 hw_bss_idx; 358 u8 omac_idx; 359 u8 band_idx; 360 u8 rsv0; 361 __le32 conn_type; 362 u32 rsv1; 363 } __packed; 364 365 struct bss_info_basic { 366 __le16 tag; 367 __le16 len; 368 __le32 network_type; 369 u8 active; 370 u8 rsv0; 371 __le16 bcn_interval; 372 u8 bssid[ETH_ALEN]; 373 u8 wmm_idx; 374 u8 dtim_period; 375 u8 bmc_tx_wlan_idx; 376 u8 cipher; /* not used */ 377 u8 phymode; /* not used */ 378 u8 rsv1[5]; 379 } __packed; 380 381 struct bss_info_rf_ch { 382 __le16 tag; 383 __le16 len; 384 u8 pri_ch; 385 u8 central_ch0; 386 u8 central_ch1; 387 u8 bw; 388 } __packed; 389 390 struct bss_info_ext_bss { 391 __le16 tag; 392 __le16 len; 393 __le32 mbss_tsf_offset; /* in unit of us */ 394 u8 rsv[8]; 395 } __packed; 396 397 enum { 398 BSS_INFO_OMAC, 399 BSS_INFO_BASIC, 400 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */ 401 BSS_INFO_PM, /* sta only */ 402 BSS_INFO_UAPSD, /* sta only */ 403 BSS_INFO_ROAM_DETECTION, /* obsoleted */ 404 BSS_INFO_LQ_RM, /* obsoleted */ 405 BSS_INFO_EXT_BSS, 406 BSS_INFO_BMC_INFO, /* for bmc rate control in CR4 */ 407 BSS_INFO_SYNC_MODE, /* obsoleted */ 408 BSS_INFO_RA, 409 BSS_INFO_MAX_NUM 410 }; 411 412 enum { 413 WTBL_RESET_AND_SET = 1, 414 WTBL_SET, 415 WTBL_QUERY, 416 WTBL_RESET_ALL 417 }; 418 419 struct wtbl_req_hdr { 420 u8 wlan_idx; 421 u8 operation; 422 __le16 tlv_num; 423 u8 rsv[4]; 424 } __packed; 425 426 struct wtbl_generic { 427 __le16 tag; 428 __le16 len; 429 u8 peer_addr[ETH_ALEN]; 430 u8 muar_idx; 431 u8 skip_tx; 432 u8 cf_ack; 433 u8 qos; 434 u8 mesh; 435 u8 adm; 436 __le16 partial_aid; 437 u8 baf_en; 438 u8 aad_om; 439 } __packed; 440 441 struct wtbl_rx { 442 __le16 tag; 443 __le16 len; 444 u8 rcid; 445 u8 rca1; 446 u8 rca2; 447 u8 rv; 448 u8 rsv[4]; 449 } __packed; 450 451 struct wtbl_ht { 452 __le16 tag; 453 __le16 len; 454 u8 ht; 455 u8 ldpc; 456 u8 af; 457 u8 mm; 458 u8 rsv[4]; 459 } __packed; 460 461 struct wtbl_vht { 462 __le16 tag; 463 __le16 len; 464 u8 ldpc; 465 u8 dyn_bw; 466 u8 vht; 467 u8 txop_ps; 468 u8 rsv[4]; 469 } __packed; 470 471 struct wtbl_tx_ps { 472 __le16 tag; 473 __le16 len; 474 u8 txps; 475 u8 rsv[3]; 476 } __packed; 477 478 struct wtbl_hdr_trans { 479 __le16 tag; 480 __le16 len; 481 u8 to_ds; 482 u8 from_ds; 483 u8 disable_rx_trans; 484 u8 rsv; 485 } __packed; 486 487 enum { 488 MT_BA_TYPE_INVALID, 489 MT_BA_TYPE_ORIGINATOR, 490 MT_BA_TYPE_RECIPIENT 491 }; 492 493 enum { 494 RST_BA_MAC_TID_MATCH, 495 RST_BA_MAC_MATCH, 496 RST_BA_NO_MATCH 497 }; 498 499 struct wtbl_ba { 500 __le16 tag; 501 __le16 len; 502 /* common */ 503 u8 tid; 504 u8 ba_type; 505 u8 rsv0[2]; 506 /* originator only */ 507 __le16 sn; 508 u8 ba_en; 509 u8 ba_winsize_idx; 510 __le16 ba_winsize; 511 /* recipient only */ 512 u8 peer_addr[ETH_ALEN]; 513 u8 rst_ba_tid; 514 u8 rst_ba_sel; 515 u8 rst_ba_sb; 516 u8 band_idx; 517 u8 rsv1[4]; 518 } __packed; 519 520 struct wtbl_bf { 521 __le16 tag; 522 __le16 len; 523 u8 ibf; 524 u8 ebf; 525 u8 ibf_vht; 526 u8 ebf_vht; 527 u8 gid; 528 u8 pfmu_idx; 529 u8 rsv[2]; 530 } __packed; 531 532 struct wtbl_smps { 533 __le16 tag; 534 __le16 len; 535 u8 smps; 536 u8 rsv[3]; 537 } __packed; 538 539 struct wtbl_pn { 540 __le16 tag; 541 __le16 len; 542 u8 pn[6]; 543 u8 rsv[2]; 544 } __packed; 545 546 struct wtbl_spe { 547 __le16 tag; 548 __le16 len; 549 u8 spe_idx; 550 u8 rsv[3]; 551 } __packed; 552 553 struct wtbl_raw { 554 __le16 tag; 555 __le16 len; 556 u8 wtbl_idx; 557 u8 dw; 558 u8 rsv[2]; 559 __le32 msk; 560 __le32 val; 561 } __packed; 562 563 #define MT7615_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \ 564 sizeof(struct wtbl_generic) + \ 565 sizeof(struct wtbl_rx) + \ 566 sizeof(struct wtbl_ht) + \ 567 sizeof(struct wtbl_vht) + \ 568 sizeof(struct wtbl_tx_ps) + \ 569 sizeof(struct wtbl_hdr_trans) +\ 570 sizeof(struct wtbl_ba) + \ 571 sizeof(struct wtbl_bf) + \ 572 sizeof(struct wtbl_smps) + \ 573 sizeof(struct wtbl_pn) + \ 574 sizeof(struct wtbl_spe)) 575 576 #define MT7615_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \ 577 sizeof(struct sta_rec_basic) + \ 578 sizeof(struct sta_rec_ht) + \ 579 sizeof(struct sta_rec_vht) + \ 580 sizeof(struct tlv) + \ 581 MT7615_WTBL_UPDATE_MAX_SIZE) 582 583 #define MT7615_WTBL_UPDATE_BA_SIZE (sizeof(struct wtbl_req_hdr) + \ 584 sizeof(struct wtbl_ba)) 585 586 enum { 587 WTBL_GENERIC, 588 WTBL_RX, 589 WTBL_HT, 590 WTBL_VHT, 591 WTBL_PEER_PS, /* not used */ 592 WTBL_TX_PS, 593 WTBL_HDR_TRANS, 594 WTBL_SEC_KEY, 595 WTBL_BA, 596 WTBL_RDG, /* obsoleted */ 597 WTBL_PROTECT, /* not used */ 598 WTBL_CLEAR, /* not used */ 599 WTBL_BF, 600 WTBL_SMPS, 601 WTBL_RAW_DATA, /* debug only */ 602 WTBL_PN, 603 WTBL_SPE, 604 WTBL_MAX_NUM 605 }; 606 607 struct sta_ntlv_hdr { 608 u8 rsv[2]; 609 __le16 tlv_num; 610 } __packed; 611 612 struct sta_req_hdr { 613 u8 bss_idx; 614 u8 wlan_idx; 615 __le16 tlv_num; 616 u8 is_tlv_append; 617 u8 muar_idx; 618 u8 rsv[2]; 619 } __packed; 620 621 struct sta_rec_state { 622 __le16 tag; 623 __le16 len; 624 u8 state; 625 __le32 flags; 626 u8 vhtop; 627 u8 pad[2]; 628 } __packed; 629 630 struct sta_rec_basic { 631 __le16 tag; 632 __le16 len; 633 __le32 conn_type; 634 u8 conn_state; 635 u8 qos; 636 __le16 aid; 637 u8 peer_addr[ETH_ALEN]; 638 #define EXTRA_INFO_VER BIT(0) 639 #define EXTRA_INFO_NEW BIT(1) 640 __le16 extra_info; 641 } __packed; 642 643 struct sta_rec_ht { 644 __le16 tag; 645 __le16 len; 646 __le16 ht_cap; 647 u16 rsv; 648 } __packed; 649 650 struct sta_rec_vht { 651 __le16 tag; 652 __le16 len; 653 __le32 vht_cap; 654 __le16 vht_rx_mcs_map; 655 __le16 vht_tx_mcs_map; 656 } __packed; 657 658 struct sta_rec_ba { 659 __le16 tag; 660 __le16 len; 661 u8 tid; 662 u8 ba_type; 663 u8 amsdu; 664 u8 ba_en; 665 __le16 ssn; 666 __le16 winsize; 667 } __packed; 668 669 enum { 670 STA_REC_BASIC, 671 STA_REC_RA, 672 STA_REC_RA_CMM_INFO, 673 STA_REC_RA_UPDATE, 674 STA_REC_BF, 675 STA_REC_AMSDU, /* for CR4 */ 676 STA_REC_BA, 677 STA_REC_STATE, 678 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */ 679 STA_REC_HT, 680 STA_REC_VHT, 681 STA_REC_APPS, 682 STA_REC_WTBL = 13, 683 STA_REC_MAX_NUM 684 }; 685 686 enum { 687 CMD_CBW_20MHZ, 688 CMD_CBW_40MHZ, 689 CMD_CBW_80MHZ, 690 CMD_CBW_160MHZ, 691 CMD_CBW_10MHZ, 692 CMD_CBW_5MHZ, 693 CMD_CBW_8080MHZ 694 }; 695 696 enum { 697 CH_SWITCH_NORMAL = 0, 698 CH_SWITCH_SCAN = 3, 699 CH_SWITCH_MCC = 4, 700 CH_SWITCH_DFS = 5, 701 CH_SWITCH_BACKGROUND_SCAN_START = 6, 702 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7, 703 CH_SWITCH_BACKGROUND_SCAN_STOP = 8, 704 CH_SWITCH_SCAN_BYPASS_DPD = 9 705 }; 706 707 static inline struct sk_buff * 708 mt7615_mcu_msg_alloc(const void *data, int len) 709 { 710 return mt76_mcu_msg_alloc(data, sizeof(struct mt7615_mcu_txd), 711 len, 0); 712 } 713 714 #endif 715