1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics SA 2017 5 * Authors: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 * Gerald Baeza <gerald_baeza@yahoo.fr> 7 */ 8 9 #define DRIVER_NAME "stm32-usart" 10 11 struct stm32_usart_offsets { 12 u8 cr1; 13 u8 cr2; 14 u8 cr3; 15 u8 brr; 16 u8 gtpr; 17 u8 rtor; 18 u8 rqr; 19 u8 isr; 20 u8 icr; 21 u8 rdr; 22 u8 tdr; 23 }; 24 25 struct stm32_usart_config { 26 u8 uart_enable_bit; /* USART_CR1_UE */ 27 bool has_7bits_data; 28 bool has_wakeup; 29 bool has_fifo; 30 int fifosize; 31 }; 32 33 struct stm32_usart_info { 34 struct stm32_usart_offsets ofs; 35 struct stm32_usart_config cfg; 36 }; 37 38 #define UNDEF_REG 0xff 39 40 /* Register offsets */ 41 struct stm32_usart_info stm32f4_info = { 42 .ofs = { 43 .isr = 0x00, 44 .rdr = 0x04, 45 .tdr = 0x04, 46 .brr = 0x08, 47 .cr1 = 0x0c, 48 .cr2 = 0x10, 49 .cr3 = 0x14, 50 .gtpr = 0x18, 51 .rtor = UNDEF_REG, 52 .rqr = UNDEF_REG, 53 .icr = UNDEF_REG, 54 }, 55 .cfg = { 56 .uart_enable_bit = 13, 57 .has_7bits_data = false, 58 .fifosize = 1, 59 } 60 }; 61 62 struct stm32_usart_info stm32f7_info = { 63 .ofs = { 64 .cr1 = 0x00, 65 .cr2 = 0x04, 66 .cr3 = 0x08, 67 .brr = 0x0c, 68 .gtpr = 0x10, 69 .rtor = 0x14, 70 .rqr = 0x18, 71 .isr = 0x1c, 72 .icr = 0x20, 73 .rdr = 0x24, 74 .tdr = 0x28, 75 }, 76 .cfg = { 77 .uart_enable_bit = 0, 78 .has_7bits_data = true, 79 .fifosize = 1, 80 } 81 }; 82 83 struct stm32_usart_info stm32h7_info = { 84 .ofs = { 85 .cr1 = 0x00, 86 .cr2 = 0x04, 87 .cr3 = 0x08, 88 .brr = 0x0c, 89 .gtpr = 0x10, 90 .rtor = 0x14, 91 .rqr = 0x18, 92 .isr = 0x1c, 93 .icr = 0x20, 94 .rdr = 0x24, 95 .tdr = 0x28, 96 }, 97 .cfg = { 98 .uart_enable_bit = 0, 99 .has_7bits_data = true, 100 .has_wakeup = true, 101 .has_fifo = true, 102 .fifosize = 16, 103 } 104 }; 105 106 /* USART_SR (F4) / USART_ISR (F7) */ 107 #define USART_SR_PE BIT(0) 108 #define USART_SR_FE BIT(1) 109 #define USART_SR_NF BIT(2) 110 #define USART_SR_ORE BIT(3) 111 #define USART_SR_IDLE BIT(4) 112 #define USART_SR_RXNE BIT(5) 113 #define USART_SR_TC BIT(6) 114 #define USART_SR_TXE BIT(7) 115 #define USART_SR_CTSIF BIT(9) 116 #define USART_SR_CTS BIT(10) /* F7 */ 117 #define USART_SR_RTOF BIT(11) /* F7 */ 118 #define USART_SR_EOBF BIT(12) /* F7 */ 119 #define USART_SR_ABRE BIT(14) /* F7 */ 120 #define USART_SR_ABRF BIT(15) /* F7 */ 121 #define USART_SR_BUSY BIT(16) /* F7 */ 122 #define USART_SR_CMF BIT(17) /* F7 */ 123 #define USART_SR_SBKF BIT(18) /* F7 */ 124 #define USART_SR_WUF BIT(20) /* H7 */ 125 #define USART_SR_TEACK BIT(21) /* F7 */ 126 #define USART_SR_ERR_MASK (USART_SR_ORE | USART_SR_FE | USART_SR_PE) 127 /* Dummy bits */ 128 #define USART_SR_DUMMY_RX BIT(16) 129 130 /* USART_ICR (F7) */ 131 #define USART_CR_TC BIT(6) 132 133 /* USART_DR */ 134 #define USART_DR_MASK GENMASK(8, 0) 135 136 /* USART_BRR */ 137 #define USART_BRR_DIV_F_MASK GENMASK(3, 0) 138 #define USART_BRR_DIV_M_MASK GENMASK(15, 4) 139 #define USART_BRR_DIV_M_SHIFT 4 140 #define USART_BRR_04_R_SHIFT 1 141 142 /* USART_CR1 */ 143 #define USART_CR1_SBK BIT(0) 144 #define USART_CR1_RWU BIT(1) /* F4 */ 145 #define USART_CR1_UESM BIT(1) /* H7 */ 146 #define USART_CR1_RE BIT(2) 147 #define USART_CR1_TE BIT(3) 148 #define USART_CR1_IDLEIE BIT(4) 149 #define USART_CR1_RXNEIE BIT(5) 150 #define USART_CR1_TCIE BIT(6) 151 #define USART_CR1_TXEIE BIT(7) 152 #define USART_CR1_PEIE BIT(8) 153 #define USART_CR1_PS BIT(9) 154 #define USART_CR1_PCE BIT(10) 155 #define USART_CR1_WAKE BIT(11) 156 #define USART_CR1_M0 BIT(12) /* F7 (CR1_M for F4) */ 157 #define USART_CR1_MME BIT(13) /* F7 */ 158 #define USART_CR1_CMIE BIT(14) /* F7 */ 159 #define USART_CR1_OVER8 BIT(15) 160 #define USART_CR1_DEDT_MASK GENMASK(20, 16) /* F7 */ 161 #define USART_CR1_DEAT_MASK GENMASK(25, 21) /* F7 */ 162 #define USART_CR1_RTOIE BIT(26) /* F7 */ 163 #define USART_CR1_EOBIE BIT(27) /* F7 */ 164 #define USART_CR1_M1 BIT(28) /* F7 */ 165 #define USART_CR1_IE_MASK (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27)) 166 #define USART_CR1_FIFOEN BIT(29) /* H7 */ 167 #define USART_CR1_DEAT_SHIFT 21 168 #define USART_CR1_DEDT_SHIFT 16 169 170 /* USART_CR2 */ 171 #define USART_CR2_ADD_MASK GENMASK(3, 0) /* F4 */ 172 #define USART_CR2_ADDM7 BIT(4) /* F7 */ 173 #define USART_CR2_LBCL BIT(8) 174 #define USART_CR2_CPHA BIT(9) 175 #define USART_CR2_CPOL BIT(10) 176 #define USART_CR2_CLKEN BIT(11) 177 #define USART_CR2_STOP_2B BIT(13) 178 #define USART_CR2_STOP_MASK GENMASK(13, 12) 179 #define USART_CR2_LINEN BIT(14) 180 #define USART_CR2_SWAP BIT(15) /* F7 */ 181 #define USART_CR2_RXINV BIT(16) /* F7 */ 182 #define USART_CR2_TXINV BIT(17) /* F7 */ 183 #define USART_CR2_DATAINV BIT(18) /* F7 */ 184 #define USART_CR2_MSBFIRST BIT(19) /* F7 */ 185 #define USART_CR2_ABREN BIT(20) /* F7 */ 186 #define USART_CR2_ABRMOD_MASK GENMASK(22, 21) /* F7 */ 187 #define USART_CR2_RTOEN BIT(23) /* F7 */ 188 #define USART_CR2_ADD_F7_MASK GENMASK(31, 24) /* F7 */ 189 190 /* USART_CR3 */ 191 #define USART_CR3_EIE BIT(0) 192 #define USART_CR3_IREN BIT(1) 193 #define USART_CR3_IRLP BIT(2) 194 #define USART_CR3_HDSEL BIT(3) 195 #define USART_CR3_NACK BIT(4) 196 #define USART_CR3_SCEN BIT(5) 197 #define USART_CR3_DMAR BIT(6) 198 #define USART_CR3_DMAT BIT(7) 199 #define USART_CR3_RTSE BIT(8) 200 #define USART_CR3_CTSE BIT(9) 201 #define USART_CR3_CTSIE BIT(10) 202 #define USART_CR3_ONEBIT BIT(11) 203 #define USART_CR3_OVRDIS BIT(12) /* F7 */ 204 #define USART_CR3_DDRE BIT(13) /* F7 */ 205 #define USART_CR3_DEM BIT(14) /* F7 */ 206 #define USART_CR3_DEP BIT(15) /* F7 */ 207 #define USART_CR3_SCARCNT_MASK GENMASK(19, 17) /* F7 */ 208 #define USART_CR3_WUS_MASK GENMASK(21, 20) /* H7 */ 209 #define USART_CR3_WUS_START_BIT BIT(21) /* H7 */ 210 #define USART_CR3_WUFIE BIT(22) /* H7 */ 211 #define USART_CR3_TXFTIE BIT(23) /* H7 */ 212 #define USART_CR3_TCBGTIE BIT(24) /* H7 */ 213 #define USART_CR3_RXFTCFG_MASK GENMASK(27, 25) /* H7 */ 214 #define USART_CR3_RXFTCFG_SHIFT 25 /* H7 */ 215 #define USART_CR3_RXFTIE BIT(28) /* H7 */ 216 #define USART_CR3_TXFTCFG_MASK GENMASK(31, 29) /* H7 */ 217 #define USART_CR3_TXFTCFG_SHIFT 29 /* H7 */ 218 219 /* TX FIFO threashold set to half of its depth */ 220 #define USART_CR3_TXFTCFG_HALF 0x2 221 222 /* RX FIFO threashold set to half of its depth */ 223 #define USART_CR3_RXFTCFG_HALF 0x2 224 225 /* USART_GTPR */ 226 #define USART_GTPR_PSC_MASK GENMASK(7, 0) 227 #define USART_GTPR_GT_MASK GENMASK(15, 8) 228 229 /* USART_RTOR */ 230 #define USART_RTOR_RTO_MASK GENMASK(23, 0) /* F7 */ 231 #define USART_RTOR_BLEN_MASK GENMASK(31, 24) /* F7 */ 232 233 /* USART_RQR */ 234 #define USART_RQR_ABRRQ BIT(0) /* F7 */ 235 #define USART_RQR_SBKRQ BIT(1) /* F7 */ 236 #define USART_RQR_MMRQ BIT(2) /* F7 */ 237 #define USART_RQR_RXFRQ BIT(3) /* F7 */ 238 #define USART_RQR_TXFRQ BIT(4) /* F7 */ 239 240 /* USART_ICR */ 241 #define USART_ICR_PECF BIT(0) /* F7 */ 242 #define USART_ICR_FECF BIT(1) /* F7 */ 243 #define USART_ICR_ORECF BIT(3) /* F7 */ 244 #define USART_ICR_IDLECF BIT(4) /* F7 */ 245 #define USART_ICR_TCCF BIT(6) /* F7 */ 246 #define USART_ICR_CTSCF BIT(9) /* F7 */ 247 #define USART_ICR_RTOCF BIT(11) /* F7 */ 248 #define USART_ICR_EOBCF BIT(12) /* F7 */ 249 #define USART_ICR_CMCF BIT(17) /* F7 */ 250 #define USART_ICR_WUCF BIT(20) /* H7 */ 251 252 #define STM32_SERIAL_NAME "ttySTM" 253 #define STM32_MAX_PORTS 8 254 255 #define RX_BUF_L 200 /* dma rx buffer length */ 256 #define RX_BUF_P RX_BUF_L /* dma rx buffer period */ 257 #define TX_BUF_L 200 /* dma tx buffer length */ 258 259 struct stm32_port { 260 struct uart_port port; 261 struct clk *clk; 262 struct stm32_usart_info *info; 263 struct dma_chan *rx_ch; /* dma rx channel */ 264 dma_addr_t rx_dma_buf; /* dma rx buffer bus address */ 265 unsigned char *rx_buf; /* dma rx buffer cpu address */ 266 struct dma_chan *tx_ch; /* dma tx channel */ 267 dma_addr_t tx_dma_buf; /* dma tx buffer bus address */ 268 unsigned char *tx_buf; /* dma tx buffer cpu address */ 269 u32 cr1_irq; /* USART_CR1_RXNEIE or RTOIE */ 270 u32 cr3_irq; /* USART_CR3_RXFTIE */ 271 int last_res; 272 bool tx_dma_busy; /* dma tx busy */ 273 bool hw_flow_control; 274 bool fifoen; 275 int wakeirq; 276 int rdr_mask; /* receive data register mask */ 277 struct mctrl_gpios *gpios; /* modem control gpios */ 278 }; 279 280 static struct stm32_port stm32_ports[STM32_MAX_PORTS]; 281 static struct uart_driver stm32_usart_driver; 282