1 /* QLogic qede NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #include "qede_ptp.h" 33 #define QEDE_PTP_TX_TIMEOUT (2 * HZ) 34 35 struct qede_ptp { 36 const struct qed_eth_ptp_ops *ops; 37 struct ptp_clock_info clock_info; 38 struct cyclecounter cc; 39 struct timecounter tc; 40 struct ptp_clock *clock; 41 struct work_struct work; 42 unsigned long ptp_tx_start; 43 struct qede_dev *edev; 44 struct sk_buff *tx_skb; 45 46 /* ptp spinlock is used for protecting the cycle/time counter fields 47 * and, also for serializing the qed PTP API invocations. 48 */ 49 spinlock_t lock; 50 bool hw_ts_ioctl_called; 51 u16 tx_type; 52 u16 rx_filter; 53 }; 54 55 /** 56 * qede_ptp_adjfreq 57 * @ptp: the ptp clock structure 58 * @ppb: parts per billion adjustment from base 59 * 60 * Adjust the frequency of the ptp cycle counter by the 61 * indicated ppb from the base frequency. 62 */ 63 static int qede_ptp_adjfreq(struct ptp_clock_info *info, s32 ppb) 64 { 65 struct qede_ptp *ptp = container_of(info, struct qede_ptp, clock_info); 66 struct qede_dev *edev = ptp->edev; 67 int rc; 68 69 __qede_lock(edev); 70 if (edev->state == QEDE_STATE_OPEN) { 71 spin_lock_bh(&ptp->lock); 72 rc = ptp->ops->adjfreq(edev->cdev, ppb); 73 spin_unlock_bh(&ptp->lock); 74 } else { 75 DP_ERR(edev, "PTP adjfreq called while interface is down\n"); 76 rc = -EFAULT; 77 } 78 __qede_unlock(edev); 79 80 return rc; 81 } 82 83 static int qede_ptp_adjtime(struct ptp_clock_info *info, s64 delta) 84 { 85 struct qede_dev *edev; 86 struct qede_ptp *ptp; 87 88 ptp = container_of(info, struct qede_ptp, clock_info); 89 edev = ptp->edev; 90 91 DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP adjtime called, delta = %llx\n", 92 delta); 93 94 spin_lock_bh(&ptp->lock); 95 timecounter_adjtime(&ptp->tc, delta); 96 spin_unlock_bh(&ptp->lock); 97 98 return 0; 99 } 100 101 static int qede_ptp_gettime(struct ptp_clock_info *info, struct timespec64 *ts) 102 { 103 struct qede_dev *edev; 104 struct qede_ptp *ptp; 105 u64 ns; 106 107 ptp = container_of(info, struct qede_ptp, clock_info); 108 edev = ptp->edev; 109 110 spin_lock_bh(&ptp->lock); 111 ns = timecounter_read(&ptp->tc); 112 spin_unlock_bh(&ptp->lock); 113 114 DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP gettime called, ns = %llu\n", ns); 115 116 *ts = ns_to_timespec64(ns); 117 118 return 0; 119 } 120 121 static int qede_ptp_settime(struct ptp_clock_info *info, 122 const struct timespec64 *ts) 123 { 124 struct qede_dev *edev; 125 struct qede_ptp *ptp; 126 u64 ns; 127 128 ptp = container_of(info, struct qede_ptp, clock_info); 129 edev = ptp->edev; 130 131 ns = timespec64_to_ns(ts); 132 133 DP_VERBOSE(edev, QED_MSG_DEBUG, "PTP settime called, ns = %llu\n", ns); 134 135 /* Re-init the timecounter */ 136 spin_lock_bh(&ptp->lock); 137 timecounter_init(&ptp->tc, &ptp->cc, ns); 138 spin_unlock_bh(&ptp->lock); 139 140 return 0; 141 } 142 143 /* Enable (or disable) ancillary features of the phc subsystem */ 144 static int qede_ptp_ancillary_feature_enable(struct ptp_clock_info *info, 145 struct ptp_clock_request *rq, 146 int on) 147 { 148 struct qede_dev *edev; 149 struct qede_ptp *ptp; 150 151 ptp = container_of(info, struct qede_ptp, clock_info); 152 edev = ptp->edev; 153 154 DP_ERR(edev, "PHC ancillary features are not supported\n"); 155 156 return -ENOTSUPP; 157 } 158 159 static void qede_ptp_task(struct work_struct *work) 160 { 161 struct skb_shared_hwtstamps shhwtstamps; 162 struct qede_dev *edev; 163 struct qede_ptp *ptp; 164 u64 timestamp, ns; 165 bool timedout; 166 int rc; 167 168 ptp = container_of(work, struct qede_ptp, work); 169 edev = ptp->edev; 170 timedout = time_is_before_jiffies(ptp->ptp_tx_start + 171 QEDE_PTP_TX_TIMEOUT); 172 173 /* Read Tx timestamp registers */ 174 spin_lock_bh(&ptp->lock); 175 rc = ptp->ops->read_tx_ts(edev->cdev, ×tamp); 176 spin_unlock_bh(&ptp->lock); 177 if (rc) { 178 if (unlikely(timedout)) { 179 DP_INFO(edev, "Tx timestamp is not recorded\n"); 180 dev_kfree_skb_any(ptp->tx_skb); 181 ptp->tx_skb = NULL; 182 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, 183 &edev->flags); 184 edev->ptp_skip_txts++; 185 } else { 186 /* Reschedule to keep checking for a valid TS value */ 187 schedule_work(&ptp->work); 188 } 189 return; 190 } 191 192 ns = timecounter_cyc2time(&ptp->tc, timestamp); 193 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 194 shhwtstamps.hwtstamp = ns_to_ktime(ns); 195 skb_tstamp_tx(ptp->tx_skb, &shhwtstamps); 196 dev_kfree_skb_any(ptp->tx_skb); 197 ptp->tx_skb = NULL; 198 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags); 199 200 DP_VERBOSE(edev, QED_MSG_DEBUG, 201 "Tx timestamp, timestamp cycles = %llu, ns = %llu\n", 202 timestamp, ns); 203 } 204 205 /* Read the PHC. This API is invoked with ptp_lock held. */ 206 static u64 qede_ptp_read_cc(const struct cyclecounter *cc) 207 { 208 struct qede_dev *edev; 209 struct qede_ptp *ptp; 210 u64 phc_cycles; 211 int rc; 212 213 ptp = container_of(cc, struct qede_ptp, cc); 214 edev = ptp->edev; 215 rc = ptp->ops->read_cc(edev->cdev, &phc_cycles); 216 if (rc) 217 WARN_ONCE(1, "PHC read err %d\n", rc); 218 219 DP_VERBOSE(edev, QED_MSG_DEBUG, "PHC read cycles = %llu\n", phc_cycles); 220 221 return phc_cycles; 222 } 223 224 static int qede_ptp_cfg_filters(struct qede_dev *edev) 225 { 226 enum qed_ptp_hwtstamp_tx_type tx_type = QED_PTP_HWTSTAMP_TX_ON; 227 enum qed_ptp_filter_type rx_filter = QED_PTP_FILTER_NONE; 228 struct qede_ptp *ptp = edev->ptp; 229 230 if (!ptp) 231 return -EIO; 232 233 if (!ptp->hw_ts_ioctl_called) { 234 DP_INFO(edev, "TS IOCTL not called\n"); 235 return 0; 236 } 237 238 switch (ptp->tx_type) { 239 case HWTSTAMP_TX_ON: 240 set_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags); 241 tx_type = QED_PTP_HWTSTAMP_TX_ON; 242 break; 243 244 case HWTSTAMP_TX_OFF: 245 clear_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags); 246 tx_type = QED_PTP_HWTSTAMP_TX_OFF; 247 break; 248 249 case HWTSTAMP_TX_ONESTEP_SYNC: 250 case HWTSTAMP_TX_ONESTEP_P2P: 251 DP_ERR(edev, "One-step timestamping is not supported\n"); 252 return -ERANGE; 253 } 254 255 spin_lock_bh(&ptp->lock); 256 switch (ptp->rx_filter) { 257 case HWTSTAMP_FILTER_NONE: 258 rx_filter = QED_PTP_FILTER_NONE; 259 break; 260 case HWTSTAMP_FILTER_ALL: 261 case HWTSTAMP_FILTER_SOME: 262 case HWTSTAMP_FILTER_NTP_ALL: 263 ptp->rx_filter = HWTSTAMP_FILTER_NONE; 264 rx_filter = QED_PTP_FILTER_ALL; 265 break; 266 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 267 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 268 rx_filter = QED_PTP_FILTER_V1_L4_EVENT; 269 break; 270 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 271 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 272 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 273 /* Initialize PTP detection for UDP/IPv4 events */ 274 rx_filter = QED_PTP_FILTER_V1_L4_GEN; 275 break; 276 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 277 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 278 rx_filter = QED_PTP_FILTER_V2_L4_EVENT; 279 break; 280 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 281 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 282 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 283 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */ 284 rx_filter = QED_PTP_FILTER_V2_L4_GEN; 285 break; 286 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 287 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 288 rx_filter = QED_PTP_FILTER_V2_L2_EVENT; 289 break; 290 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 291 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 292 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT; 293 /* Initialize PTP detection L2 events */ 294 rx_filter = QED_PTP_FILTER_V2_L2_GEN; 295 break; 296 case HWTSTAMP_FILTER_PTP_V2_EVENT: 297 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 298 rx_filter = QED_PTP_FILTER_V2_EVENT; 299 break; 300 case HWTSTAMP_FILTER_PTP_V2_SYNC: 301 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 302 ptp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 303 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */ 304 rx_filter = QED_PTP_FILTER_V2_GEN; 305 break; 306 } 307 308 ptp->ops->cfg_filters(edev->cdev, rx_filter, tx_type); 309 310 spin_unlock_bh(&ptp->lock); 311 312 return 0; 313 } 314 315 int qede_ptp_hw_ts(struct qede_dev *edev, struct ifreq *ifr) 316 { 317 struct hwtstamp_config config; 318 struct qede_ptp *ptp; 319 int rc; 320 321 ptp = edev->ptp; 322 if (!ptp) 323 return -EIO; 324 325 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 326 return -EFAULT; 327 328 DP_VERBOSE(edev, QED_MSG_DEBUG, 329 "HWTSTAMP IOCTL: Requested tx_type = %d, requested rx_filters = %d\n", 330 config.tx_type, config.rx_filter); 331 332 if (config.flags) { 333 DP_ERR(edev, "config.flags is reserved for future use\n"); 334 return -EINVAL; 335 } 336 337 ptp->hw_ts_ioctl_called = 1; 338 ptp->tx_type = config.tx_type; 339 ptp->rx_filter = config.rx_filter; 340 341 rc = qede_ptp_cfg_filters(edev); 342 if (rc) 343 return rc; 344 345 config.rx_filter = ptp->rx_filter; 346 347 return copy_to_user(ifr->ifr_data, &config, 348 sizeof(config)) ? -EFAULT : 0; 349 } 350 351 int qede_ptp_get_ts_info(struct qede_dev *edev, struct ethtool_ts_info *info) 352 { 353 struct qede_ptp *ptp = edev->ptp; 354 355 if (!ptp) { 356 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 357 SOF_TIMESTAMPING_RX_SOFTWARE | 358 SOF_TIMESTAMPING_SOFTWARE; 359 info->phc_index = -1; 360 361 return 0; 362 } 363 364 info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE | 365 SOF_TIMESTAMPING_RX_SOFTWARE | 366 SOF_TIMESTAMPING_SOFTWARE | 367 SOF_TIMESTAMPING_TX_HARDWARE | 368 SOF_TIMESTAMPING_RX_HARDWARE | 369 SOF_TIMESTAMPING_RAW_HARDWARE; 370 371 if (ptp->clock) 372 info->phc_index = ptp_clock_index(ptp->clock); 373 else 374 info->phc_index = -1; 375 376 info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) | 377 BIT(HWTSTAMP_FILTER_PTP_V1_L4_EVENT) | 378 BIT(HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 379 BIT(HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 380 BIT(HWTSTAMP_FILTER_PTP_V2_L4_EVENT) | 381 BIT(HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 382 BIT(HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 383 BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT) | 384 BIT(HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 385 BIT(HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 386 BIT(HWTSTAMP_FILTER_PTP_V2_EVENT) | 387 BIT(HWTSTAMP_FILTER_PTP_V2_SYNC) | 388 BIT(HWTSTAMP_FILTER_PTP_V2_DELAY_REQ); 389 390 info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON); 391 392 return 0; 393 } 394 395 void qede_ptp_disable(struct qede_dev *edev) 396 { 397 struct qede_ptp *ptp; 398 399 ptp = edev->ptp; 400 if (!ptp) 401 return; 402 403 if (ptp->clock) { 404 ptp_clock_unregister(ptp->clock); 405 ptp->clock = NULL; 406 } 407 408 /* Cancel PTP work queue. Should be done after the Tx queues are 409 * drained to prevent additional scheduling. 410 */ 411 cancel_work_sync(&ptp->work); 412 if (ptp->tx_skb) { 413 dev_kfree_skb_any(ptp->tx_skb); 414 ptp->tx_skb = NULL; 415 } 416 417 /* Disable PTP in HW */ 418 spin_lock_bh(&ptp->lock); 419 ptp->ops->disable(edev->cdev); 420 spin_unlock_bh(&ptp->lock); 421 422 kfree(ptp); 423 edev->ptp = NULL; 424 } 425 426 static int qede_ptp_init(struct qede_dev *edev, bool init_tc) 427 { 428 struct qede_ptp *ptp; 429 int rc; 430 431 ptp = edev->ptp; 432 if (!ptp) 433 return -EINVAL; 434 435 spin_lock_init(&ptp->lock); 436 437 /* Configure PTP in HW */ 438 rc = ptp->ops->enable(edev->cdev); 439 if (rc) { 440 DP_INFO(edev, "PTP HW enable failed\n"); 441 return rc; 442 } 443 444 /* Init work queue for Tx timestamping */ 445 INIT_WORK(&ptp->work, qede_ptp_task); 446 447 /* Init cyclecounter and timecounter. This is done only in the first 448 * load. If done in every load, PTP application will fail when doing 449 * unload / load (e.g. MTU change) while it is running. 450 */ 451 if (init_tc) { 452 memset(&ptp->cc, 0, sizeof(ptp->cc)); 453 ptp->cc.read = qede_ptp_read_cc; 454 ptp->cc.mask = CYCLECOUNTER_MASK(64); 455 ptp->cc.shift = 0; 456 ptp->cc.mult = 1; 457 458 timecounter_init(&ptp->tc, &ptp->cc, 459 ktime_to_ns(ktime_get_real())); 460 } 461 462 return rc; 463 } 464 465 int qede_ptp_enable(struct qede_dev *edev, bool init_tc) 466 { 467 struct qede_ptp *ptp; 468 int rc; 469 470 ptp = kzalloc(sizeof(*ptp), GFP_KERNEL); 471 if (!ptp) { 472 DP_INFO(edev, "Failed to allocate struct for PTP\n"); 473 return -ENOMEM; 474 } 475 476 ptp->edev = edev; 477 ptp->ops = edev->ops->ptp; 478 if (!ptp->ops) { 479 DP_INFO(edev, "PTP enable failed\n"); 480 rc = -EIO; 481 goto err1; 482 } 483 484 edev->ptp = ptp; 485 486 rc = qede_ptp_init(edev, init_tc); 487 if (rc) 488 goto err1; 489 490 qede_ptp_cfg_filters(edev); 491 492 /* Fill the ptp_clock_info struct and register PTP clock */ 493 ptp->clock_info.owner = THIS_MODULE; 494 snprintf(ptp->clock_info.name, 16, "%s", edev->ndev->name); 495 ptp->clock_info.max_adj = QED_MAX_PHC_DRIFT_PPB; 496 ptp->clock_info.n_alarm = 0; 497 ptp->clock_info.n_ext_ts = 0; 498 ptp->clock_info.n_per_out = 0; 499 ptp->clock_info.pps = 0; 500 ptp->clock_info.adjfreq = qede_ptp_adjfreq; 501 ptp->clock_info.adjtime = qede_ptp_adjtime; 502 ptp->clock_info.gettime64 = qede_ptp_gettime; 503 ptp->clock_info.settime64 = qede_ptp_settime; 504 ptp->clock_info.enable = qede_ptp_ancillary_feature_enable; 505 506 ptp->clock = ptp_clock_register(&ptp->clock_info, &edev->pdev->dev); 507 if (IS_ERR(ptp->clock)) { 508 DP_ERR(edev, "PTP clock registration failed\n"); 509 qede_ptp_disable(edev); 510 rc = -EINVAL; 511 goto err2; 512 } 513 514 return 0; 515 516 err1: 517 kfree(ptp); 518 err2: 519 edev->ptp = NULL; 520 521 return rc; 522 } 523 524 void qede_ptp_tx_ts(struct qede_dev *edev, struct sk_buff *skb) 525 { 526 struct qede_ptp *ptp; 527 528 ptp = edev->ptp; 529 if (!ptp) 530 return; 531 532 if (test_and_set_bit_lock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, 533 &edev->flags)) { 534 DP_ERR(edev, "Timestamping in progress\n"); 535 edev->ptp_skip_txts++; 536 return; 537 } 538 539 if (unlikely(!test_bit(QEDE_FLAGS_TX_TIMESTAMPING_EN, &edev->flags))) { 540 DP_ERR(edev, 541 "Tx timestamping was not enabled, this packet will not be timestamped\n"); 542 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags); 543 edev->ptp_skip_txts++; 544 } else if (unlikely(ptp->tx_skb)) { 545 DP_ERR(edev, 546 "The device supports only a single outstanding packet to timestamp, this packet will not be timestamped\n"); 547 clear_bit_unlock(QEDE_FLAGS_PTP_TX_IN_PRORGESS, &edev->flags); 548 edev->ptp_skip_txts++; 549 } else { 550 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 551 /* schedule check for Tx timestamp */ 552 ptp->tx_skb = skb_get(skb); 553 ptp->ptp_tx_start = jiffies; 554 schedule_work(&ptp->work); 555 } 556 } 557 558 void qede_ptp_rx_ts(struct qede_dev *edev, struct sk_buff *skb) 559 { 560 struct qede_ptp *ptp; 561 u64 timestamp, ns; 562 int rc; 563 564 ptp = edev->ptp; 565 if (!ptp) 566 return; 567 568 spin_lock_bh(&ptp->lock); 569 rc = ptp->ops->read_rx_ts(edev->cdev, ×tamp); 570 if (rc) { 571 spin_unlock_bh(&ptp->lock); 572 DP_INFO(edev, "Invalid Rx timestamp\n"); 573 return; 574 } 575 576 ns = timecounter_cyc2time(&ptp->tc, timestamp); 577 spin_unlock_bh(&ptp->lock); 578 skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns); 579 DP_VERBOSE(edev, QED_MSG_DEBUG, 580 "Rx timestamp, timestamp cycles = %llu, ns = %llu\n", 581 timestamp, ns); 582 } 583