1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 39 select BUILDTIME_TABLE_SORT if MMU 40 select CLONE_BACKWARDS 41 select CPU_PM if SUSPEND || CPU_IDLE 42 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 43 select DMA_DECLARE_COHERENT 44 select DMA_OPS 45 select DMA_REMAP if MMU 46 select EDAC_SUPPORT 47 select EDAC_ATOMIC_SCRUB 48 select GENERIC_ALLOCATOR 49 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 50 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 51 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 52 select GENERIC_CPU_AUTOPROBE 53 select GENERIC_EARLY_IOREMAP 54 select GENERIC_IDLE_POLL_SETUP 55 select GENERIC_IRQ_PROBE 56 select GENERIC_IRQ_SHOW 57 select GENERIC_IRQ_SHOW_LEVEL 58 select GENERIC_PCI_IOMAP 59 select GENERIC_SCHED_CLOCK 60 select GENERIC_SMP_IDLE_THREAD 61 select GENERIC_STRNCPY_FROM_USER 62 select GENERIC_STRNLEN_USER 63 select HANDLE_DOMAIN_IRQ 64 select HARDIRQS_SW_RESEND 65 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 66 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 67 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 68 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 69 select HAVE_ARCH_MMAP_RND_BITS if MMU 70 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 71 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 72 select HAVE_ARCH_TRACEHOOK 73 select HAVE_ARM_SMCCC if CPU_V7 74 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 75 select HAVE_CONTEXT_TRACKING 76 select HAVE_C_RECORDMCOUNT 77 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 78 select HAVE_DMA_CONTIGUOUS if MMU 79 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 80 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 81 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 82 select HAVE_EXIT_THREAD 83 select HAVE_FAST_GUP if ARM_LPAE 84 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 85 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 86 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000) 87 select HAVE_GCC_PLUGINS 88 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 89 select HAVE_IDE if PCI || ISA || PCMCIA 90 select HAVE_IRQ_TIME_ACCOUNTING 91 select HAVE_KERNEL_GZIP 92 select HAVE_KERNEL_LZ4 93 select HAVE_KERNEL_LZMA 94 select HAVE_KERNEL_LZO 95 select HAVE_KERNEL_XZ 96 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 97 select HAVE_KRETPROBES if HAVE_KPROBES 98 select HAVE_MOD_ARCH_SPECIFIC 99 select HAVE_NMI 100 select HAVE_OPROFILE if HAVE_PERF_EVENTS 101 select HAVE_OPTPROBES if !THUMB2_KERNEL 102 select HAVE_PERF_EVENTS 103 select HAVE_PERF_REGS 104 select HAVE_PERF_USER_STACK_DUMP 105 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 106 select HAVE_REGS_AND_STACK_ACCESS_API 107 select HAVE_RSEQ 108 select HAVE_STACKPROTECTOR 109 select HAVE_SYSCALL_TRACEPOINTS 110 select HAVE_UID16 111 select HAVE_VIRT_CPU_ACCOUNTING_GEN 112 select IRQ_FORCED_THREADING 113 select MODULES_USE_ELF_REL 114 select NEED_DMA_MAP_STATE 115 select OF_EARLY_FLATTREE if OF 116 select OLD_SIGACTION 117 select OLD_SIGSUSPEND3 118 select PCI_SYSCALL if PCI 119 select PERF_USE_VMALLOC 120 select RTC_LIB 121 select SYS_SUPPORTS_APM_EMULATION 122 # Above selects are sorted alphabetically; please add new ones 123 # according to that. Thanks. 124 help 125 The ARM series is a line of low-power-consumption RISC chip designs 126 licensed by ARM Ltd and targeted at embedded applications and 127 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 128 manufactured, but legacy ARM-based PC hardware remains popular in 129 Europe. There is an ARM Linux project with a web page at 130 <http://www.arm.linux.org.uk/>. 131 132config ARM_HAS_SG_CHAIN 133 bool 134 135config ARM_DMA_USE_IOMMU 136 bool 137 select ARM_HAS_SG_CHAIN 138 select NEED_SG_DMA_LENGTH 139 140if ARM_DMA_USE_IOMMU 141 142config ARM_DMA_IOMMU_ALIGNMENT 143 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 144 range 4 9 145 default 8 146 help 147 DMA mapping framework by default aligns all buffers to the smallest 148 PAGE_SIZE order which is greater than or equal to the requested buffer 149 size. This works well for buffers up to a few hundreds kilobytes, but 150 for larger buffers it just a waste of address space. Drivers which has 151 relatively small addressing window (like 64Mib) might run out of 152 virtual space with just a few allocations. 153 154 With this parameter you can specify the maximum PAGE_SIZE order for 155 DMA IOMMU buffers. Larger buffers will be aligned only to this 156 specified order. The order is expressed as a power of two multiplied 157 by the PAGE_SIZE. 158 159endif 160 161config SYS_SUPPORTS_APM_EMULATION 162 bool 163 164config HAVE_TCM 165 bool 166 select GENERIC_ALLOCATOR 167 168config HAVE_PROC_CPU 169 bool 170 171config NO_IOPORT_MAP 172 bool 173 174config SBUS 175 bool 176 177config STACKTRACE_SUPPORT 178 bool 179 default y 180 181config LOCKDEP_SUPPORT 182 bool 183 default y 184 185config TRACE_IRQFLAGS_SUPPORT 186 bool 187 default !CPU_V7M 188 189config ARCH_HAS_ILOG2_U32 190 bool 191 192config ARCH_HAS_ILOG2_U64 193 bool 194 195config ARCH_HAS_BANDGAP 196 bool 197 198config FIX_EARLYCON_MEM 199 def_bool y if MMU 200 201config GENERIC_HWEIGHT 202 bool 203 default y 204 205config GENERIC_CALIBRATE_DELAY 206 bool 207 default y 208 209config ARCH_MAY_HAVE_PC_FDC 210 bool 211 212config ZONE_DMA 213 bool 214 215config ARCH_SUPPORTS_UPROBES 216 def_bool y 217 218config ARCH_HAS_DMA_SET_COHERENT_MASK 219 bool 220 221config GENERIC_ISA_DMA 222 bool 223 224config FIQ 225 bool 226 227config NEED_RET_TO_USER 228 bool 229 230config ARCH_MTD_XIP 231 bool 232 233config ARM_PATCH_PHYS_VIRT 234 bool "Patch physical to virtual translations at runtime" if EMBEDDED 235 default y 236 depends on !XIP_KERNEL && MMU 237 help 238 Patch phys-to-virt and virt-to-phys translation functions at 239 boot and module load time according to the position of the 240 kernel in system memory. 241 242 This can only be used with non-XIP MMU kernels where the base 243 of physical memory is at a 16MB boundary. 244 245 Only disable this option if you know that you do not require 246 this feature (eg, building a kernel for a single machine) and 247 you need to shrink the kernel to the minimal size. 248 249config NEED_MACH_IO_H 250 bool 251 help 252 Select this when mach/io.h is required to provide special 253 definitions for this platform. The need for mach/io.h should 254 be avoided when possible. 255 256config NEED_MACH_MEMORY_H 257 bool 258 help 259 Select this when mach/memory.h is required to provide special 260 definitions for this platform. The need for mach/memory.h should 261 be avoided when possible. 262 263config PHYS_OFFSET 264 hex "Physical address of main memory" if MMU 265 depends on !ARM_PATCH_PHYS_VIRT 266 default DRAM_BASE if !MMU 267 default 0x00000000 if ARCH_EBSA110 || \ 268 ARCH_FOOTBRIDGE || \ 269 ARCH_INTEGRATOR || \ 270 ARCH_REALVIEW 271 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 272 default 0x20000000 if ARCH_S5PV210 273 default 0xc0000000 if ARCH_SA1100 274 help 275 Please provide the physical address corresponding to the 276 location of main memory in your system. 277 278config GENERIC_BUG 279 def_bool y 280 depends on BUG 281 282config PGTABLE_LEVELS 283 int 284 default 3 if ARM_LPAE 285 default 2 286 287menu "System Type" 288 289config MMU 290 bool "MMU-based Paged Memory Management Support" 291 default y 292 help 293 Select if you want MMU-based virtualised addressing space 294 support by paged memory management. If unsure, say 'Y'. 295 296config ARCH_MMAP_RND_BITS_MIN 297 default 8 298 299config ARCH_MMAP_RND_BITS_MAX 300 default 14 if PAGE_OFFSET=0x40000000 301 default 15 if PAGE_OFFSET=0x80000000 302 default 16 303 304# 305# The "ARM system type" choice list is ordered alphabetically by option 306# text. Please add new entries in the option alphabetic order. 307# 308choice 309 prompt "ARM system type" 310 default ARM_SINGLE_ARMV7M if !MMU 311 default ARCH_MULTIPLATFORM if MMU 312 313config ARCH_MULTIPLATFORM 314 bool "Allow multiple platforms to be selected" 315 depends on MMU 316 select ARCH_FLATMEM_ENABLE 317 select ARCH_SPARSEMEM_ENABLE 318 select ARCH_SELECT_MEMORY_MODEL 319 select ARM_HAS_SG_CHAIN 320 select ARM_PATCH_PHYS_VIRT 321 select AUTO_ZRELADDR 322 select TIMER_OF 323 select COMMON_CLK 324 select GENERIC_CLOCKEVENTS 325 select GENERIC_IRQ_MULTI_HANDLER 326 select HAVE_PCI 327 select PCI_DOMAINS_GENERIC if PCI 328 select SPARSE_IRQ 329 select USE_OF 330 331config ARM_SINGLE_ARMV7M 332 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 333 depends on !MMU 334 select ARM_NVIC 335 select AUTO_ZRELADDR 336 select TIMER_OF 337 select COMMON_CLK 338 select CPU_V7M 339 select GENERIC_CLOCKEVENTS 340 select NO_IOPORT_MAP 341 select SPARSE_IRQ 342 select USE_OF 343 344config ARCH_EBSA110 345 bool "EBSA-110" 346 select ARCH_USES_GETTIMEOFFSET 347 select CPU_SA110 348 select ISA 349 select NEED_MACH_IO_H 350 select NEED_MACH_MEMORY_H 351 select NO_IOPORT_MAP 352 help 353 This is an evaluation board for the StrongARM processor available 354 from Digital. It has limited hardware on-board, including an 355 Ethernet interface, two PCMCIA sockets, two serial ports and a 356 parallel port. 357 358config ARCH_EP93XX 359 bool "EP93xx-based" 360 select ARCH_SPARSEMEM_ENABLE 361 select ARM_AMBA 362 imply ARM_PATCH_PHYS_VIRT 363 select ARM_VIC 364 select AUTO_ZRELADDR 365 select CLKDEV_LOOKUP 366 select CLKSRC_MMIO 367 select CPU_ARM920T 368 select GENERIC_CLOCKEVENTS 369 select GPIOLIB 370 select HAVE_LEGACY_CLK 371 help 372 This enables support for the Cirrus EP93xx series of CPUs. 373 374config ARCH_FOOTBRIDGE 375 bool "FootBridge" 376 select CPU_SA110 377 select FOOTBRIDGE 378 select GENERIC_CLOCKEVENTS 379 select HAVE_IDE 380 select NEED_MACH_IO_H if !MMU 381 select NEED_MACH_MEMORY_H 382 help 383 Support for systems based on the DC21285 companion chip 384 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 385 386config ARCH_IOP32X 387 bool "IOP32x-based" 388 depends on MMU 389 select CPU_XSCALE 390 select GPIO_IOP 391 select GPIOLIB 392 select NEED_RET_TO_USER 393 select FORCE_PCI 394 select PLAT_IOP 395 help 396 Support for Intel's 80219 and IOP32X (XScale) family of 397 processors. 398 399config ARCH_IXP4XX 400 bool "IXP4xx-based" 401 depends on MMU 402 select ARCH_HAS_DMA_SET_COHERENT_MASK 403 select ARCH_SUPPORTS_BIG_ENDIAN 404 select CPU_XSCALE 405 select DMABOUNCE if PCI 406 select GENERIC_CLOCKEVENTS 407 select GENERIC_IRQ_MULTI_HANDLER 408 select GPIO_IXP4XX 409 select GPIOLIB 410 select HAVE_PCI 411 select IXP4XX_IRQ 412 select IXP4XX_TIMER 413 select NEED_MACH_IO_H 414 select USB_EHCI_BIG_ENDIAN_DESC 415 select USB_EHCI_BIG_ENDIAN_MMIO 416 help 417 Support for Intel's IXP4XX (XScale) family of processors. 418 419config ARCH_DOVE 420 bool "Marvell Dove" 421 select CPU_PJ4 422 select GENERIC_CLOCKEVENTS 423 select GENERIC_IRQ_MULTI_HANDLER 424 select GPIOLIB 425 select HAVE_PCI 426 select MVEBU_MBUS 427 select PINCTRL 428 select PINCTRL_DOVE 429 select PLAT_ORION_LEGACY 430 select SPARSE_IRQ 431 select PM_GENERIC_DOMAINS if PM 432 help 433 Support for the Marvell Dove SoC 88AP510 434 435config ARCH_PXA 436 bool "PXA2xx/PXA3xx-based" 437 depends on MMU 438 select ARCH_MTD_XIP 439 select ARM_CPU_SUSPEND if PM 440 select AUTO_ZRELADDR 441 select COMMON_CLK 442 select CLKSRC_PXA 443 select CLKSRC_MMIO 444 select TIMER_OF 445 select CPU_XSCALE if !CPU_XSC3 446 select GENERIC_CLOCKEVENTS 447 select GENERIC_IRQ_MULTI_HANDLER 448 select GPIO_PXA 449 select GPIOLIB 450 select HAVE_IDE 451 select IRQ_DOMAIN 452 select PLAT_PXA 453 select SPARSE_IRQ 454 help 455 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 456 457config ARCH_RPC 458 bool "RiscPC" 459 depends on MMU 460 select ARCH_ACORN 461 select ARCH_MAY_HAVE_PC_FDC 462 select ARCH_SPARSEMEM_ENABLE 463 select ARM_HAS_SG_CHAIN 464 select CPU_SA110 465 select FIQ 466 select HAVE_IDE 467 select HAVE_PATA_PLATFORM 468 select ISA_DMA_API 469 select NEED_MACH_IO_H 470 select NEED_MACH_MEMORY_H 471 select NO_IOPORT_MAP 472 help 473 On the Acorn Risc-PC, Linux can support the internal IDE disk and 474 CD-ROM interface, serial and parallel port, and the floppy drive. 475 476config ARCH_SA1100 477 bool "SA1100-based" 478 select ARCH_MTD_XIP 479 select ARCH_SPARSEMEM_ENABLE 480 select CLKSRC_MMIO 481 select CLKSRC_PXA 482 select TIMER_OF if OF 483 select COMMON_CLK 484 select CPU_FREQ 485 select CPU_SA1100 486 select GENERIC_CLOCKEVENTS 487 select GENERIC_IRQ_MULTI_HANDLER 488 select GPIOLIB 489 select HAVE_IDE 490 select IRQ_DOMAIN 491 select ISA 492 select NEED_MACH_MEMORY_H 493 select SPARSE_IRQ 494 help 495 Support for StrongARM 11x0 based boards. 496 497config ARCH_S3C24XX 498 bool "Samsung S3C24XX SoCs" 499 select ATAGS 500 select CLKSRC_SAMSUNG_PWM 501 select GENERIC_CLOCKEVENTS 502 select GPIO_SAMSUNG 503 select GPIOLIB 504 select GENERIC_IRQ_MULTI_HANDLER 505 select HAVE_S3C2410_I2C if I2C 506 select HAVE_S3C2410_WATCHDOG if WATCHDOG 507 select HAVE_S3C_RTC if RTC_CLASS 508 select NEED_MACH_IO_H 509 select SAMSUNG_ATAGS 510 select USE_OF 511 help 512 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 513 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 514 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 515 Samsung SMDK2410 development board (and derivatives). 516 517config ARCH_OMAP1 518 bool "TI OMAP1" 519 depends on MMU 520 select ARCH_HAS_HOLES_MEMORYMODEL 521 select ARCH_OMAP 522 select CLKDEV_LOOKUP 523 select CLKSRC_MMIO 524 select GENERIC_CLOCKEVENTS 525 select GENERIC_IRQ_CHIP 526 select GENERIC_IRQ_MULTI_HANDLER 527 select GPIOLIB 528 select HAVE_IDE 529 select HAVE_LEGACY_CLK 530 select IRQ_DOMAIN 531 select NEED_MACH_IO_H if PCCARD 532 select NEED_MACH_MEMORY_H 533 select SPARSE_IRQ 534 help 535 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 536 537endchoice 538 539menu "Multiple platform selection" 540 depends on ARCH_MULTIPLATFORM 541 542comment "CPU Core family selection" 543 544config ARCH_MULTI_V4 545 bool "ARMv4 based platforms (FA526)" 546 depends on !ARCH_MULTI_V6_V7 547 select ARCH_MULTI_V4_V5 548 select CPU_FA526 549 550config ARCH_MULTI_V4T 551 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 552 depends on !ARCH_MULTI_V6_V7 553 select ARCH_MULTI_V4_V5 554 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 555 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 556 CPU_ARM925T || CPU_ARM940T) 557 558config ARCH_MULTI_V5 559 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 560 depends on !ARCH_MULTI_V6_V7 561 select ARCH_MULTI_V4_V5 562 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 563 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 564 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 565 566config ARCH_MULTI_V4_V5 567 bool 568 569config ARCH_MULTI_V6 570 bool "ARMv6 based platforms (ARM11)" 571 select ARCH_MULTI_V6_V7 572 select CPU_V6K 573 574config ARCH_MULTI_V7 575 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 576 default y 577 select ARCH_MULTI_V6_V7 578 select CPU_V7 579 select HAVE_SMP 580 581config ARCH_MULTI_V6_V7 582 bool 583 select MIGHT_HAVE_CACHE_L2X0 584 585config ARCH_MULTI_CPU_AUTO 586 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 587 select ARCH_MULTI_V5 588 589endmenu 590 591config ARCH_VIRT 592 bool "Dummy Virtual Machine" 593 depends on ARCH_MULTI_V7 594 select ARM_AMBA 595 select ARM_GIC 596 select ARM_GIC_V2M if PCI 597 select ARM_GIC_V3 598 select ARM_GIC_V3_ITS if PCI 599 select ARM_PSCI 600 select HAVE_ARM_ARCH_TIMER 601 select ARCH_SUPPORTS_BIG_ENDIAN 602 603# 604# This is sorted alphabetically by mach-* pathname. However, plat-* 605# Kconfigs may be included either alphabetically (according to the 606# plat- suffix) or along side the corresponding mach-* source. 607# 608source "arch/arm/mach-actions/Kconfig" 609 610source "arch/arm/mach-alpine/Kconfig" 611 612source "arch/arm/mach-artpec/Kconfig" 613 614source "arch/arm/mach-asm9260/Kconfig" 615 616source "arch/arm/mach-aspeed/Kconfig" 617 618source "arch/arm/mach-at91/Kconfig" 619 620source "arch/arm/mach-axxia/Kconfig" 621 622source "arch/arm/mach-bcm/Kconfig" 623 624source "arch/arm/mach-berlin/Kconfig" 625 626source "arch/arm/mach-clps711x/Kconfig" 627 628source "arch/arm/mach-cns3xxx/Kconfig" 629 630source "arch/arm/mach-davinci/Kconfig" 631 632source "arch/arm/mach-digicolor/Kconfig" 633 634source "arch/arm/mach-dove/Kconfig" 635 636source "arch/arm/mach-ep93xx/Kconfig" 637 638source "arch/arm/mach-exynos/Kconfig" 639source "arch/arm/plat-samsung/Kconfig" 640 641source "arch/arm/mach-footbridge/Kconfig" 642 643source "arch/arm/mach-gemini/Kconfig" 644 645source "arch/arm/mach-highbank/Kconfig" 646 647source "arch/arm/mach-hisi/Kconfig" 648 649source "arch/arm/mach-imx/Kconfig" 650 651source "arch/arm/mach-integrator/Kconfig" 652 653source "arch/arm/mach-iop32x/Kconfig" 654 655source "arch/arm/mach-ixp4xx/Kconfig" 656 657source "arch/arm/mach-keystone/Kconfig" 658 659source "arch/arm/mach-lpc32xx/Kconfig" 660 661source "arch/arm/mach-mediatek/Kconfig" 662 663source "arch/arm/mach-meson/Kconfig" 664 665source "arch/arm/mach-milbeaut/Kconfig" 666 667source "arch/arm/mach-mmp/Kconfig" 668 669source "arch/arm/mach-moxart/Kconfig" 670 671source "arch/arm/mach-mstar/Kconfig" 672 673source "arch/arm/mach-mv78xx0/Kconfig" 674 675source "arch/arm/mach-mvebu/Kconfig" 676 677source "arch/arm/mach-mxs/Kconfig" 678 679source "arch/arm/mach-nomadik/Kconfig" 680 681source "arch/arm/mach-npcm/Kconfig" 682 683source "arch/arm/mach-nspire/Kconfig" 684 685source "arch/arm/plat-omap/Kconfig" 686 687source "arch/arm/mach-omap1/Kconfig" 688 689source "arch/arm/mach-omap2/Kconfig" 690 691source "arch/arm/mach-orion5x/Kconfig" 692 693source "arch/arm/mach-oxnas/Kconfig" 694 695source "arch/arm/mach-picoxcell/Kconfig" 696 697source "arch/arm/mach-prima2/Kconfig" 698 699source "arch/arm/mach-pxa/Kconfig" 700source "arch/arm/plat-pxa/Kconfig" 701 702source "arch/arm/mach-qcom/Kconfig" 703 704source "arch/arm/mach-rda/Kconfig" 705 706source "arch/arm/mach-realtek/Kconfig" 707 708source "arch/arm/mach-realview/Kconfig" 709 710source "arch/arm/mach-rockchip/Kconfig" 711 712source "arch/arm/mach-s3c24xx/Kconfig" 713 714source "arch/arm/mach-s3c64xx/Kconfig" 715 716source "arch/arm/mach-s5pv210/Kconfig" 717 718source "arch/arm/mach-sa1100/Kconfig" 719 720source "arch/arm/mach-shmobile/Kconfig" 721 722source "arch/arm/mach-socfpga/Kconfig" 723 724source "arch/arm/mach-spear/Kconfig" 725 726source "arch/arm/mach-sti/Kconfig" 727 728source "arch/arm/mach-stm32/Kconfig" 729 730source "arch/arm/mach-sunxi/Kconfig" 731 732source "arch/arm/mach-tango/Kconfig" 733 734source "arch/arm/mach-tegra/Kconfig" 735 736source "arch/arm/mach-u300/Kconfig" 737 738source "arch/arm/mach-uniphier/Kconfig" 739 740source "arch/arm/mach-ux500/Kconfig" 741 742source "arch/arm/mach-versatile/Kconfig" 743 744source "arch/arm/mach-vexpress/Kconfig" 745 746source "arch/arm/mach-vt8500/Kconfig" 747 748source "arch/arm/mach-zx/Kconfig" 749 750source "arch/arm/mach-zynq/Kconfig" 751 752# ARMv7-M architecture 753config ARCH_EFM32 754 bool "Energy Micro efm32" 755 depends on ARM_SINGLE_ARMV7M 756 select GPIOLIB 757 help 758 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 759 processors. 760 761config ARCH_LPC18XX 762 bool "NXP LPC18xx/LPC43xx" 763 depends on ARM_SINGLE_ARMV7M 764 select ARCH_HAS_RESET_CONTROLLER 765 select ARM_AMBA 766 select CLKSRC_LPC32XX 767 select PINCTRL 768 help 769 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 770 high performance microcontrollers. 771 772config ARCH_MPS2 773 bool "ARM MPS2 platform" 774 depends on ARM_SINGLE_ARMV7M 775 select ARM_AMBA 776 select CLKSRC_MPS2 777 help 778 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 779 with a range of available cores like Cortex-M3/M4/M7. 780 781 Please, note that depends which Application Note is used memory map 782 for the platform may vary, so adjustment of RAM base might be needed. 783 784# Definitions to make life easier 785config ARCH_ACORN 786 bool 787 788config PLAT_IOP 789 bool 790 select GENERIC_CLOCKEVENTS 791 792config PLAT_ORION 793 bool 794 select CLKSRC_MMIO 795 select COMMON_CLK 796 select GENERIC_IRQ_CHIP 797 select IRQ_DOMAIN 798 799config PLAT_ORION_LEGACY 800 bool 801 select PLAT_ORION 802 803config PLAT_PXA 804 bool 805 806config PLAT_VERSATILE 807 bool 808 809source "arch/arm/mm/Kconfig" 810 811config IWMMXT 812 bool "Enable iWMMXt support" 813 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 814 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 815 help 816 Enable support for iWMMXt context switching at run time if 817 running on a CPU that supports it. 818 819if !MMU 820source "arch/arm/Kconfig-nommu" 821endif 822 823config PJ4B_ERRATA_4742 824 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 825 depends on CPU_PJ4B && MACH_ARMADA_370 826 default y 827 help 828 When coming out of either a Wait for Interrupt (WFI) or a Wait for 829 Event (WFE) IDLE states, a specific timing sensitivity exists between 830 the retiring WFI/WFE instructions and the newly issued subsequent 831 instructions. This sensitivity can result in a CPU hang scenario. 832 Workaround: 833 The software must insert either a Data Synchronization Barrier (DSB) 834 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 835 instruction 836 837config ARM_ERRATA_326103 838 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 839 depends on CPU_V6 840 help 841 Executing a SWP instruction to read-only memory does not set bit 11 842 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 843 treat the access as a read, preventing a COW from occurring and 844 causing the faulting task to livelock. 845 846config ARM_ERRATA_411920 847 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 848 depends on CPU_V6 || CPU_V6K 849 help 850 Invalidation of the Instruction Cache operation can 851 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 852 It does not affect the MPCore. This option enables the ARM Ltd. 853 recommended workaround. 854 855config ARM_ERRATA_430973 856 bool "ARM errata: Stale prediction on replaced interworking branch" 857 depends on CPU_V7 858 help 859 This option enables the workaround for the 430973 Cortex-A8 860 r1p* erratum. If a code sequence containing an ARM/Thumb 861 interworking branch is replaced with another code sequence at the 862 same virtual address, whether due to self-modifying code or virtual 863 to physical address re-mapping, Cortex-A8 does not recover from the 864 stale interworking branch prediction. This results in Cortex-A8 865 executing the new code sequence in the incorrect ARM or Thumb state. 866 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 867 and also flushes the branch target cache at every context switch. 868 Note that setting specific bits in the ACTLR register may not be 869 available in non-secure mode. 870 871config ARM_ERRATA_458693 872 bool "ARM errata: Processor deadlock when a false hazard is created" 873 depends on CPU_V7 874 depends on !ARCH_MULTIPLATFORM 875 help 876 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 877 erratum. For very specific sequences of memory operations, it is 878 possible for a hazard condition intended for a cache line to instead 879 be incorrectly associated with a different cache line. This false 880 hazard might then cause a processor deadlock. The workaround enables 881 the L1 caching of the NEON accesses and disables the PLD instruction 882 in the ACTLR register. Note that setting specific bits in the ACTLR 883 register may not be available in non-secure mode. 884 885config ARM_ERRATA_460075 886 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 887 depends on CPU_V7 888 depends on !ARCH_MULTIPLATFORM 889 help 890 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 891 erratum. Any asynchronous access to the L2 cache may encounter a 892 situation in which recent store transactions to the L2 cache are lost 893 and overwritten with stale memory contents from external memory. The 894 workaround disables the write-allocate mode for the L2 cache via the 895 ACTLR register. Note that setting specific bits in the ACTLR register 896 may not be available in non-secure mode. 897 898config ARM_ERRATA_742230 899 bool "ARM errata: DMB operation may be faulty" 900 depends on CPU_V7 && SMP 901 depends on !ARCH_MULTIPLATFORM 902 help 903 This option enables the workaround for the 742230 Cortex-A9 904 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 905 between two write operations may not ensure the correct visibility 906 ordering of the two writes. This workaround sets a specific bit in 907 the diagnostic register of the Cortex-A9 which causes the DMB 908 instruction to behave as a DSB, ensuring the correct behaviour of 909 the two writes. 910 911config ARM_ERRATA_742231 912 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 913 depends on CPU_V7 && SMP 914 depends on !ARCH_MULTIPLATFORM 915 help 916 This option enables the workaround for the 742231 Cortex-A9 917 (r2p0..r2p2) erratum. Under certain conditions, specific to the 918 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 919 accessing some data located in the same cache line, may get corrupted 920 data due to bad handling of the address hazard when the line gets 921 replaced from one of the CPUs at the same time as another CPU is 922 accessing it. This workaround sets specific bits in the diagnostic 923 register of the Cortex-A9 which reduces the linefill issuing 924 capabilities of the processor. 925 926config ARM_ERRATA_643719 927 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 928 depends on CPU_V7 && SMP 929 default y 930 help 931 This option enables the workaround for the 643719 Cortex-A9 (prior to 932 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 933 register returns zero when it should return one. The workaround 934 corrects this value, ensuring cache maintenance operations which use 935 it behave as intended and avoiding data corruption. 936 937config ARM_ERRATA_720789 938 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 939 depends on CPU_V7 940 help 941 This option enables the workaround for the 720789 Cortex-A9 (prior to 942 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 943 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 944 As a consequence of this erratum, some TLB entries which should be 945 invalidated are not, resulting in an incoherency in the system page 946 tables. The workaround changes the TLB flushing routines to invalidate 947 entries regardless of the ASID. 948 949config ARM_ERRATA_743622 950 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 951 depends on CPU_V7 952 depends on !ARCH_MULTIPLATFORM 953 help 954 This option enables the workaround for the 743622 Cortex-A9 955 (r2p*) erratum. Under very rare conditions, a faulty 956 optimisation in the Cortex-A9 Store Buffer may lead to data 957 corruption. This workaround sets a specific bit in the diagnostic 958 register of the Cortex-A9 which disables the Store Buffer 959 optimisation, preventing the defect from occurring. This has no 960 visible impact on the overall performance or power consumption of the 961 processor. 962 963config ARM_ERRATA_751472 964 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 965 depends on CPU_V7 966 depends on !ARCH_MULTIPLATFORM 967 help 968 This option enables the workaround for the 751472 Cortex-A9 (prior 969 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 970 completion of a following broadcasted operation if the second 971 operation is received by a CPU before the ICIALLUIS has completed, 972 potentially leading to corrupted entries in the cache or TLB. 973 974config ARM_ERRATA_754322 975 bool "ARM errata: possible faulty MMU translations following an ASID switch" 976 depends on CPU_V7 977 help 978 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 979 r3p*) erratum. A speculative memory access may cause a page table walk 980 which starts prior to an ASID switch but completes afterwards. This 981 can populate the micro-TLB with a stale entry which may be hit with 982 the new ASID. This workaround places two dsb instructions in the mm 983 switching code so that no page table walks can cross the ASID switch. 984 985config ARM_ERRATA_754327 986 bool "ARM errata: no automatic Store Buffer drain" 987 depends on CPU_V7 && SMP 988 help 989 This option enables the workaround for the 754327 Cortex-A9 (prior to 990 r2p0) erratum. The Store Buffer does not have any automatic draining 991 mechanism and therefore a livelock may occur if an external agent 992 continuously polls a memory location waiting to observe an update. 993 This workaround defines cpu_relax() as smp_mb(), preventing correctly 994 written polling loops from denying visibility of updates to memory. 995 996config ARM_ERRATA_364296 997 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 998 depends on CPU_V6 999 help 1000 This options enables the workaround for the 364296 ARM1136 1001 r0p2 erratum (possible cache data corruption with 1002 hit-under-miss enabled). It sets the undocumented bit 31 in 1003 the auxiliary control register and the FI bit in the control 1004 register, thus disabling hit-under-miss without putting the 1005 processor into full low interrupt latency mode. ARM11MPCore 1006 is not affected. 1007 1008config ARM_ERRATA_764369 1009 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1010 depends on CPU_V7 && SMP 1011 help 1012 This option enables the workaround for erratum 764369 1013 affecting Cortex-A9 MPCore with two or more processors (all 1014 current revisions). Under certain timing circumstances, a data 1015 cache line maintenance operation by MVA targeting an Inner 1016 Shareable memory region may fail to proceed up to either the 1017 Point of Coherency or to the Point of Unification of the 1018 system. This workaround adds a DSB instruction before the 1019 relevant cache maintenance functions and sets a specific bit 1020 in the diagnostic control register of the SCU. 1021 1022config ARM_ERRATA_775420 1023 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1024 depends on CPU_V7 1025 help 1026 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1027 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1028 operation aborts with MMU exception, it might cause the processor 1029 to deadlock. This workaround puts DSB before executing ISB if 1030 an abort may occur on cache maintenance. 1031 1032config ARM_ERRATA_798181 1033 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1034 depends on CPU_V7 && SMP 1035 help 1036 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1037 adequately shooting down all use of the old entries. This 1038 option enables the Linux kernel workaround for this erratum 1039 which sends an IPI to the CPUs that are running the same ASID 1040 as the one being invalidated. 1041 1042config ARM_ERRATA_773022 1043 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1044 depends on CPU_V7 1045 help 1046 This option enables the workaround for the 773022 Cortex-A15 1047 (up to r0p4) erratum. In certain rare sequences of code, the 1048 loop buffer may deliver incorrect instructions. This 1049 workaround disables the loop buffer to avoid the erratum. 1050 1051config ARM_ERRATA_818325_852422 1052 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1053 depends on CPU_V7 1054 help 1055 This option enables the workaround for: 1056 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1057 instruction might deadlock. Fixed in r0p1. 1058 - Cortex-A12 852422: Execution of a sequence of instructions might 1059 lead to either a data corruption or a CPU deadlock. Not fixed in 1060 any Cortex-A12 cores yet. 1061 This workaround for all both errata involves setting bit[12] of the 1062 Feature Register. This bit disables an optimisation applied to a 1063 sequence of 2 instructions that use opposing condition codes. 1064 1065config ARM_ERRATA_821420 1066 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1067 depends on CPU_V7 1068 help 1069 This option enables the workaround for the 821420 Cortex-A12 1070 (all revs) erratum. In very rare timing conditions, a sequence 1071 of VMOV to Core registers instructions, for which the second 1072 one is in the shadow of a branch or abort, can lead to a 1073 deadlock when the VMOV instructions are issued out-of-order. 1074 1075config ARM_ERRATA_825619 1076 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1077 depends on CPU_V7 1078 help 1079 This option enables the workaround for the 825619 Cortex-A12 1080 (all revs) erratum. Within rare timing constraints, executing a 1081 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1082 and Device/Strongly-Ordered loads and stores might cause deadlock 1083 1084config ARM_ERRATA_857271 1085 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1086 depends on CPU_V7 1087 help 1088 This option enables the workaround for the 857271 Cortex-A12 1089 (all revs) erratum. Under very rare timing conditions, the CPU might 1090 hang. The workaround is expected to have a < 1% performance impact. 1091 1092config ARM_ERRATA_852421 1093 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1094 depends on CPU_V7 1095 help 1096 This option enables the workaround for the 852421 Cortex-A17 1097 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1098 execution of a DMB ST instruction might fail to properly order 1099 stores from GroupA and stores from GroupB. 1100 1101config ARM_ERRATA_852423 1102 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1103 depends on CPU_V7 1104 help 1105 This option enables the workaround for: 1106 - Cortex-A17 852423: Execution of a sequence of instructions might 1107 lead to either a data corruption or a CPU deadlock. Not fixed in 1108 any Cortex-A17 cores yet. 1109 This is identical to Cortex-A12 erratum 852422. It is a separate 1110 config option from the A12 erratum due to the way errata are checked 1111 for and handled. 1112 1113config ARM_ERRATA_857272 1114 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1115 depends on CPU_V7 1116 help 1117 This option enables the workaround for the 857272 Cortex-A17 erratum. 1118 This erratum is not known to be fixed in any A17 revision. 1119 This is identical to Cortex-A12 erratum 857271. It is a separate 1120 config option from the A12 erratum due to the way errata are checked 1121 for and handled. 1122 1123endmenu 1124 1125source "arch/arm/common/Kconfig" 1126 1127menu "Bus support" 1128 1129config ISA 1130 bool 1131 help 1132 Find out whether you have ISA slots on your motherboard. ISA is the 1133 name of a bus system, i.e. the way the CPU talks to the other stuff 1134 inside your box. Other bus systems are PCI, EISA, MicroChannel 1135 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1136 newer boards don't support it. If you have ISA, say Y, otherwise N. 1137 1138# Select ISA DMA controller support 1139config ISA_DMA 1140 bool 1141 select ISA_DMA_API 1142 1143# Select ISA DMA interface 1144config ISA_DMA_API 1145 bool 1146 1147config PCI_NANOENGINE 1148 bool "BSE nanoEngine PCI support" 1149 depends on SA1100_NANOENGINE 1150 help 1151 Enable PCI on the BSE nanoEngine board. 1152 1153config ARM_ERRATA_814220 1154 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1155 depends on CPU_V7 1156 help 1157 The v7 ARM states that all cache and branch predictor maintenance 1158 operations that do not specify an address execute, relative to 1159 each other, in program order. 1160 However, because of this erratum, an L2 set/way cache maintenance 1161 operation can overtake an L1 set/way cache maintenance operation. 1162 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1163 r0p4, r0p5. 1164 1165endmenu 1166 1167menu "Kernel Features" 1168 1169config HAVE_SMP 1170 bool 1171 help 1172 This option should be selected by machines which have an SMP- 1173 capable CPU. 1174 1175 The only effect of this option is to make the SMP-related 1176 options available to the user for configuration. 1177 1178config SMP 1179 bool "Symmetric Multi-Processing" 1180 depends on CPU_V6K || CPU_V7 1181 depends on GENERIC_CLOCKEVENTS 1182 depends on HAVE_SMP 1183 depends on MMU || ARM_MPU 1184 select IRQ_WORK 1185 help 1186 This enables support for systems with more than one CPU. If you have 1187 a system with only one CPU, say N. If you have a system with more 1188 than one CPU, say Y. 1189 1190 If you say N here, the kernel will run on uni- and multiprocessor 1191 machines, but will use only one CPU of a multiprocessor machine. If 1192 you say Y here, the kernel will run on many, but not all, 1193 uniprocessor machines. On a uniprocessor machine, the kernel 1194 will run faster if you say N here. 1195 1196 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1197 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1198 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1199 1200 If you don't know what to do here, say N. 1201 1202config SMP_ON_UP 1203 bool "Allow booting SMP kernel on uniprocessor systems" 1204 depends on SMP && !XIP_KERNEL && MMU 1205 default y 1206 help 1207 SMP kernels contain instructions which fail on non-SMP processors. 1208 Enabling this option allows the kernel to modify itself to make 1209 these instructions safe. Disabling it allows about 1K of space 1210 savings. 1211 1212 If you don't know what to do here, say Y. 1213 1214config ARM_CPU_TOPOLOGY 1215 bool "Support cpu topology definition" 1216 depends on SMP && CPU_V7 1217 default y 1218 help 1219 Support ARM cpu topology definition. The MPIDR register defines 1220 affinity between processors which is then used to describe the cpu 1221 topology of an ARM System. 1222 1223config SCHED_MC 1224 bool "Multi-core scheduler support" 1225 depends on ARM_CPU_TOPOLOGY 1226 help 1227 Multi-core scheduler support improves the CPU scheduler's decision 1228 making when dealing with multi-core CPU chips at a cost of slightly 1229 increased overhead in some places. If unsure say N here. 1230 1231config SCHED_SMT 1232 bool "SMT scheduler support" 1233 depends on ARM_CPU_TOPOLOGY 1234 help 1235 Improves the CPU scheduler's decision making when dealing with 1236 MultiThreading at a cost of slightly increased overhead in some 1237 places. If unsure say N here. 1238 1239config HAVE_ARM_SCU 1240 bool 1241 help 1242 This option enables support for the ARM snoop control unit 1243 1244config HAVE_ARM_ARCH_TIMER 1245 bool "Architected timer support" 1246 depends on CPU_V7 1247 select ARM_ARCH_TIMER 1248 help 1249 This option enables support for the ARM architected timer 1250 1251config HAVE_ARM_TWD 1252 bool 1253 help 1254 This options enables support for the ARM timer and watchdog unit 1255 1256config MCPM 1257 bool "Multi-Cluster Power Management" 1258 depends on CPU_V7 && SMP 1259 help 1260 This option provides the common power management infrastructure 1261 for (multi-)cluster based systems, such as big.LITTLE based 1262 systems. 1263 1264config MCPM_QUAD_CLUSTER 1265 bool 1266 depends on MCPM 1267 help 1268 To avoid wasting resources unnecessarily, MCPM only supports up 1269 to 2 clusters by default. 1270 Platforms with 3 or 4 clusters that use MCPM must select this 1271 option to allow the additional clusters to be managed. 1272 1273config BIG_LITTLE 1274 bool "big.LITTLE support (Experimental)" 1275 depends on CPU_V7 && SMP 1276 select MCPM 1277 help 1278 This option enables support selections for the big.LITTLE 1279 system architecture. 1280 1281config BL_SWITCHER 1282 bool "big.LITTLE switcher support" 1283 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1284 select CPU_PM 1285 help 1286 The big.LITTLE "switcher" provides the core functionality to 1287 transparently handle transition between a cluster of A15's 1288 and a cluster of A7's in a big.LITTLE system. 1289 1290config BL_SWITCHER_DUMMY_IF 1291 tristate "Simple big.LITTLE switcher user interface" 1292 depends on BL_SWITCHER && DEBUG_KERNEL 1293 help 1294 This is a simple and dummy char dev interface to control 1295 the big.LITTLE switcher core code. It is meant for 1296 debugging purposes only. 1297 1298choice 1299 prompt "Memory split" 1300 depends on MMU 1301 default VMSPLIT_3G 1302 help 1303 Select the desired split between kernel and user memory. 1304 1305 If you are not absolutely sure what you are doing, leave this 1306 option alone! 1307 1308 config VMSPLIT_3G 1309 bool "3G/1G user/kernel split" 1310 config VMSPLIT_3G_OPT 1311 depends on !ARM_LPAE 1312 bool "3G/1G user/kernel split (for full 1G low memory)" 1313 config VMSPLIT_2G 1314 bool "2G/2G user/kernel split" 1315 config VMSPLIT_1G 1316 bool "1G/3G user/kernel split" 1317endchoice 1318 1319config PAGE_OFFSET 1320 hex 1321 default PHYS_OFFSET if !MMU 1322 default 0x40000000 if VMSPLIT_1G 1323 default 0x80000000 if VMSPLIT_2G 1324 default 0xB0000000 if VMSPLIT_3G_OPT 1325 default 0xC0000000 1326 1327config NR_CPUS 1328 int "Maximum number of CPUs (2-32)" 1329 range 2 32 1330 depends on SMP 1331 default "4" 1332 1333config HOTPLUG_CPU 1334 bool "Support for hot-pluggable CPUs" 1335 depends on SMP 1336 select GENERIC_IRQ_MIGRATION 1337 help 1338 Say Y here to experiment with turning CPUs off and on. CPUs 1339 can be controlled through /sys/devices/system/cpu. 1340 1341config ARM_PSCI 1342 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1343 depends on HAVE_ARM_SMCCC 1344 select ARM_PSCI_FW 1345 help 1346 Say Y here if you want Linux to communicate with system firmware 1347 implementing the PSCI specification for CPU-centric power 1348 management operations described in ARM document number ARM DEN 1349 0022A ("Power State Coordination Interface System Software on 1350 ARM processors"). 1351 1352# The GPIO number here must be sorted by descending number. In case of 1353# a multiplatform kernel, we just want the highest value required by the 1354# selected platforms. 1355config ARCH_NR_GPIO 1356 int 1357 default 2048 if ARCH_SOCFPGA 1358 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1359 ARCH_ZYNQ || ARCH_ASPEED 1360 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1361 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1362 default 416 if ARCH_SUNXI 1363 default 392 if ARCH_U8500 1364 default 352 if ARCH_VT8500 1365 default 288 if ARCH_ROCKCHIP 1366 default 264 if MACH_H4700 1367 default 0 1368 help 1369 Maximum number of GPIOs in the system. 1370 1371 If unsure, leave the default value. 1372 1373config HZ_FIXED 1374 int 1375 default 200 if ARCH_EBSA110 1376 default 128 if SOC_AT91RM9200 1377 default 0 1378 1379choice 1380 depends on HZ_FIXED = 0 1381 prompt "Timer frequency" 1382 1383config HZ_100 1384 bool "100 Hz" 1385 1386config HZ_200 1387 bool "200 Hz" 1388 1389config HZ_250 1390 bool "250 Hz" 1391 1392config HZ_300 1393 bool "300 Hz" 1394 1395config HZ_500 1396 bool "500 Hz" 1397 1398config HZ_1000 1399 bool "1000 Hz" 1400 1401endchoice 1402 1403config HZ 1404 int 1405 default HZ_FIXED if HZ_FIXED != 0 1406 default 100 if HZ_100 1407 default 200 if HZ_200 1408 default 250 if HZ_250 1409 default 300 if HZ_300 1410 default 500 if HZ_500 1411 default 1000 1412 1413config SCHED_HRTICK 1414 def_bool HIGH_RES_TIMERS 1415 1416config THUMB2_KERNEL 1417 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1418 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1419 default y if CPU_THUMBONLY 1420 select ARM_UNWIND 1421 help 1422 By enabling this option, the kernel will be compiled in 1423 Thumb-2 mode. 1424 1425 If unsure, say N. 1426 1427config ARM_PATCH_IDIV 1428 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1429 depends on CPU_32v7 && !XIP_KERNEL 1430 default y 1431 help 1432 The ARM compiler inserts calls to __aeabi_idiv() and 1433 __aeabi_uidiv() when it needs to perform division on signed 1434 and unsigned integers. Some v7 CPUs have support for the sdiv 1435 and udiv instructions that can be used to implement those 1436 functions. 1437 1438 Enabling this option allows the kernel to modify itself to 1439 replace the first two instructions of these library functions 1440 with the sdiv or udiv plus "bx lr" instructions when the CPU 1441 it is running on supports them. Typically this will be faster 1442 and less power intensive than running the original library 1443 code to do integer division. 1444 1445config AEABI 1446 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1447 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1448 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1449 help 1450 This option allows for the kernel to be compiled using the latest 1451 ARM ABI (aka EABI). This is only useful if you are using a user 1452 space environment that is also compiled with EABI. 1453 1454 Since there are major incompatibilities between the legacy ABI and 1455 EABI, especially with regard to structure member alignment, this 1456 option also changes the kernel syscall calling convention to 1457 disambiguate both ABIs and allow for backward compatibility support 1458 (selected with CONFIG_OABI_COMPAT). 1459 1460 To use this you need GCC version 4.0.0 or later. 1461 1462config OABI_COMPAT 1463 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1464 depends on AEABI && !THUMB2_KERNEL 1465 help 1466 This option preserves the old syscall interface along with the 1467 new (ARM EABI) one. It also provides a compatibility layer to 1468 intercept syscalls that have structure arguments which layout 1469 in memory differs between the legacy ABI and the new ARM EABI 1470 (only for non "thumb" binaries). This option adds a tiny 1471 overhead to all syscalls and produces a slightly larger kernel. 1472 1473 The seccomp filter system will not be available when this is 1474 selected, since there is no way yet to sensibly distinguish 1475 between calling conventions during filtering. 1476 1477 If you know you'll be using only pure EABI user space then you 1478 can say N here. If this option is not selected and you attempt 1479 to execute a legacy ABI binary then the result will be 1480 UNPREDICTABLE (in fact it can be predicted that it won't work 1481 at all). If in doubt say N. 1482 1483config ARCH_HAS_HOLES_MEMORYMODEL 1484 bool 1485 1486config ARCH_SELECT_MEMORY_MODEL 1487 bool 1488 1489config ARCH_FLATMEM_ENABLE 1490 bool 1491 1492config ARCH_SPARSEMEM_ENABLE 1493 bool 1494 select SPARSEMEM_STATIC if SPARSEMEM 1495 1496config HAVE_ARCH_PFN_VALID 1497 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1498 1499config HIGHMEM 1500 bool "High Memory Support" 1501 depends on MMU 1502 help 1503 The address space of ARM processors is only 4 Gigabytes large 1504 and it has to accommodate user address space, kernel address 1505 space as well as some memory mapped IO. That means that, if you 1506 have a large amount of physical memory and/or IO, not all of the 1507 memory can be "permanently mapped" by the kernel. The physical 1508 memory that is not permanently mapped is called "high memory". 1509 1510 Depending on the selected kernel/user memory split, minimum 1511 vmalloc space and actual amount of RAM, you may not need this 1512 option which should result in a slightly faster kernel. 1513 1514 If unsure, say n. 1515 1516config HIGHPTE 1517 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1518 depends on HIGHMEM 1519 default y 1520 help 1521 The VM uses one page of physical memory for each page table. 1522 For systems with a lot of processes, this can use a lot of 1523 precious low memory, eventually leading to low memory being 1524 consumed by page tables. Setting this option will allow 1525 user-space 2nd level page tables to reside in high memory. 1526 1527config CPU_SW_DOMAIN_PAN 1528 bool "Enable use of CPU domains to implement privileged no-access" 1529 depends on MMU && !ARM_LPAE 1530 default y 1531 help 1532 Increase kernel security by ensuring that normal kernel accesses 1533 are unable to access userspace addresses. This can help prevent 1534 use-after-free bugs becoming an exploitable privilege escalation 1535 by ensuring that magic values (such as LIST_POISON) will always 1536 fault when dereferenced. 1537 1538 CPUs with low-vector mappings use a best-efforts implementation. 1539 Their lower 1MB needs to remain accessible for the vectors, but 1540 the remainder of userspace will become appropriately inaccessible. 1541 1542config HW_PERF_EVENTS 1543 def_bool y 1544 depends on ARM_PMU 1545 1546config SYS_SUPPORTS_HUGETLBFS 1547 def_bool y 1548 depends on ARM_LPAE 1549 1550config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1551 def_bool y 1552 depends on ARM_LPAE 1553 1554config ARCH_WANT_GENERAL_HUGETLB 1555 def_bool y 1556 1557config ARM_MODULE_PLTS 1558 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1559 depends on MODULES 1560 default y 1561 help 1562 Allocate PLTs when loading modules so that jumps and calls whose 1563 targets are too far away for their relative offsets to be encoded 1564 in the instructions themselves can be bounced via veneers in the 1565 module's PLT. This allows modules to be allocated in the generic 1566 vmalloc area after the dedicated module memory area has been 1567 exhausted. The modules will use slightly more memory, but after 1568 rounding up to page size, the actual memory footprint is usually 1569 the same. 1570 1571 Disabling this is usually safe for small single-platform 1572 configurations. If unsure, say y. 1573 1574config FORCE_MAX_ZONEORDER 1575 int "Maximum zone order" 1576 default "12" if SOC_AM33XX 1577 default "9" if SA1111 || ARCH_EFM32 1578 default "11" 1579 help 1580 The kernel memory allocator divides physically contiguous memory 1581 blocks into "zones", where each zone is a power of two number of 1582 pages. This option selects the largest power of two that the kernel 1583 keeps in the memory allocator. If you need to allocate very large 1584 blocks of physically contiguous memory, then you may need to 1585 increase this value. 1586 1587 This config option is actually maximum order plus one. For example, 1588 a value of 11 means that the largest free memory block is 2^10 pages. 1589 1590config ALIGNMENT_TRAP 1591 bool 1592 depends on CPU_CP15_MMU 1593 default y if !ARCH_EBSA110 1594 select HAVE_PROC_CPU if PROC_FS 1595 help 1596 ARM processors cannot fetch/store information which is not 1597 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1598 address divisible by 4. On 32-bit ARM processors, these non-aligned 1599 fetch/store instructions will be emulated in software if you say 1600 here, which has a severe performance impact. This is necessary for 1601 correct operation of some network protocols. With an IP-only 1602 configuration it is safe to say N, otherwise say Y. 1603 1604config UACCESS_WITH_MEMCPY 1605 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1606 depends on MMU 1607 default y if CPU_FEROCEON 1608 help 1609 Implement faster copy_to_user and clear_user methods for CPU 1610 cores where a 8-word STM instruction give significantly higher 1611 memory write throughput than a sequence of individual 32bit stores. 1612 1613 A possible side effect is a slight increase in scheduling latency 1614 between threads sharing the same address space if they invoke 1615 such copy operations with large buffers. 1616 1617 However, if the CPU data cache is using a write-allocate mode, 1618 this option is unlikely to provide any performance gain. 1619 1620config SECCOMP 1621 bool 1622 prompt "Enable seccomp to safely compute untrusted bytecode" 1623 help 1624 This kernel feature is useful for number crunching applications 1625 that may need to compute untrusted bytecode during their 1626 execution. By using pipes or other transports made available to 1627 the process as file descriptors supporting the read/write 1628 syscalls, it's possible to isolate those applications in 1629 their own address space using seccomp. Once seccomp is 1630 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1631 and the task is only allowed to execute a few safe syscalls 1632 defined by each seccomp mode. 1633 1634config PARAVIRT 1635 bool "Enable paravirtualization code" 1636 help 1637 This changes the kernel so it can modify itself when it is run 1638 under a hypervisor, potentially improving performance significantly 1639 over full virtualization. 1640 1641config PARAVIRT_TIME_ACCOUNTING 1642 bool "Paravirtual steal time accounting" 1643 select PARAVIRT 1644 help 1645 Select this option to enable fine granularity task steal time 1646 accounting. Time spent executing other tasks in parallel with 1647 the current vCPU is discounted from the vCPU power. To account for 1648 that, there can be a small performance impact. 1649 1650 If in doubt, say N here. 1651 1652config XEN_DOM0 1653 def_bool y 1654 depends on XEN 1655 1656config XEN 1657 bool "Xen guest support on ARM" 1658 depends on ARM && AEABI && OF 1659 depends on CPU_V7 && !CPU_V6 1660 depends on !GENERIC_ATOMIC64 1661 depends on MMU 1662 select ARCH_DMA_ADDR_T_64BIT 1663 select ARM_PSCI 1664 select SWIOTLB 1665 select SWIOTLB_XEN 1666 select PARAVIRT 1667 help 1668 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1669 1670config STACKPROTECTOR_PER_TASK 1671 bool "Use a unique stack canary value for each task" 1672 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1673 select GCC_PLUGIN_ARM_SSP_PER_TASK 1674 default y 1675 help 1676 Due to the fact that GCC uses an ordinary symbol reference from 1677 which to load the value of the stack canary, this value can only 1678 change at reboot time on SMP systems, and all tasks running in the 1679 kernel's address space are forced to use the same canary value for 1680 the entire duration that the system is up. 1681 1682 Enable this option to switch to a different method that uses a 1683 different canary value for each task. 1684 1685endmenu 1686 1687menu "Boot options" 1688 1689config USE_OF 1690 bool "Flattened Device Tree support" 1691 select IRQ_DOMAIN 1692 select OF 1693 help 1694 Include support for flattened device tree machine descriptions. 1695 1696config ATAGS 1697 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1698 default y 1699 help 1700 This is the traditional way of passing data to the kernel at boot 1701 time. If you are solely relying on the flattened device tree (or 1702 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1703 to remove ATAGS support from your kernel binary. If unsure, 1704 leave this to y. 1705 1706config DEPRECATED_PARAM_STRUCT 1707 bool "Provide old way to pass kernel parameters" 1708 depends on ATAGS 1709 help 1710 This was deprecated in 2001 and announced to live on for 5 years. 1711 Some old boot loaders still use this way. 1712 1713# Compressed boot loader in ROM. Yes, we really want to ask about 1714# TEXT and BSS so we preserve their values in the config files. 1715config ZBOOT_ROM_TEXT 1716 hex "Compressed ROM boot loader base address" 1717 default 0x0 1718 help 1719 The physical address at which the ROM-able zImage is to be 1720 placed in the target. Platforms which normally make use of 1721 ROM-able zImage formats normally set this to a suitable 1722 value in their defconfig file. 1723 1724 If ZBOOT_ROM is not enabled, this has no effect. 1725 1726config ZBOOT_ROM_BSS 1727 hex "Compressed ROM boot loader BSS address" 1728 default 0x0 1729 help 1730 The base address of an area of read/write memory in the target 1731 for the ROM-able zImage which must be available while the 1732 decompressor is running. It must be large enough to hold the 1733 entire decompressed kernel plus an additional 128 KiB. 1734 Platforms which normally make use of ROM-able zImage formats 1735 normally set this to a suitable value in their defconfig file. 1736 1737 If ZBOOT_ROM is not enabled, this has no effect. 1738 1739config ZBOOT_ROM 1740 bool "Compressed boot loader in ROM/flash" 1741 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1742 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1743 help 1744 Say Y here if you intend to execute your compressed kernel image 1745 (zImage) directly from ROM or flash. If unsure, say N. 1746 1747config ARM_APPENDED_DTB 1748 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1749 depends on OF 1750 help 1751 With this option, the boot code will look for a device tree binary 1752 (DTB) appended to zImage 1753 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1754 1755 This is meant as a backward compatibility convenience for those 1756 systems with a bootloader that can't be upgraded to accommodate 1757 the documented boot protocol using a device tree. 1758 1759 Beware that there is very little in terms of protection against 1760 this option being confused by leftover garbage in memory that might 1761 look like a DTB header after a reboot if no actual DTB is appended 1762 to zImage. Do not leave this option active in a production kernel 1763 if you don't intend to always append a DTB. Proper passing of the 1764 location into r2 of a bootloader provided DTB is always preferable 1765 to this option. 1766 1767config ARM_ATAG_DTB_COMPAT 1768 bool "Supplement the appended DTB with traditional ATAG information" 1769 depends on ARM_APPENDED_DTB 1770 help 1771 Some old bootloaders can't be updated to a DTB capable one, yet 1772 they provide ATAGs with memory configuration, the ramdisk address, 1773 the kernel cmdline string, etc. Such information is dynamically 1774 provided by the bootloader and can't always be stored in a static 1775 DTB. To allow a device tree enabled kernel to be used with such 1776 bootloaders, this option allows zImage to extract the information 1777 from the ATAG list and store it at run time into the appended DTB. 1778 1779choice 1780 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1781 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1782 1783config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1784 bool "Use bootloader kernel arguments if available" 1785 help 1786 Uses the command-line options passed by the boot loader instead of 1787 the device tree bootargs property. If the boot loader doesn't provide 1788 any, the device tree bootargs property will be used. 1789 1790config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1791 bool "Extend with bootloader kernel arguments" 1792 help 1793 The command-line arguments provided by the boot loader will be 1794 appended to the the device tree bootargs property. 1795 1796endchoice 1797 1798config CMDLINE 1799 string "Default kernel command string" 1800 default "" 1801 help 1802 On some architectures (EBSA110 and CATS), there is currently no way 1803 for the boot loader to pass arguments to the kernel. For these 1804 architectures, you should supply some command-line options at build 1805 time by entering them here. As a minimum, you should specify the 1806 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1807 1808choice 1809 prompt "Kernel command line type" if CMDLINE != "" 1810 default CMDLINE_FROM_BOOTLOADER 1811 depends on ATAGS 1812 1813config CMDLINE_FROM_BOOTLOADER 1814 bool "Use bootloader kernel arguments if available" 1815 help 1816 Uses the command-line options passed by the boot loader. If 1817 the boot loader doesn't provide any, the default kernel command 1818 string provided in CMDLINE will be used. 1819 1820config CMDLINE_EXTEND 1821 bool "Extend bootloader kernel arguments" 1822 help 1823 The command-line arguments provided by the boot loader will be 1824 appended to the default kernel command string. 1825 1826config CMDLINE_FORCE 1827 bool "Always use the default kernel command string" 1828 help 1829 Always use the default kernel command string, even if the boot 1830 loader passes other arguments to the kernel. 1831 This is useful if you cannot or don't want to change the 1832 command-line options your boot loader passes to the kernel. 1833endchoice 1834 1835config XIP_KERNEL 1836 bool "Kernel Execute-In-Place from ROM" 1837 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1838 help 1839 Execute-In-Place allows the kernel to run from non-volatile storage 1840 directly addressable by the CPU, such as NOR flash. This saves RAM 1841 space since the text section of the kernel is not loaded from flash 1842 to RAM. Read-write sections, such as the data section and stack, 1843 are still copied to RAM. The XIP kernel is not compressed since 1844 it has to run directly from flash, so it will take more space to 1845 store it. The flash address used to link the kernel object files, 1846 and for storing it, is configuration dependent. Therefore, if you 1847 say Y here, you must know the proper physical address where to 1848 store the kernel image depending on your own flash memory usage. 1849 1850 Also note that the make target becomes "make xipImage" rather than 1851 "make zImage" or "make Image". The final kernel binary to put in 1852 ROM memory will be arch/arm/boot/xipImage. 1853 1854 If unsure, say N. 1855 1856config XIP_PHYS_ADDR 1857 hex "XIP Kernel Physical Location" 1858 depends on XIP_KERNEL 1859 default "0x00080000" 1860 help 1861 This is the physical address in your flash memory the kernel will 1862 be linked for and stored to. This address is dependent on your 1863 own flash usage. 1864 1865config XIP_DEFLATED_DATA 1866 bool "Store kernel .data section compressed in ROM" 1867 depends on XIP_KERNEL 1868 select ZLIB_INFLATE 1869 help 1870 Before the kernel is actually executed, its .data section has to be 1871 copied to RAM from ROM. This option allows for storing that data 1872 in compressed form and decompressed to RAM rather than merely being 1873 copied, saving some precious ROM space. A possible drawback is a 1874 slightly longer boot delay. 1875 1876config KEXEC 1877 bool "Kexec system call (EXPERIMENTAL)" 1878 depends on (!SMP || PM_SLEEP_SMP) 1879 depends on MMU 1880 select KEXEC_CORE 1881 help 1882 kexec is a system call that implements the ability to shutdown your 1883 current kernel, and to start another kernel. It is like a reboot 1884 but it is independent of the system firmware. And like a reboot 1885 you can start any kernel with it, not just Linux. 1886 1887 It is an ongoing process to be certain the hardware in a machine 1888 is properly shutdown, so do not be surprised if this code does not 1889 initially work for you. 1890 1891config ATAGS_PROC 1892 bool "Export atags in procfs" 1893 depends on ATAGS && KEXEC 1894 default y 1895 help 1896 Should the atags used to boot the kernel be exported in an "atags" 1897 file in procfs. Useful with kexec. 1898 1899config CRASH_DUMP 1900 bool "Build kdump crash kernel (EXPERIMENTAL)" 1901 help 1902 Generate crash dump after being started by kexec. This should 1903 be normally only set in special crash dump kernels which are 1904 loaded in the main kernel with kexec-tools into a specially 1905 reserved region and then later executed after a crash by 1906 kdump/kexec. The crash dump kernel must be compiled to a 1907 memory address not used by the main kernel 1908 1909 For more details see Documentation/admin-guide/kdump/kdump.rst 1910 1911config AUTO_ZRELADDR 1912 bool "Auto calculation of the decompressed kernel image address" 1913 help 1914 ZRELADDR is the physical address where the decompressed kernel 1915 image will be placed. If AUTO_ZRELADDR is selected, the address 1916 will be determined at run-time by masking the current IP with 1917 0xf8000000. This assumes the zImage being placed in the first 128MB 1918 from start of memory. 1919 1920config EFI_STUB 1921 bool 1922 1923config EFI 1924 bool "UEFI runtime support" 1925 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1926 select UCS2_STRING 1927 select EFI_PARAMS_FROM_FDT 1928 select EFI_STUB 1929 select EFI_GENERIC_STUB 1930 select EFI_RUNTIME_WRAPPERS 1931 help 1932 This option provides support for runtime services provided 1933 by UEFI firmware (such as non-volatile variables, realtime 1934 clock, and platform reset). A UEFI stub is also provided to 1935 allow the kernel to be booted as an EFI application. This 1936 is only useful for kernels that may run on systems that have 1937 UEFI firmware. 1938 1939config DMI 1940 bool "Enable support for SMBIOS (DMI) tables" 1941 depends on EFI 1942 default y 1943 help 1944 This enables SMBIOS/DMI feature for systems. 1945 1946 This option is only useful on systems that have UEFI firmware. 1947 However, even with this option, the resultant kernel should 1948 continue to boot on existing non-UEFI platforms. 1949 1950 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1951 i.e., the the practice of identifying the platform via DMI to 1952 decide whether certain workarounds for buggy hardware and/or 1953 firmware need to be enabled. This would require the DMI subsystem 1954 to be enabled much earlier than we do on ARM, which is non-trivial. 1955 1956endmenu 1957 1958menu "CPU Power Management" 1959 1960source "drivers/cpufreq/Kconfig" 1961 1962source "drivers/cpuidle/Kconfig" 1963 1964endmenu 1965 1966menu "Floating point emulation" 1967 1968comment "At least one emulation must be selected" 1969 1970config FPE_NWFPE 1971 bool "NWFPE math emulation" 1972 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1973 help 1974 Say Y to include the NWFPE floating point emulator in the kernel. 1975 This is necessary to run most binaries. Linux does not currently 1976 support floating point hardware so you need to say Y here even if 1977 your machine has an FPA or floating point co-processor podule. 1978 1979 You may say N here if you are going to load the Acorn FPEmulator 1980 early in the bootup. 1981 1982config FPE_NWFPE_XP 1983 bool "Support extended precision" 1984 depends on FPE_NWFPE 1985 help 1986 Say Y to include 80-bit support in the kernel floating-point 1987 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1988 Note that gcc does not generate 80-bit operations by default, 1989 so in most cases this option only enlarges the size of the 1990 floating point emulator without any good reason. 1991 1992 You almost surely want to say N here. 1993 1994config FPE_FASTFPE 1995 bool "FastFPE math emulation (EXPERIMENTAL)" 1996 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1997 help 1998 Say Y here to include the FAST floating point emulator in the kernel. 1999 This is an experimental much faster emulator which now also has full 2000 precision for the mantissa. It does not support any exceptions. 2001 It is very simple, and approximately 3-6 times faster than NWFPE. 2002 2003 It should be sufficient for most programs. It may be not suitable 2004 for scientific calculations, but you have to check this for yourself. 2005 If you do not feel you need a faster FP emulation you should better 2006 choose NWFPE. 2007 2008config VFP 2009 bool "VFP-format floating point maths" 2010 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2011 help 2012 Say Y to include VFP support code in the kernel. This is needed 2013 if your hardware includes a VFP unit. 2014 2015 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2016 release notes and additional status information. 2017 2018 Say N if your target does not have VFP hardware. 2019 2020config VFPv3 2021 bool 2022 depends on VFP 2023 default y if CPU_V7 2024 2025config NEON 2026 bool "Advanced SIMD (NEON) Extension support" 2027 depends on VFPv3 && CPU_V7 2028 help 2029 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2030 Extension. 2031 2032config KERNEL_MODE_NEON 2033 bool "Support for NEON in kernel mode" 2034 depends on NEON && AEABI 2035 help 2036 Say Y to include support for NEON in kernel mode. 2037 2038endmenu 2039 2040menu "Power management options" 2041 2042source "kernel/power/Kconfig" 2043 2044config ARCH_SUSPEND_POSSIBLE 2045 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2046 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2047 def_bool y 2048 2049config ARM_CPU_SUSPEND 2050 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2051 depends on ARCH_SUSPEND_POSSIBLE 2052 2053config ARCH_HIBERNATION_POSSIBLE 2054 bool 2055 depends on MMU 2056 default y if ARCH_SUSPEND_POSSIBLE 2057 2058endmenu 2059 2060source "drivers/firmware/Kconfig" 2061 2062if CRYPTO 2063source "arch/arm/crypto/Kconfig" 2064endif 2065 2066source "arch/arm/Kconfig.assembler" 2067