1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 * 23 * Author: Shobhit Kumar <shobhit.kumar@intel.com> 24 * 25 */ 26 27 #include <linux/gpio/consumer.h> 28 #include <linux/gpio/machine.h> 29 #include <linux/mfd/intel_soc_pmic.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/machine.h> 32 #include <linux/slab.h> 33 34 #include <asm/intel-mid.h> 35 #include <asm/unaligned.h> 36 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_edid.h> 39 #include <drm/i915_drm.h> 40 41 #include <video/mipi_display.h> 42 43 #include "i915_drv.h" 44 #include "intel_display_types.h" 45 #include "intel_dsi.h" 46 #include "intel_sideband.h" 47 48 #define MIPI_TRANSFER_MODE_SHIFT 0 49 #define MIPI_VIRTUAL_CHANNEL_SHIFT 1 50 #define MIPI_PORT_SHIFT 3 51 52 /* base offsets for gpio pads */ 53 #define VLV_GPIO_NC_0_HV_DDI0_HPD 0x4130 54 #define VLV_GPIO_NC_1_HV_DDI0_DDC_SDA 0x4120 55 #define VLV_GPIO_NC_2_HV_DDI0_DDC_SCL 0x4110 56 #define VLV_GPIO_NC_3_PANEL0_VDDEN 0x4140 57 #define VLV_GPIO_NC_4_PANEL0_BKLTEN 0x4150 58 #define VLV_GPIO_NC_5_PANEL0_BKLTCTL 0x4160 59 #define VLV_GPIO_NC_6_HV_DDI1_HPD 0x4180 60 #define VLV_GPIO_NC_7_HV_DDI1_DDC_SDA 0x4190 61 #define VLV_GPIO_NC_8_HV_DDI1_DDC_SCL 0x4170 62 #define VLV_GPIO_NC_9_PANEL1_VDDEN 0x4100 63 #define VLV_GPIO_NC_10_PANEL1_BKLTEN 0x40E0 64 #define VLV_GPIO_NC_11_PANEL1_BKLTCTL 0x40F0 65 66 #define VLV_GPIO_PCONF0(base_offset) (base_offset) 67 #define VLV_GPIO_PAD_VAL(base_offset) ((base_offset) + 8) 68 69 struct gpio_map { 70 u16 base_offset; 71 bool init; 72 }; 73 74 static struct gpio_map vlv_gpio_table[] = { 75 { VLV_GPIO_NC_0_HV_DDI0_HPD }, 76 { VLV_GPIO_NC_1_HV_DDI0_DDC_SDA }, 77 { VLV_GPIO_NC_2_HV_DDI0_DDC_SCL }, 78 { VLV_GPIO_NC_3_PANEL0_VDDEN }, 79 { VLV_GPIO_NC_4_PANEL0_BKLTEN }, 80 { VLV_GPIO_NC_5_PANEL0_BKLTCTL }, 81 { VLV_GPIO_NC_6_HV_DDI1_HPD }, 82 { VLV_GPIO_NC_7_HV_DDI1_DDC_SDA }, 83 { VLV_GPIO_NC_8_HV_DDI1_DDC_SCL }, 84 { VLV_GPIO_NC_9_PANEL1_VDDEN }, 85 { VLV_GPIO_NC_10_PANEL1_BKLTEN }, 86 { VLV_GPIO_NC_11_PANEL1_BKLTCTL }, 87 }; 88 89 struct i2c_adapter_lookup { 90 u16 slave_addr; 91 struct intel_dsi *intel_dsi; 92 acpi_handle dev_handle; 93 }; 94 95 #define CHV_GPIO_IDX_START_N 0 96 #define CHV_GPIO_IDX_START_E 73 97 #define CHV_GPIO_IDX_START_SW 100 98 #define CHV_GPIO_IDX_START_SE 198 99 100 #define CHV_VBT_MAX_PINS_PER_FMLY 15 101 102 #define CHV_GPIO_PAD_CFG0(f, i) (0x4400 + (f) * 0x400 + (i) * 8) 103 #define CHV_GPIO_GPIOEN (1 << 15) 104 #define CHV_GPIO_GPIOCFG_GPIO (0 << 8) 105 #define CHV_GPIO_GPIOCFG_GPO (1 << 8) 106 #define CHV_GPIO_GPIOCFG_GPI (2 << 8) 107 #define CHV_GPIO_GPIOCFG_HIZ (3 << 8) 108 #define CHV_GPIO_GPIOTXSTATE(state) ((!!(state)) << 1) 109 110 #define CHV_GPIO_PAD_CFG1(f, i) (0x4400 + (f) * 0x400 + (i) * 8 + 4) 111 #define CHV_GPIO_CFGLOCK (1 << 31) 112 113 /* ICL DSI Display GPIO Pins */ 114 #define ICL_GPIO_DDSP_HPD_A 0 115 #define ICL_GPIO_L_VDDEN_1 1 116 #define ICL_GPIO_L_BKLTEN_1 2 117 #define ICL_GPIO_DDPA_CTRLCLK_1 3 118 #define ICL_GPIO_DDPA_CTRLDATA_1 4 119 #define ICL_GPIO_DDSP_HPD_B 5 120 #define ICL_GPIO_L_VDDEN_2 6 121 #define ICL_GPIO_L_BKLTEN_2 7 122 #define ICL_GPIO_DDPA_CTRLCLK_2 8 123 #define ICL_GPIO_DDPA_CTRLDATA_2 9 124 125 static inline enum port intel_dsi_seq_port_to_port(u8 port) 126 { 127 return port ? PORT_C : PORT_A; 128 } 129 130 static const u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, 131 const u8 *data) 132 { 133 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 134 struct mipi_dsi_device *dsi_device; 135 u8 type, flags, seq_port; 136 u16 len; 137 enum port port; 138 139 DRM_DEBUG_KMS("\n"); 140 141 flags = *data++; 142 type = *data++; 143 144 len = *((u16 *) data); 145 data += 2; 146 147 seq_port = (flags >> MIPI_PORT_SHIFT) & 3; 148 149 /* For DSI single link on Port A & C, the seq_port value which is 150 * parsed from Sequence Block#53 of VBT has been set to 0 151 * Now, read/write of packets for the DSI single link on Port A and 152 * Port C will based on the DVO port from VBT block 2. 153 */ 154 if (intel_dsi->ports == (1 << PORT_C)) 155 port = PORT_C; 156 else 157 port = intel_dsi_seq_port_to_port(seq_port); 158 159 dsi_device = intel_dsi->dsi_hosts[port]->device; 160 if (!dsi_device) { 161 DRM_DEBUG_KMS("no dsi device for port %c\n", port_name(port)); 162 goto out; 163 } 164 165 if ((flags >> MIPI_TRANSFER_MODE_SHIFT) & 1) 166 dsi_device->mode_flags &= ~MIPI_DSI_MODE_LPM; 167 else 168 dsi_device->mode_flags |= MIPI_DSI_MODE_LPM; 169 170 dsi_device->channel = (flags >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 3; 171 172 switch (type) { 173 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 174 mipi_dsi_generic_write(dsi_device, NULL, 0); 175 break; 176 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 177 mipi_dsi_generic_write(dsi_device, data, 1); 178 break; 179 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 180 mipi_dsi_generic_write(dsi_device, data, 2); 181 break; 182 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 183 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 184 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 185 DRM_DEBUG_DRIVER("Generic Read not yet implemented or used\n"); 186 break; 187 case MIPI_DSI_GENERIC_LONG_WRITE: 188 mipi_dsi_generic_write(dsi_device, data, len); 189 break; 190 case MIPI_DSI_DCS_SHORT_WRITE: 191 mipi_dsi_dcs_write_buffer(dsi_device, data, 1); 192 break; 193 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 194 mipi_dsi_dcs_write_buffer(dsi_device, data, 2); 195 break; 196 case MIPI_DSI_DCS_READ: 197 DRM_DEBUG_DRIVER("DCS Read not yet implemented or used\n"); 198 break; 199 case MIPI_DSI_DCS_LONG_WRITE: 200 mipi_dsi_dcs_write_buffer(dsi_device, data, len); 201 break; 202 } 203 204 if (INTEL_GEN(dev_priv) < 11) 205 vlv_dsi_wait_for_fifo_empty(intel_dsi, port); 206 207 out: 208 data += len; 209 210 return data; 211 } 212 213 static const u8 *mipi_exec_delay(struct intel_dsi *intel_dsi, const u8 *data) 214 { 215 u32 delay = *((const u32 *) data); 216 217 DRM_DEBUG_KMS("\n"); 218 219 usleep_range(delay, delay + 10); 220 data += 4; 221 222 return data; 223 } 224 225 static void vlv_exec_gpio(struct drm_i915_private *dev_priv, 226 u8 gpio_source, u8 gpio_index, bool value) 227 { 228 struct gpio_map *map; 229 u16 pconf0, padval; 230 u32 tmp; 231 u8 port; 232 233 if (gpio_index >= ARRAY_SIZE(vlv_gpio_table)) { 234 DRM_DEBUG_KMS("unknown gpio index %u\n", gpio_index); 235 return; 236 } 237 238 map = &vlv_gpio_table[gpio_index]; 239 240 if (dev_priv->vbt.dsi.seq_version >= 3) { 241 /* XXX: this assumes vlv_gpio_table only has NC GPIOs. */ 242 port = IOSF_PORT_GPIO_NC; 243 } else { 244 if (gpio_source == 0) { 245 port = IOSF_PORT_GPIO_NC; 246 } else if (gpio_source == 1) { 247 DRM_DEBUG_KMS("SC gpio not supported\n"); 248 return; 249 } else { 250 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); 251 return; 252 } 253 } 254 255 pconf0 = VLV_GPIO_PCONF0(map->base_offset); 256 padval = VLV_GPIO_PAD_VAL(map->base_offset); 257 258 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 259 if (!map->init) { 260 /* FIXME: remove constant below */ 261 vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00); 262 map->init = true; 263 } 264 265 tmp = 0x4 | value; 266 vlv_iosf_sb_write(dev_priv, port, padval, tmp); 267 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 268 } 269 270 static void chv_exec_gpio(struct drm_i915_private *dev_priv, 271 u8 gpio_source, u8 gpio_index, bool value) 272 { 273 u16 cfg0, cfg1; 274 u16 family_num; 275 u8 port; 276 277 if (dev_priv->vbt.dsi.seq_version >= 3) { 278 if (gpio_index >= CHV_GPIO_IDX_START_SE) { 279 /* XXX: it's unclear whether 255->57 is part of SE. */ 280 gpio_index -= CHV_GPIO_IDX_START_SE; 281 port = CHV_IOSF_PORT_GPIO_SE; 282 } else if (gpio_index >= CHV_GPIO_IDX_START_SW) { 283 gpio_index -= CHV_GPIO_IDX_START_SW; 284 port = CHV_IOSF_PORT_GPIO_SW; 285 } else if (gpio_index >= CHV_GPIO_IDX_START_E) { 286 gpio_index -= CHV_GPIO_IDX_START_E; 287 port = CHV_IOSF_PORT_GPIO_E; 288 } else { 289 port = CHV_IOSF_PORT_GPIO_N; 290 } 291 } else { 292 /* XXX: The spec is unclear about CHV GPIO on seq v2 */ 293 if (gpio_source != 0) { 294 DRM_DEBUG_KMS("unknown gpio source %u\n", gpio_source); 295 return; 296 } 297 298 if (gpio_index >= CHV_GPIO_IDX_START_E) { 299 DRM_DEBUG_KMS("invalid gpio index %u for GPIO N\n", 300 gpio_index); 301 return; 302 } 303 304 port = CHV_IOSF_PORT_GPIO_N; 305 } 306 307 family_num = gpio_index / CHV_VBT_MAX_PINS_PER_FMLY; 308 gpio_index = gpio_index % CHV_VBT_MAX_PINS_PER_FMLY; 309 310 cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index); 311 cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index); 312 313 vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 314 vlv_iosf_sb_write(dev_priv, port, cfg1, 0); 315 vlv_iosf_sb_write(dev_priv, port, cfg0, 316 CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO | 317 CHV_GPIO_GPIOTXSTATE(value)); 318 vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO)); 319 } 320 321 static void bxt_exec_gpio(struct drm_i915_private *dev_priv, 322 u8 gpio_source, u8 gpio_index, bool value) 323 { 324 /* XXX: this table is a quick ugly hack. */ 325 static struct gpio_desc *bxt_gpio_table[U8_MAX + 1]; 326 struct gpio_desc *gpio_desc = bxt_gpio_table[gpio_index]; 327 328 if (!gpio_desc) { 329 gpio_desc = devm_gpiod_get_index(dev_priv->drm.dev, 330 NULL, gpio_index, 331 value ? GPIOD_OUT_LOW : 332 GPIOD_OUT_HIGH); 333 334 if (IS_ERR_OR_NULL(gpio_desc)) { 335 DRM_ERROR("GPIO index %u request failed (%ld)\n", 336 gpio_index, PTR_ERR(gpio_desc)); 337 return; 338 } 339 340 bxt_gpio_table[gpio_index] = gpio_desc; 341 } 342 343 gpiod_set_value(gpio_desc, value); 344 } 345 346 static void icl_exec_gpio(struct drm_i915_private *dev_priv, 347 u8 gpio_source, u8 gpio_index, bool value) 348 { 349 DRM_DEBUG_KMS("Skipping ICL GPIO element execution\n"); 350 } 351 352 static const u8 *mipi_exec_gpio(struct intel_dsi *intel_dsi, const u8 *data) 353 { 354 struct drm_device *dev = intel_dsi->base.base.dev; 355 struct drm_i915_private *dev_priv = to_i915(dev); 356 u8 gpio_source, gpio_index = 0, gpio_number; 357 bool value; 358 359 DRM_DEBUG_KMS("\n"); 360 361 if (dev_priv->vbt.dsi.seq_version >= 3) 362 gpio_index = *data++; 363 364 gpio_number = *data++; 365 366 /* gpio source in sequence v2 only */ 367 if (dev_priv->vbt.dsi.seq_version == 2) 368 gpio_source = (*data >> 1) & 3; 369 else 370 gpio_source = 0; 371 372 /* pull up/down */ 373 value = *data++ & 1; 374 375 if (INTEL_GEN(dev_priv) >= 11) 376 icl_exec_gpio(dev_priv, gpio_source, gpio_index, value); 377 else if (IS_VALLEYVIEW(dev_priv)) 378 vlv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 379 else if (IS_CHERRYVIEW(dev_priv)) 380 chv_exec_gpio(dev_priv, gpio_source, gpio_number, value); 381 else 382 bxt_exec_gpio(dev_priv, gpio_source, gpio_index, value); 383 384 return data; 385 } 386 387 static int i2c_adapter_lookup(struct acpi_resource *ares, void *data) 388 { 389 struct i2c_adapter_lookup *lookup = data; 390 struct intel_dsi *intel_dsi = lookup->intel_dsi; 391 struct acpi_resource_i2c_serialbus *sb; 392 struct i2c_adapter *adapter; 393 acpi_handle adapter_handle; 394 acpi_status status; 395 396 if (intel_dsi->i2c_bus_num >= 0 || 397 !i2c_acpi_get_i2c_resource(ares, &sb)) 398 return 1; 399 400 if (lookup->slave_addr != sb->slave_address) 401 return 1; 402 403 status = acpi_get_handle(lookup->dev_handle, 404 sb->resource_source.string_ptr, 405 &adapter_handle); 406 if (ACPI_FAILURE(status)) 407 return 1; 408 409 adapter = i2c_acpi_find_adapter_by_handle(adapter_handle); 410 if (adapter) 411 intel_dsi->i2c_bus_num = adapter->nr; 412 413 return 1; 414 } 415 416 static const u8 *mipi_exec_i2c(struct intel_dsi *intel_dsi, const u8 *data) 417 { 418 struct drm_device *drm_dev = intel_dsi->base.base.dev; 419 struct device *dev = &drm_dev->pdev->dev; 420 struct i2c_adapter *adapter; 421 struct acpi_device *acpi_dev; 422 struct list_head resource_list; 423 struct i2c_adapter_lookup lookup; 424 struct i2c_msg msg; 425 int ret; 426 u8 vbt_i2c_bus_num = *(data + 2); 427 u16 slave_addr = *(u16 *)(data + 3); 428 u8 reg_offset = *(data + 5); 429 u8 payload_size = *(data + 6); 430 u8 *payload_data; 431 432 if (intel_dsi->i2c_bus_num < 0) { 433 intel_dsi->i2c_bus_num = vbt_i2c_bus_num; 434 435 acpi_dev = ACPI_COMPANION(dev); 436 if (acpi_dev) { 437 memset(&lookup, 0, sizeof(lookup)); 438 lookup.slave_addr = slave_addr; 439 lookup.intel_dsi = intel_dsi; 440 lookup.dev_handle = acpi_device_handle(acpi_dev); 441 442 INIT_LIST_HEAD(&resource_list); 443 acpi_dev_get_resources(acpi_dev, &resource_list, 444 i2c_adapter_lookup, 445 &lookup); 446 acpi_dev_free_resource_list(&resource_list); 447 } 448 } 449 450 adapter = i2c_get_adapter(intel_dsi->i2c_bus_num); 451 if (!adapter) { 452 DRM_DEV_ERROR(dev, "Cannot find a valid i2c bus for xfer\n"); 453 goto err_bus; 454 } 455 456 payload_data = kzalloc(payload_size + 1, GFP_KERNEL); 457 if (!payload_data) 458 goto err_alloc; 459 460 payload_data[0] = reg_offset; 461 memcpy(&payload_data[1], (data + 7), payload_size); 462 463 msg.addr = slave_addr; 464 msg.flags = 0; 465 msg.len = payload_size + 1; 466 msg.buf = payload_data; 467 468 ret = i2c_transfer(adapter, &msg, 1); 469 if (ret < 0) 470 DRM_DEV_ERROR(dev, 471 "Failed to xfer payload of size (%u) to reg (%u)\n", 472 payload_size, reg_offset); 473 474 kfree(payload_data); 475 err_alloc: 476 i2c_put_adapter(adapter); 477 err_bus: 478 return data + payload_size + 7; 479 } 480 481 static const u8 *mipi_exec_spi(struct intel_dsi *intel_dsi, const u8 *data) 482 { 483 DRM_DEBUG_KMS("Skipping SPI element execution\n"); 484 485 return data + *(data + 5) + 6; 486 } 487 488 static const u8 *mipi_exec_pmic(struct intel_dsi *intel_dsi, const u8 *data) 489 { 490 #ifdef CONFIG_PMIC_OPREGION 491 u32 value, mask, reg_address; 492 u16 i2c_address; 493 int ret; 494 495 /* byte 0 aka PMIC Flag is reserved */ 496 i2c_address = get_unaligned_le16(data + 1); 497 reg_address = get_unaligned_le32(data + 3); 498 value = get_unaligned_le32(data + 7); 499 mask = get_unaligned_le32(data + 11); 500 501 ret = intel_soc_pmic_exec_mipi_pmic_seq_element(i2c_address, 502 reg_address, 503 value, mask); 504 if (ret) 505 DRM_ERROR("%s failed, error: %d\n", __func__, ret); 506 #else 507 DRM_ERROR("Your hardware requires CONFIG_PMIC_OPREGION and it is not set\n"); 508 #endif 509 510 return data + 15; 511 } 512 513 typedef const u8 * (*fn_mipi_elem_exec)(struct intel_dsi *intel_dsi, 514 const u8 *data); 515 static const fn_mipi_elem_exec exec_elem[] = { 516 [MIPI_SEQ_ELEM_SEND_PKT] = mipi_exec_send_packet, 517 [MIPI_SEQ_ELEM_DELAY] = mipi_exec_delay, 518 [MIPI_SEQ_ELEM_GPIO] = mipi_exec_gpio, 519 [MIPI_SEQ_ELEM_I2C] = mipi_exec_i2c, 520 [MIPI_SEQ_ELEM_SPI] = mipi_exec_spi, 521 [MIPI_SEQ_ELEM_PMIC] = mipi_exec_pmic, 522 }; 523 524 /* 525 * MIPI Sequence from VBT #53 parsing logic 526 * We have already separated each seqence during bios parsing 527 * Following is generic execution function for any sequence 528 */ 529 530 static const char * const seq_name[] = { 531 [MIPI_SEQ_DEASSERT_RESET] = "MIPI_SEQ_DEASSERT_RESET", 532 [MIPI_SEQ_INIT_OTP] = "MIPI_SEQ_INIT_OTP", 533 [MIPI_SEQ_DISPLAY_ON] = "MIPI_SEQ_DISPLAY_ON", 534 [MIPI_SEQ_DISPLAY_OFF] = "MIPI_SEQ_DISPLAY_OFF", 535 [MIPI_SEQ_ASSERT_RESET] = "MIPI_SEQ_ASSERT_RESET", 536 [MIPI_SEQ_BACKLIGHT_ON] = "MIPI_SEQ_BACKLIGHT_ON", 537 [MIPI_SEQ_BACKLIGHT_OFF] = "MIPI_SEQ_BACKLIGHT_OFF", 538 [MIPI_SEQ_TEAR_ON] = "MIPI_SEQ_TEAR_ON", 539 [MIPI_SEQ_TEAR_OFF] = "MIPI_SEQ_TEAR_OFF", 540 [MIPI_SEQ_POWER_ON] = "MIPI_SEQ_POWER_ON", 541 [MIPI_SEQ_POWER_OFF] = "MIPI_SEQ_POWER_OFF", 542 }; 543 544 static const char *sequence_name(enum mipi_seq seq_id) 545 { 546 if (seq_id < ARRAY_SIZE(seq_name) && seq_name[seq_id]) 547 return seq_name[seq_id]; 548 else 549 return "(unknown)"; 550 } 551 552 static void intel_dsi_vbt_exec(struct intel_dsi *intel_dsi, 553 enum mipi_seq seq_id) 554 { 555 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 556 const u8 *data; 557 fn_mipi_elem_exec mipi_elem_exec; 558 559 if (WARN_ON(seq_id >= ARRAY_SIZE(dev_priv->vbt.dsi.sequence))) 560 return; 561 562 data = dev_priv->vbt.dsi.sequence[seq_id]; 563 if (!data) 564 return; 565 566 WARN_ON(*data != seq_id); 567 568 DRM_DEBUG_KMS("Starting MIPI sequence %d - %s\n", 569 seq_id, sequence_name(seq_id)); 570 571 /* Skip Sequence Byte. */ 572 data++; 573 574 /* Skip Size of Sequence. */ 575 if (dev_priv->vbt.dsi.seq_version >= 3) 576 data += 4; 577 578 while (1) { 579 u8 operation_byte = *data++; 580 u8 operation_size = 0; 581 582 if (operation_byte == MIPI_SEQ_ELEM_END) 583 break; 584 585 if (operation_byte < ARRAY_SIZE(exec_elem)) 586 mipi_elem_exec = exec_elem[operation_byte]; 587 else 588 mipi_elem_exec = NULL; 589 590 /* Size of Operation. */ 591 if (dev_priv->vbt.dsi.seq_version >= 3) 592 operation_size = *data++; 593 594 if (mipi_elem_exec) { 595 const u8 *next = data + operation_size; 596 597 data = mipi_elem_exec(intel_dsi, data); 598 599 /* Consistency check if we have size. */ 600 if (operation_size && data != next) { 601 DRM_ERROR("Inconsistent operation size\n"); 602 return; 603 } 604 } else if (operation_size) { 605 /* We have size, skip. */ 606 DRM_DEBUG_KMS("Unsupported MIPI operation byte %u\n", 607 operation_byte); 608 data += operation_size; 609 } else { 610 /* No size, can't skip without parsing. */ 611 DRM_ERROR("Unsupported MIPI operation byte %u\n", 612 operation_byte); 613 return; 614 } 615 } 616 } 617 618 void intel_dsi_vbt_exec_sequence(struct intel_dsi *intel_dsi, 619 enum mipi_seq seq_id) 620 { 621 if (seq_id == MIPI_SEQ_POWER_ON && intel_dsi->gpio_panel) 622 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); 623 if (seq_id == MIPI_SEQ_BACKLIGHT_ON && intel_dsi->gpio_backlight) 624 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 1); 625 626 intel_dsi_vbt_exec(intel_dsi, seq_id); 627 628 if (seq_id == MIPI_SEQ_POWER_OFF && intel_dsi->gpio_panel) 629 gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); 630 if (seq_id == MIPI_SEQ_BACKLIGHT_OFF && intel_dsi->gpio_backlight) 631 gpiod_set_value_cansleep(intel_dsi->gpio_backlight, 0); 632 } 633 634 void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec) 635 { 636 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); 637 638 /* For v3 VBTs in vid-mode the delays are part of the VBT sequences */ 639 if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3) 640 return; 641 642 msleep(msec); 643 } 644 645 void intel_dsi_log_params(struct intel_dsi *intel_dsi) 646 { 647 DRM_DEBUG_KMS("Pclk %d\n", intel_dsi->pclk); 648 DRM_DEBUG_KMS("Pixel overlap %d\n", intel_dsi->pixel_overlap); 649 DRM_DEBUG_KMS("Lane count %d\n", intel_dsi->lane_count); 650 DRM_DEBUG_KMS("DPHY param reg 0x%x\n", intel_dsi->dphy_reg); 651 DRM_DEBUG_KMS("Video mode format %s\n", 652 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE ? 653 "non-burst with sync pulse" : 654 intel_dsi->video_mode_format == VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS ? 655 "non-burst with sync events" : 656 intel_dsi->video_mode_format == VIDEO_MODE_BURST ? 657 "burst" : "<unknown>"); 658 DRM_DEBUG_KMS("Burst mode ratio %d\n", intel_dsi->burst_mode_ratio); 659 DRM_DEBUG_KMS("Reset timer %d\n", intel_dsi->rst_timer_val); 660 DRM_DEBUG_KMS("Eot %s\n", enableddisabled(intel_dsi->eotp_pkt)); 661 DRM_DEBUG_KMS("Clockstop %s\n", enableddisabled(!intel_dsi->clock_stop)); 662 DRM_DEBUG_KMS("Mode %s\n", intel_dsi->operation_mode ? "command" : "video"); 663 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) 664 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_FRONT_BACK\n"); 665 else if (intel_dsi->dual_link == DSI_DUAL_LINK_PIXEL_ALT) 666 DRM_DEBUG_KMS("Dual link: DSI_DUAL_LINK_PIXEL_ALT\n"); 667 else 668 DRM_DEBUG_KMS("Dual link: NONE\n"); 669 DRM_DEBUG_KMS("Pixel Format %d\n", intel_dsi->pixel_format); 670 DRM_DEBUG_KMS("TLPX %d\n", intel_dsi->escape_clk_div); 671 DRM_DEBUG_KMS("LP RX Timeout 0x%x\n", intel_dsi->lp_rx_timeout); 672 DRM_DEBUG_KMS("Turnaround Timeout 0x%x\n", intel_dsi->turn_arnd_val); 673 DRM_DEBUG_KMS("Init Count 0x%x\n", intel_dsi->init_count); 674 DRM_DEBUG_KMS("HS to LP Count 0x%x\n", intel_dsi->hs_to_lp_count); 675 DRM_DEBUG_KMS("LP Byte Clock %d\n", intel_dsi->lp_byte_clk); 676 DRM_DEBUG_KMS("DBI BW Timer 0x%x\n", intel_dsi->bw_timer); 677 DRM_DEBUG_KMS("LP to HS Clock Count 0x%x\n", intel_dsi->clk_lp_to_hs_count); 678 DRM_DEBUG_KMS("HS to LP Clock Count 0x%x\n", intel_dsi->clk_hs_to_lp_count); 679 DRM_DEBUG_KMS("BTA %s\n", 680 enableddisabled(!(intel_dsi->video_frmt_cfg_bits & DISABLE_VIDEO_BTA))); 681 } 682 683 bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) 684 { 685 struct drm_device *dev = intel_dsi->base.base.dev; 686 struct drm_i915_private *dev_priv = to_i915(dev); 687 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 688 struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; 689 struct drm_display_mode *mode = dev_priv->vbt.lfp_lvds_vbt_mode; 690 u16 burst_mode_ratio; 691 enum port port; 692 693 DRM_DEBUG_KMS("\n"); 694 695 intel_dsi->eotp_pkt = mipi_config->eot_pkt_disabled ? 0 : 1; 696 intel_dsi->clock_stop = mipi_config->enable_clk_stop ? 1 : 0; 697 intel_dsi->lane_count = mipi_config->lane_cnt + 1; 698 intel_dsi->pixel_format = 699 pixel_format_from_register_bits( 700 mipi_config->videomode_color_format << 7); 701 702 intel_dsi->dual_link = mipi_config->dual_link; 703 intel_dsi->pixel_overlap = mipi_config->pixel_overlap; 704 intel_dsi->operation_mode = mipi_config->is_cmd_mode; 705 intel_dsi->video_mode_format = mipi_config->video_transfer_mode; 706 intel_dsi->escape_clk_div = mipi_config->byte_clk_sel; 707 intel_dsi->lp_rx_timeout = mipi_config->lp_rx_timeout; 708 intel_dsi->hs_tx_timeout = mipi_config->hs_tx_timeout; 709 intel_dsi->turn_arnd_val = mipi_config->turn_around_timeout; 710 intel_dsi->rst_timer_val = mipi_config->device_reset_timer; 711 intel_dsi->init_count = mipi_config->master_init_timer; 712 intel_dsi->bw_timer = mipi_config->dbi_bw_timer; 713 intel_dsi->video_frmt_cfg_bits = 714 mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0; 715 intel_dsi->bgr_enabled = mipi_config->rgb_flip; 716 717 /* Starting point, adjusted depending on dual link and burst mode */ 718 intel_dsi->pclk = mode->clock; 719 720 /* In dual link mode each port needs half of pixel clock */ 721 if (intel_dsi->dual_link) { 722 intel_dsi->pclk /= 2; 723 724 /* we can enable pixel_overlap if needed by panel. In this 725 * case we need to increase the pixelclock for extra pixels 726 */ 727 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { 728 intel_dsi->pclk += DIV_ROUND_UP(mode->vtotal * intel_dsi->pixel_overlap * 60, 1000); 729 } 730 } 731 732 /* Burst Mode Ratio 733 * Target ddr frequency from VBT / non burst ddr freq 734 * multiply by 100 to preserve remainder 735 */ 736 if (intel_dsi->video_mode_format == VIDEO_MODE_BURST) { 737 if (mipi_config->target_burst_mode_freq) { 738 u32 bitrate = intel_dsi_bitrate(intel_dsi); 739 740 /* 741 * Sometimes the VBT contains a slightly lower clock, 742 * then the bitrate we have calculated, in this case 743 * just replace it with the calculated bitrate. 744 */ 745 if (mipi_config->target_burst_mode_freq < bitrate && 746 intel_fuzzy_clock_check( 747 mipi_config->target_burst_mode_freq, 748 bitrate)) 749 mipi_config->target_burst_mode_freq = bitrate; 750 751 if (mipi_config->target_burst_mode_freq < bitrate) { 752 DRM_ERROR("Burst mode freq is less than computed\n"); 753 return false; 754 } 755 756 burst_mode_ratio = DIV_ROUND_UP( 757 mipi_config->target_burst_mode_freq * 100, 758 bitrate); 759 760 intel_dsi->pclk = DIV_ROUND_UP(intel_dsi->pclk * burst_mode_ratio, 100); 761 } else { 762 DRM_ERROR("Burst mode target is not set\n"); 763 return false; 764 } 765 } else 766 burst_mode_ratio = 100; 767 768 intel_dsi->burst_mode_ratio = burst_mode_ratio; 769 770 /* delays in VBT are in unit of 100us, so need to convert 771 * here in ms 772 * Delay (100us) * 100 /1000 = Delay / 10 (ms) */ 773 intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; 774 intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; 775 intel_dsi->panel_on_delay = pps->panel_on_delay / 10; 776 intel_dsi->panel_off_delay = pps->panel_off_delay / 10; 777 intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; 778 779 intel_dsi->i2c_bus_num = -1; 780 781 /* a regular driver would get the device in probe */ 782 for_each_dsi_port(port, intel_dsi->ports) { 783 mipi_dsi_attach(intel_dsi->dsi_hosts[port]->device); 784 } 785 786 return true; 787 } 788 789 /* 790 * On some BYT/CHT devs some sequences are incomplete and we need to manually 791 * control some GPIOs. We need to add a GPIO lookup table before we get these. 792 * If the GOP did not initialize the panel (HDMI inserted) we may need to also 793 * change the pinmux for the SoC's PWM0 pin from GPIO to PWM. 794 */ 795 static struct gpiod_lookup_table pmic_panel_gpio_table = { 796 /* Intel GFX is consumer */ 797 .dev_id = "0000:00:02.0", 798 .table = { 799 /* Panel EN/DISABLE */ 800 GPIO_LOOKUP("gpio_crystalcove", 94, "panel", GPIO_ACTIVE_HIGH), 801 { } 802 }, 803 }; 804 805 static struct gpiod_lookup_table soc_panel_gpio_table = { 806 .dev_id = "0000:00:02.0", 807 .table = { 808 GPIO_LOOKUP("INT33FC:01", 10, "backlight", GPIO_ACTIVE_HIGH), 809 GPIO_LOOKUP("INT33FC:01", 11, "panel", GPIO_ACTIVE_HIGH), 810 { } 811 }, 812 }; 813 814 static const struct pinctrl_map soc_pwm_pinctrl_map[] = { 815 PIN_MAP_MUX_GROUP("0000:00:02.0", "soc_pwm0", "INT33FC:00", 816 "pwm0_grp", "pwm"), 817 }; 818 819 void intel_dsi_vbt_gpio_init(struct intel_dsi *intel_dsi, bool panel_is_on) 820 { 821 struct drm_device *dev = intel_dsi->base.base.dev; 822 struct drm_i915_private *dev_priv = to_i915(dev); 823 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 824 enum gpiod_flags flags = panel_is_on ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW; 825 bool want_backlight_gpio = false; 826 bool want_panel_gpio = false; 827 struct pinctrl *pinctrl; 828 int ret; 829 830 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 831 mipi_config->pwm_blc == PPS_BLC_PMIC) { 832 gpiod_add_lookup_table(&pmic_panel_gpio_table); 833 want_panel_gpio = true; 834 } 835 836 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 837 gpiod_add_lookup_table(&soc_panel_gpio_table); 838 want_panel_gpio = true; 839 want_backlight_gpio = true; 840 841 /* Ensure PWM0 pin is muxed as PWM instead of GPIO */ 842 ret = pinctrl_register_mappings(soc_pwm_pinctrl_map, 843 ARRAY_SIZE(soc_pwm_pinctrl_map)); 844 if (ret) 845 DRM_ERROR("Failed to register pwm0 pinmux mapping\n"); 846 847 pinctrl = devm_pinctrl_get_select(dev->dev, "soc_pwm0"); 848 if (IS_ERR(pinctrl)) 849 DRM_ERROR("Failed to set pinmux to PWM\n"); 850 } 851 852 if (want_panel_gpio) { 853 intel_dsi->gpio_panel = gpiod_get(dev->dev, "panel", flags); 854 if (IS_ERR(intel_dsi->gpio_panel)) { 855 DRM_ERROR("Failed to own gpio for panel control\n"); 856 intel_dsi->gpio_panel = NULL; 857 } 858 } 859 860 if (want_backlight_gpio) { 861 intel_dsi->gpio_backlight = 862 gpiod_get(dev->dev, "backlight", flags); 863 if (IS_ERR(intel_dsi->gpio_backlight)) { 864 DRM_ERROR("Failed to own gpio for backlight control\n"); 865 intel_dsi->gpio_backlight = NULL; 866 } 867 } 868 } 869 870 void intel_dsi_vbt_gpio_cleanup(struct intel_dsi *intel_dsi) 871 { 872 struct drm_device *dev = intel_dsi->base.base.dev; 873 struct drm_i915_private *dev_priv = to_i915(dev); 874 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; 875 876 if (intel_dsi->gpio_panel) { 877 gpiod_put(intel_dsi->gpio_panel); 878 intel_dsi->gpio_panel = NULL; 879 } 880 881 if (intel_dsi->gpio_backlight) { 882 gpiod_put(intel_dsi->gpio_backlight); 883 intel_dsi->gpio_backlight = NULL; 884 } 885 886 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 887 mipi_config->pwm_blc == PPS_BLC_PMIC) 888 gpiod_remove_lookup_table(&pmic_panel_gpio_table); 889 890 if (IS_VALLEYVIEW(dev_priv) && mipi_config->pwm_blc == PPS_BLC_SOC) { 891 pinctrl_unregister_mappings(soc_pwm_pinctrl_map); 892 gpiod_remove_lookup_table(&soc_panel_gpio_table); 893 } 894 } 895