1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Leilk Liu <leilk.liu@mediatek.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/ioport.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_gpio.h> 16 #include <linux/platform_device.h> 17 #include <linux/platform_data/spi-mt65xx.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/spi/spi.h> 20 #include <linux/dma-mapping.h> 21 22 #define SPI_CFG0_REG 0x0000 23 #define SPI_CFG1_REG 0x0004 24 #define SPI_TX_SRC_REG 0x0008 25 #define SPI_RX_DST_REG 0x000c 26 #define SPI_TX_DATA_REG 0x0010 27 #define SPI_RX_DATA_REG 0x0014 28 #define SPI_CMD_REG 0x0018 29 #define SPI_STATUS0_REG 0x001c 30 #define SPI_PAD_SEL_REG 0x0024 31 #define SPI_CFG2_REG 0x0028 32 #define SPI_TX_SRC_REG_64 0x002c 33 #define SPI_RX_DST_REG_64 0x0030 34 35 #define SPI_CFG0_SCK_HIGH_OFFSET 0 36 #define SPI_CFG0_SCK_LOW_OFFSET 8 37 #define SPI_CFG0_CS_HOLD_OFFSET 16 38 #define SPI_CFG0_CS_SETUP_OFFSET 24 39 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET 0 40 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET 16 41 42 #define SPI_CFG1_CS_IDLE_OFFSET 0 43 #define SPI_CFG1_PACKET_LOOP_OFFSET 8 44 #define SPI_CFG1_PACKET_LENGTH_OFFSET 16 45 #define SPI_CFG1_GET_TICK_DLY_OFFSET 30 46 47 #define SPI_CFG1_CS_IDLE_MASK 0xff 48 #define SPI_CFG1_PACKET_LOOP_MASK 0xff00 49 #define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 50 #define SPI_CFG2_SCK_HIGH_OFFSET 0 51 #define SPI_CFG2_SCK_LOW_OFFSET 16 52 53 #define SPI_CMD_ACT BIT(0) 54 #define SPI_CMD_RESUME BIT(1) 55 #define SPI_CMD_RST BIT(2) 56 #define SPI_CMD_PAUSE_EN BIT(4) 57 #define SPI_CMD_DEASSERT BIT(5) 58 #define SPI_CMD_SAMPLE_SEL BIT(6) 59 #define SPI_CMD_CS_POL BIT(7) 60 #define SPI_CMD_CPHA BIT(8) 61 #define SPI_CMD_CPOL BIT(9) 62 #define SPI_CMD_RX_DMA BIT(10) 63 #define SPI_CMD_TX_DMA BIT(11) 64 #define SPI_CMD_TXMSBF BIT(12) 65 #define SPI_CMD_RXMSBF BIT(13) 66 #define SPI_CMD_RX_ENDIAN BIT(14) 67 #define SPI_CMD_TX_ENDIAN BIT(15) 68 #define SPI_CMD_FINISH_IE BIT(16) 69 #define SPI_CMD_PAUSE_IE BIT(17) 70 71 #define MT8173_SPI_MAX_PAD_SEL 3 72 73 #define MTK_SPI_PAUSE_INT_STATUS 0x2 74 75 #define MTK_SPI_IDLE 0 76 #define MTK_SPI_PAUSED 1 77 78 #define MTK_SPI_MAX_FIFO_SIZE 32U 79 #define MTK_SPI_PACKET_SIZE 1024 80 #define MTK_SPI_32BITS_MASK (0xffffffff) 81 82 #define DMA_ADDR_EXT_BITS (36) 83 #define DMA_ADDR_DEF_BITS (32) 84 85 struct mtk_spi_compatible { 86 bool need_pad_sel; 87 /* Must explicitly send dummy Tx bytes to do Rx only transfer */ 88 bool must_tx; 89 /* some IC design adjust cfg register to enhance time accuracy */ 90 bool enhance_timing; 91 /* some IC support DMA addr extension */ 92 bool dma_ext; 93 }; 94 95 struct mtk_spi { 96 void __iomem *base; 97 u32 state; 98 int pad_num; 99 u32 *pad_sel; 100 struct clk *parent_clk, *sel_clk, *spi_clk; 101 struct spi_transfer *cur_transfer; 102 u32 xfer_len; 103 u32 num_xfered; 104 struct scatterlist *tx_sgl, *rx_sgl; 105 u32 tx_sgl_len, rx_sgl_len; 106 const struct mtk_spi_compatible *dev_comp; 107 }; 108 109 static const struct mtk_spi_compatible mtk_common_compat; 110 111 static const struct mtk_spi_compatible mt2712_compat = { 112 .must_tx = true, 113 }; 114 115 static const struct mtk_spi_compatible mt6765_compat = { 116 .need_pad_sel = true, 117 .must_tx = true, 118 .enhance_timing = true, 119 .dma_ext = true, 120 }; 121 122 static const struct mtk_spi_compatible mt7622_compat = { 123 .must_tx = true, 124 .enhance_timing = true, 125 }; 126 127 static const struct mtk_spi_compatible mt8173_compat = { 128 .need_pad_sel = true, 129 .must_tx = true, 130 }; 131 132 static const struct mtk_spi_compatible mt8183_compat = { 133 .need_pad_sel = true, 134 .must_tx = true, 135 .enhance_timing = true, 136 }; 137 138 /* 139 * A piece of default chip info unless the platform 140 * supplies it. 141 */ 142 static const struct mtk_chip_config mtk_default_chip_info = { 143 .sample_sel = 0, 144 }; 145 146 static const struct of_device_id mtk_spi_of_match[] = { 147 { .compatible = "mediatek,mt2701-spi", 148 .data = (void *)&mtk_common_compat, 149 }, 150 { .compatible = "mediatek,mt2712-spi", 151 .data = (void *)&mt2712_compat, 152 }, 153 { .compatible = "mediatek,mt6589-spi", 154 .data = (void *)&mtk_common_compat, 155 }, 156 { .compatible = "mediatek,mt6765-spi", 157 .data = (void *)&mt6765_compat, 158 }, 159 { .compatible = "mediatek,mt7622-spi", 160 .data = (void *)&mt7622_compat, 161 }, 162 { .compatible = "mediatek,mt7629-spi", 163 .data = (void *)&mt7622_compat, 164 }, 165 { .compatible = "mediatek,mt8135-spi", 166 .data = (void *)&mtk_common_compat, 167 }, 168 { .compatible = "mediatek,mt8173-spi", 169 .data = (void *)&mt8173_compat, 170 }, 171 { .compatible = "mediatek,mt8183-spi", 172 .data = (void *)&mt8183_compat, 173 }, 174 { .compatible = "mediatek,mt8192-spi", 175 .data = (void *)&mt6765_compat, 176 }, 177 {} 178 }; 179 MODULE_DEVICE_TABLE(of, mtk_spi_of_match); 180 181 static void mtk_spi_reset(struct mtk_spi *mdata) 182 { 183 u32 reg_val; 184 185 /* set the software reset bit in SPI_CMD_REG. */ 186 reg_val = readl(mdata->base + SPI_CMD_REG); 187 reg_val |= SPI_CMD_RST; 188 writel(reg_val, mdata->base + SPI_CMD_REG); 189 190 reg_val = readl(mdata->base + SPI_CMD_REG); 191 reg_val &= ~SPI_CMD_RST; 192 writel(reg_val, mdata->base + SPI_CMD_REG); 193 } 194 195 static int mtk_spi_prepare_message(struct spi_master *master, 196 struct spi_message *msg) 197 { 198 u16 cpha, cpol; 199 u32 reg_val; 200 struct spi_device *spi = msg->spi; 201 struct mtk_chip_config *chip_config = spi->controller_data; 202 struct mtk_spi *mdata = spi_master_get_devdata(master); 203 204 cpha = spi->mode & SPI_CPHA ? 1 : 0; 205 cpol = spi->mode & SPI_CPOL ? 1 : 0; 206 207 reg_val = readl(mdata->base + SPI_CMD_REG); 208 if (cpha) 209 reg_val |= SPI_CMD_CPHA; 210 else 211 reg_val &= ~SPI_CMD_CPHA; 212 if (cpol) 213 reg_val |= SPI_CMD_CPOL; 214 else 215 reg_val &= ~SPI_CMD_CPOL; 216 217 /* set the mlsbx and mlsbtx */ 218 if (spi->mode & SPI_LSB_FIRST) { 219 reg_val &= ~SPI_CMD_TXMSBF; 220 reg_val &= ~SPI_CMD_RXMSBF; 221 } else { 222 reg_val |= SPI_CMD_TXMSBF; 223 reg_val |= SPI_CMD_RXMSBF; 224 } 225 226 /* set the tx/rx endian */ 227 #ifdef __LITTLE_ENDIAN 228 reg_val &= ~SPI_CMD_TX_ENDIAN; 229 reg_val &= ~SPI_CMD_RX_ENDIAN; 230 #else 231 reg_val |= SPI_CMD_TX_ENDIAN; 232 reg_val |= SPI_CMD_RX_ENDIAN; 233 #endif 234 235 if (mdata->dev_comp->enhance_timing) { 236 /* set CS polarity */ 237 if (spi->mode & SPI_CS_HIGH) 238 reg_val |= SPI_CMD_CS_POL; 239 else 240 reg_val &= ~SPI_CMD_CS_POL; 241 242 if (chip_config->sample_sel) 243 reg_val |= SPI_CMD_SAMPLE_SEL; 244 else 245 reg_val &= ~SPI_CMD_SAMPLE_SEL; 246 } 247 248 /* set finish and pause interrupt always enable */ 249 reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE; 250 251 /* disable dma mode */ 252 reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA); 253 254 /* disable deassert mode */ 255 reg_val &= ~SPI_CMD_DEASSERT; 256 257 writel(reg_val, mdata->base + SPI_CMD_REG); 258 259 /* pad select */ 260 if (mdata->dev_comp->need_pad_sel) 261 writel(mdata->pad_sel[spi->chip_select], 262 mdata->base + SPI_PAD_SEL_REG); 263 264 return 0; 265 } 266 267 static void mtk_spi_set_cs(struct spi_device *spi, bool enable) 268 { 269 u32 reg_val; 270 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); 271 272 if (spi->mode & SPI_CS_HIGH) 273 enable = !enable; 274 275 reg_val = readl(mdata->base + SPI_CMD_REG); 276 if (!enable) { 277 reg_val |= SPI_CMD_PAUSE_EN; 278 writel(reg_val, mdata->base + SPI_CMD_REG); 279 } else { 280 reg_val &= ~SPI_CMD_PAUSE_EN; 281 writel(reg_val, mdata->base + SPI_CMD_REG); 282 mdata->state = MTK_SPI_IDLE; 283 mtk_spi_reset(mdata); 284 } 285 } 286 287 static void mtk_spi_prepare_transfer(struct spi_master *master, 288 struct spi_transfer *xfer) 289 { 290 u32 spi_clk_hz, div, sck_time, cs_time, reg_val; 291 struct mtk_spi *mdata = spi_master_get_devdata(master); 292 293 spi_clk_hz = clk_get_rate(mdata->spi_clk); 294 if (xfer->speed_hz < spi_clk_hz / 2) 295 div = DIV_ROUND_UP(spi_clk_hz, xfer->speed_hz); 296 else 297 div = 1; 298 299 sck_time = (div + 1) / 2; 300 cs_time = sck_time * 2; 301 302 if (mdata->dev_comp->enhance_timing) { 303 reg_val = (((sck_time - 1) & 0xffff) 304 << SPI_CFG2_SCK_HIGH_OFFSET); 305 reg_val |= (((sck_time - 1) & 0xffff) 306 << SPI_CFG2_SCK_LOW_OFFSET); 307 writel(reg_val, mdata->base + SPI_CFG2_REG); 308 reg_val = (((cs_time - 1) & 0xffff) 309 << SPI_ADJUST_CFG0_CS_HOLD_OFFSET); 310 reg_val |= (((cs_time - 1) & 0xffff) 311 << SPI_ADJUST_CFG0_CS_SETUP_OFFSET); 312 writel(reg_val, mdata->base + SPI_CFG0_REG); 313 } else { 314 reg_val = (((sck_time - 1) & 0xff) 315 << SPI_CFG0_SCK_HIGH_OFFSET); 316 reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET); 317 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET); 318 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG0_CS_SETUP_OFFSET); 319 writel(reg_val, mdata->base + SPI_CFG0_REG); 320 } 321 322 reg_val = readl(mdata->base + SPI_CFG1_REG); 323 reg_val &= ~SPI_CFG1_CS_IDLE_MASK; 324 reg_val |= (((cs_time - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET); 325 writel(reg_val, mdata->base + SPI_CFG1_REG); 326 } 327 328 static void mtk_spi_setup_packet(struct spi_master *master) 329 { 330 u32 packet_size, packet_loop, reg_val; 331 struct mtk_spi *mdata = spi_master_get_devdata(master); 332 333 packet_size = min_t(u32, mdata->xfer_len, MTK_SPI_PACKET_SIZE); 334 packet_loop = mdata->xfer_len / packet_size; 335 336 reg_val = readl(mdata->base + SPI_CFG1_REG); 337 reg_val &= ~(SPI_CFG1_PACKET_LENGTH_MASK | SPI_CFG1_PACKET_LOOP_MASK); 338 reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET; 339 reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET; 340 writel(reg_val, mdata->base + SPI_CFG1_REG); 341 } 342 343 static void mtk_spi_enable_transfer(struct spi_master *master) 344 { 345 u32 cmd; 346 struct mtk_spi *mdata = spi_master_get_devdata(master); 347 348 cmd = readl(mdata->base + SPI_CMD_REG); 349 if (mdata->state == MTK_SPI_IDLE) 350 cmd |= SPI_CMD_ACT; 351 else 352 cmd |= SPI_CMD_RESUME; 353 writel(cmd, mdata->base + SPI_CMD_REG); 354 } 355 356 static int mtk_spi_get_mult_delta(u32 xfer_len) 357 { 358 u32 mult_delta; 359 360 if (xfer_len > MTK_SPI_PACKET_SIZE) 361 mult_delta = xfer_len % MTK_SPI_PACKET_SIZE; 362 else 363 mult_delta = 0; 364 365 return mult_delta; 366 } 367 368 static void mtk_spi_update_mdata_len(struct spi_master *master) 369 { 370 int mult_delta; 371 struct mtk_spi *mdata = spi_master_get_devdata(master); 372 373 if (mdata->tx_sgl_len && mdata->rx_sgl_len) { 374 if (mdata->tx_sgl_len > mdata->rx_sgl_len) { 375 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); 376 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; 377 mdata->rx_sgl_len = mult_delta; 378 mdata->tx_sgl_len -= mdata->xfer_len; 379 } else { 380 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); 381 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; 382 mdata->tx_sgl_len = mult_delta; 383 mdata->rx_sgl_len -= mdata->xfer_len; 384 } 385 } else if (mdata->tx_sgl_len) { 386 mult_delta = mtk_spi_get_mult_delta(mdata->tx_sgl_len); 387 mdata->xfer_len = mdata->tx_sgl_len - mult_delta; 388 mdata->tx_sgl_len = mult_delta; 389 } else if (mdata->rx_sgl_len) { 390 mult_delta = mtk_spi_get_mult_delta(mdata->rx_sgl_len); 391 mdata->xfer_len = mdata->rx_sgl_len - mult_delta; 392 mdata->rx_sgl_len = mult_delta; 393 } 394 } 395 396 static void mtk_spi_setup_dma_addr(struct spi_master *master, 397 struct spi_transfer *xfer) 398 { 399 struct mtk_spi *mdata = spi_master_get_devdata(master); 400 401 if (mdata->tx_sgl) { 402 writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK), 403 mdata->base + SPI_TX_SRC_REG); 404 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 405 if (mdata->dev_comp->dma_ext) 406 writel((u32)(xfer->tx_dma >> 32), 407 mdata->base + SPI_TX_SRC_REG_64); 408 #endif 409 } 410 411 if (mdata->rx_sgl) { 412 writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK), 413 mdata->base + SPI_RX_DST_REG); 414 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 415 if (mdata->dev_comp->dma_ext) 416 writel((u32)(xfer->rx_dma >> 32), 417 mdata->base + SPI_RX_DST_REG_64); 418 #endif 419 } 420 } 421 422 static int mtk_spi_fifo_transfer(struct spi_master *master, 423 struct spi_device *spi, 424 struct spi_transfer *xfer) 425 { 426 int cnt, remainder; 427 u32 reg_val; 428 struct mtk_spi *mdata = spi_master_get_devdata(master); 429 430 mdata->cur_transfer = xfer; 431 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len); 432 mdata->num_xfered = 0; 433 mtk_spi_prepare_transfer(master, xfer); 434 mtk_spi_setup_packet(master); 435 436 cnt = xfer->len / 4; 437 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt); 438 439 remainder = xfer->len % 4; 440 if (remainder > 0) { 441 reg_val = 0; 442 memcpy(®_val, xfer->tx_buf + (cnt * 4), remainder); 443 writel(reg_val, mdata->base + SPI_TX_DATA_REG); 444 } 445 446 mtk_spi_enable_transfer(master); 447 448 return 1; 449 } 450 451 static int mtk_spi_dma_transfer(struct spi_master *master, 452 struct spi_device *spi, 453 struct spi_transfer *xfer) 454 { 455 int cmd; 456 struct mtk_spi *mdata = spi_master_get_devdata(master); 457 458 mdata->tx_sgl = NULL; 459 mdata->rx_sgl = NULL; 460 mdata->tx_sgl_len = 0; 461 mdata->rx_sgl_len = 0; 462 mdata->cur_transfer = xfer; 463 mdata->num_xfered = 0; 464 465 mtk_spi_prepare_transfer(master, xfer); 466 467 cmd = readl(mdata->base + SPI_CMD_REG); 468 if (xfer->tx_buf) 469 cmd |= SPI_CMD_TX_DMA; 470 if (xfer->rx_buf) 471 cmd |= SPI_CMD_RX_DMA; 472 writel(cmd, mdata->base + SPI_CMD_REG); 473 474 if (xfer->tx_buf) 475 mdata->tx_sgl = xfer->tx_sg.sgl; 476 if (xfer->rx_buf) 477 mdata->rx_sgl = xfer->rx_sg.sgl; 478 479 if (mdata->tx_sgl) { 480 xfer->tx_dma = sg_dma_address(mdata->tx_sgl); 481 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); 482 } 483 if (mdata->rx_sgl) { 484 xfer->rx_dma = sg_dma_address(mdata->rx_sgl); 485 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); 486 } 487 488 mtk_spi_update_mdata_len(master); 489 mtk_spi_setup_packet(master); 490 mtk_spi_setup_dma_addr(master, xfer); 491 mtk_spi_enable_transfer(master); 492 493 return 1; 494 } 495 496 static int mtk_spi_transfer_one(struct spi_master *master, 497 struct spi_device *spi, 498 struct spi_transfer *xfer) 499 { 500 if (master->can_dma(master, spi, xfer)) 501 return mtk_spi_dma_transfer(master, spi, xfer); 502 else 503 return mtk_spi_fifo_transfer(master, spi, xfer); 504 } 505 506 static bool mtk_spi_can_dma(struct spi_master *master, 507 struct spi_device *spi, 508 struct spi_transfer *xfer) 509 { 510 /* Buffers for DMA transactions must be 4-byte aligned */ 511 return (xfer->len > MTK_SPI_MAX_FIFO_SIZE && 512 (unsigned long)xfer->tx_buf % 4 == 0 && 513 (unsigned long)xfer->rx_buf % 4 == 0); 514 } 515 516 static int mtk_spi_setup(struct spi_device *spi) 517 { 518 struct mtk_spi *mdata = spi_master_get_devdata(spi->master); 519 520 if (!spi->controller_data) 521 spi->controller_data = (void *)&mtk_default_chip_info; 522 523 if (mdata->dev_comp->need_pad_sel && gpio_is_valid(spi->cs_gpio)) 524 gpio_direction_output(spi->cs_gpio, !(spi->mode & SPI_CS_HIGH)); 525 526 return 0; 527 } 528 529 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id) 530 { 531 u32 cmd, reg_val, cnt, remainder, len; 532 struct spi_master *master = dev_id; 533 struct mtk_spi *mdata = spi_master_get_devdata(master); 534 struct spi_transfer *trans = mdata->cur_transfer; 535 536 reg_val = readl(mdata->base + SPI_STATUS0_REG); 537 if (reg_val & MTK_SPI_PAUSE_INT_STATUS) 538 mdata->state = MTK_SPI_PAUSED; 539 else 540 mdata->state = MTK_SPI_IDLE; 541 542 if (!master->can_dma(master, master->cur_msg->spi, trans)) { 543 if (trans->rx_buf) { 544 cnt = mdata->xfer_len / 4; 545 ioread32_rep(mdata->base + SPI_RX_DATA_REG, 546 trans->rx_buf + mdata->num_xfered, cnt); 547 remainder = mdata->xfer_len % 4; 548 if (remainder > 0) { 549 reg_val = readl(mdata->base + SPI_RX_DATA_REG); 550 memcpy(trans->rx_buf + 551 mdata->num_xfered + 552 (cnt * 4), 553 ®_val, 554 remainder); 555 } 556 } 557 558 mdata->num_xfered += mdata->xfer_len; 559 if (mdata->num_xfered == trans->len) { 560 spi_finalize_current_transfer(master); 561 return IRQ_HANDLED; 562 } 563 564 len = trans->len - mdata->num_xfered; 565 mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len); 566 mtk_spi_setup_packet(master); 567 568 cnt = mdata->xfer_len / 4; 569 iowrite32_rep(mdata->base + SPI_TX_DATA_REG, 570 trans->tx_buf + mdata->num_xfered, cnt); 571 572 remainder = mdata->xfer_len % 4; 573 if (remainder > 0) { 574 reg_val = 0; 575 memcpy(®_val, 576 trans->tx_buf + (cnt * 4) + mdata->num_xfered, 577 remainder); 578 writel(reg_val, mdata->base + SPI_TX_DATA_REG); 579 } 580 581 mtk_spi_enable_transfer(master); 582 583 return IRQ_HANDLED; 584 } 585 586 if (mdata->tx_sgl) 587 trans->tx_dma += mdata->xfer_len; 588 if (mdata->rx_sgl) 589 trans->rx_dma += mdata->xfer_len; 590 591 if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) { 592 mdata->tx_sgl = sg_next(mdata->tx_sgl); 593 if (mdata->tx_sgl) { 594 trans->tx_dma = sg_dma_address(mdata->tx_sgl); 595 mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl); 596 } 597 } 598 if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) { 599 mdata->rx_sgl = sg_next(mdata->rx_sgl); 600 if (mdata->rx_sgl) { 601 trans->rx_dma = sg_dma_address(mdata->rx_sgl); 602 mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl); 603 } 604 } 605 606 if (!mdata->tx_sgl && !mdata->rx_sgl) { 607 /* spi disable dma */ 608 cmd = readl(mdata->base + SPI_CMD_REG); 609 cmd &= ~SPI_CMD_TX_DMA; 610 cmd &= ~SPI_CMD_RX_DMA; 611 writel(cmd, mdata->base + SPI_CMD_REG); 612 613 spi_finalize_current_transfer(master); 614 return IRQ_HANDLED; 615 } 616 617 mtk_spi_update_mdata_len(master); 618 mtk_spi_setup_packet(master); 619 mtk_spi_setup_dma_addr(master, trans); 620 mtk_spi_enable_transfer(master); 621 622 return IRQ_HANDLED; 623 } 624 625 static int mtk_spi_probe(struct platform_device *pdev) 626 { 627 struct spi_master *master; 628 struct mtk_spi *mdata; 629 const struct of_device_id *of_id; 630 int i, irq, ret, addr_bits; 631 632 master = spi_alloc_master(&pdev->dev, sizeof(*mdata)); 633 if (!master) { 634 dev_err(&pdev->dev, "failed to alloc spi master\n"); 635 return -ENOMEM; 636 } 637 638 master->auto_runtime_pm = true; 639 master->dev.of_node = pdev->dev.of_node; 640 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; 641 642 master->set_cs = mtk_spi_set_cs; 643 master->prepare_message = mtk_spi_prepare_message; 644 master->transfer_one = mtk_spi_transfer_one; 645 master->can_dma = mtk_spi_can_dma; 646 master->setup = mtk_spi_setup; 647 648 of_id = of_match_node(mtk_spi_of_match, pdev->dev.of_node); 649 if (!of_id) { 650 dev_err(&pdev->dev, "failed to probe of_node\n"); 651 ret = -EINVAL; 652 goto err_put_master; 653 } 654 655 mdata = spi_master_get_devdata(master); 656 mdata->dev_comp = of_id->data; 657 658 if (mdata->dev_comp->enhance_timing) 659 master->mode_bits |= SPI_CS_HIGH; 660 661 if (mdata->dev_comp->must_tx) 662 master->flags = SPI_MASTER_MUST_TX; 663 664 if (mdata->dev_comp->need_pad_sel) { 665 mdata->pad_num = of_property_count_u32_elems( 666 pdev->dev.of_node, 667 "mediatek,pad-select"); 668 if (mdata->pad_num < 0) { 669 dev_err(&pdev->dev, 670 "No 'mediatek,pad-select' property\n"); 671 ret = -EINVAL; 672 goto err_put_master; 673 } 674 675 mdata->pad_sel = devm_kmalloc_array(&pdev->dev, mdata->pad_num, 676 sizeof(u32), GFP_KERNEL); 677 if (!mdata->pad_sel) { 678 ret = -ENOMEM; 679 goto err_put_master; 680 } 681 682 for (i = 0; i < mdata->pad_num; i++) { 683 of_property_read_u32_index(pdev->dev.of_node, 684 "mediatek,pad-select", 685 i, &mdata->pad_sel[i]); 686 if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL) { 687 dev_err(&pdev->dev, "wrong pad-sel[%d]: %u\n", 688 i, mdata->pad_sel[i]); 689 ret = -EINVAL; 690 goto err_put_master; 691 } 692 } 693 } 694 695 platform_set_drvdata(pdev, master); 696 mdata->base = devm_platform_ioremap_resource(pdev, 0); 697 if (IS_ERR(mdata->base)) { 698 ret = PTR_ERR(mdata->base); 699 goto err_put_master; 700 } 701 702 irq = platform_get_irq(pdev, 0); 703 if (irq < 0) { 704 ret = irq; 705 goto err_put_master; 706 } 707 708 if (!pdev->dev.dma_mask) 709 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; 710 711 ret = devm_request_irq(&pdev->dev, irq, mtk_spi_interrupt, 712 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), master); 713 if (ret) { 714 dev_err(&pdev->dev, "failed to register irq (%d)\n", ret); 715 goto err_put_master; 716 } 717 718 mdata->parent_clk = devm_clk_get(&pdev->dev, "parent-clk"); 719 if (IS_ERR(mdata->parent_clk)) { 720 ret = PTR_ERR(mdata->parent_clk); 721 dev_err(&pdev->dev, "failed to get parent-clk: %d\n", ret); 722 goto err_put_master; 723 } 724 725 mdata->sel_clk = devm_clk_get(&pdev->dev, "sel-clk"); 726 if (IS_ERR(mdata->sel_clk)) { 727 ret = PTR_ERR(mdata->sel_clk); 728 dev_err(&pdev->dev, "failed to get sel-clk: %d\n", ret); 729 goto err_put_master; 730 } 731 732 mdata->spi_clk = devm_clk_get(&pdev->dev, "spi-clk"); 733 if (IS_ERR(mdata->spi_clk)) { 734 ret = PTR_ERR(mdata->spi_clk); 735 dev_err(&pdev->dev, "failed to get spi-clk: %d\n", ret); 736 goto err_put_master; 737 } 738 739 ret = clk_prepare_enable(mdata->spi_clk); 740 if (ret < 0) { 741 dev_err(&pdev->dev, "failed to enable spi_clk (%d)\n", ret); 742 goto err_put_master; 743 } 744 745 ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk); 746 if (ret < 0) { 747 dev_err(&pdev->dev, "failed to clk_set_parent (%d)\n", ret); 748 clk_disable_unprepare(mdata->spi_clk); 749 goto err_put_master; 750 } 751 752 clk_disable_unprepare(mdata->spi_clk); 753 754 pm_runtime_enable(&pdev->dev); 755 756 ret = devm_spi_register_master(&pdev->dev, master); 757 if (ret) { 758 dev_err(&pdev->dev, "failed to register master (%d)\n", ret); 759 goto err_disable_runtime_pm; 760 } 761 762 if (mdata->dev_comp->need_pad_sel) { 763 if (mdata->pad_num != master->num_chipselect) { 764 dev_err(&pdev->dev, 765 "pad_num does not match num_chipselect(%d != %d)\n", 766 mdata->pad_num, master->num_chipselect); 767 ret = -EINVAL; 768 goto err_disable_runtime_pm; 769 } 770 771 if (!master->cs_gpios && master->num_chipselect > 1) { 772 dev_err(&pdev->dev, 773 "cs_gpios not specified and num_chipselect > 1\n"); 774 ret = -EINVAL; 775 goto err_disable_runtime_pm; 776 } 777 778 if (master->cs_gpios) { 779 for (i = 0; i < master->num_chipselect; i++) { 780 ret = devm_gpio_request(&pdev->dev, 781 master->cs_gpios[i], 782 dev_name(&pdev->dev)); 783 if (ret) { 784 dev_err(&pdev->dev, 785 "can't get CS GPIO %i\n", i); 786 goto err_disable_runtime_pm; 787 } 788 } 789 } 790 } 791 792 if (mdata->dev_comp->dma_ext) 793 addr_bits = DMA_ADDR_EXT_BITS; 794 else 795 addr_bits = DMA_ADDR_DEF_BITS; 796 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(addr_bits)); 797 if (ret) 798 dev_notice(&pdev->dev, "SPI dma_set_mask(%d) failed, ret:%d\n", 799 addr_bits, ret); 800 801 return 0; 802 803 err_disable_runtime_pm: 804 pm_runtime_disable(&pdev->dev); 805 err_put_master: 806 spi_master_put(master); 807 808 return ret; 809 } 810 811 static int mtk_spi_remove(struct platform_device *pdev) 812 { 813 struct spi_master *master = platform_get_drvdata(pdev); 814 struct mtk_spi *mdata = spi_master_get_devdata(master); 815 816 pm_runtime_disable(&pdev->dev); 817 818 mtk_spi_reset(mdata); 819 820 return 0; 821 } 822 823 #ifdef CONFIG_PM_SLEEP 824 static int mtk_spi_suspend(struct device *dev) 825 { 826 int ret; 827 struct spi_master *master = dev_get_drvdata(dev); 828 struct mtk_spi *mdata = spi_master_get_devdata(master); 829 830 ret = spi_master_suspend(master); 831 if (ret) 832 return ret; 833 834 if (!pm_runtime_suspended(dev)) 835 clk_disable_unprepare(mdata->spi_clk); 836 837 return ret; 838 } 839 840 static int mtk_spi_resume(struct device *dev) 841 { 842 int ret; 843 struct spi_master *master = dev_get_drvdata(dev); 844 struct mtk_spi *mdata = spi_master_get_devdata(master); 845 846 if (!pm_runtime_suspended(dev)) { 847 ret = clk_prepare_enable(mdata->spi_clk); 848 if (ret < 0) { 849 dev_err(dev, "failed to enable spi_clk (%d)\n", ret); 850 return ret; 851 } 852 } 853 854 ret = spi_master_resume(master); 855 if (ret < 0) 856 clk_disable_unprepare(mdata->spi_clk); 857 858 return ret; 859 } 860 #endif /* CONFIG_PM_SLEEP */ 861 862 #ifdef CONFIG_PM 863 static int mtk_spi_runtime_suspend(struct device *dev) 864 { 865 struct spi_master *master = dev_get_drvdata(dev); 866 struct mtk_spi *mdata = spi_master_get_devdata(master); 867 868 clk_disable_unprepare(mdata->spi_clk); 869 870 return 0; 871 } 872 873 static int mtk_spi_runtime_resume(struct device *dev) 874 { 875 struct spi_master *master = dev_get_drvdata(dev); 876 struct mtk_spi *mdata = spi_master_get_devdata(master); 877 int ret; 878 879 ret = clk_prepare_enable(mdata->spi_clk); 880 if (ret < 0) { 881 dev_err(dev, "failed to enable spi_clk (%d)\n", ret); 882 return ret; 883 } 884 885 return 0; 886 } 887 #endif /* CONFIG_PM */ 888 889 static const struct dev_pm_ops mtk_spi_pm = { 890 SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume) 891 SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend, 892 mtk_spi_runtime_resume, NULL) 893 }; 894 895 static struct platform_driver mtk_spi_driver = { 896 .driver = { 897 .name = "mtk-spi", 898 .pm = &mtk_spi_pm, 899 .of_match_table = mtk_spi_of_match, 900 }, 901 .probe = mtk_spi_probe, 902 .remove = mtk_spi_remove, 903 }; 904 905 module_platform_driver(mtk_spi_driver); 906 907 MODULE_DESCRIPTION("MTK SPI Controller driver"); 908 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>"); 909 MODULE_LICENSE("GPL v2"); 910 MODULE_ALIAS("platform:mtk-spi"); 911