1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM memory mapped architected timer
8
9maintainers:
10  - Marc Zyngier <marc.zyngier@arm.com>
11  - Mark Rutland <mark.rutland@arm.com>
12
13description: |+
14  ARM cores may have a memory mapped architected timer, which provides up to 8
15  frames with a physical and optional virtual timer per frame.
16
17  The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
18
19properties:
20  compatible:
21    items:
22      - enum:
23          - arm,armv7-timer-mem
24
25  reg:
26    maxItems: 1
27    description: The control frame base address
28
29  '#address-cells':
30    enum: [1, 2]
31
32  '#size-cells':
33    const: 1
34
35  ranges: true
36
37  clock-frequency:
38    description: The frequency of the main counter, in Hz. Should be present
39      only where necessary to work around broken firmware which does not configure
40      CNTFRQ on all CPUs to a uniform correct value. Use of this property is
41      strongly discouraged; fix your firmware unless absolutely impossible.
42
43  always-on:
44    type: boolean
45    description: If present, the timer is powered through an always-on power
46      domain, therefore it never loses context.
47
48  arm,cpu-registers-not-fw-configured:
49    type: boolean
50    description: Firmware does not initialize any of the generic timer CPU
51      registers, which contain their architecturally-defined reset values. Only
52      supported for 32-bit systems which follow the ARMv7 architected reset
53      values.
54
55  arm,no-tick-in-suspend:
56    type: boolean
57    description: The main counter does not tick when the system is in
58      low-power system suspend on some SoCs. This behavior does not match the
59      Architecture Reference Manual's specification that the system counter "must
60      be implemented in an always-on power domain."
61
62patternProperties:
63  '^frame@[0-9a-z]*$':
64    type: object
65    description: A timer node has up to 8 frame sub-nodes, each with the following properties.
66    properties:
67      frame-number:
68        $ref: "/schemas/types.yaml#/definitions/uint32"
69        minimum: 0
70        maximum: 7
71
72      interrupts:
73        minItems: 1
74        maxItems: 2
75        items:
76          - description: physical timer irq
77          - description: virtual timer irq
78
79      reg:
80        minItems: 1
81        maxItems: 2
82        items:
83          - description: 1st view base address
84          - description: 2nd optional view base address
85
86    required:
87      - frame-number
88      - interrupts
89      - reg
90
91required:
92  - compatible
93  - reg
94  - '#address-cells'
95  - '#size-cells'
96
97additionalProperties: false
98
99examples:
100  - |
101    timer@f0000000 {
102      compatible = "arm,armv7-timer-mem";
103      #address-cells = <1>;
104      #size-cells = <1>;
105      ranges = <0 0xf0001000 0x1000>;
106      reg = <0xf0000000 0x1000>;
107      clock-frequency = <50000000>;
108
109      frame@0 {
110        frame-number = <0>;
111        interrupts = <0 13 0x8>,
112               <0 14 0x8>;
113        reg = <0x0000 0x1000>,
114              <0x1000 0x1000>;
115      };
116
117      frame@2000 {
118        frame-number = <1>;
119        interrupts = <0 15 0x8>;
120        reg = <0x2000 0x1000>;
121      };
122    };
123
124...
125