1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/arm/cpus.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM CPUs bindings
8
9maintainers:
10  - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11
12description: |+
13  The device tree allows to describe the layout of CPUs in a system through
14  the "cpus" node, which in turn contains a number of subnodes (ie "cpu")
15  defining properties for every cpu.
16
17  Bindings for CPU nodes follow the Devicetree Specification, available from:
18
19  https://www.devicetree.org/specifications/
20
21  with updates for 32-bit and 64-bit ARM systems provided in this document.
22
23  ================================
24  Convention used in this document
25  ================================
26
27  This document follows the conventions described in the Devicetree
28  Specification, with the addition:
29
30  - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31    the reg property contained in bits 7 down to 0
32
33  =====================================
34  cpus and cpu node bindings definition
35  =====================================
36
37  The ARM architecture, in accordance with the Devicetree Specification,
38  requires the cpus and cpu nodes to be present and contain the properties
39  described below.
40
41properties:
42  reg:
43    maxItems: 1
44    description: |
45      Usage and definition depend on ARM architecture version and
46      configuration:
47
48      On uniprocessor ARM architectures previous to v7
49      this property is required and must be set to 0.
50
51      On ARM 11 MPcore based systems this property is
52        required and matches the CPUID[11:0] register bits.
53
54        Bits [11:0] in the reg cell must be set to
55        bits [11:0] in CPU ID register.
56
57        All other bits in the reg cell must be set to 0.
58
59      On 32-bit ARM v7 or later systems this property is
60        required and matches the CPU MPIDR[23:0] register
61        bits.
62
63        Bits [23:0] in the reg cell must be set to
64        bits [23:0] in MPIDR.
65
66        All other bits in the reg cell must be set to 0.
67
68      On ARM v8 64-bit systems this property is required
69        and matches the MPIDR_EL1 register affinity bits.
70
71        * If cpus node's #address-cells property is set to 2
72
73          The first reg cell bits [7:0] must be set to
74          bits [39:32] of MPIDR_EL1.
75
76          The second reg cell bits [23:0] must be set to
77          bits [23:0] of MPIDR_EL1.
78
79        * If cpus node's #address-cells property is set to 1
80
81          The reg cell bits [23:0] must be set to bits [23:0]
82          of MPIDR_EL1.
83
84      All other bits in the reg cells must be set to 0.
85
86  compatible:
87    enum:
88      - arm,arm710t
89      - arm,arm720t
90      - arm,arm740t
91      - arm,arm7ej-s
92      - arm,arm7tdmi
93      - arm,arm7tdmi-s
94      - arm,arm9es
95      - arm,arm9ej-s
96      - arm,arm920t
97      - arm,arm922t
98      - arm,arm925
99      - arm,arm926e-s
100      - arm,arm926ej-s
101      - arm,arm940t
102      - arm,arm946e-s
103      - arm,arm966e-s
104      - arm,arm968e-s
105      - arm,arm9tdmi
106      - arm,arm1020e
107      - arm,arm1020t
108      - arm,arm1022e
109      - arm,arm1026ej-s
110      - arm,arm1136j-s
111      - arm,arm1136jf-s
112      - arm,arm1156t2-s
113      - arm,arm1156t2f-s
114      - arm,arm1176jzf
115      - arm,arm1176jz-s
116      - arm,arm1176jzf-s
117      - arm,arm11mpcore
118      - arm,armv8 # Only for s/w models
119      - arm,cortex-a5
120      - arm,cortex-a7
121      - arm,cortex-a8
122      - arm,cortex-a9
123      - arm,cortex-a12
124      - arm,cortex-a15
125      - arm,cortex-a17
126      - arm,cortex-a32
127      - arm,cortex-a34
128      - arm,cortex-a35
129      - arm,cortex-a53
130      - arm,cortex-a55
131      - arm,cortex-a57
132      - arm,cortex-a65
133      - arm,cortex-a72
134      - arm,cortex-a73
135      - arm,cortex-a75
136      - arm,cortex-a76
137      - arm,cortex-a77
138      - arm,cortex-m0
139      - arm,cortex-m0+
140      - arm,cortex-m1
141      - arm,cortex-m3
142      - arm,cortex-m4
143      - arm,cortex-r4
144      - arm,cortex-r5
145      - arm,cortex-r7
146      - arm,neoverse-e1
147      - arm,neoverse-n1
148      - brcm,brahma-b15
149      - brcm,brahma-b53
150      - brcm,vulcan
151      - cavium,thunder
152      - cavium,thunder2
153      - faraday,fa526
154      - intel,sa110
155      - intel,sa1100
156      - marvell,feroceon
157      - marvell,mohawk
158      - marvell,pj4a
159      - marvell,pj4b
160      - marvell,sheeva-v5
161      - marvell,sheeva-v7
162      - nvidia,tegra132-denver
163      - nvidia,tegra186-denver
164      - nvidia,tegra194-carmel
165      - qcom,krait
166      - qcom,kryo
167      - qcom,kryo260
168      - qcom,kryo280
169      - qcom,kryo385
170      - qcom,kryo468
171      - qcom,kryo485
172      - qcom,scorpion
173
174  enable-method:
175    $ref: '/schemas/types.yaml#/definitions/string'
176    oneOf:
177      # On ARM v8 64-bit this property is required
178      - enum:
179          - psci
180          - spin-table
181      # On ARM 32-bit systems this property is optional
182      - enum:
183          - actions,s500-smp
184          - allwinner,sun6i-a31
185          - allwinner,sun8i-a23
186          - allwinner,sun9i-a80-smp
187          - allwinner,sun8i-a83t-smp
188          - amlogic,meson8-smp
189          - amlogic,meson8b-smp
190          - arm,realview-smp
191          - aspeed,ast2600-smp
192          - brcm,bcm11351-cpu-method
193          - brcm,bcm23550
194          - brcm,bcm2836-smp
195          - brcm,bcm63138
196          - brcm,bcm-nsp-smp
197          - brcm,brahma-b15
198          - marvell,armada-375-smp
199          - marvell,armada-380-smp
200          - marvell,armada-390-smp
201          - marvell,armada-xp-smp
202          - marvell,98dx3236-smp
203          - marvell,mmp3-smp
204          - mediatek,mt6589-smp
205          - mediatek,mt81xx-tz-smp
206          - qcom,gcc-msm8660
207          - qcom,kpss-acc-v1
208          - qcom,kpss-acc-v2
209          - renesas,apmu
210          - renesas,r9a06g032-smp
211          - rockchip,rk3036-smp
212          - rockchip,rk3066-smp
213          - socionext,milbeaut-m10v-smp
214          - ste,dbx500-smp
215          - ti,am3352
216          - ti,am4372
217
218  cpu-release-addr:
219    $ref: '/schemas/types.yaml#/definitions/uint64'
220
221    description:
222      Required for systems that have an "enable-method"
223        property value of "spin-table".
224      On ARM v8 64-bit systems must be a two cell
225        property identifying a 64-bit zero-initialised
226        memory location.
227
228  cpu-idle-states:
229    $ref: '/schemas/types.yaml#/definitions/phandle-array'
230    description: |
231      List of phandles to idle state nodes supported
232      by this cpu (see ./idle-states.yaml).
233
234  capacity-dmips-mhz:
235    $ref: '/schemas/types.yaml#/definitions/uint32'
236    description:
237      u32 value representing CPU capacity (see ./cpu-capacity.txt) in
238      DMIPS/MHz, relative to highest capacity-dmips-mhz
239      in the system.
240
241  dynamic-power-coefficient:
242    $ref: '/schemas/types.yaml#/definitions/uint32'
243    description:
244      A u32 value that represents the running time dynamic
245      power coefficient in units of uW/MHz/V^2. The
246      coefficient can either be calculated from power
247      measurements or derived by analysis.
248
249      The dynamic power consumption of the CPU  is
250      proportional to the square of the Voltage (V) and
251      the clock frequency (f). The coefficient is used to
252      calculate the dynamic power as below -
253
254      Pdyn = dynamic-power-coefficient * V^2 * f
255
256      where voltage is in V, frequency is in MHz.
257
258  power-domains:
259    $ref: '/schemas/types.yaml#/definitions/phandle-array'
260    description:
261      List of phandles and PM domain specifiers, as defined by bindings of the
262      PM domain provider (see also ../power_domain.txt).
263
264  power-domain-names:
265    $ref: '/schemas/types.yaml#/definitions/string-array'
266    description:
267      A list of power domain name strings sorted in the same order as the
268      power-domains property.
269
270      For PSCI based platforms, the name corresponding to the index of the PSCI
271      PM domain provider, must be "psci".
272
273  qcom,saw:
274    $ref: '/schemas/types.yaml#/definitions/phandle'
275    description: |
276      Specifies the SAW* node associated with this CPU.
277
278      Required for systems that have an "enable-method" property
279      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
280
281      * arm/msm/qcom,saw2.txt
282
283  qcom,acc:
284    $ref: '/schemas/types.yaml#/definitions/phandle'
285    description: |
286      Specifies the ACC* node associated with this CPU.
287
288      Required for systems that have an "enable-method" property
289      value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
290
291      * arm/msm/qcom,kpss-acc.txt
292
293  rockchip,pmu:
294    $ref: '/schemas/types.yaml#/definitions/phandle'
295    description: |
296      Specifies the syscon node controlling the cpu core power domains.
297
298      Optional for systems that have an "enable-method"
299      property value of "rockchip,rk3066-smp"
300      While optional, it is the preferred way to get access to
301      the cpu-core power-domains.
302
303  secondary-boot-reg:
304    $ref: '/schemas/types.yaml#/definitions/uint32'
305    description: |
306      Required for systems that have an "enable-method" property value of
307      "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
308
309      This includes the following SoCs: |
310      BCM11130, BCM11140, BCM11351, BCM28145, BCM28155, BCM21664, BCM23550
311      BCM58522, BCM58525, BCM58535, BCM58622, BCM58623, BCM58625, BCM88312
312
313      The secondary-boot-reg property is a u32 value that specifies the
314      physical address of the register used to request the ROM holding pen
315      code release a secondary CPU. The value written to the register is
316      formed by encoding the target CPU id into the low bits of the
317      physical start address it should jump to.
318
319if:
320  # If the enable-method property contains one of those values
321  properties:
322    enable-method:
323      contains:
324        enum:
325          - brcm,bcm11351-cpu-method
326          - brcm,bcm23550
327          - brcm,bcm-nsp-smp
328  # and if enable-method is present
329  required:
330    - enable-method
331
332then:
333   required:
334     - secondary-boot-reg
335
336required:
337  - device_type
338  - reg
339  - compatible
340
341dependencies:
342  rockchip,pmu: [enable-method]
343
344examples:
345  - |
346    cpus {
347      #size-cells = <0>;
348      #address-cells = <1>;
349
350      cpu@0 {
351        device_type = "cpu";
352        compatible = "arm,cortex-a15";
353        reg = <0x0>;
354      };
355
356      cpu@1 {
357        device_type = "cpu";
358        compatible = "arm,cortex-a15";
359        reg = <0x1>;
360      };
361
362      cpu@100 {
363        device_type = "cpu";
364        compatible = "arm,cortex-a7";
365        reg = <0x100>;
366      };
367
368      cpu@101 {
369        device_type = "cpu";
370        compatible = "arm,cortex-a7";
371        reg = <0x101>;
372      };
373    };
374
375  - |
376    // Example 2 (Cortex-A8 uniprocessor 32-bit system):
377    cpus {
378      #size-cells = <0>;
379      #address-cells = <1>;
380
381      cpu@0 {
382        device_type = "cpu";
383        compatible = "arm,cortex-a8";
384        reg = <0x0>;
385      };
386    };
387
388  - |
389    // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
390    cpus {
391      #size-cells = <0>;
392      #address-cells = <1>;
393
394      cpu@0 {
395        device_type = "cpu";
396        compatible = "arm,arm926ej-s";
397        reg = <0x0>;
398      };
399    };
400
401  - |
402    //  Example 4 (ARM Cortex-A57 64-bit system):
403    cpus {
404      #size-cells = <0>;
405      #address-cells = <2>;
406
407      cpu@0 {
408        device_type = "cpu";
409        compatible = "arm,cortex-a57";
410        reg = <0x0 0x0>;
411        enable-method = "spin-table";
412        cpu-release-addr = <0 0x20000000>;
413      };
414
415      cpu@1 {
416        device_type = "cpu";
417        compatible = "arm,cortex-a57";
418        reg = <0x0 0x1>;
419        enable-method = "spin-table";
420        cpu-release-addr = <0 0x20000000>;
421      };
422
423      cpu@100 {
424        device_type = "cpu";
425        compatible = "arm,cortex-a57";
426        reg = <0x0 0x100>;
427        enable-method = "spin-table";
428        cpu-release-addr = <0 0x20000000>;
429      };
430
431      cpu@101 {
432        device_type = "cpu";
433        compatible = "arm,cortex-a57";
434        reg = <0x0 0x101>;
435        enable-method = "spin-table";
436        cpu-release-addr = <0 0x20000000>;
437      };
438
439      cpu@10000 {
440        device_type = "cpu";
441        compatible = "arm,cortex-a57";
442        reg = <0x0 0x10000>;
443        enable-method = "spin-table";
444        cpu-release-addr = <0 0x20000000>;
445      };
446
447      cpu@10001 {
448        device_type = "cpu";
449        compatible = "arm,cortex-a57";
450        reg = <0x0 0x10001>;
451        enable-method = "spin-table";
452        cpu-release-addr = <0 0x20000000>;
453      };
454
455      cpu@10100 {
456        device_type = "cpu";
457        compatible = "arm,cortex-a57";
458        reg = <0x0 0x10100>;
459        enable-method = "spin-table";
460        cpu-release-addr = <0 0x20000000>;
461      };
462
463      cpu@10101 {
464        device_type = "cpu";
465        compatible = "arm,cortex-a57";
466        reg = <0x0 0x10101>;
467        enable-method = "spin-table";
468        cpu-release-addr = <0 0x20000000>;
469      };
470
471      cpu@100000000 {
472        device_type = "cpu";
473        compatible = "arm,cortex-a57";
474        reg = <0x1 0x0>;
475        enable-method = "spin-table";
476        cpu-release-addr = <0 0x20000000>;
477      };
478
479      cpu@100000001 {
480        device_type = "cpu";
481        compatible = "arm,cortex-a57";
482        reg = <0x1 0x1>;
483        enable-method = "spin-table";
484        cpu-release-addr = <0 0x20000000>;
485      };
486
487      cpu@100000100 {
488        device_type = "cpu";
489        compatible = "arm,cortex-a57";
490        reg = <0x1 0x100>;
491        enable-method = "spin-table";
492        cpu-release-addr = <0 0x20000000>;
493      };
494
495      cpu@100000101 {
496        device_type = "cpu";
497        compatible = "arm,cortex-a57";
498        reg = <0x1 0x101>;
499        enable-method = "spin-table";
500        cpu-release-addr = <0 0x20000000>;
501      };
502
503      cpu@100010000 {
504        device_type = "cpu";
505        compatible = "arm,cortex-a57";
506        reg = <0x1 0x10000>;
507        enable-method = "spin-table";
508        cpu-release-addr = <0 0x20000000>;
509      };
510
511      cpu@100010001 {
512        device_type = "cpu";
513        compatible = "arm,cortex-a57";
514        reg = <0x1 0x10001>;
515        enable-method = "spin-table";
516        cpu-release-addr = <0 0x20000000>;
517      };
518
519      cpu@100010100 {
520        device_type = "cpu";
521        compatible = "arm,cortex-a57";
522        reg = <0x1 0x10100>;
523        enable-method = "spin-table";
524        cpu-release-addr = <0 0x20000000>;
525      };
526
527      cpu@100010101 {
528        device_type = "cpu";
529        compatible = "arm,cortex-a57";
530        reg = <0x1 0x10101>;
531        enable-method = "spin-table";
532        cpu-release-addr = <0 0x20000000>;
533      };
534    };
535...
536