1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/include/asm/kvm_host.h: 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #ifndef __ARM64_KVM_HOST_H__ 12 #define __ARM64_KVM_HOST_H__ 13 14 #include <linux/bitmap.h> 15 #include <linux/types.h> 16 #include <linux/jump_label.h> 17 #include <linux/kvm_types.h> 18 #include <linux/percpu.h> 19 #include <asm/arch_gicv3.h> 20 #include <asm/barrier.h> 21 #include <asm/cpufeature.h> 22 #include <asm/cputype.h> 23 #include <asm/daifflags.h> 24 #include <asm/fpsimd.h> 25 #include <asm/kvm.h> 26 #include <asm/kvm_asm.h> 27 #include <asm/thread_info.h> 28 29 #define __KVM_HAVE_ARCH_INTC_INITIALIZED 30 31 #define KVM_USER_MEM_SLOTS 512 32 #define KVM_HALT_POLL_NS_DEFAULT 500000 33 34 #include <kvm/arm_vgic.h> 35 #include <kvm/arm_arch_timer.h> 36 #include <kvm/arm_pmu.h> 37 38 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS 39 40 #define KVM_VCPU_MAX_FEATURES 7 41 42 #define KVM_REQ_SLEEP \ 43 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP) 44 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1) 45 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2) 46 #define KVM_REQ_RECORD_STEAL KVM_ARCH_REQ(3) 47 #define KVM_REQ_RELOAD_GICv4 KVM_ARCH_REQ(4) 48 49 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use); 50 51 extern unsigned int kvm_sve_max_vl; 52 int kvm_arm_init_sve(void); 53 54 int __attribute_const__ kvm_target_cpu(void); 55 int kvm_reset_vcpu(struct kvm_vcpu *vcpu); 56 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu); 57 int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext); 58 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start); 59 60 struct kvm_vmid { 61 /* The VMID generation used for the virt. memory system */ 62 u64 vmid_gen; 63 u32 vmid; 64 }; 65 66 struct kvm_arch { 67 struct kvm_vmid vmid; 68 69 /* stage2 entry level table */ 70 pgd_t *pgd; 71 phys_addr_t pgd_phys; 72 73 /* VTCR_EL2 value for this VM */ 74 u64 vtcr; 75 76 /* The last vcpu id that ran on each physical CPU */ 77 int __percpu *last_vcpu_ran; 78 79 /* The maximum number of vCPUs depends on the used GIC model */ 80 int max_vcpus; 81 82 /* Interrupt controller */ 83 struct vgic_dist vgic; 84 85 /* Mandated version of PSCI */ 86 u32 psci_version; 87 88 /* 89 * If we encounter a data abort without valid instruction syndrome 90 * information, report this to user space. User space can (and 91 * should) opt in to this feature if KVM_CAP_ARM_NISV_TO_USER is 92 * supported. 93 */ 94 bool return_nisv_io_abort_to_user; 95 }; 96 97 #define KVM_NR_MEM_OBJS 40 98 99 /* 100 * We don't want allocation failures within the mmu code, so we preallocate 101 * enough memory for a single page fault in a cache. 102 */ 103 struct kvm_mmu_memory_cache { 104 int nobjs; 105 void *objects[KVM_NR_MEM_OBJS]; 106 }; 107 108 struct kvm_vcpu_fault_info { 109 u32 esr_el2; /* Hyp Syndrom Register */ 110 u64 far_el2; /* Hyp Fault Address Register */ 111 u64 hpfar_el2; /* Hyp IPA Fault Address Register */ 112 u64 disr_el1; /* Deferred [SError] Status Register */ 113 }; 114 115 /* 116 * 0 is reserved as an invalid value. 117 * Order should be kept in sync with the save/restore code. 118 */ 119 enum vcpu_sysreg { 120 __INVALID_SYSREG__, 121 MPIDR_EL1, /* MultiProcessor Affinity Register */ 122 CSSELR_EL1, /* Cache Size Selection Register */ 123 SCTLR_EL1, /* System Control Register */ 124 ACTLR_EL1, /* Auxiliary Control Register */ 125 CPACR_EL1, /* Coprocessor Access Control */ 126 ZCR_EL1, /* SVE Control */ 127 TTBR0_EL1, /* Translation Table Base Register 0 */ 128 TTBR1_EL1, /* Translation Table Base Register 1 */ 129 TCR_EL1, /* Translation Control Register */ 130 ESR_EL1, /* Exception Syndrome Register */ 131 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */ 132 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */ 133 FAR_EL1, /* Fault Address Register */ 134 MAIR_EL1, /* Memory Attribute Indirection Register */ 135 VBAR_EL1, /* Vector Base Address Register */ 136 CONTEXTIDR_EL1, /* Context ID Register */ 137 TPIDR_EL0, /* Thread ID, User R/W */ 138 TPIDRRO_EL0, /* Thread ID, User R/O */ 139 TPIDR_EL1, /* Thread ID, Privileged */ 140 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */ 141 CNTKCTL_EL1, /* Timer Control Register (EL1) */ 142 PAR_EL1, /* Physical Address Register */ 143 MDSCR_EL1, /* Monitor Debug System Control Register */ 144 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */ 145 DISR_EL1, /* Deferred Interrupt Status Register */ 146 147 /* Performance Monitors Registers */ 148 PMCR_EL0, /* Control Register */ 149 PMSELR_EL0, /* Event Counter Selection Register */ 150 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */ 151 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30, 152 PMCCNTR_EL0, /* Cycle Counter Register */ 153 PMEVTYPER0_EL0, /* Event Type Register (0-30) */ 154 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30, 155 PMCCFILTR_EL0, /* Cycle Count Filter Register */ 156 PMCNTENSET_EL0, /* Count Enable Set Register */ 157 PMINTENSET_EL1, /* Interrupt Enable Set Register */ 158 PMOVSSET_EL0, /* Overflow Flag Status Set Register */ 159 PMSWINC_EL0, /* Software Increment Register */ 160 PMUSERENR_EL0, /* User Enable Register */ 161 162 /* Pointer Authentication Registers in a strict increasing order. */ 163 APIAKEYLO_EL1, 164 APIAKEYHI_EL1, 165 APIBKEYLO_EL1, 166 APIBKEYHI_EL1, 167 APDAKEYLO_EL1, 168 APDAKEYHI_EL1, 169 APDBKEYLO_EL1, 170 APDBKEYHI_EL1, 171 APGAKEYLO_EL1, 172 APGAKEYHI_EL1, 173 174 /* 32bit specific registers. Keep them at the end of the range */ 175 DACR32_EL2, /* Domain Access Control Register */ 176 IFSR32_EL2, /* Instruction Fault Status Register */ 177 FPEXC32_EL2, /* Floating-Point Exception Control Register */ 178 DBGVCR32_EL2, /* Debug Vector Catch Register */ 179 180 NR_SYS_REGS /* Nothing after this line! */ 181 }; 182 183 /* 32bit mapping */ 184 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */ 185 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */ 186 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */ 187 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */ 188 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */ 189 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */ 190 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */ 191 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */ 192 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */ 193 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */ 194 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */ 195 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */ 196 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */ 197 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */ 198 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */ 199 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */ 200 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */ 201 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */ 202 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */ 203 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */ 204 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */ 205 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */ 206 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */ 207 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */ 208 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */ 209 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */ 210 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */ 211 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */ 212 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */ 213 214 #define cp14_DBGDSCRext (MDSCR_EL1 * 2) 215 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2) 216 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2) 217 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1) 218 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2) 219 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2) 220 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2) 221 222 #define NR_COPRO_REGS (NR_SYS_REGS * 2) 223 224 struct kvm_cpu_context { 225 struct kvm_regs gp_regs; 226 union { 227 u64 sys_regs[NR_SYS_REGS]; 228 u32 copro[NR_COPRO_REGS]; 229 }; 230 231 struct kvm_vcpu *__hyp_running_vcpu; 232 }; 233 234 struct kvm_pmu_events { 235 u32 events_host; 236 u32 events_guest; 237 }; 238 239 struct kvm_host_data { 240 struct kvm_cpu_context host_ctxt; 241 struct kvm_pmu_events pmu_events; 242 }; 243 244 typedef struct kvm_host_data kvm_host_data_t; 245 246 struct vcpu_reset_state { 247 unsigned long pc; 248 unsigned long r0; 249 bool be; 250 bool reset; 251 }; 252 253 struct kvm_vcpu_arch { 254 struct kvm_cpu_context ctxt; 255 void *sve_state; 256 unsigned int sve_max_vl; 257 258 /* HYP configuration */ 259 u64 hcr_el2; 260 u32 mdcr_el2; 261 262 /* Exception Information */ 263 struct kvm_vcpu_fault_info fault; 264 265 /* State of various workarounds, see kvm_asm.h for bit assignment */ 266 u64 workaround_flags; 267 268 /* Miscellaneous vcpu state flags */ 269 u64 flags; 270 271 /* 272 * We maintain more than a single set of debug registers to support 273 * debugging the guest from the host and to maintain separate host and 274 * guest state during world switches. vcpu_debug_state are the debug 275 * registers of the vcpu as the guest sees them. host_debug_state are 276 * the host registers which are saved and restored during 277 * world switches. external_debug_state contains the debug 278 * values we want to debug the guest. This is set via the 279 * KVM_SET_GUEST_DEBUG ioctl. 280 * 281 * debug_ptr points to the set of debug registers that should be loaded 282 * onto the hardware when running the guest. 283 */ 284 struct kvm_guest_debug_arch *debug_ptr; 285 struct kvm_guest_debug_arch vcpu_debug_state; 286 struct kvm_guest_debug_arch external_debug_state; 287 288 /* Pointer to host CPU context */ 289 struct kvm_cpu_context *host_cpu_context; 290 291 struct thread_info *host_thread_info; /* hyp VA */ 292 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */ 293 294 struct { 295 /* {Break,watch}point registers */ 296 struct kvm_guest_debug_arch regs; 297 /* Statistical profiling extension */ 298 u64 pmscr_el1; 299 } host_debug_state; 300 301 /* VGIC state */ 302 struct vgic_cpu vgic_cpu; 303 struct arch_timer_cpu timer_cpu; 304 struct kvm_pmu pmu; 305 306 /* 307 * Anything that is not used directly from assembly code goes 308 * here. 309 */ 310 311 /* 312 * Guest registers we preserve during guest debugging. 313 * 314 * These shadow registers are updated by the kvm_handle_sys_reg 315 * trap handler if the guest accesses or updates them while we 316 * are using guest debug. 317 */ 318 struct { 319 u32 mdscr_el1; 320 } guest_debug_preserved; 321 322 /* vcpu power-off state */ 323 bool power_off; 324 325 /* Don't run the guest (internal implementation need) */ 326 bool pause; 327 328 /* Cache some mmu pages needed inside spinlock regions */ 329 struct kvm_mmu_memory_cache mmu_page_cache; 330 331 /* Target CPU and feature flags */ 332 int target; 333 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES); 334 335 /* Detect first run of a vcpu */ 336 bool has_run_once; 337 338 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */ 339 u64 vsesr_el2; 340 341 /* Additional reset state */ 342 struct vcpu_reset_state reset_state; 343 344 /* True when deferrable sysregs are loaded on the physical CPU, 345 * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */ 346 bool sysregs_loaded_on_cpu; 347 348 /* Guest PV state */ 349 struct { 350 u64 steal; 351 u64 last_steal; 352 gpa_t base; 353 } steal; 354 }; 355 356 /* Pointer to the vcpu's SVE FFR for sve_{save,load}_state() */ 357 #define vcpu_sve_pffr(vcpu) ((void *)((char *)((vcpu)->arch.sve_state) + \ 358 sve_ffr_offset((vcpu)->arch.sve_max_vl))) 359 360 #define vcpu_sve_state_size(vcpu) ({ \ 361 size_t __size_ret; \ 362 unsigned int __vcpu_vq; \ 363 \ 364 if (WARN_ON(!sve_vl_valid((vcpu)->arch.sve_max_vl))) { \ 365 __size_ret = 0; \ 366 } else { \ 367 __vcpu_vq = sve_vq_from_vl((vcpu)->arch.sve_max_vl); \ 368 __size_ret = SVE_SIG_REGS_SIZE(__vcpu_vq); \ 369 } \ 370 \ 371 __size_ret; \ 372 }) 373 374 /* vcpu_arch flags field values: */ 375 #define KVM_ARM64_DEBUG_DIRTY (1 << 0) 376 #define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */ 377 #define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */ 378 #define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */ 379 #define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */ 380 #define KVM_ARM64_GUEST_HAS_SVE (1 << 5) /* SVE exposed to guest */ 381 #define KVM_ARM64_VCPU_SVE_FINALIZED (1 << 6) /* SVE config completed */ 382 #define KVM_ARM64_GUEST_HAS_PTRAUTH (1 << 7) /* PTRAUTH exposed to guest */ 383 384 #define vcpu_has_sve(vcpu) (system_supports_sve() && \ 385 ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_SVE)) 386 387 #define vcpu_has_ptrauth(vcpu) ((system_supports_address_auth() || \ 388 system_supports_generic_auth()) && \ 389 ((vcpu)->arch.flags & KVM_ARM64_GUEST_HAS_PTRAUTH)) 390 391 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs) 392 393 /* 394 * Only use __vcpu_sys_reg if you know you want the memory backed version of a 395 * register, and not the one most recently accessed by a running VCPU. For 396 * example, for userspace access or for system registers that are never context 397 * switched, but only emulated. 398 */ 399 #define __vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)]) 400 401 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg); 402 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg); 403 404 /* 405 * CP14 and CP15 live in the same array, as they are backed by the 406 * same system registers. 407 */ 408 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)]) 409 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)]) 410 411 struct kvm_vm_stat { 412 ulong remote_tlb_flush; 413 }; 414 415 struct kvm_vcpu_stat { 416 u64 halt_successful_poll; 417 u64 halt_attempted_poll; 418 u64 halt_poll_invalid; 419 u64 halt_wakeup; 420 u64 hvc_exit_stat; 421 u64 wfe_exit_stat; 422 u64 wfi_exit_stat; 423 u64 mmio_exit_user; 424 u64 mmio_exit_kernel; 425 u64 exits; 426 }; 427 428 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init); 429 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu); 430 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices); 431 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 432 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg); 433 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu, 434 struct kvm_vcpu_events *events); 435 436 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu, 437 struct kvm_vcpu_events *events); 438 439 #define KVM_ARCH_WANT_MMU_NOTIFIER 440 int kvm_unmap_hva_range(struct kvm *kvm, 441 unsigned long start, unsigned long end); 442 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte); 443 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end); 444 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva); 445 446 void kvm_arm_halt_guest(struct kvm *kvm); 447 void kvm_arm_resume_guest(struct kvm *kvm); 448 449 u64 __kvm_call_hyp(void *hypfn, ...); 450 451 /* 452 * The couple of isb() below are there to guarantee the same behaviour 453 * on VHE as on !VHE, where the eret to EL1 acts as a context 454 * synchronization event. 455 */ 456 #define kvm_call_hyp(f, ...) \ 457 do { \ 458 if (has_vhe()) { \ 459 f(__VA_ARGS__); \ 460 isb(); \ 461 } else { \ 462 __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__); \ 463 } \ 464 } while(0) 465 466 #define kvm_call_hyp_ret(f, ...) \ 467 ({ \ 468 typeof(f(__VA_ARGS__)) ret; \ 469 \ 470 if (has_vhe()) { \ 471 ret = f(__VA_ARGS__); \ 472 isb(); \ 473 } else { \ 474 ret = __kvm_call_hyp(kvm_ksym_ref(f), \ 475 ##__VA_ARGS__); \ 476 } \ 477 \ 478 ret; \ 479 }) 480 481 void force_vm_exit(const cpumask_t *mask); 482 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot); 483 484 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run, 485 int exception_index); 486 void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run, 487 int exception_index); 488 489 /* MMIO helpers */ 490 void kvm_mmio_write_buf(void *buf, unsigned int len, unsigned long data); 491 unsigned long kvm_mmio_read_buf(const void *buf, unsigned int len); 492 493 int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run); 494 int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run, 495 phys_addr_t fault_ipa); 496 497 int kvm_perf_init(void); 498 int kvm_perf_teardown(void); 499 500 long kvm_hypercall_pv_features(struct kvm_vcpu *vcpu); 501 gpa_t kvm_init_stolen_time(struct kvm_vcpu *vcpu); 502 void kvm_update_stolen_time(struct kvm_vcpu *vcpu); 503 504 int kvm_arm_pvtime_set_attr(struct kvm_vcpu *vcpu, 505 struct kvm_device_attr *attr); 506 int kvm_arm_pvtime_get_attr(struct kvm_vcpu *vcpu, 507 struct kvm_device_attr *attr); 508 int kvm_arm_pvtime_has_attr(struct kvm_vcpu *vcpu, 509 struct kvm_device_attr *attr); 510 511 static inline void kvm_arm_pvtime_vcpu_init(struct kvm_vcpu_arch *vcpu_arch) 512 { 513 vcpu_arch->steal.base = GPA_INVALID; 514 } 515 516 static inline bool kvm_arm_is_pvtime_enabled(struct kvm_vcpu_arch *vcpu_arch) 517 { 518 return (vcpu_arch->steal.base != GPA_INVALID); 519 } 520 521 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome); 522 523 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr); 524 525 DECLARE_PER_CPU(kvm_host_data_t, kvm_host_data); 526 527 static inline void kvm_init_host_cpu_context(struct kvm_cpu_context *cpu_ctxt) 528 { 529 /* The host's MPIDR is immutable, so let's set it up at boot time */ 530 cpu_ctxt->sys_regs[MPIDR_EL1] = read_cpuid_mpidr(); 531 } 532 533 void __kvm_enable_ssbs(void); 534 535 static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr, 536 unsigned long hyp_stack_ptr, 537 unsigned long vector_ptr) 538 { 539 /* 540 * Calculate the raw per-cpu offset without a translation from the 541 * kernel's mapping to the linear mapping, and store it in tpidr_el2 542 * so that we can use adr_l to access per-cpu variables in EL2. 543 */ 544 u64 tpidr_el2 = ((u64)this_cpu_ptr(&kvm_host_data) - 545 (u64)kvm_ksym_ref(kvm_host_data)); 546 547 /* 548 * Call initialization code, and switch to the full blown HYP code. 549 * If the cpucaps haven't been finalized yet, something has gone very 550 * wrong, and hyp will crash and burn when it uses any 551 * cpus_have_const_cap() wrapper. 552 */ 553 BUG_ON(!system_capabilities_finalized()); 554 __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr, tpidr_el2); 555 556 /* 557 * Disabling SSBD on a non-VHE system requires us to enable SSBS 558 * at EL2. 559 */ 560 if (!has_vhe() && this_cpu_has_cap(ARM64_SSBS) && 561 arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) { 562 kvm_call_hyp(__kvm_enable_ssbs); 563 } 564 } 565 566 static inline bool kvm_arch_requires_vhe(void) 567 { 568 /* 569 * The Arm architecture specifies that implementation of SVE 570 * requires VHE also to be implemented. The KVM code for arm64 571 * relies on this when SVE is present: 572 */ 573 if (system_supports_sve()) 574 return true; 575 576 /* Some implementations have defects that confine them to VHE */ 577 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_AT_VHE)) 578 return true; 579 580 return false; 581 } 582 583 void kvm_arm_vcpu_ptrauth_trap(struct kvm_vcpu *vcpu); 584 585 static inline void kvm_arch_hardware_unsetup(void) {} 586 static inline void kvm_arch_sync_events(struct kvm *kvm) {} 587 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {} 588 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {} 589 590 void kvm_arm_init_debug(void); 591 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu); 592 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu); 593 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu); 594 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, 595 struct kvm_device_attr *attr); 596 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, 597 struct kvm_device_attr *attr); 598 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, 599 struct kvm_device_attr *attr); 600 601 static inline void __cpu_init_stage2(void) {} 602 603 /* Guest/host FPSIMD coordination helpers */ 604 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu); 605 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu); 606 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); 607 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); 608 609 static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) 610 { 611 return (!has_vhe() && attr->exclude_host); 612 } 613 614 #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */ 615 static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) 616 { 617 return kvm_arch_vcpu_run_map_fp(vcpu); 618 } 619 620 void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); 621 void kvm_clr_pmu_events(u32 clr); 622 623 void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu); 624 void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); 625 #else 626 static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} 627 static inline void kvm_clr_pmu_events(u32 clr) {} 628 #endif 629 630 #define KVM_BP_HARDEN_UNKNOWN -1 631 #define KVM_BP_HARDEN_WA_NEEDED 0 632 #define KVM_BP_HARDEN_NOT_REQUIRED 1 633 634 static inline int kvm_arm_harden_branch_predictor(void) 635 { 636 switch (get_spectre_v2_workaround_state()) { 637 case ARM64_BP_HARDEN_WA_NEEDED: 638 return KVM_BP_HARDEN_WA_NEEDED; 639 case ARM64_BP_HARDEN_NOT_REQUIRED: 640 return KVM_BP_HARDEN_NOT_REQUIRED; 641 case ARM64_BP_HARDEN_UNKNOWN: 642 default: 643 return KVM_BP_HARDEN_UNKNOWN; 644 } 645 } 646 647 #define KVM_SSBD_UNKNOWN -1 648 #define KVM_SSBD_FORCE_DISABLE 0 649 #define KVM_SSBD_KERNEL 1 650 #define KVM_SSBD_FORCE_ENABLE 2 651 #define KVM_SSBD_MITIGATED 3 652 653 static inline int kvm_arm_have_ssbd(void) 654 { 655 switch (arm64_get_ssbd_state()) { 656 case ARM64_SSBD_FORCE_DISABLE: 657 return KVM_SSBD_FORCE_DISABLE; 658 case ARM64_SSBD_KERNEL: 659 return KVM_SSBD_KERNEL; 660 case ARM64_SSBD_FORCE_ENABLE: 661 return KVM_SSBD_FORCE_ENABLE; 662 case ARM64_SSBD_MITIGATED: 663 return KVM_SSBD_MITIGATED; 664 case ARM64_SSBD_UNKNOWN: 665 default: 666 return KVM_SSBD_UNKNOWN; 667 } 668 } 669 670 void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu); 671 void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu); 672 673 void kvm_set_ipa_limit(void); 674 675 #define __KVM_HAVE_ARCH_VM_ALLOC 676 struct kvm *kvm_arch_alloc_vm(void); 677 void kvm_arch_free_vm(struct kvm *kvm); 678 679 int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type); 680 681 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature); 682 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); 683 684 #define kvm_arm_vcpu_sve_finalized(vcpu) \ 685 ((vcpu)->arch.flags & KVM_ARM64_VCPU_SVE_FINALIZED) 686 687 #endif /* __ARM64_KVM_HOST_H__ */ 688