1 /* 2 * Copyright 2015 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs <bskeggs@redhat.com> 23 */ 24 #include "gf100.h" 25 #include "ctxgf100.h" 26 27 #include <core/firmware.h> 28 #include <subdev/acr.h> 29 #include <subdev/secboot.h> 30 31 #include <nvfw/flcn.h> 32 33 #include <nvif/class.h> 34 35 /******************************************************************************* 36 * PGRAPH engine/subdev functions 37 ******************************************************************************/ 38 39 static void 40 gm200_gr_acr_bld_patch(struct nvkm_acr *acr, u32 bld, s64 adjust) 41 { 42 struct flcn_bl_dmem_desc_v1 hdr; 43 nvkm_robj(acr->wpr, bld, &hdr, sizeof(hdr)); 44 hdr.code_dma_base = hdr.code_dma_base + adjust; 45 hdr.data_dma_base = hdr.data_dma_base + adjust; 46 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); 47 flcn_bl_dmem_desc_v1_dump(&acr->subdev, &hdr); 48 } 49 50 static void 51 gm200_gr_acr_bld_write(struct nvkm_acr *acr, u32 bld, 52 struct nvkm_acr_lsfw *lsfw) 53 { 54 const u64 base = lsfw->offset.img + lsfw->app_start_offset; 55 const u64 code = base + lsfw->app_resident_code_offset; 56 const u64 data = base + lsfw->app_resident_data_offset; 57 const struct flcn_bl_dmem_desc_v1 hdr = { 58 .ctx_dma = FALCON_DMAIDX_UCODE, 59 .code_dma_base = code, 60 .non_sec_code_off = lsfw->app_resident_code_offset, 61 .non_sec_code_size = lsfw->app_resident_code_size, 62 .code_entry_point = lsfw->app_imem_entry, 63 .data_dma_base = data, 64 .data_size = lsfw->app_resident_data_size, 65 }; 66 67 nvkm_wobj(acr->wpr, bld, &hdr, sizeof(hdr)); 68 } 69 70 const struct nvkm_acr_lsf_func 71 gm200_gr_gpccs_acr = { 72 .flags = NVKM_ACR_LSF_FORCE_PRIV_LOAD, 73 .bld_size = sizeof(struct flcn_bl_dmem_desc_v1), 74 .bld_write = gm200_gr_acr_bld_write, 75 .bld_patch = gm200_gr_acr_bld_patch, 76 }; 77 78 const struct nvkm_acr_lsf_func 79 gm200_gr_fecs_acr = { 80 .bld_size = sizeof(struct flcn_bl_dmem_desc_v1), 81 .bld_write = gm200_gr_acr_bld_write, 82 .bld_patch = gm200_gr_acr_bld_patch, 83 }; 84 85 int 86 gm200_gr_rops(struct gf100_gr *gr) 87 { 88 return nvkm_rd32(gr->base.engine.subdev.device, 0x12006c); 89 } 90 91 void 92 gm200_gr_init_ds_hww_esr_2(struct gf100_gr *gr) 93 { 94 struct nvkm_device *device = gr->base.engine.subdev.device; 95 nvkm_wr32(device, 0x405848, 0xc0000000); 96 nvkm_mask(device, 0x40584c, 0x00000001, 0x00000001); 97 } 98 99 void 100 gm200_gr_init_num_active_ltcs(struct gf100_gr *gr) 101 { 102 struct nvkm_device *device = gr->base.engine.subdev.device; 103 nvkm_wr32(device, GPC_BCAST(0x08ac), nvkm_rd32(device, 0x100800)); 104 nvkm_wr32(device, GPC_BCAST(0x033c), nvkm_rd32(device, 0x100804)); 105 } 106 107 void 108 gm200_gr_init_gpc_mmu(struct gf100_gr *gr) 109 { 110 struct nvkm_device *device = gr->base.engine.subdev.device; 111 112 nvkm_wr32(device, 0x418880, nvkm_rd32(device, 0x100c80) & 0xf0001fff); 113 nvkm_wr32(device, 0x418890, 0x00000000); 114 nvkm_wr32(device, 0x418894, 0x00000000); 115 116 nvkm_wr32(device, 0x4188b4, nvkm_rd32(device, 0x100cc8)); 117 nvkm_wr32(device, 0x4188b8, nvkm_rd32(device, 0x100ccc)); 118 nvkm_wr32(device, 0x4188b0, nvkm_rd32(device, 0x100cc4)); 119 } 120 121 static void 122 gm200_gr_init_rop_active_fbps(struct gf100_gr *gr) 123 { 124 struct nvkm_device *device = gr->base.engine.subdev.device; 125 const u32 fbp_count = nvkm_rd32(device, 0x12006c); 126 nvkm_mask(device, 0x408850, 0x0000000f, fbp_count); /* zrop */ 127 nvkm_mask(device, 0x408958, 0x0000000f, fbp_count); /* crop */ 128 } 129 130 static u8 131 gm200_gr_tile_map_6_24[] = { 132 0, 1, 2, 3, 4, 5, 3, 4, 5, 0, 1, 2, 0, 1, 2, 3, 4, 5, 3, 4, 5, 0, 1, 2, 133 }; 134 135 static u8 136 gm200_gr_tile_map_4_16[] = { 137 0, 1, 2, 3, 2, 3, 0, 1, 3, 0, 1, 2, 1, 2, 3, 0, 138 }; 139 140 static u8 141 gm200_gr_tile_map_2_8[] = { 142 0, 1, 1, 0, 0, 1, 1, 0, 143 }; 144 145 void 146 gm200_gr_oneinit_sm_id(struct gf100_gr *gr) 147 { 148 /*XXX: There's a different algorithm here I've not yet figured out. */ 149 gf100_gr_oneinit_sm_id(gr); 150 } 151 152 void 153 gm200_gr_oneinit_tiles(struct gf100_gr *gr) 154 { 155 /*XXX: Not sure what this is about. The algorithm from NVGPU 156 * seems to work for all boards I tried from earlier (and 157 * later) GPUs except in these specific configurations. 158 * 159 * Let's just hardcode them for now. 160 */ 161 if (gr->gpc_nr == 2 && gr->tpc_total == 8) { 162 memcpy(gr->tile, gm200_gr_tile_map_2_8, gr->tpc_total); 163 gr->screen_tile_row_offset = 1; 164 } else 165 if (gr->gpc_nr == 4 && gr->tpc_total == 16) { 166 memcpy(gr->tile, gm200_gr_tile_map_4_16, gr->tpc_total); 167 gr->screen_tile_row_offset = 4; 168 } else 169 if (gr->gpc_nr == 6 && gr->tpc_total == 24) { 170 memcpy(gr->tile, gm200_gr_tile_map_6_24, gr->tpc_total); 171 gr->screen_tile_row_offset = 5; 172 } else { 173 gf100_gr_oneinit_tiles(gr); 174 } 175 } 176 177 static const struct gf100_gr_func 178 gm200_gr = { 179 .oneinit_tiles = gm200_gr_oneinit_tiles, 180 .oneinit_sm_id = gm200_gr_oneinit_sm_id, 181 .init = gf100_gr_init, 182 .init_gpc_mmu = gm200_gr_init_gpc_mmu, 183 .init_bios = gm107_gr_init_bios, 184 .init_vsc_stream_master = gk104_gr_init_vsc_stream_master, 185 .init_zcull = gf117_gr_init_zcull, 186 .init_num_active_ltcs = gm200_gr_init_num_active_ltcs, 187 .init_rop_active_fbps = gm200_gr_init_rop_active_fbps, 188 .init_fecs_exceptions = gf100_gr_init_fecs_exceptions, 189 .init_ds_hww_esr_2 = gm200_gr_init_ds_hww_esr_2, 190 .init_sked_hww_esr = gk104_gr_init_sked_hww_esr, 191 .init_419cc0 = gf100_gr_init_419cc0, 192 .init_ppc_exceptions = gk104_gr_init_ppc_exceptions, 193 .init_tex_hww_esr = gf100_gr_init_tex_hww_esr, 194 .init_504430 = gm107_gr_init_504430, 195 .init_shader_exceptions = gm107_gr_init_shader_exceptions, 196 .init_400054 = gm107_gr_init_400054, 197 .trap_mp = gf100_gr_trap_mp, 198 .rops = gm200_gr_rops, 199 .tpc_nr = 4, 200 .ppc_nr = 2, 201 .grctx = &gm200_grctx, 202 .zbc = &gf100_gr_zbc, 203 .sclass = { 204 { -1, -1, FERMI_TWOD_A }, 205 { -1, -1, KEPLER_INLINE_TO_MEMORY_B }, 206 { -1, -1, MAXWELL_B, &gf100_fermi }, 207 { -1, -1, MAXWELL_COMPUTE_B }, 208 {} 209 } 210 }; 211 212 int 213 gm200_gr_load(struct gf100_gr *gr, int ver, const struct gf100_gr_fwif *fwif) 214 { 215 int ret; 216 217 ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev, 218 &gr->fecs.falcon, 219 NVKM_ACR_LSF_FECS, 220 "gr/fecs_", ver, fwif->fecs); 221 if (ret) 222 return ret; 223 224 ret = nvkm_acr_lsfw_load_bl_inst_data_sig(&gr->base.engine.subdev, 225 &gr->gpccs.falcon, 226 NVKM_ACR_LSF_GPCCS, 227 "gr/gpccs_", ver, 228 fwif->gpccs); 229 if (ret) 230 return ret; 231 232 gr->firmware = true; 233 234 return gk20a_gr_load_sw(gr, "gr/", ver); 235 } 236 237 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_bl.bin"); 238 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_inst.bin"); 239 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_data.bin"); 240 MODULE_FIRMWARE("nvidia/gm200/gr/fecs_sig.bin"); 241 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_bl.bin"); 242 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_inst.bin"); 243 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_data.bin"); 244 MODULE_FIRMWARE("nvidia/gm200/gr/gpccs_sig.bin"); 245 MODULE_FIRMWARE("nvidia/gm200/gr/sw_ctx.bin"); 246 MODULE_FIRMWARE("nvidia/gm200/gr/sw_nonctx.bin"); 247 MODULE_FIRMWARE("nvidia/gm200/gr/sw_bundle_init.bin"); 248 MODULE_FIRMWARE("nvidia/gm200/gr/sw_method_init.bin"); 249 250 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_bl.bin"); 251 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_inst.bin"); 252 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_data.bin"); 253 MODULE_FIRMWARE("nvidia/gm204/gr/fecs_sig.bin"); 254 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_bl.bin"); 255 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_inst.bin"); 256 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_data.bin"); 257 MODULE_FIRMWARE("nvidia/gm204/gr/gpccs_sig.bin"); 258 MODULE_FIRMWARE("nvidia/gm204/gr/sw_ctx.bin"); 259 MODULE_FIRMWARE("nvidia/gm204/gr/sw_nonctx.bin"); 260 MODULE_FIRMWARE("nvidia/gm204/gr/sw_bundle_init.bin"); 261 MODULE_FIRMWARE("nvidia/gm204/gr/sw_method_init.bin"); 262 263 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_bl.bin"); 264 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_inst.bin"); 265 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_data.bin"); 266 MODULE_FIRMWARE("nvidia/gm206/gr/fecs_sig.bin"); 267 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_bl.bin"); 268 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_inst.bin"); 269 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_data.bin"); 270 MODULE_FIRMWARE("nvidia/gm206/gr/gpccs_sig.bin"); 271 MODULE_FIRMWARE("nvidia/gm206/gr/sw_ctx.bin"); 272 MODULE_FIRMWARE("nvidia/gm206/gr/sw_nonctx.bin"); 273 MODULE_FIRMWARE("nvidia/gm206/gr/sw_bundle_init.bin"); 274 MODULE_FIRMWARE("nvidia/gm206/gr/sw_method_init.bin"); 275 276 static const struct gf100_gr_fwif 277 gm200_gr_fwif[] = { 278 { 0, gm200_gr_load, &gm200_gr, &gm200_gr_fecs_acr, &gm200_gr_gpccs_acr }, 279 {} 280 }; 281 282 int 283 gm200_gr_new(struct nvkm_device *device, int index, struct nvkm_gr **pgr) 284 { 285 return gf100_gr_new_(gm200_gr_fwif, device, index, pgr); 286 } 287