1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 // 3 // Copyright (c) 2018 BayLibre, SAS. 4 // Author: Jerome Brunet <jbrunet@baylibre.com> 5 6 #include <linux/clk.h> 7 #include <linux/module.h> 8 #include <linux/of_platform.h> 9 #include <sound/pcm_params.h> 10 #include <sound/soc.h> 11 #include <sound/soc-dai.h> 12 13 #include "axg-tdm.h" 14 15 enum { 16 TDM_IFACE_PAD, 17 TDM_IFACE_LOOPBACK, 18 }; 19 20 static unsigned int axg_tdm_slots_total(u32 *mask) 21 { 22 unsigned int slots = 0; 23 int i; 24 25 if (!mask) 26 return 0; 27 28 /* Count the total number of slots provided by all 4 lanes */ 29 for (i = 0; i < AXG_TDM_NUM_LANES; i++) 30 slots += hweight32(mask[i]); 31 32 return slots; 33 } 34 35 int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32 *tx_mask, 36 u32 *rx_mask, unsigned int slots, 37 unsigned int slot_width) 38 { 39 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai); 40 struct axg_tdm_stream *tx = (struct axg_tdm_stream *) 41 dai->playback_dma_data; 42 struct axg_tdm_stream *rx = (struct axg_tdm_stream *) 43 dai->capture_dma_data; 44 unsigned int tx_slots, rx_slots; 45 unsigned int fmt = 0; 46 47 tx_slots = axg_tdm_slots_total(tx_mask); 48 rx_slots = axg_tdm_slots_total(rx_mask); 49 50 /* We should at least have a slot for a valid interface */ 51 if (!tx_slots && !rx_slots) { 52 dev_err(dai->dev, "interface has no slot\n"); 53 return -EINVAL; 54 } 55 56 iface->slots = slots; 57 58 switch (slot_width) { 59 case 0: 60 slot_width = 32; 61 /* Fall-through */ 62 case 32: 63 fmt |= SNDRV_PCM_FMTBIT_S32_LE; 64 /* Fall-through */ 65 case 24: 66 fmt |= SNDRV_PCM_FMTBIT_S24_LE; 67 fmt |= SNDRV_PCM_FMTBIT_S20_LE; 68 /* Fall-through */ 69 case 16: 70 fmt |= SNDRV_PCM_FMTBIT_S16_LE; 71 /* Fall-through */ 72 case 8: 73 fmt |= SNDRV_PCM_FMTBIT_S8; 74 break; 75 default: 76 dev_err(dai->dev, "unsupported slot width: %d\n", slot_width); 77 return -EINVAL; 78 } 79 80 iface->slot_width = slot_width; 81 82 /* Amend the dai driver and let dpcm merge do its job */ 83 if (tx) { 84 tx->mask = tx_mask; 85 dai->driver->playback.channels_max = tx_slots; 86 dai->driver->playback.formats = fmt; 87 } 88 89 if (rx) { 90 rx->mask = rx_mask; 91 dai->driver->capture.channels_max = rx_slots; 92 dai->driver->capture.formats = fmt; 93 } 94 95 return 0; 96 } 97 EXPORT_SYMBOL_GPL(axg_tdm_set_tdm_slots); 98 99 static int axg_tdm_iface_set_sysclk(struct snd_soc_dai *dai, int clk_id, 100 unsigned int freq, int dir) 101 { 102 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai); 103 int ret = -ENOTSUPP; 104 105 if (dir == SND_SOC_CLOCK_OUT && clk_id == 0) { 106 if (!iface->mclk) { 107 dev_warn(dai->dev, "master clock not provided\n"); 108 } else { 109 ret = clk_set_rate(iface->mclk, freq); 110 if (!ret) 111 iface->mclk_rate = freq; 112 } 113 } 114 115 return ret; 116 } 117 118 static int axg_tdm_iface_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 119 { 120 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai); 121 122 /* These modes are not supported */ 123 if (fmt & (SND_SOC_DAIFMT_CBS_CFM | SND_SOC_DAIFMT_CBM_CFS)) { 124 dev_err(dai->dev, "only CBS_CFS and CBM_CFM are supported\n"); 125 return -EINVAL; 126 } 127 128 /* If the TDM interface is the clock master, it requires mclk */ 129 if (!iface->mclk && (fmt & SND_SOC_DAIFMT_CBS_CFS)) { 130 dev_err(dai->dev, "cpu clock master: mclk missing\n"); 131 return -ENODEV; 132 } 133 134 iface->fmt = fmt; 135 return 0; 136 } 137 138 static int axg_tdm_iface_startup(struct snd_pcm_substream *substream, 139 struct snd_soc_dai *dai) 140 { 141 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai); 142 struct axg_tdm_stream *ts = 143 snd_soc_dai_get_dma_data(dai, substream); 144 int ret; 145 146 if (!axg_tdm_slots_total(ts->mask)) { 147 dev_err(dai->dev, "interface has not slots\n"); 148 return -EINVAL; 149 } 150 151 /* Apply component wide rate symmetry */ 152 if (snd_soc_component_active(dai->component)) { 153 ret = snd_pcm_hw_constraint_single(substream->runtime, 154 SNDRV_PCM_HW_PARAM_RATE, 155 iface->rate); 156 if (ret < 0) { 157 dev_err(dai->dev, 158 "can't set iface rate constraint\n"); 159 return ret; 160 } 161 } 162 163 return 0; 164 } 165 166 static int axg_tdm_iface_set_stream(struct snd_pcm_substream *substream, 167 struct snd_pcm_hw_params *params, 168 struct snd_soc_dai *dai) 169 { 170 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai); 171 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream); 172 unsigned int channels = params_channels(params); 173 unsigned int width = params_width(params); 174 175 /* Save rate and sample_bits for component symmetry */ 176 iface->rate = params_rate(params); 177 178 /* Make sure this interface can cope with the stream */ 179 if (axg_tdm_slots_total(ts->mask) < channels) { 180 dev_err(dai->dev, "not enough slots for channels\n"); 181 return -EINVAL; 182 } 183 184 if (iface->slot_width < width) { 185 dev_err(dai->dev, "incompatible slots width for stream\n"); 186 return -EINVAL; 187 } 188 189 /* Save the parameter for tdmout/tdmin widgets */ 190 ts->physical_width = params_physical_width(params); 191 ts->width = params_width(params); 192 ts->channels = params_channels(params); 193 194 return 0; 195 } 196 197 static int axg_tdm_iface_set_lrclk(struct snd_soc_dai *dai, 198 struct snd_pcm_hw_params *params) 199 { 200 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai); 201 unsigned int ratio_num; 202 int ret; 203 204 ret = clk_set_rate(iface->lrclk, params_rate(params)); 205 if (ret) { 206 dev_err(dai->dev, "setting sample clock failed: %d\n", ret); 207 return ret; 208 } 209 210 switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 211 case SND_SOC_DAIFMT_I2S: 212 case SND_SOC_DAIFMT_LEFT_J: 213 case SND_SOC_DAIFMT_RIGHT_J: 214 /* 50% duty cycle ratio */ 215 ratio_num = 1; 216 break; 217 218 case SND_SOC_DAIFMT_DSP_A: 219 case SND_SOC_DAIFMT_DSP_B: 220 /* 221 * A zero duty cycle ratio will result in setting the mininum 222 * ratio possible which, for this clock, is 1 cycle of the 223 * parent bclk clock high and the rest low, This is exactly 224 * what we want here. 225 */ 226 ratio_num = 0; 227 break; 228 229 default: 230 return -EINVAL; 231 } 232 233 ret = clk_set_duty_cycle(iface->lrclk, ratio_num, 2); 234 if (ret) { 235 dev_err(dai->dev, 236 "setting sample clock duty cycle failed: %d\n", ret); 237 return ret; 238 } 239 240 /* Set sample clock inversion */ 241 ret = clk_set_phase(iface->lrclk, 242 axg_tdm_lrclk_invert(iface->fmt) ? 180 : 0); 243 if (ret) { 244 dev_err(dai->dev, 245 "setting sample clock phase failed: %d\n", ret); 246 return ret; 247 } 248 249 return 0; 250 } 251 252 static int axg_tdm_iface_set_sclk(struct snd_soc_dai *dai, 253 struct snd_pcm_hw_params *params) 254 { 255 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai); 256 unsigned long srate; 257 int ret; 258 259 srate = iface->slots * iface->slot_width * params_rate(params); 260 261 if (!iface->mclk_rate) { 262 /* If no specific mclk is requested, default to bit clock * 4 */ 263 clk_set_rate(iface->mclk, 4 * srate); 264 } else { 265 /* Check if we can actually get the bit clock from mclk */ 266 if (iface->mclk_rate % srate) { 267 dev_err(dai->dev, 268 "can't derive sclk %lu from mclk %lu\n", 269 srate, iface->mclk_rate); 270 return -EINVAL; 271 } 272 } 273 274 ret = clk_set_rate(iface->sclk, srate); 275 if (ret) { 276 dev_err(dai->dev, "setting bit clock failed: %d\n", ret); 277 return ret; 278 } 279 280 /* Set the bit clock inversion */ 281 ret = clk_set_phase(iface->sclk, 282 axg_tdm_sclk_invert(iface->fmt) ? 0 : 180); 283 if (ret) { 284 dev_err(dai->dev, "setting bit clock phase failed: %d\n", ret); 285 return ret; 286 } 287 288 return ret; 289 } 290 291 static int axg_tdm_iface_hw_params(struct snd_pcm_substream *substream, 292 struct snd_pcm_hw_params *params, 293 struct snd_soc_dai *dai) 294 { 295 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai); 296 int ret; 297 298 switch (iface->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 299 case SND_SOC_DAIFMT_I2S: 300 case SND_SOC_DAIFMT_LEFT_J: 301 case SND_SOC_DAIFMT_RIGHT_J: 302 if (iface->slots > 2) { 303 dev_err(dai->dev, "bad slot number for format: %d\n", 304 iface->slots); 305 return -EINVAL; 306 } 307 break; 308 309 case SND_SOC_DAIFMT_DSP_A: 310 case SND_SOC_DAIFMT_DSP_B: 311 break; 312 313 default: 314 dev_err(dai->dev, "unsupported dai format\n"); 315 return -EINVAL; 316 } 317 318 ret = axg_tdm_iface_set_stream(substream, params, dai); 319 if (ret) 320 return ret; 321 322 if (iface->fmt & SND_SOC_DAIFMT_CBS_CFS) { 323 ret = axg_tdm_iface_set_sclk(dai, params); 324 if (ret) 325 return ret; 326 327 ret = axg_tdm_iface_set_lrclk(dai, params); 328 if (ret) 329 return ret; 330 } 331 332 return 0; 333 } 334 335 static int axg_tdm_iface_hw_free(struct snd_pcm_substream *substream, 336 struct snd_soc_dai *dai) 337 { 338 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream); 339 340 /* Stop all attached formatters */ 341 axg_tdm_stream_stop(ts); 342 343 return 0; 344 } 345 346 static int axg_tdm_iface_prepare(struct snd_pcm_substream *substream, 347 struct snd_soc_dai *dai) 348 { 349 struct axg_tdm_stream *ts = snd_soc_dai_get_dma_data(dai, substream); 350 351 /* Force all attached formatters to update */ 352 return axg_tdm_stream_reset(ts); 353 } 354 355 static int axg_tdm_iface_remove_dai(struct snd_soc_dai *dai) 356 { 357 if (dai->capture_dma_data) 358 axg_tdm_stream_free(dai->capture_dma_data); 359 360 if (dai->playback_dma_data) 361 axg_tdm_stream_free(dai->playback_dma_data); 362 363 return 0; 364 } 365 366 static int axg_tdm_iface_probe_dai(struct snd_soc_dai *dai) 367 { 368 struct axg_tdm_iface *iface = snd_soc_dai_get_drvdata(dai); 369 370 if (dai->capture_widget) { 371 dai->capture_dma_data = axg_tdm_stream_alloc(iface); 372 if (!dai->capture_dma_data) 373 return -ENOMEM; 374 } 375 376 if (dai->playback_widget) { 377 dai->playback_dma_data = axg_tdm_stream_alloc(iface); 378 if (!dai->playback_dma_data) { 379 axg_tdm_iface_remove_dai(dai); 380 return -ENOMEM; 381 } 382 } 383 384 return 0; 385 } 386 387 static const struct snd_soc_dai_ops axg_tdm_iface_ops = { 388 .set_sysclk = axg_tdm_iface_set_sysclk, 389 .set_fmt = axg_tdm_iface_set_fmt, 390 .startup = axg_tdm_iface_startup, 391 .hw_params = axg_tdm_iface_hw_params, 392 .prepare = axg_tdm_iface_prepare, 393 .hw_free = axg_tdm_iface_hw_free, 394 }; 395 396 /* TDM Backend DAIs */ 397 static const struct snd_soc_dai_driver axg_tdm_iface_dai_drv[] = { 398 [TDM_IFACE_PAD] = { 399 .name = "TDM Pad", 400 .playback = { 401 .stream_name = "Playback", 402 .channels_min = 1, 403 .channels_max = AXG_TDM_CHANNEL_MAX, 404 .rates = AXG_TDM_RATES, 405 .formats = AXG_TDM_FORMATS, 406 }, 407 .capture = { 408 .stream_name = "Capture", 409 .channels_min = 1, 410 .channels_max = AXG_TDM_CHANNEL_MAX, 411 .rates = AXG_TDM_RATES, 412 .formats = AXG_TDM_FORMATS, 413 }, 414 .id = TDM_IFACE_PAD, 415 .ops = &axg_tdm_iface_ops, 416 .probe = axg_tdm_iface_probe_dai, 417 .remove = axg_tdm_iface_remove_dai, 418 }, 419 [TDM_IFACE_LOOPBACK] = { 420 .name = "TDM Loopback", 421 .capture = { 422 .stream_name = "Loopback", 423 .channels_min = 1, 424 .channels_max = AXG_TDM_CHANNEL_MAX, 425 .rates = AXG_TDM_RATES, 426 .formats = AXG_TDM_FORMATS, 427 }, 428 .id = TDM_IFACE_LOOPBACK, 429 .ops = &axg_tdm_iface_ops, 430 .probe = axg_tdm_iface_probe_dai, 431 .remove = axg_tdm_iface_remove_dai, 432 }, 433 }; 434 435 static int axg_tdm_iface_set_bias_level(struct snd_soc_component *component, 436 enum snd_soc_bias_level level) 437 { 438 struct axg_tdm_iface *iface = snd_soc_component_get_drvdata(component); 439 enum snd_soc_bias_level now = 440 snd_soc_component_get_bias_level(component); 441 int ret = 0; 442 443 switch (level) { 444 case SND_SOC_BIAS_PREPARE: 445 if (now == SND_SOC_BIAS_STANDBY) 446 ret = clk_prepare_enable(iface->mclk); 447 break; 448 449 case SND_SOC_BIAS_STANDBY: 450 if (now == SND_SOC_BIAS_PREPARE) 451 clk_disable_unprepare(iface->mclk); 452 break; 453 454 case SND_SOC_BIAS_OFF: 455 case SND_SOC_BIAS_ON: 456 break; 457 } 458 459 return ret; 460 } 461 462 static const struct snd_soc_component_driver axg_tdm_iface_component_drv = { 463 .set_bias_level = axg_tdm_iface_set_bias_level, 464 }; 465 466 static const struct of_device_id axg_tdm_iface_of_match[] = { 467 { .compatible = "amlogic,axg-tdm-iface", }, 468 {} 469 }; 470 MODULE_DEVICE_TABLE(of, axg_tdm_iface_of_match); 471 472 static int axg_tdm_iface_probe(struct platform_device *pdev) 473 { 474 struct device *dev = &pdev->dev; 475 struct snd_soc_dai_driver *dai_drv; 476 struct axg_tdm_iface *iface; 477 int ret, i; 478 479 iface = devm_kzalloc(dev, sizeof(*iface), GFP_KERNEL); 480 if (!iface) 481 return -ENOMEM; 482 platform_set_drvdata(pdev, iface); 483 484 /* 485 * Duplicate dai driver: depending on the slot masks configuration 486 * We'll change the number of channel provided by DAI stream, so dpcm 487 * channel merge can be done properly 488 */ 489 dai_drv = devm_kcalloc(dev, ARRAY_SIZE(axg_tdm_iface_dai_drv), 490 sizeof(*dai_drv), GFP_KERNEL); 491 if (!dai_drv) 492 return -ENOMEM; 493 494 for (i = 0; i < ARRAY_SIZE(axg_tdm_iface_dai_drv); i++) 495 memcpy(&dai_drv[i], &axg_tdm_iface_dai_drv[i], 496 sizeof(*dai_drv)); 497 498 /* Bit clock provided on the pad */ 499 iface->sclk = devm_clk_get(dev, "sclk"); 500 if (IS_ERR(iface->sclk)) { 501 ret = PTR_ERR(iface->sclk); 502 if (ret != -EPROBE_DEFER) 503 dev_err(dev, "failed to get sclk: %d\n", ret); 504 return ret; 505 } 506 507 /* Sample clock provided on the pad */ 508 iface->lrclk = devm_clk_get(dev, "lrclk"); 509 if (IS_ERR(iface->lrclk)) { 510 ret = PTR_ERR(iface->lrclk); 511 if (ret != -EPROBE_DEFER) 512 dev_err(dev, "failed to get lrclk: %d\n", ret); 513 return ret; 514 } 515 516 /* 517 * mclk maybe be missing when the cpu dai is in slave mode and 518 * the codec does not require it to provide a master clock. 519 * At this point, ignore the error if mclk is missing. We'll 520 * throw an error if the cpu dai is master and mclk is missing 521 */ 522 iface->mclk = devm_clk_get(dev, "mclk"); 523 if (IS_ERR(iface->mclk)) { 524 ret = PTR_ERR(iface->mclk); 525 if (ret == -ENOENT) { 526 iface->mclk = NULL; 527 } else { 528 if (ret != -EPROBE_DEFER) 529 dev_err(dev, "failed to get mclk: %d\n", ret); 530 return ret; 531 } 532 } 533 534 return devm_snd_soc_register_component(dev, 535 &axg_tdm_iface_component_drv, dai_drv, 536 ARRAY_SIZE(axg_tdm_iface_dai_drv)); 537 } 538 539 static struct platform_driver axg_tdm_iface_pdrv = { 540 .probe = axg_tdm_iface_probe, 541 .driver = { 542 .name = "axg-tdm-iface", 543 .of_match_table = axg_tdm_iface_of_match, 544 }, 545 }; 546 module_platform_driver(axg_tdm_iface_pdrv); 547 548 MODULE_DESCRIPTION("Amlogic AXG TDM interface driver"); 549 MODULE_AUTHOR("Jerome Brunet <jbrunet@baylibre.com>"); 550 MODULE_LICENSE("GPL v2"); 551