1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ 2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */ 3 4 #ifndef _MLXSW_REG_H 5 #define _MLXSW_REG_H 6 7 #include <linux/kernel.h> 8 #include <linux/string.h> 9 #include <linux/bitops.h> 10 #include <linux/if_vlan.h> 11 12 #include "item.h" 13 #include "port.h" 14 15 struct mlxsw_reg_info { 16 u16 id; 17 u16 len; /* In u8 */ 18 const char *name; 19 }; 20 21 #define MLXSW_REG_DEFINE(_name, _id, _len) \ 22 static const struct mlxsw_reg_info mlxsw_reg_##_name = { \ 23 .id = _id, \ 24 .len = _len, \ 25 .name = #_name, \ 26 } 27 28 #define MLXSW_REG(type) (&mlxsw_reg_##type) 29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len 30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len) 31 32 /* SGCR - Switch General Configuration Register 33 * -------------------------------------------- 34 * This register is used for configuration of the switch capabilities. 35 */ 36 #define MLXSW_REG_SGCR_ID 0x2000 37 #define MLXSW_REG_SGCR_LEN 0x10 38 39 MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN); 40 41 /* reg_sgcr_llb 42 * Link Local Broadcast (Default=0) 43 * When set, all Link Local packets (224.0.0.X) will be treated as broadcast 44 * packets and ignore the IGMP snooping entries. 45 * Access: RW 46 */ 47 MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1); 48 49 static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb) 50 { 51 MLXSW_REG_ZERO(sgcr, payload); 52 mlxsw_reg_sgcr_llb_set(payload, !!llb); 53 } 54 55 /* SPAD - Switch Physical Address Register 56 * --------------------------------------- 57 * The SPAD register configures the switch physical MAC address. 58 */ 59 #define MLXSW_REG_SPAD_ID 0x2002 60 #define MLXSW_REG_SPAD_LEN 0x10 61 62 MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN); 63 64 /* reg_spad_base_mac 65 * Base MAC address for the switch partitions. 66 * Per switch partition MAC address is equal to: 67 * base_mac + swid 68 * Access: RW 69 */ 70 MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6); 71 72 /* SMID - Switch Multicast ID 73 * -------------------------- 74 * The MID record maps from a MID (Multicast ID), which is a unique identifier 75 * of the multicast group within the stacking domain, into a list of local 76 * ports into which the packet is replicated. 77 */ 78 #define MLXSW_REG_SMID_ID 0x2007 79 #define MLXSW_REG_SMID_LEN 0x240 80 81 MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN); 82 83 /* reg_smid_swid 84 * Switch partition ID. 85 * Access: Index 86 */ 87 MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8); 88 89 /* reg_smid_mid 90 * Multicast identifier - global identifier that represents the multicast group 91 * across all devices. 92 * Access: Index 93 */ 94 MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16); 95 96 /* reg_smid_port 97 * Local port memebership (1 bit per port). 98 * Access: RW 99 */ 100 MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1); 101 102 /* reg_smid_port_mask 103 * Local port mask (1 bit per port). 104 * Access: W 105 */ 106 MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1); 107 108 static inline void mlxsw_reg_smid_pack(char *payload, u16 mid, 109 u8 port, bool set) 110 { 111 MLXSW_REG_ZERO(smid, payload); 112 mlxsw_reg_smid_swid_set(payload, 0); 113 mlxsw_reg_smid_mid_set(payload, mid); 114 mlxsw_reg_smid_port_set(payload, port, set); 115 mlxsw_reg_smid_port_mask_set(payload, port, 1); 116 } 117 118 /* SSPR - Switch System Port Record Register 119 * ----------------------------------------- 120 * Configures the system port to local port mapping. 121 */ 122 #define MLXSW_REG_SSPR_ID 0x2008 123 #define MLXSW_REG_SSPR_LEN 0x8 124 125 MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN); 126 127 /* reg_sspr_m 128 * Master - if set, then the record describes the master system port. 129 * This is needed in case a local port is mapped into several system ports 130 * (for multipathing). That number will be reported as the source system 131 * port when packets are forwarded to the CPU. Only one master port is allowed 132 * per local port. 133 * 134 * Note: Must be set for Spectrum. 135 * Access: RW 136 */ 137 MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1); 138 139 /* reg_sspr_local_port 140 * Local port number. 141 * 142 * Access: RW 143 */ 144 MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8); 145 146 /* reg_sspr_sub_port 147 * Virtual port within the physical port. 148 * Should be set to 0 when virtual ports are not enabled on the port. 149 * 150 * Access: RW 151 */ 152 MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8); 153 154 /* reg_sspr_system_port 155 * Unique identifier within the stacking domain that represents all the ports 156 * that are available in the system (external ports). 157 * 158 * Currently, only single-ASIC configurations are supported, so we default to 159 * 1:1 mapping between system ports and local ports. 160 * Access: Index 161 */ 162 MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16); 163 164 static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port) 165 { 166 MLXSW_REG_ZERO(sspr, payload); 167 mlxsw_reg_sspr_m_set(payload, 1); 168 mlxsw_reg_sspr_local_port_set(payload, local_port); 169 mlxsw_reg_sspr_sub_port_set(payload, 0); 170 mlxsw_reg_sspr_system_port_set(payload, local_port); 171 } 172 173 /* SFDAT - Switch Filtering Database Aging Time 174 * -------------------------------------------- 175 * Controls the Switch aging time. Aging time is able to be set per Switch 176 * Partition. 177 */ 178 #define MLXSW_REG_SFDAT_ID 0x2009 179 #define MLXSW_REG_SFDAT_LEN 0x8 180 181 MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN); 182 183 /* reg_sfdat_swid 184 * Switch partition ID. 185 * Access: Index 186 */ 187 MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8); 188 189 /* reg_sfdat_age_time 190 * Aging time in seconds 191 * Min - 10 seconds 192 * Max - 1,000,000 seconds 193 * Default is 300 seconds. 194 * Access: RW 195 */ 196 MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20); 197 198 static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time) 199 { 200 MLXSW_REG_ZERO(sfdat, payload); 201 mlxsw_reg_sfdat_swid_set(payload, 0); 202 mlxsw_reg_sfdat_age_time_set(payload, age_time); 203 } 204 205 /* SFD - Switch Filtering Database 206 * ------------------------------- 207 * The following register defines the access to the filtering database. 208 * The register supports querying, adding, removing and modifying the database. 209 * The access is optimized for bulk updates in which case more than one 210 * FDB record is present in the same command. 211 */ 212 #define MLXSW_REG_SFD_ID 0x200A 213 #define MLXSW_REG_SFD_BASE_LEN 0x10 /* base length, without records */ 214 #define MLXSW_REG_SFD_REC_LEN 0x10 /* record length */ 215 #define MLXSW_REG_SFD_REC_MAX_COUNT 64 216 #define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \ 217 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT) 218 219 MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN); 220 221 /* reg_sfd_swid 222 * Switch partition ID for queries. Reserved on Write. 223 * Access: Index 224 */ 225 MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8); 226 227 enum mlxsw_reg_sfd_op { 228 /* Dump entire FDB a (process according to record_locator) */ 229 MLXSW_REG_SFD_OP_QUERY_DUMP = 0, 230 /* Query records by {MAC, VID/FID} value */ 231 MLXSW_REG_SFD_OP_QUERY_QUERY = 1, 232 /* Query and clear activity. Query records by {MAC, VID/FID} value */ 233 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2, 234 /* Test. Response indicates if each of the records could be 235 * added to the FDB. 236 */ 237 MLXSW_REG_SFD_OP_WRITE_TEST = 0, 238 /* Add/modify. Aged-out records cannot be added. This command removes 239 * the learning notification of the {MAC, VID/FID}. Response includes 240 * the entries that were added to the FDB. 241 */ 242 MLXSW_REG_SFD_OP_WRITE_EDIT = 1, 243 /* Remove record by {MAC, VID/FID}. This command also removes 244 * the learning notification and aged-out notifications 245 * of the {MAC, VID/FID}. The response provides current (pre-removal) 246 * entries as non-aged-out. 247 */ 248 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2, 249 /* Remove learned notification by {MAC, VID/FID}. The response provides 250 * the removed learning notification. 251 */ 252 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2, 253 }; 254 255 /* reg_sfd_op 256 * Operation. 257 * Access: OP 258 */ 259 MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2); 260 261 /* reg_sfd_record_locator 262 * Used for querying the FDB. Use record_locator=0 to initiate the 263 * query. When a record is returned, a new record_locator is 264 * returned to be used in the subsequent query. 265 * Reserved for database update. 266 * Access: Index 267 */ 268 MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30); 269 270 /* reg_sfd_num_rec 271 * Request: Number of records to read/add/modify/remove 272 * Response: Number of records read/added/replaced/removed 273 * See above description for more details. 274 * Ranges 0..64 275 * Access: RW 276 */ 277 MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8); 278 279 static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op, 280 u32 record_locator) 281 { 282 MLXSW_REG_ZERO(sfd, payload); 283 mlxsw_reg_sfd_op_set(payload, op); 284 mlxsw_reg_sfd_record_locator_set(payload, record_locator); 285 } 286 287 /* reg_sfd_rec_swid 288 * Switch partition ID. 289 * Access: Index 290 */ 291 MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8, 292 MLXSW_REG_SFD_REC_LEN, 0x00, false); 293 294 enum mlxsw_reg_sfd_rec_type { 295 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0, 296 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1, 297 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2, 298 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL = 0xC, 299 }; 300 301 /* reg_sfd_rec_type 302 * FDB record type. 303 * Access: RW 304 */ 305 MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4, 306 MLXSW_REG_SFD_REC_LEN, 0x00, false); 307 308 enum mlxsw_reg_sfd_rec_policy { 309 /* Replacement disabled, aging disabled. */ 310 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0, 311 /* (mlag remote): Replacement enabled, aging disabled, 312 * learning notification enabled on this port. 313 */ 314 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1, 315 /* (ingress device): Replacement enabled, aging enabled. */ 316 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3, 317 }; 318 319 /* reg_sfd_rec_policy 320 * Policy. 321 * Access: RW 322 */ 323 MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2, 324 MLXSW_REG_SFD_REC_LEN, 0x00, false); 325 326 /* reg_sfd_rec_a 327 * Activity. Set for new static entries. Set for static entries if a frame SMAC 328 * lookup hits on the entry. 329 * To clear the a bit, use "query and clear activity" op. 330 * Access: RO 331 */ 332 MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1, 333 MLXSW_REG_SFD_REC_LEN, 0x00, false); 334 335 /* reg_sfd_rec_mac 336 * MAC address. 337 * Access: Index 338 */ 339 MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6, 340 MLXSW_REG_SFD_REC_LEN, 0x02); 341 342 enum mlxsw_reg_sfd_rec_action { 343 /* forward */ 344 MLXSW_REG_SFD_REC_ACTION_NOP = 0, 345 /* forward and trap, trap_id is FDB_TRAP */ 346 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1, 347 /* trap and do not forward, trap_id is FDB_TRAP */ 348 MLXSW_REG_SFD_REC_ACTION_TRAP = 2, 349 /* forward to IP router */ 350 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3, 351 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15, 352 }; 353 354 /* reg_sfd_rec_action 355 * Action to apply on the packet. 356 * Note: Dynamic entries can only be configured with NOP action. 357 * Access: RW 358 */ 359 MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4, 360 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 361 362 /* reg_sfd_uc_sub_port 363 * VEPA channel on local port. 364 * Valid only if local port is a non-stacking port. Must be 0 if multichannel 365 * VEPA is not enabled. 366 * Access: RW 367 */ 368 MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 369 MLXSW_REG_SFD_REC_LEN, 0x08, false); 370 371 /* reg_sfd_uc_fid_vid 372 * Filtering ID or VLAN ID 373 * For SwitchX and SwitchX-2: 374 * - Dynamic entries (policy 2,3) use FID 375 * - Static entries (policy 0) use VID 376 * - When independent learning is configured, VID=FID 377 * For Spectrum: use FID for both Dynamic and Static entries. 378 * VID should not be used. 379 * Access: Index 380 */ 381 MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 382 MLXSW_REG_SFD_REC_LEN, 0x08, false); 383 384 /* reg_sfd_uc_system_port 385 * Unique port identifier for the final destination of the packet. 386 * Access: RW 387 */ 388 MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16, 389 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 390 391 static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index, 392 enum mlxsw_reg_sfd_rec_type rec_type, 393 const char *mac, 394 enum mlxsw_reg_sfd_rec_action action) 395 { 396 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload); 397 398 if (rec_index >= num_rec) 399 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1); 400 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0); 401 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type); 402 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac); 403 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action); 404 } 405 406 static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index, 407 enum mlxsw_reg_sfd_rec_policy policy, 408 const char *mac, u16 fid_vid, 409 enum mlxsw_reg_sfd_rec_action action, 410 u8 local_port) 411 { 412 mlxsw_reg_sfd_rec_pack(payload, rec_index, 413 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action); 414 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 415 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0); 416 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid); 417 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port); 418 } 419 420 static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index, 421 char *mac, u16 *p_fid_vid, 422 u8 *p_local_port) 423 { 424 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 425 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index); 426 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index); 427 } 428 429 /* reg_sfd_uc_lag_sub_port 430 * LAG sub port. 431 * Must be 0 if multichannel VEPA is not enabled. 432 * Access: RW 433 */ 434 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8, 435 MLXSW_REG_SFD_REC_LEN, 0x08, false); 436 437 /* reg_sfd_uc_lag_fid_vid 438 * Filtering ID or VLAN ID 439 * For SwitchX and SwitchX-2: 440 * - Dynamic entries (policy 2,3) use FID 441 * - Static entries (policy 0) use VID 442 * - When independent learning is configured, VID=FID 443 * For Spectrum: use FID for both Dynamic and Static entries. 444 * VID should not be used. 445 * Access: Index 446 */ 447 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 448 MLXSW_REG_SFD_REC_LEN, 0x08, false); 449 450 /* reg_sfd_uc_lag_lag_vid 451 * Indicates VID in case of vFIDs. Reserved for FIDs. 452 * Access: RW 453 */ 454 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12, 455 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 456 457 /* reg_sfd_uc_lag_lag_id 458 * LAG Identifier - pointer into the LAG descriptor table. 459 * Access: RW 460 */ 461 MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10, 462 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 463 464 static inline void 465 mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index, 466 enum mlxsw_reg_sfd_rec_policy policy, 467 const char *mac, u16 fid_vid, 468 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid, 469 u16 lag_id) 470 { 471 mlxsw_reg_sfd_rec_pack(payload, rec_index, 472 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG, 473 mac, action); 474 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 475 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0); 476 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid); 477 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid); 478 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id); 479 } 480 481 static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index, 482 char *mac, u16 *p_vid, 483 u16 *p_lag_id) 484 { 485 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac); 486 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index); 487 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index); 488 } 489 490 /* reg_sfd_mc_pgi 491 * 492 * Multicast port group index - index into the port group table. 493 * Value 0x1FFF indicates the pgi should point to the MID entry. 494 * For Spectrum this value must be set to 0x1FFF 495 * Access: RW 496 */ 497 MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13, 498 MLXSW_REG_SFD_REC_LEN, 0x08, false); 499 500 /* reg_sfd_mc_fid_vid 501 * 502 * Filtering ID or VLAN ID 503 * Access: Index 504 */ 505 MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 506 MLXSW_REG_SFD_REC_LEN, 0x08, false); 507 508 /* reg_sfd_mc_mid 509 * 510 * Multicast identifier - global identifier that represents the multicast 511 * group across all devices. 512 * Access: RW 513 */ 514 MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 515 MLXSW_REG_SFD_REC_LEN, 0x0C, false); 516 517 static inline void 518 mlxsw_reg_sfd_mc_pack(char *payload, int rec_index, 519 const char *mac, u16 fid_vid, 520 enum mlxsw_reg_sfd_rec_action action, u16 mid) 521 { 522 mlxsw_reg_sfd_rec_pack(payload, rec_index, 523 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action); 524 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF); 525 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid); 526 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid); 527 } 528 529 /* reg_sfd_uc_tunnel_uip_msb 530 * When protocol is IPv4, the most significant byte of the underlay IPv4 531 * destination IP. 532 * When protocol is IPv6, reserved. 533 * Access: RW 534 */ 535 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_msb, MLXSW_REG_SFD_BASE_LEN, 24, 536 8, MLXSW_REG_SFD_REC_LEN, 0x08, false); 537 538 /* reg_sfd_uc_tunnel_fid 539 * Filtering ID. 540 * Access: Index 541 */ 542 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_fid, MLXSW_REG_SFD_BASE_LEN, 0, 16, 543 MLXSW_REG_SFD_REC_LEN, 0x08, false); 544 545 enum mlxsw_reg_sfd_uc_tunnel_protocol { 546 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV4, 547 MLXSW_REG_SFD_UC_TUNNEL_PROTOCOL_IPV6, 548 }; 549 550 /* reg_sfd_uc_tunnel_protocol 551 * IP protocol. 552 * Access: RW 553 */ 554 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_protocol, MLXSW_REG_SFD_BASE_LEN, 27, 555 1, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 556 557 /* reg_sfd_uc_tunnel_uip_lsb 558 * When protocol is IPv4, the least significant bytes of the underlay 559 * IPv4 destination IP. 560 * When protocol is IPv6, pointer to the underlay IPv6 destination IP 561 * which is configured by RIPS. 562 * Access: RW 563 */ 564 MLXSW_ITEM32_INDEXED(reg, sfd, uc_tunnel_uip_lsb, MLXSW_REG_SFD_BASE_LEN, 0, 565 24, MLXSW_REG_SFD_REC_LEN, 0x0C, false); 566 567 static inline void 568 mlxsw_reg_sfd_uc_tunnel_pack(char *payload, int rec_index, 569 enum mlxsw_reg_sfd_rec_policy policy, 570 const char *mac, u16 fid, 571 enum mlxsw_reg_sfd_rec_action action, u32 uip, 572 enum mlxsw_reg_sfd_uc_tunnel_protocol proto) 573 { 574 mlxsw_reg_sfd_rec_pack(payload, rec_index, 575 MLXSW_REG_SFD_REC_TYPE_UNICAST_TUNNEL, mac, 576 action); 577 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy); 578 mlxsw_reg_sfd_uc_tunnel_uip_msb_set(payload, rec_index, uip >> 24); 579 mlxsw_reg_sfd_uc_tunnel_uip_lsb_set(payload, rec_index, uip); 580 mlxsw_reg_sfd_uc_tunnel_fid_set(payload, rec_index, fid); 581 mlxsw_reg_sfd_uc_tunnel_protocol_set(payload, rec_index, proto); 582 } 583 584 /* SFN - Switch FDB Notification Register 585 * ------------------------------------------- 586 * The switch provides notifications on newly learned FDB entries and 587 * aged out entries. The notifications can be polled by software. 588 */ 589 #define MLXSW_REG_SFN_ID 0x200B 590 #define MLXSW_REG_SFN_BASE_LEN 0x10 /* base length, without records */ 591 #define MLXSW_REG_SFN_REC_LEN 0x10 /* record length */ 592 #define MLXSW_REG_SFN_REC_MAX_COUNT 64 593 #define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \ 594 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT) 595 596 MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN); 597 598 /* reg_sfn_swid 599 * Switch partition ID. 600 * Access: Index 601 */ 602 MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8); 603 604 /* reg_sfn_end 605 * Forces the current session to end. 606 * Access: OP 607 */ 608 MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1); 609 610 /* reg_sfn_num_rec 611 * Request: Number of learned notifications and aged-out notification 612 * records requested. 613 * Response: Number of notification records returned (must be smaller 614 * than or equal to the value requested) 615 * Ranges 0..64 616 * Access: OP 617 */ 618 MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8); 619 620 static inline void mlxsw_reg_sfn_pack(char *payload) 621 { 622 MLXSW_REG_ZERO(sfn, payload); 623 mlxsw_reg_sfn_swid_set(payload, 0); 624 mlxsw_reg_sfn_end_set(payload, 0); 625 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT); 626 } 627 628 /* reg_sfn_rec_swid 629 * Switch partition ID. 630 * Access: RO 631 */ 632 MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8, 633 MLXSW_REG_SFN_REC_LEN, 0x00, false); 634 635 enum mlxsw_reg_sfn_rec_type { 636 /* MAC addresses learned on a regular port. */ 637 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5, 638 /* MAC addresses learned on a LAG port. */ 639 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6, 640 /* Aged-out MAC address on a regular port. */ 641 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7, 642 /* Aged-out MAC address on a LAG port. */ 643 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8, 644 /* Learned unicast tunnel record. */ 645 MLXSW_REG_SFN_REC_TYPE_LEARNED_UNICAST_TUNNEL = 0xD, 646 /* Aged-out unicast tunnel record. */ 647 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_UNICAST_TUNNEL = 0xE, 648 }; 649 650 /* reg_sfn_rec_type 651 * Notification record type. 652 * Access: RO 653 */ 654 MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4, 655 MLXSW_REG_SFN_REC_LEN, 0x00, false); 656 657 /* reg_sfn_rec_mac 658 * MAC address. 659 * Access: RO 660 */ 661 MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6, 662 MLXSW_REG_SFN_REC_LEN, 0x02); 663 664 /* reg_sfn_mac_sub_port 665 * VEPA channel on the local port. 666 * 0 if multichannel VEPA is not enabled. 667 * Access: RO 668 */ 669 MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8, 670 MLXSW_REG_SFN_REC_LEN, 0x08, false); 671 672 /* reg_sfn_mac_fid 673 * Filtering identifier. 674 * Access: RO 675 */ 676 MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16, 677 MLXSW_REG_SFN_REC_LEN, 0x08, false); 678 679 /* reg_sfn_mac_system_port 680 * Unique port identifier for the final destination of the packet. 681 * Access: RO 682 */ 683 MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16, 684 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 685 686 static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index, 687 char *mac, u16 *p_vid, 688 u8 *p_local_port) 689 { 690 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 691 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 692 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index); 693 } 694 695 /* reg_sfn_mac_lag_lag_id 696 * LAG ID (pointer into the LAG descriptor table). 697 * Access: RO 698 */ 699 MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10, 700 MLXSW_REG_SFN_REC_LEN, 0x0C, false); 701 702 static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index, 703 char *mac, u16 *p_vid, 704 u16 *p_lag_id) 705 { 706 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 707 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 708 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index); 709 } 710 711 /* reg_sfn_uc_tunnel_uip_msb 712 * When protocol is IPv4, the most significant byte of the underlay IPv4 713 * address of the remote VTEP. 714 * When protocol is IPv6, reserved. 715 * Access: RO 716 */ 717 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_msb, MLXSW_REG_SFN_BASE_LEN, 24, 718 8, MLXSW_REG_SFN_REC_LEN, 0x08, false); 719 720 enum mlxsw_reg_sfn_uc_tunnel_protocol { 721 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV4, 722 MLXSW_REG_SFN_UC_TUNNEL_PROTOCOL_IPV6, 723 }; 724 725 /* reg_sfn_uc_tunnel_protocol 726 * IP protocol. 727 * Access: RO 728 */ 729 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_protocol, MLXSW_REG_SFN_BASE_LEN, 27, 730 1, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 731 732 /* reg_sfn_uc_tunnel_uip_lsb 733 * When protocol is IPv4, the least significant bytes of the underlay 734 * IPv4 address of the remote VTEP. 735 * When protocol is IPv6, ipv6_id to be queried from TNIPSD. 736 * Access: RO 737 */ 738 MLXSW_ITEM32_INDEXED(reg, sfn, uc_tunnel_uip_lsb, MLXSW_REG_SFN_BASE_LEN, 0, 739 24, MLXSW_REG_SFN_REC_LEN, 0x0C, false); 740 741 enum mlxsw_reg_sfn_tunnel_port { 742 MLXSW_REG_SFN_TUNNEL_PORT_NVE, 743 MLXSW_REG_SFN_TUNNEL_PORT_VPLS, 744 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL0, 745 MLXSW_REG_SFN_TUNNEL_FLEX_TUNNEL1, 746 }; 747 748 /* reg_sfn_uc_tunnel_port 749 * Tunnel port. 750 * Reserved on Spectrum. 751 * Access: RO 752 */ 753 MLXSW_ITEM32_INDEXED(reg, sfn, tunnel_port, MLXSW_REG_SFN_BASE_LEN, 0, 4, 754 MLXSW_REG_SFN_REC_LEN, 0x10, false); 755 756 static inline void 757 mlxsw_reg_sfn_uc_tunnel_unpack(char *payload, int rec_index, char *mac, 758 u16 *p_fid, u32 *p_uip, 759 enum mlxsw_reg_sfn_uc_tunnel_protocol *p_proto) 760 { 761 u32 uip_msb, uip_lsb; 762 763 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac); 764 *p_fid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index); 765 uip_msb = mlxsw_reg_sfn_uc_tunnel_uip_msb_get(payload, rec_index); 766 uip_lsb = mlxsw_reg_sfn_uc_tunnel_uip_lsb_get(payload, rec_index); 767 *p_uip = uip_msb << 24 | uip_lsb; 768 *p_proto = mlxsw_reg_sfn_uc_tunnel_protocol_get(payload, rec_index); 769 } 770 771 /* SPMS - Switch Port MSTP/RSTP State Register 772 * ------------------------------------------- 773 * Configures the spanning tree state of a physical port. 774 */ 775 #define MLXSW_REG_SPMS_ID 0x200D 776 #define MLXSW_REG_SPMS_LEN 0x404 777 778 MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN); 779 780 /* reg_spms_local_port 781 * Local port number. 782 * Access: Index 783 */ 784 MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8); 785 786 enum mlxsw_reg_spms_state { 787 MLXSW_REG_SPMS_STATE_NO_CHANGE, 788 MLXSW_REG_SPMS_STATE_DISCARDING, 789 MLXSW_REG_SPMS_STATE_LEARNING, 790 MLXSW_REG_SPMS_STATE_FORWARDING, 791 }; 792 793 /* reg_spms_state 794 * Spanning tree state of each VLAN ID (VID) of the local port. 795 * 0 - Do not change spanning tree state (used only when writing). 796 * 1 - Discarding. No learning or forwarding to/from this port (default). 797 * 2 - Learning. Port is learning, but not forwarding. 798 * 3 - Forwarding. Port is learning and forwarding. 799 * Access: RW 800 */ 801 MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2); 802 803 static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port) 804 { 805 MLXSW_REG_ZERO(spms, payload); 806 mlxsw_reg_spms_local_port_set(payload, local_port); 807 } 808 809 static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid, 810 enum mlxsw_reg_spms_state state) 811 { 812 mlxsw_reg_spms_state_set(payload, vid, state); 813 } 814 815 /* SPVID - Switch Port VID 816 * ----------------------- 817 * The switch port VID configures the default VID for a port. 818 */ 819 #define MLXSW_REG_SPVID_ID 0x200E 820 #define MLXSW_REG_SPVID_LEN 0x08 821 822 MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN); 823 824 /* reg_spvid_local_port 825 * Local port number. 826 * Access: Index 827 */ 828 MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8); 829 830 /* reg_spvid_sub_port 831 * Virtual port within the physical port. 832 * Should be set to 0 when virtual ports are not enabled on the port. 833 * Access: Index 834 */ 835 MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8); 836 837 /* reg_spvid_pvid 838 * Port default VID 839 * Access: RW 840 */ 841 MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12); 842 843 static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid) 844 { 845 MLXSW_REG_ZERO(spvid, payload); 846 mlxsw_reg_spvid_local_port_set(payload, local_port); 847 mlxsw_reg_spvid_pvid_set(payload, pvid); 848 } 849 850 /* SPVM - Switch Port VLAN Membership 851 * ---------------------------------- 852 * The Switch Port VLAN Membership register configures the VLAN membership 853 * of a port in a VLAN denoted by VID. VLAN membership is managed per 854 * virtual port. The register can be used to add and remove VID(s) from a port. 855 */ 856 #define MLXSW_REG_SPVM_ID 0x200F 857 #define MLXSW_REG_SPVM_BASE_LEN 0x04 /* base length, without records */ 858 #define MLXSW_REG_SPVM_REC_LEN 0x04 /* record length */ 859 #define MLXSW_REG_SPVM_REC_MAX_COUNT 255 860 #define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \ 861 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT) 862 863 MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN); 864 865 /* reg_spvm_pt 866 * Priority tagged. If this bit is set, packets forwarded to the port with 867 * untagged VLAN membership (u bit is set) will be tagged with priority tag 868 * (VID=0) 869 * Access: RW 870 */ 871 MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1); 872 873 /* reg_spvm_pte 874 * Priority Tagged Update Enable. On Write operations, if this bit is cleared, 875 * the pt bit will NOT be updated. To update the pt bit, pte must be set. 876 * Access: WO 877 */ 878 MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1); 879 880 /* reg_spvm_local_port 881 * Local port number. 882 * Access: Index 883 */ 884 MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8); 885 886 /* reg_spvm_sub_port 887 * Virtual port within the physical port. 888 * Should be set to 0 when virtual ports are not enabled on the port. 889 * Access: Index 890 */ 891 MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8); 892 893 /* reg_spvm_num_rec 894 * Number of records to update. Each record contains: i, e, u, vid. 895 * Access: OP 896 */ 897 MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8); 898 899 /* reg_spvm_rec_i 900 * Ingress membership in VLAN ID. 901 * Access: Index 902 */ 903 MLXSW_ITEM32_INDEXED(reg, spvm, rec_i, 904 MLXSW_REG_SPVM_BASE_LEN, 14, 1, 905 MLXSW_REG_SPVM_REC_LEN, 0, false); 906 907 /* reg_spvm_rec_e 908 * Egress membership in VLAN ID. 909 * Access: Index 910 */ 911 MLXSW_ITEM32_INDEXED(reg, spvm, rec_e, 912 MLXSW_REG_SPVM_BASE_LEN, 13, 1, 913 MLXSW_REG_SPVM_REC_LEN, 0, false); 914 915 /* reg_spvm_rec_u 916 * Untagged - port is an untagged member - egress transmission uses untagged 917 * frames on VID<n> 918 * Access: Index 919 */ 920 MLXSW_ITEM32_INDEXED(reg, spvm, rec_u, 921 MLXSW_REG_SPVM_BASE_LEN, 12, 1, 922 MLXSW_REG_SPVM_REC_LEN, 0, false); 923 924 /* reg_spvm_rec_vid 925 * Egress membership in VLAN ID. 926 * Access: Index 927 */ 928 MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid, 929 MLXSW_REG_SPVM_BASE_LEN, 0, 12, 930 MLXSW_REG_SPVM_REC_LEN, 0, false); 931 932 static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port, 933 u16 vid_begin, u16 vid_end, 934 bool is_member, bool untagged) 935 { 936 int size = vid_end - vid_begin + 1; 937 int i; 938 939 MLXSW_REG_ZERO(spvm, payload); 940 mlxsw_reg_spvm_local_port_set(payload, local_port); 941 mlxsw_reg_spvm_num_rec_set(payload, size); 942 943 for (i = 0; i < size; i++) { 944 mlxsw_reg_spvm_rec_i_set(payload, i, is_member); 945 mlxsw_reg_spvm_rec_e_set(payload, i, is_member); 946 mlxsw_reg_spvm_rec_u_set(payload, i, untagged); 947 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i); 948 } 949 } 950 951 /* SPAFT - Switch Port Acceptable Frame Types 952 * ------------------------------------------ 953 * The Switch Port Acceptable Frame Types register configures the frame 954 * admittance of the port. 955 */ 956 #define MLXSW_REG_SPAFT_ID 0x2010 957 #define MLXSW_REG_SPAFT_LEN 0x08 958 959 MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN); 960 961 /* reg_spaft_local_port 962 * Local port number. 963 * Access: Index 964 * 965 * Note: CPU port is not supported (all tag types are allowed). 966 */ 967 MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8); 968 969 /* reg_spaft_sub_port 970 * Virtual port within the physical port. 971 * Should be set to 0 when virtual ports are not enabled on the port. 972 * Access: RW 973 */ 974 MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8); 975 976 /* reg_spaft_allow_untagged 977 * When set, untagged frames on the ingress are allowed (default). 978 * Access: RW 979 */ 980 MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1); 981 982 /* reg_spaft_allow_prio_tagged 983 * When set, priority tagged frames on the ingress are allowed (default). 984 * Access: RW 985 */ 986 MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1); 987 988 /* reg_spaft_allow_tagged 989 * When set, tagged frames on the ingress are allowed (default). 990 * Access: RW 991 */ 992 MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1); 993 994 static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port, 995 bool allow_untagged) 996 { 997 MLXSW_REG_ZERO(spaft, payload); 998 mlxsw_reg_spaft_local_port_set(payload, local_port); 999 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged); 1000 mlxsw_reg_spaft_allow_prio_tagged_set(payload, allow_untagged); 1001 mlxsw_reg_spaft_allow_tagged_set(payload, true); 1002 } 1003 1004 /* SFGC - Switch Flooding Group Configuration 1005 * ------------------------------------------ 1006 * The following register controls the association of flooding tables and MIDs 1007 * to packet types used for flooding. 1008 */ 1009 #define MLXSW_REG_SFGC_ID 0x2011 1010 #define MLXSW_REG_SFGC_LEN 0x10 1011 1012 MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN); 1013 1014 enum mlxsw_reg_sfgc_type { 1015 MLXSW_REG_SFGC_TYPE_BROADCAST, 1016 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST, 1017 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4, 1018 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6, 1019 MLXSW_REG_SFGC_TYPE_RESERVED, 1020 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP, 1021 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL, 1022 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST, 1023 MLXSW_REG_SFGC_TYPE_MAX, 1024 }; 1025 1026 /* reg_sfgc_type 1027 * The traffic type to reach the flooding table. 1028 * Access: Index 1029 */ 1030 MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4); 1031 1032 enum mlxsw_reg_sfgc_bridge_type { 1033 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0, 1034 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1, 1035 }; 1036 1037 /* reg_sfgc_bridge_type 1038 * Access: Index 1039 * 1040 * Note: SwitchX-2 only supports 802.1Q mode. 1041 */ 1042 MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3); 1043 1044 enum mlxsw_flood_table_type { 1045 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1, 1046 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2, 1047 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0, 1048 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3, 1049 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4, 1050 }; 1051 1052 /* reg_sfgc_table_type 1053 * See mlxsw_flood_table_type 1054 * Access: RW 1055 * 1056 * Note: FID offset and FID types are not supported in SwitchX-2. 1057 */ 1058 MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3); 1059 1060 /* reg_sfgc_flood_table 1061 * Flooding table index to associate with the specific type on the specific 1062 * switch partition. 1063 * Access: RW 1064 */ 1065 MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6); 1066 1067 /* reg_sfgc_mid 1068 * The multicast ID for the swid. Not supported for Spectrum 1069 * Access: RW 1070 */ 1071 MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16); 1072 1073 /* reg_sfgc_counter_set_type 1074 * Counter Set Type for flow counters. 1075 * Access: RW 1076 */ 1077 MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8); 1078 1079 /* reg_sfgc_counter_index 1080 * Counter Index for flow counters. 1081 * Access: RW 1082 */ 1083 MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24); 1084 1085 static inline void 1086 mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type, 1087 enum mlxsw_reg_sfgc_bridge_type bridge_type, 1088 enum mlxsw_flood_table_type table_type, 1089 unsigned int flood_table) 1090 { 1091 MLXSW_REG_ZERO(sfgc, payload); 1092 mlxsw_reg_sfgc_type_set(payload, type); 1093 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type); 1094 mlxsw_reg_sfgc_table_type_set(payload, table_type); 1095 mlxsw_reg_sfgc_flood_table_set(payload, flood_table); 1096 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID); 1097 } 1098 1099 /* SFTR - Switch Flooding Table Register 1100 * ------------------------------------- 1101 * The switch flooding table is used for flooding packet replication. The table 1102 * defines a bit mask of ports for packet replication. 1103 */ 1104 #define MLXSW_REG_SFTR_ID 0x2012 1105 #define MLXSW_REG_SFTR_LEN 0x420 1106 1107 MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN); 1108 1109 /* reg_sftr_swid 1110 * Switch partition ID with which to associate the port. 1111 * Access: Index 1112 */ 1113 MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8); 1114 1115 /* reg_sftr_flood_table 1116 * Flooding table index to associate with the specific type on the specific 1117 * switch partition. 1118 * Access: Index 1119 */ 1120 MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6); 1121 1122 /* reg_sftr_index 1123 * Index. Used as an index into the Flooding Table in case the table is 1124 * configured to use VID / FID or FID Offset. 1125 * Access: Index 1126 */ 1127 MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16); 1128 1129 /* reg_sftr_table_type 1130 * See mlxsw_flood_table_type 1131 * Access: RW 1132 */ 1133 MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3); 1134 1135 /* reg_sftr_range 1136 * Range of entries to update 1137 * Access: Index 1138 */ 1139 MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16); 1140 1141 /* reg_sftr_port 1142 * Local port membership (1 bit per port). 1143 * Access: RW 1144 */ 1145 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1); 1146 1147 /* reg_sftr_cpu_port_mask 1148 * CPU port mask (1 bit per port). 1149 * Access: W 1150 */ 1151 MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1); 1152 1153 static inline void mlxsw_reg_sftr_pack(char *payload, 1154 unsigned int flood_table, 1155 unsigned int index, 1156 enum mlxsw_flood_table_type table_type, 1157 unsigned int range, u8 port, bool set) 1158 { 1159 MLXSW_REG_ZERO(sftr, payload); 1160 mlxsw_reg_sftr_swid_set(payload, 0); 1161 mlxsw_reg_sftr_flood_table_set(payload, flood_table); 1162 mlxsw_reg_sftr_index_set(payload, index); 1163 mlxsw_reg_sftr_table_type_set(payload, table_type); 1164 mlxsw_reg_sftr_range_set(payload, range); 1165 mlxsw_reg_sftr_port_set(payload, port, set); 1166 mlxsw_reg_sftr_port_mask_set(payload, port, 1); 1167 } 1168 1169 /* SFDF - Switch Filtering DB Flush 1170 * -------------------------------- 1171 * The switch filtering DB flush register is used to flush the FDB. 1172 * Note that FDB notifications are flushed as well. 1173 */ 1174 #define MLXSW_REG_SFDF_ID 0x2013 1175 #define MLXSW_REG_SFDF_LEN 0x14 1176 1177 MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN); 1178 1179 /* reg_sfdf_swid 1180 * Switch partition ID. 1181 * Access: Index 1182 */ 1183 MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8); 1184 1185 enum mlxsw_reg_sfdf_flush_type { 1186 MLXSW_REG_SFDF_FLUSH_PER_SWID, 1187 MLXSW_REG_SFDF_FLUSH_PER_FID, 1188 MLXSW_REG_SFDF_FLUSH_PER_PORT, 1189 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID, 1190 MLXSW_REG_SFDF_FLUSH_PER_LAG, 1191 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID, 1192 MLXSW_REG_SFDF_FLUSH_PER_NVE, 1193 MLXSW_REG_SFDF_FLUSH_PER_NVE_AND_FID, 1194 }; 1195 1196 /* reg_sfdf_flush_type 1197 * Flush type. 1198 * 0 - All SWID dynamic entries are flushed. 1199 * 1 - All FID dynamic entries are flushed. 1200 * 2 - All dynamic entries pointing to port are flushed. 1201 * 3 - All FID dynamic entries pointing to port are flushed. 1202 * 4 - All dynamic entries pointing to LAG are flushed. 1203 * 5 - All FID dynamic entries pointing to LAG are flushed. 1204 * 6 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1205 * flushed. 1206 * 7 - All entries of type "Unicast Tunnel" or "Multicast Tunnel" are 1207 * flushed, per FID. 1208 * Access: RW 1209 */ 1210 MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4); 1211 1212 /* reg_sfdf_flush_static 1213 * Static. 1214 * 0 - Flush only dynamic entries. 1215 * 1 - Flush both dynamic and static entries. 1216 * Access: RW 1217 */ 1218 MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1); 1219 1220 static inline void mlxsw_reg_sfdf_pack(char *payload, 1221 enum mlxsw_reg_sfdf_flush_type type) 1222 { 1223 MLXSW_REG_ZERO(sfdf, payload); 1224 mlxsw_reg_sfdf_flush_type_set(payload, type); 1225 mlxsw_reg_sfdf_flush_static_set(payload, true); 1226 } 1227 1228 /* reg_sfdf_fid 1229 * FID to flush. 1230 * Access: RW 1231 */ 1232 MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16); 1233 1234 /* reg_sfdf_system_port 1235 * Port to flush. 1236 * Access: RW 1237 */ 1238 MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16); 1239 1240 /* reg_sfdf_port_fid_system_port 1241 * Port to flush, pointed to by FID. 1242 * Access: RW 1243 */ 1244 MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16); 1245 1246 /* reg_sfdf_lag_id 1247 * LAG ID to flush. 1248 * Access: RW 1249 */ 1250 MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10); 1251 1252 /* reg_sfdf_lag_fid_lag_id 1253 * LAG ID to flush, pointed to by FID. 1254 * Access: RW 1255 */ 1256 MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10); 1257 1258 /* SLDR - Switch LAG Descriptor Register 1259 * ----------------------------------------- 1260 * The switch LAG descriptor register is populated by LAG descriptors. 1261 * Each LAG descriptor is indexed by lag_id. The LAG ID runs from 0 to 1262 * max_lag-1. 1263 */ 1264 #define MLXSW_REG_SLDR_ID 0x2014 1265 #define MLXSW_REG_SLDR_LEN 0x0C /* counting in only one port in list */ 1266 1267 MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN); 1268 1269 enum mlxsw_reg_sldr_op { 1270 /* Indicates a creation of a new LAG-ID, lag_id must be valid */ 1271 MLXSW_REG_SLDR_OP_LAG_CREATE, 1272 MLXSW_REG_SLDR_OP_LAG_DESTROY, 1273 /* Ports that appear in the list have the Distributor enabled */ 1274 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST, 1275 /* Removes ports from the disributor list */ 1276 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST, 1277 }; 1278 1279 /* reg_sldr_op 1280 * Operation. 1281 * Access: RW 1282 */ 1283 MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3); 1284 1285 /* reg_sldr_lag_id 1286 * LAG identifier. The lag_id is the index into the LAG descriptor table. 1287 * Access: Index 1288 */ 1289 MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10); 1290 1291 static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id) 1292 { 1293 MLXSW_REG_ZERO(sldr, payload); 1294 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE); 1295 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1296 } 1297 1298 static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id) 1299 { 1300 MLXSW_REG_ZERO(sldr, payload); 1301 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY); 1302 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1303 } 1304 1305 /* reg_sldr_num_ports 1306 * The number of member ports of the LAG. 1307 * Reserved for Create / Destroy operations 1308 * For Add / Remove operations - indicates the number of ports in the list. 1309 * Access: RW 1310 */ 1311 MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8); 1312 1313 /* reg_sldr_system_port 1314 * System port. 1315 * Access: RW 1316 */ 1317 MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false); 1318 1319 static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id, 1320 u8 local_port) 1321 { 1322 MLXSW_REG_ZERO(sldr, payload); 1323 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST); 1324 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1325 mlxsw_reg_sldr_num_ports_set(payload, 1); 1326 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1327 } 1328 1329 static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id, 1330 u8 local_port) 1331 { 1332 MLXSW_REG_ZERO(sldr, payload); 1333 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST); 1334 mlxsw_reg_sldr_lag_id_set(payload, lag_id); 1335 mlxsw_reg_sldr_num_ports_set(payload, 1); 1336 mlxsw_reg_sldr_system_port_set(payload, 0, local_port); 1337 } 1338 1339 /* SLCR - Switch LAG Configuration 2 Register 1340 * ------------------------------------------- 1341 * The Switch LAG Configuration register is used for configuring the 1342 * LAG properties of the switch. 1343 */ 1344 #define MLXSW_REG_SLCR_ID 0x2015 1345 #define MLXSW_REG_SLCR_LEN 0x10 1346 1347 MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN); 1348 1349 enum mlxsw_reg_slcr_pp { 1350 /* Global Configuration (for all ports) */ 1351 MLXSW_REG_SLCR_PP_GLOBAL, 1352 /* Per port configuration, based on local_port field */ 1353 MLXSW_REG_SLCR_PP_PER_PORT, 1354 }; 1355 1356 /* reg_slcr_pp 1357 * Per Port Configuration 1358 * Note: Reading at Global mode results in reading port 1 configuration. 1359 * Access: Index 1360 */ 1361 MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1); 1362 1363 /* reg_slcr_local_port 1364 * Local port number 1365 * Supported from CPU port 1366 * Not supported from router port 1367 * Reserved when pp = Global Configuration 1368 * Access: Index 1369 */ 1370 MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8); 1371 1372 enum mlxsw_reg_slcr_type { 1373 MLXSW_REG_SLCR_TYPE_CRC, /* default */ 1374 MLXSW_REG_SLCR_TYPE_XOR, 1375 MLXSW_REG_SLCR_TYPE_RANDOM, 1376 }; 1377 1378 /* reg_slcr_type 1379 * Hash type 1380 * Access: RW 1381 */ 1382 MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4); 1383 1384 /* Ingress port */ 1385 #define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0) 1386 /* SMAC - for IPv4 and IPv6 packets */ 1387 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1) 1388 /* SMAC - for non-IP packets */ 1389 #define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2) 1390 #define MLXSW_REG_SLCR_LAG_HASH_SMAC \ 1391 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \ 1392 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP) 1393 /* DMAC - for IPv4 and IPv6 packets */ 1394 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3) 1395 /* DMAC - for non-IP packets */ 1396 #define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4) 1397 #define MLXSW_REG_SLCR_LAG_HASH_DMAC \ 1398 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \ 1399 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP) 1400 /* Ethertype - for IPv4 and IPv6 packets */ 1401 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5) 1402 /* Ethertype - for non-IP packets */ 1403 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6) 1404 #define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \ 1405 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \ 1406 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP) 1407 /* VLAN ID - for IPv4 and IPv6 packets */ 1408 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7) 1409 /* VLAN ID - for non-IP packets */ 1410 #define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8) 1411 #define MLXSW_REG_SLCR_LAG_HASH_VLANID \ 1412 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \ 1413 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP) 1414 /* Source IP address (can be IPv4 or IPv6) */ 1415 #define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9) 1416 /* Destination IP address (can be IPv4 or IPv6) */ 1417 #define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10) 1418 /* TCP/UDP source port */ 1419 #define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11) 1420 /* TCP/UDP destination port*/ 1421 #define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12) 1422 /* IPv4 Protocol/IPv6 Next Header */ 1423 #define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13) 1424 /* IPv6 Flow label */ 1425 #define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14) 1426 /* SID - FCoE source ID */ 1427 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15) 1428 /* DID - FCoE destination ID */ 1429 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16) 1430 /* OXID - FCoE originator exchange ID */ 1431 #define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17) 1432 /* Destination QP number - for RoCE packets */ 1433 #define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19) 1434 1435 /* reg_slcr_lag_hash 1436 * LAG hashing configuration. This is a bitmask, in which each set 1437 * bit includes the corresponding item in the LAG hash calculation. 1438 * The default lag_hash contains SMAC, DMAC, VLANID and 1439 * Ethertype (for all packet types). 1440 * Access: RW 1441 */ 1442 MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20); 1443 1444 /* reg_slcr_seed 1445 * LAG seed value. The seed is the same for all ports. 1446 * Access: RW 1447 */ 1448 MLXSW_ITEM32(reg, slcr, seed, 0x08, 0, 32); 1449 1450 static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash, u32 seed) 1451 { 1452 MLXSW_REG_ZERO(slcr, payload); 1453 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL); 1454 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC); 1455 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash); 1456 mlxsw_reg_slcr_seed_set(payload, seed); 1457 } 1458 1459 /* SLCOR - Switch LAG Collector Register 1460 * ------------------------------------- 1461 * The Switch LAG Collector register controls the Local Port membership 1462 * in a LAG and enablement of the collector. 1463 */ 1464 #define MLXSW_REG_SLCOR_ID 0x2016 1465 #define MLXSW_REG_SLCOR_LEN 0x10 1466 1467 MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN); 1468 1469 enum mlxsw_reg_slcor_col { 1470 /* Port is added with collector disabled */ 1471 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT, 1472 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED, 1473 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED, 1474 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT, 1475 }; 1476 1477 /* reg_slcor_col 1478 * Collector configuration 1479 * Access: RW 1480 */ 1481 MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2); 1482 1483 /* reg_slcor_local_port 1484 * Local port number 1485 * Not supported for CPU port 1486 * Access: Index 1487 */ 1488 MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8); 1489 1490 /* reg_slcor_lag_id 1491 * LAG Identifier. Index into the LAG descriptor table. 1492 * Access: Index 1493 */ 1494 MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10); 1495 1496 /* reg_slcor_port_index 1497 * Port index in the LAG list. Only valid on Add Port to LAG col. 1498 * Valid range is from 0 to cap_max_lag_members-1 1499 * Access: RW 1500 */ 1501 MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10); 1502 1503 static inline void mlxsw_reg_slcor_pack(char *payload, 1504 u8 local_port, u16 lag_id, 1505 enum mlxsw_reg_slcor_col col) 1506 { 1507 MLXSW_REG_ZERO(slcor, payload); 1508 mlxsw_reg_slcor_col_set(payload, col); 1509 mlxsw_reg_slcor_local_port_set(payload, local_port); 1510 mlxsw_reg_slcor_lag_id_set(payload, lag_id); 1511 } 1512 1513 static inline void mlxsw_reg_slcor_port_add_pack(char *payload, 1514 u8 local_port, u16 lag_id, 1515 u8 port_index) 1516 { 1517 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1518 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT); 1519 mlxsw_reg_slcor_port_index_set(payload, port_index); 1520 } 1521 1522 static inline void mlxsw_reg_slcor_port_remove_pack(char *payload, 1523 u8 local_port, u16 lag_id) 1524 { 1525 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1526 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT); 1527 } 1528 1529 static inline void mlxsw_reg_slcor_col_enable_pack(char *payload, 1530 u8 local_port, u16 lag_id) 1531 { 1532 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1533 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1534 } 1535 1536 static inline void mlxsw_reg_slcor_col_disable_pack(char *payload, 1537 u8 local_port, u16 lag_id) 1538 { 1539 mlxsw_reg_slcor_pack(payload, local_port, lag_id, 1540 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED); 1541 } 1542 1543 /* SPMLR - Switch Port MAC Learning Register 1544 * ----------------------------------------- 1545 * Controls the Switch MAC learning policy per port. 1546 */ 1547 #define MLXSW_REG_SPMLR_ID 0x2018 1548 #define MLXSW_REG_SPMLR_LEN 0x8 1549 1550 MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN); 1551 1552 /* reg_spmlr_local_port 1553 * Local port number. 1554 * Access: Index 1555 */ 1556 MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8); 1557 1558 /* reg_spmlr_sub_port 1559 * Virtual port within the physical port. 1560 * Should be set to 0 when virtual ports are not enabled on the port. 1561 * Access: Index 1562 */ 1563 MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8); 1564 1565 enum mlxsw_reg_spmlr_learn_mode { 1566 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0, 1567 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2, 1568 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3, 1569 }; 1570 1571 /* reg_spmlr_learn_mode 1572 * Learning mode on the port. 1573 * 0 - Learning disabled. 1574 * 2 - Learning enabled. 1575 * 3 - Security mode. 1576 * 1577 * In security mode the switch does not learn MACs on the port, but uses the 1578 * SMAC to see if it exists on another ingress port. If so, the packet is 1579 * classified as a bad packet and is discarded unless the software registers 1580 * to receive port security error packets usign HPKT. 1581 */ 1582 MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2); 1583 1584 static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port, 1585 enum mlxsw_reg_spmlr_learn_mode mode) 1586 { 1587 MLXSW_REG_ZERO(spmlr, payload); 1588 mlxsw_reg_spmlr_local_port_set(payload, local_port); 1589 mlxsw_reg_spmlr_sub_port_set(payload, 0); 1590 mlxsw_reg_spmlr_learn_mode_set(payload, mode); 1591 } 1592 1593 /* SVFA - Switch VID to FID Allocation Register 1594 * -------------------------------------------- 1595 * Controls the VID to FID mapping and {Port, VID} to FID mapping for 1596 * virtualized ports. 1597 */ 1598 #define MLXSW_REG_SVFA_ID 0x201C 1599 #define MLXSW_REG_SVFA_LEN 0x10 1600 1601 MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN); 1602 1603 /* reg_svfa_swid 1604 * Switch partition ID. 1605 * Access: Index 1606 */ 1607 MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8); 1608 1609 /* reg_svfa_local_port 1610 * Local port number. 1611 * Access: Index 1612 * 1613 * Note: Reserved for 802.1Q FIDs. 1614 */ 1615 MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8); 1616 1617 enum mlxsw_reg_svfa_mt { 1618 MLXSW_REG_SVFA_MT_VID_TO_FID, 1619 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID, 1620 }; 1621 1622 /* reg_svfa_mapping_table 1623 * Mapping table: 1624 * 0 - VID to FID 1625 * 1 - {Port, VID} to FID 1626 * Access: Index 1627 * 1628 * Note: Reserved for SwitchX-2. 1629 */ 1630 MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3); 1631 1632 /* reg_svfa_v 1633 * Valid. 1634 * Valid if set. 1635 * Access: RW 1636 * 1637 * Note: Reserved for SwitchX-2. 1638 */ 1639 MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1); 1640 1641 /* reg_svfa_fid 1642 * Filtering ID. 1643 * Access: RW 1644 */ 1645 MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16); 1646 1647 /* reg_svfa_vid 1648 * VLAN ID. 1649 * Access: Index 1650 */ 1651 MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12); 1652 1653 /* reg_svfa_counter_set_type 1654 * Counter set type for flow counters. 1655 * Access: RW 1656 * 1657 * Note: Reserved for SwitchX-2. 1658 */ 1659 MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8); 1660 1661 /* reg_svfa_counter_index 1662 * Counter index for flow counters. 1663 * Access: RW 1664 * 1665 * Note: Reserved for SwitchX-2. 1666 */ 1667 MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24); 1668 1669 static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port, 1670 enum mlxsw_reg_svfa_mt mt, bool valid, 1671 u16 fid, u16 vid) 1672 { 1673 MLXSW_REG_ZERO(svfa, payload); 1674 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port; 1675 mlxsw_reg_svfa_swid_set(payload, 0); 1676 mlxsw_reg_svfa_local_port_set(payload, local_port); 1677 mlxsw_reg_svfa_mapping_table_set(payload, mt); 1678 mlxsw_reg_svfa_v_set(payload, valid); 1679 mlxsw_reg_svfa_fid_set(payload, fid); 1680 mlxsw_reg_svfa_vid_set(payload, vid); 1681 } 1682 1683 /* SVPE - Switch Virtual-Port Enabling Register 1684 * -------------------------------------------- 1685 * Enables port virtualization. 1686 */ 1687 #define MLXSW_REG_SVPE_ID 0x201E 1688 #define MLXSW_REG_SVPE_LEN 0x4 1689 1690 MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN); 1691 1692 /* reg_svpe_local_port 1693 * Local port number 1694 * Access: Index 1695 * 1696 * Note: CPU port is not supported (uses VLAN mode only). 1697 */ 1698 MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8); 1699 1700 /* reg_svpe_vp_en 1701 * Virtual port enable. 1702 * 0 - Disable, VLAN mode (VID to FID). 1703 * 1 - Enable, Virtual port mode ({Port, VID} to FID). 1704 * Access: RW 1705 */ 1706 MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1); 1707 1708 static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port, 1709 bool enable) 1710 { 1711 MLXSW_REG_ZERO(svpe, payload); 1712 mlxsw_reg_svpe_local_port_set(payload, local_port); 1713 mlxsw_reg_svpe_vp_en_set(payload, enable); 1714 } 1715 1716 /* SFMR - Switch FID Management Register 1717 * ------------------------------------- 1718 * Creates and configures FIDs. 1719 */ 1720 #define MLXSW_REG_SFMR_ID 0x201F 1721 #define MLXSW_REG_SFMR_LEN 0x18 1722 1723 MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN); 1724 1725 enum mlxsw_reg_sfmr_op { 1726 MLXSW_REG_SFMR_OP_CREATE_FID, 1727 MLXSW_REG_SFMR_OP_DESTROY_FID, 1728 }; 1729 1730 /* reg_sfmr_op 1731 * Operation. 1732 * 0 - Create or edit FID. 1733 * 1 - Destroy FID. 1734 * Access: WO 1735 */ 1736 MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4); 1737 1738 /* reg_sfmr_fid 1739 * Filtering ID. 1740 * Access: Index 1741 */ 1742 MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16); 1743 1744 /* reg_sfmr_fid_offset 1745 * FID offset. 1746 * Used to point into the flooding table selected by SFGC register if 1747 * the table is of type FID-Offset. Otherwise, this field is reserved. 1748 * Access: RW 1749 */ 1750 MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16); 1751 1752 /* reg_sfmr_vtfp 1753 * Valid Tunnel Flood Pointer. 1754 * If not set, then nve_tunnel_flood_ptr is reserved and considered NULL. 1755 * Access: RW 1756 * 1757 * Note: Reserved for 802.1Q FIDs. 1758 */ 1759 MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1); 1760 1761 /* reg_sfmr_nve_tunnel_flood_ptr 1762 * Underlay Flooding and BC Pointer. 1763 * Used as a pointer to the first entry of the group based link lists of 1764 * flooding or BC entries (for NVE tunnels). 1765 * Access: RW 1766 */ 1767 MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24); 1768 1769 /* reg_sfmr_vv 1770 * VNI Valid. 1771 * If not set, then vni is reserved. 1772 * Access: RW 1773 * 1774 * Note: Reserved for 802.1Q FIDs. 1775 */ 1776 MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1); 1777 1778 /* reg_sfmr_vni 1779 * Virtual Network Identifier. 1780 * Access: RW 1781 * 1782 * Note: A given VNI can only be assigned to one FID. 1783 */ 1784 MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24); 1785 1786 static inline void mlxsw_reg_sfmr_pack(char *payload, 1787 enum mlxsw_reg_sfmr_op op, u16 fid, 1788 u16 fid_offset) 1789 { 1790 MLXSW_REG_ZERO(sfmr, payload); 1791 mlxsw_reg_sfmr_op_set(payload, op); 1792 mlxsw_reg_sfmr_fid_set(payload, fid); 1793 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset); 1794 mlxsw_reg_sfmr_vtfp_set(payload, false); 1795 mlxsw_reg_sfmr_vv_set(payload, false); 1796 } 1797 1798 /* SPVMLR - Switch Port VLAN MAC Learning Register 1799 * ----------------------------------------------- 1800 * Controls the switch MAC learning policy per {Port, VID}. 1801 */ 1802 #define MLXSW_REG_SPVMLR_ID 0x2020 1803 #define MLXSW_REG_SPVMLR_BASE_LEN 0x04 /* base length, without records */ 1804 #define MLXSW_REG_SPVMLR_REC_LEN 0x04 /* record length */ 1805 #define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255 1806 #define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \ 1807 MLXSW_REG_SPVMLR_REC_LEN * \ 1808 MLXSW_REG_SPVMLR_REC_MAX_COUNT) 1809 1810 MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN); 1811 1812 /* reg_spvmlr_local_port 1813 * Local ingress port. 1814 * Access: Index 1815 * 1816 * Note: CPU port is not supported. 1817 */ 1818 MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8); 1819 1820 /* reg_spvmlr_num_rec 1821 * Number of records to update. 1822 * Access: OP 1823 */ 1824 MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8); 1825 1826 /* reg_spvmlr_rec_learn_enable 1827 * 0 - Disable learning for {Port, VID}. 1828 * 1 - Enable learning for {Port, VID}. 1829 * Access: RW 1830 */ 1831 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN, 1832 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1833 1834 /* reg_spvmlr_rec_vid 1835 * VLAN ID to be added/removed from port or for querying. 1836 * Access: Index 1837 */ 1838 MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12, 1839 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false); 1840 1841 static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port, 1842 u16 vid_begin, u16 vid_end, 1843 bool learn_enable) 1844 { 1845 int num_rec = vid_end - vid_begin + 1; 1846 int i; 1847 1848 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT); 1849 1850 MLXSW_REG_ZERO(spvmlr, payload); 1851 mlxsw_reg_spvmlr_local_port_set(payload, local_port); 1852 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec); 1853 1854 for (i = 0; i < num_rec; i++) { 1855 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable); 1856 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i); 1857 } 1858 } 1859 1860 /* CWTP - Congetion WRED ECN TClass Profile 1861 * ---------------------------------------- 1862 * Configures the profiles for queues of egress port and traffic class 1863 */ 1864 #define MLXSW_REG_CWTP_ID 0x2802 1865 #define MLXSW_REG_CWTP_BASE_LEN 0x28 1866 #define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08 1867 #define MLXSW_REG_CWTP_LEN 0x40 1868 1869 MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN); 1870 1871 /* reg_cwtp_local_port 1872 * Local port number 1873 * Not supported for CPU port 1874 * Access: Index 1875 */ 1876 MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8); 1877 1878 /* reg_cwtp_traffic_class 1879 * Traffic Class to configure 1880 * Access: Index 1881 */ 1882 MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8); 1883 1884 /* reg_cwtp_profile_min 1885 * Minimum Average Queue Size of the profile in cells. 1886 * Access: RW 1887 */ 1888 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN, 1889 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false); 1890 1891 /* reg_cwtp_profile_percent 1892 * Percentage of WRED and ECN marking for maximum Average Queue size 1893 * Range is 0 to 100, units of integer percentage 1894 * Access: RW 1895 */ 1896 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN, 1897 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1898 1899 /* reg_cwtp_profile_max 1900 * Maximum Average Queue size of the profile in cells 1901 * Access: RW 1902 */ 1903 MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN, 1904 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false); 1905 1906 #define MLXSW_REG_CWTP_MIN_VALUE 64 1907 #define MLXSW_REG_CWTP_MAX_PROFILE 2 1908 #define MLXSW_REG_CWTP_DEFAULT_PROFILE 1 1909 1910 static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port, 1911 u8 traffic_class) 1912 { 1913 int i; 1914 1915 MLXSW_REG_ZERO(cwtp, payload); 1916 mlxsw_reg_cwtp_local_port_set(payload, local_port); 1917 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class); 1918 1919 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) { 1920 mlxsw_reg_cwtp_profile_min_set(payload, i, 1921 MLXSW_REG_CWTP_MIN_VALUE); 1922 mlxsw_reg_cwtp_profile_max_set(payload, i, 1923 MLXSW_REG_CWTP_MIN_VALUE); 1924 } 1925 } 1926 1927 #define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1) 1928 1929 static inline void 1930 mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max, 1931 u32 probability) 1932 { 1933 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile); 1934 1935 mlxsw_reg_cwtp_profile_min_set(payload, index, min); 1936 mlxsw_reg_cwtp_profile_max_set(payload, index, max); 1937 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability); 1938 } 1939 1940 /* CWTPM - Congestion WRED ECN TClass and Pool Mapping 1941 * --------------------------------------------------- 1942 * The CWTPM register maps each egress port and traffic class to profile num. 1943 */ 1944 #define MLXSW_REG_CWTPM_ID 0x2803 1945 #define MLXSW_REG_CWTPM_LEN 0x44 1946 1947 MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN); 1948 1949 /* reg_cwtpm_local_port 1950 * Local port number 1951 * Not supported for CPU port 1952 * Access: Index 1953 */ 1954 MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8); 1955 1956 /* reg_cwtpm_traffic_class 1957 * Traffic Class to configure 1958 * Access: Index 1959 */ 1960 MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8); 1961 1962 /* reg_cwtpm_ew 1963 * Control enablement of WRED for traffic class: 1964 * 0 - Disable 1965 * 1 - Enable 1966 * Access: RW 1967 */ 1968 MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1); 1969 1970 /* reg_cwtpm_ee 1971 * Control enablement of ECN for traffic class: 1972 * 0 - Disable 1973 * 1 - Enable 1974 * Access: RW 1975 */ 1976 MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1); 1977 1978 /* reg_cwtpm_tcp_g 1979 * TCP Green Profile. 1980 * Index of the profile within {port, traffic class} to use. 1981 * 0 for disabling both WRED and ECN for this type of traffic. 1982 * Access: RW 1983 */ 1984 MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2); 1985 1986 /* reg_cwtpm_tcp_y 1987 * TCP Yellow Profile. 1988 * Index of the profile within {port, traffic class} to use. 1989 * 0 for disabling both WRED and ECN for this type of traffic. 1990 * Access: RW 1991 */ 1992 MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2); 1993 1994 /* reg_cwtpm_tcp_r 1995 * TCP Red Profile. 1996 * Index of the profile within {port, traffic class} to use. 1997 * 0 for disabling both WRED and ECN for this type of traffic. 1998 * Access: RW 1999 */ 2000 MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2); 2001 2002 /* reg_cwtpm_ntcp_g 2003 * Non-TCP Green Profile. 2004 * Index of the profile within {port, traffic class} to use. 2005 * 0 for disabling both WRED and ECN for this type of traffic. 2006 * Access: RW 2007 */ 2008 MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2); 2009 2010 /* reg_cwtpm_ntcp_y 2011 * Non-TCP Yellow Profile. 2012 * Index of the profile within {port, traffic class} to use. 2013 * 0 for disabling both WRED and ECN for this type of traffic. 2014 * Access: RW 2015 */ 2016 MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2); 2017 2018 /* reg_cwtpm_ntcp_r 2019 * Non-TCP Red Profile. 2020 * Index of the profile within {port, traffic class} to use. 2021 * 0 for disabling both WRED and ECN for this type of traffic. 2022 * Access: RW 2023 */ 2024 MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2); 2025 2026 #define MLXSW_REG_CWTPM_RESET_PROFILE 0 2027 2028 static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port, 2029 u8 traffic_class, u8 profile, 2030 bool wred, bool ecn) 2031 { 2032 MLXSW_REG_ZERO(cwtpm, payload); 2033 mlxsw_reg_cwtpm_local_port_set(payload, local_port); 2034 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class); 2035 mlxsw_reg_cwtpm_ew_set(payload, wred); 2036 mlxsw_reg_cwtpm_ee_set(payload, ecn); 2037 mlxsw_reg_cwtpm_tcp_g_set(payload, profile); 2038 mlxsw_reg_cwtpm_tcp_y_set(payload, profile); 2039 mlxsw_reg_cwtpm_tcp_r_set(payload, profile); 2040 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile); 2041 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile); 2042 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile); 2043 } 2044 2045 /* PGCR - Policy-Engine General Configuration Register 2046 * --------------------------------------------------- 2047 * This register configures general Policy-Engine settings. 2048 */ 2049 #define MLXSW_REG_PGCR_ID 0x3001 2050 #define MLXSW_REG_PGCR_LEN 0x20 2051 2052 MLXSW_REG_DEFINE(pgcr, MLXSW_REG_PGCR_ID, MLXSW_REG_PGCR_LEN); 2053 2054 /* reg_pgcr_default_action_pointer_base 2055 * Default action pointer base. Each region has a default action pointer 2056 * which is equal to default_action_pointer_base + region_id. 2057 * Access: RW 2058 */ 2059 MLXSW_ITEM32(reg, pgcr, default_action_pointer_base, 0x1C, 0, 24); 2060 2061 static inline void mlxsw_reg_pgcr_pack(char *payload, u32 pointer_base) 2062 { 2063 MLXSW_REG_ZERO(pgcr, payload); 2064 mlxsw_reg_pgcr_default_action_pointer_base_set(payload, pointer_base); 2065 } 2066 2067 /* PPBT - Policy-Engine Port Binding Table 2068 * --------------------------------------- 2069 * This register is used for configuration of the Port Binding Table. 2070 */ 2071 #define MLXSW_REG_PPBT_ID 0x3002 2072 #define MLXSW_REG_PPBT_LEN 0x14 2073 2074 MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN); 2075 2076 enum mlxsw_reg_pxbt_e { 2077 MLXSW_REG_PXBT_E_IACL, 2078 MLXSW_REG_PXBT_E_EACL, 2079 }; 2080 2081 /* reg_ppbt_e 2082 * Access: Index 2083 */ 2084 MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1); 2085 2086 enum mlxsw_reg_pxbt_op { 2087 MLXSW_REG_PXBT_OP_BIND, 2088 MLXSW_REG_PXBT_OP_UNBIND, 2089 }; 2090 2091 /* reg_ppbt_op 2092 * Access: RW 2093 */ 2094 MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3); 2095 2096 /* reg_ppbt_local_port 2097 * Local port. Not including CPU port. 2098 * Access: Index 2099 */ 2100 MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8); 2101 2102 /* reg_ppbt_g 2103 * group - When set, the binding is of an ACL group. When cleared, 2104 * the binding is of an ACL. 2105 * Must be set to 1 for Spectrum. 2106 * Access: RW 2107 */ 2108 MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1); 2109 2110 /* reg_ppbt_acl_info 2111 * ACL/ACL group identifier. If the g bit is set, this field should hold 2112 * the acl_group_id, else it should hold the acl_id. 2113 * Access: RW 2114 */ 2115 MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16); 2116 2117 static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e, 2118 enum mlxsw_reg_pxbt_op op, 2119 u8 local_port, u16 acl_info) 2120 { 2121 MLXSW_REG_ZERO(ppbt, payload); 2122 mlxsw_reg_ppbt_e_set(payload, e); 2123 mlxsw_reg_ppbt_op_set(payload, op); 2124 mlxsw_reg_ppbt_local_port_set(payload, local_port); 2125 mlxsw_reg_ppbt_g_set(payload, true); 2126 mlxsw_reg_ppbt_acl_info_set(payload, acl_info); 2127 } 2128 2129 /* PACL - Policy-Engine ACL Register 2130 * --------------------------------- 2131 * This register is used for configuration of the ACL. 2132 */ 2133 #define MLXSW_REG_PACL_ID 0x3004 2134 #define MLXSW_REG_PACL_LEN 0x70 2135 2136 MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN); 2137 2138 /* reg_pacl_v 2139 * Valid. Setting the v bit makes the ACL valid. It should not be cleared 2140 * while the ACL is bounded to either a port, VLAN or ACL rule. 2141 * Access: RW 2142 */ 2143 MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1); 2144 2145 /* reg_pacl_acl_id 2146 * An identifier representing the ACL (managed by software) 2147 * Range 0 .. cap_max_acl_regions - 1 2148 * Access: Index 2149 */ 2150 MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16); 2151 2152 #define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16 2153 2154 /* reg_pacl_tcam_region_info 2155 * Opaque object that represents a TCAM region. 2156 * Obtained through PTAR register. 2157 * Access: RW 2158 */ 2159 MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30, 2160 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2161 2162 static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id, 2163 bool valid, const char *tcam_region_info) 2164 { 2165 MLXSW_REG_ZERO(pacl, payload); 2166 mlxsw_reg_pacl_acl_id_set(payload, acl_id); 2167 mlxsw_reg_pacl_v_set(payload, valid); 2168 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info); 2169 } 2170 2171 /* PAGT - Policy-Engine ACL Group Table 2172 * ------------------------------------ 2173 * This register is used for configuration of the ACL Group Table. 2174 */ 2175 #define MLXSW_REG_PAGT_ID 0x3005 2176 #define MLXSW_REG_PAGT_BASE_LEN 0x30 2177 #define MLXSW_REG_PAGT_ACL_LEN 4 2178 #define MLXSW_REG_PAGT_ACL_MAX_NUM 16 2179 #define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \ 2180 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN) 2181 2182 MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN); 2183 2184 /* reg_pagt_size 2185 * Number of ACLs in the group. 2186 * Size 0 invalidates a group. 2187 * Range 0 .. cap_max_acl_group_size (hard coded to 16 for now) 2188 * Total number of ACLs in all groups must be lower or equal 2189 * to cap_max_acl_tot_groups 2190 * Note: a group which is binded must not be invalidated 2191 * Access: Index 2192 */ 2193 MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8); 2194 2195 /* reg_pagt_acl_group_id 2196 * An identifier (numbered from 0..cap_max_acl_groups-1) representing 2197 * the ACL Group identifier (managed by software). 2198 * Access: Index 2199 */ 2200 MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16); 2201 2202 /* reg_pagt_multi 2203 * Multi-ACL 2204 * 0 - This ACL is the last ACL in the multi-ACL 2205 * 1 - This ACL is part of a multi-ACL 2206 * Access: RW 2207 */ 2208 MLXSW_ITEM32_INDEXED(reg, pagt, multi, 0x30, 31, 1, 0x04, 0x00, false); 2209 2210 /* reg_pagt_acl_id 2211 * ACL identifier 2212 * Access: RW 2213 */ 2214 MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false); 2215 2216 static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id) 2217 { 2218 MLXSW_REG_ZERO(pagt, payload); 2219 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id); 2220 } 2221 2222 static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index, 2223 u16 acl_id, bool multi) 2224 { 2225 u8 size = mlxsw_reg_pagt_size_get(payload); 2226 2227 if (index >= size) 2228 mlxsw_reg_pagt_size_set(payload, index + 1); 2229 mlxsw_reg_pagt_multi_set(payload, index, multi); 2230 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id); 2231 } 2232 2233 /* PTAR - Policy-Engine TCAM Allocation Register 2234 * --------------------------------------------- 2235 * This register is used for allocation of regions in the TCAM. 2236 * Note: Query method is not supported on this register. 2237 */ 2238 #define MLXSW_REG_PTAR_ID 0x3006 2239 #define MLXSW_REG_PTAR_BASE_LEN 0x20 2240 #define MLXSW_REG_PTAR_KEY_ID_LEN 1 2241 #define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16 2242 #define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \ 2243 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN) 2244 2245 MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN); 2246 2247 enum mlxsw_reg_ptar_op { 2248 /* allocate a TCAM region */ 2249 MLXSW_REG_PTAR_OP_ALLOC, 2250 /* resize a TCAM region */ 2251 MLXSW_REG_PTAR_OP_RESIZE, 2252 /* deallocate TCAM region */ 2253 MLXSW_REG_PTAR_OP_FREE, 2254 /* test allocation */ 2255 MLXSW_REG_PTAR_OP_TEST, 2256 }; 2257 2258 /* reg_ptar_op 2259 * Access: OP 2260 */ 2261 MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4); 2262 2263 /* reg_ptar_action_set_type 2264 * Type of action set to be used on this region. 2265 * For Spectrum and Spectrum-2, this is always type 2 - "flexible" 2266 * Access: WO 2267 */ 2268 MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8); 2269 2270 enum mlxsw_reg_ptar_key_type { 2271 MLXSW_REG_PTAR_KEY_TYPE_FLEX = 0x50, /* Spetrum */ 2272 MLXSW_REG_PTAR_KEY_TYPE_FLEX2 = 0x51, /* Spectrum-2 */ 2273 }; 2274 2275 /* reg_ptar_key_type 2276 * TCAM key type for the region. 2277 * Access: WO 2278 */ 2279 MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8); 2280 2281 /* reg_ptar_region_size 2282 * TCAM region size. When allocating/resizing this is the requested size, 2283 * the response is the actual size. Note that actual size may be 2284 * larger than requested. 2285 * Allowed range 1 .. cap_max_rules-1 2286 * Reserved during op deallocate. 2287 * Access: WO 2288 */ 2289 MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16); 2290 2291 /* reg_ptar_region_id 2292 * Region identifier 2293 * Range 0 .. cap_max_regions-1 2294 * Access: Index 2295 */ 2296 MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16); 2297 2298 /* reg_ptar_tcam_region_info 2299 * Opaque object that represents the TCAM region. 2300 * Returned when allocating a region. 2301 * Provided by software for ACL generation and region deallocation and resize. 2302 * Access: RW 2303 */ 2304 MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10, 2305 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2306 2307 /* reg_ptar_flexible_key_id 2308 * Identifier of the Flexible Key. 2309 * Only valid if key_type == "FLEX_KEY" 2310 * The key size will be rounded up to one of the following values: 2311 * 9B, 18B, 36B, 54B. 2312 * This field is reserved for in resize operation. 2313 * Access: WO 2314 */ 2315 MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8, 2316 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false); 2317 2318 static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op, 2319 enum mlxsw_reg_ptar_key_type key_type, 2320 u16 region_size, u16 region_id, 2321 const char *tcam_region_info) 2322 { 2323 MLXSW_REG_ZERO(ptar, payload); 2324 mlxsw_reg_ptar_op_set(payload, op); 2325 mlxsw_reg_ptar_action_set_type_set(payload, 2); /* "flexible" */ 2326 mlxsw_reg_ptar_key_type_set(payload, key_type); 2327 mlxsw_reg_ptar_region_size_set(payload, region_size); 2328 mlxsw_reg_ptar_region_id_set(payload, region_id); 2329 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info); 2330 } 2331 2332 static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index, 2333 u16 key_id) 2334 { 2335 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id); 2336 } 2337 2338 static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info) 2339 { 2340 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info); 2341 } 2342 2343 /* PPBS - Policy-Engine Policy Based Switching Register 2344 * ---------------------------------------------------- 2345 * This register retrieves and sets Policy Based Switching Table entries. 2346 */ 2347 #define MLXSW_REG_PPBS_ID 0x300C 2348 #define MLXSW_REG_PPBS_LEN 0x14 2349 2350 MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN); 2351 2352 /* reg_ppbs_pbs_ptr 2353 * Index into the PBS table. 2354 * For Spectrum, the index points to the KVD Linear. 2355 * Access: Index 2356 */ 2357 MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24); 2358 2359 /* reg_ppbs_system_port 2360 * Unique port identifier for the final destination of the packet. 2361 * Access: RW 2362 */ 2363 MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16); 2364 2365 static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr, 2366 u16 system_port) 2367 { 2368 MLXSW_REG_ZERO(ppbs, payload); 2369 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr); 2370 mlxsw_reg_ppbs_system_port_set(payload, system_port); 2371 } 2372 2373 /* PRCR - Policy-Engine Rules Copy Register 2374 * ---------------------------------------- 2375 * This register is used for accessing rules within a TCAM region. 2376 */ 2377 #define MLXSW_REG_PRCR_ID 0x300D 2378 #define MLXSW_REG_PRCR_LEN 0x40 2379 2380 MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN); 2381 2382 enum mlxsw_reg_prcr_op { 2383 /* Move rules. Moves the rules from "tcam_region_info" starting 2384 * at offset "offset" to "dest_tcam_region_info" 2385 * at offset "dest_offset." 2386 */ 2387 MLXSW_REG_PRCR_OP_MOVE, 2388 /* Copy rules. Copies the rules from "tcam_region_info" starting 2389 * at offset "offset" to "dest_tcam_region_info" 2390 * at offset "dest_offset." 2391 */ 2392 MLXSW_REG_PRCR_OP_COPY, 2393 }; 2394 2395 /* reg_prcr_op 2396 * Access: OP 2397 */ 2398 MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4); 2399 2400 /* reg_prcr_offset 2401 * Offset within the source region to copy/move from. 2402 * Access: Index 2403 */ 2404 MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16); 2405 2406 /* reg_prcr_size 2407 * The number of rules to copy/move. 2408 * Access: WO 2409 */ 2410 MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16); 2411 2412 /* reg_prcr_tcam_region_info 2413 * Opaque object that represents the source TCAM region. 2414 * Access: Index 2415 */ 2416 MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10, 2417 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2418 2419 /* reg_prcr_dest_offset 2420 * Offset within the source region to copy/move to. 2421 * Access: Index 2422 */ 2423 MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16); 2424 2425 /* reg_prcr_dest_tcam_region_info 2426 * Opaque object that represents the destination TCAM region. 2427 * Access: Index 2428 */ 2429 MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30, 2430 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2431 2432 static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op, 2433 const char *src_tcam_region_info, 2434 u16 src_offset, 2435 const char *dest_tcam_region_info, 2436 u16 dest_offset, u16 size) 2437 { 2438 MLXSW_REG_ZERO(prcr, payload); 2439 mlxsw_reg_prcr_op_set(payload, op); 2440 mlxsw_reg_prcr_offset_set(payload, src_offset); 2441 mlxsw_reg_prcr_size_set(payload, size); 2442 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload, 2443 src_tcam_region_info); 2444 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset); 2445 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload, 2446 dest_tcam_region_info); 2447 } 2448 2449 /* PEFA - Policy-Engine Extended Flexible Action Register 2450 * ------------------------------------------------------ 2451 * This register is used for accessing an extended flexible action entry 2452 * in the central KVD Linear Database. 2453 */ 2454 #define MLXSW_REG_PEFA_ID 0x300F 2455 #define MLXSW_REG_PEFA_LEN 0xB0 2456 2457 MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN); 2458 2459 /* reg_pefa_index 2460 * Index in the KVD Linear Centralized Database. 2461 * Access: Index 2462 */ 2463 MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24); 2464 2465 /* reg_pefa_a 2466 * Index in the KVD Linear Centralized Database. 2467 * Activity 2468 * For a new entry: set if ca=0, clear if ca=1 2469 * Set if a packet lookup has hit on the specific entry 2470 * Access: RO 2471 */ 2472 MLXSW_ITEM32(reg, pefa, a, 0x04, 29, 1); 2473 2474 /* reg_pefa_ca 2475 * Clear activity 2476 * When write: activity is according to this field 2477 * When read: after reading the activity is cleared according to ca 2478 * Access: OP 2479 */ 2480 MLXSW_ITEM32(reg, pefa, ca, 0x04, 24, 1); 2481 2482 #define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8 2483 2484 /* reg_pefa_flex_action_set 2485 * Action-set to perform when rule is matched. 2486 * Must be zero padded if action set is shorter. 2487 * Access: RW 2488 */ 2489 MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN); 2490 2491 static inline void mlxsw_reg_pefa_pack(char *payload, u32 index, bool ca, 2492 const char *flex_action_set) 2493 { 2494 MLXSW_REG_ZERO(pefa, payload); 2495 mlxsw_reg_pefa_index_set(payload, index); 2496 mlxsw_reg_pefa_ca_set(payload, ca); 2497 if (flex_action_set) 2498 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, 2499 flex_action_set); 2500 } 2501 2502 static inline void mlxsw_reg_pefa_unpack(char *payload, bool *p_a) 2503 { 2504 *p_a = mlxsw_reg_pefa_a_get(payload); 2505 } 2506 2507 /* PEMRBT - Policy-Engine Multicast Router Binding Table Register 2508 * -------------------------------------------------------------- 2509 * This register is used for binding Multicast router to an ACL group 2510 * that serves the MC router. 2511 * This register is not supported by SwitchX/-2 and Spectrum. 2512 */ 2513 #define MLXSW_REG_PEMRBT_ID 0x3014 2514 #define MLXSW_REG_PEMRBT_LEN 0x14 2515 2516 MLXSW_REG_DEFINE(pemrbt, MLXSW_REG_PEMRBT_ID, MLXSW_REG_PEMRBT_LEN); 2517 2518 enum mlxsw_reg_pemrbt_protocol { 2519 MLXSW_REG_PEMRBT_PROTO_IPV4, 2520 MLXSW_REG_PEMRBT_PROTO_IPV6, 2521 }; 2522 2523 /* reg_pemrbt_protocol 2524 * Access: Index 2525 */ 2526 MLXSW_ITEM32(reg, pemrbt, protocol, 0x00, 0, 1); 2527 2528 /* reg_pemrbt_group_id 2529 * ACL group identifier. 2530 * Range 0..cap_max_acl_groups-1 2531 * Access: RW 2532 */ 2533 MLXSW_ITEM32(reg, pemrbt, group_id, 0x10, 0, 16); 2534 2535 static inline void 2536 mlxsw_reg_pemrbt_pack(char *payload, enum mlxsw_reg_pemrbt_protocol protocol, 2537 u16 group_id) 2538 { 2539 MLXSW_REG_ZERO(pemrbt, payload); 2540 mlxsw_reg_pemrbt_protocol_set(payload, protocol); 2541 mlxsw_reg_pemrbt_group_id_set(payload, group_id); 2542 } 2543 2544 /* PTCE-V2 - Policy-Engine TCAM Entry Register Version 2 2545 * ----------------------------------------------------- 2546 * This register is used for accessing rules within a TCAM region. 2547 * It is a new version of PTCE in order to support wider key, 2548 * mask and action within a TCAM region. This register is not supported 2549 * by SwitchX and SwitchX-2. 2550 */ 2551 #define MLXSW_REG_PTCE2_ID 0x3017 2552 #define MLXSW_REG_PTCE2_LEN 0x1D8 2553 2554 MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN); 2555 2556 /* reg_ptce2_v 2557 * Valid. 2558 * Access: RW 2559 */ 2560 MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1); 2561 2562 /* reg_ptce2_a 2563 * Activity. Set if a packet lookup has hit on the specific entry. 2564 * To clear the "a" bit, use "clear activity" op or "clear on read" op. 2565 * Access: RO 2566 */ 2567 MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1); 2568 2569 enum mlxsw_reg_ptce2_op { 2570 /* Read operation. */ 2571 MLXSW_REG_PTCE2_OP_QUERY_READ = 0, 2572 /* clear on read operation. Used to read entry 2573 * and clear Activity bit. 2574 */ 2575 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1, 2576 /* Write operation. Used to write a new entry to the table. 2577 * All R/W fields are relevant for new entry. Activity bit is set 2578 * for new entries - Note write with v = 0 will delete the entry. 2579 */ 2580 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0, 2581 /* Update action. Only action set will be updated. */ 2582 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1, 2583 /* Clear activity. A bit is cleared for the entry. */ 2584 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2, 2585 }; 2586 2587 /* reg_ptce2_op 2588 * Access: OP 2589 */ 2590 MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3); 2591 2592 /* reg_ptce2_offset 2593 * Access: Index 2594 */ 2595 MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16); 2596 2597 /* reg_ptce2_priority 2598 * Priority of the rule, higher values win. The range is 1..cap_kvd_size-1. 2599 * Note: priority does not have to be unique per rule. 2600 * Within a region, higher priority should have lower offset (no limitation 2601 * between regions in a multi-region). 2602 * Access: RW 2603 */ 2604 MLXSW_ITEM32(reg, ptce2, priority, 0x04, 0, 24); 2605 2606 /* reg_ptce2_tcam_region_info 2607 * Opaque object that represents the TCAM region. 2608 * Access: Index 2609 */ 2610 MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10, 2611 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2612 2613 #define MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN 96 2614 2615 /* reg_ptce2_flex_key_blocks 2616 * ACL Key. 2617 * Access: RW 2618 */ 2619 MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20, 2620 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2621 2622 /* reg_ptce2_mask 2623 * mask- in the same size as key. A bit that is set directs the TCAM 2624 * to compare the corresponding bit in key. A bit that is clear directs 2625 * the TCAM to ignore the corresponding bit in key. 2626 * Access: RW 2627 */ 2628 MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80, 2629 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2630 2631 /* reg_ptce2_flex_action_set 2632 * ACL action set. 2633 * Access: RW 2634 */ 2635 MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0, 2636 MLXSW_REG_FLEX_ACTION_SET_LEN); 2637 2638 static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid, 2639 enum mlxsw_reg_ptce2_op op, 2640 const char *tcam_region_info, 2641 u16 offset, u32 priority) 2642 { 2643 MLXSW_REG_ZERO(ptce2, payload); 2644 mlxsw_reg_ptce2_v_set(payload, valid); 2645 mlxsw_reg_ptce2_op_set(payload, op); 2646 mlxsw_reg_ptce2_offset_set(payload, offset); 2647 mlxsw_reg_ptce2_priority_set(payload, priority); 2648 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info); 2649 } 2650 2651 /* PERPT - Policy-Engine ERP Table Register 2652 * ---------------------------------------- 2653 * This register adds and removes eRPs from the eRP table. 2654 */ 2655 #define MLXSW_REG_PERPT_ID 0x3021 2656 #define MLXSW_REG_PERPT_LEN 0x80 2657 2658 MLXSW_REG_DEFINE(perpt, MLXSW_REG_PERPT_ID, MLXSW_REG_PERPT_LEN); 2659 2660 /* reg_perpt_erpt_bank 2661 * eRP table bank. 2662 * Range 0 .. cap_max_erp_table_banks - 1 2663 * Access: Index 2664 */ 2665 MLXSW_ITEM32(reg, perpt, erpt_bank, 0x00, 16, 4); 2666 2667 /* reg_perpt_erpt_index 2668 * Index to eRP table within the eRP bank. 2669 * Range is 0 .. cap_max_erp_table_bank_size - 1 2670 * Access: Index 2671 */ 2672 MLXSW_ITEM32(reg, perpt, erpt_index, 0x00, 0, 8); 2673 2674 enum mlxsw_reg_perpt_key_size { 2675 MLXSW_REG_PERPT_KEY_SIZE_2KB, 2676 MLXSW_REG_PERPT_KEY_SIZE_4KB, 2677 MLXSW_REG_PERPT_KEY_SIZE_8KB, 2678 MLXSW_REG_PERPT_KEY_SIZE_12KB, 2679 }; 2680 2681 /* reg_perpt_key_size 2682 * Access: OP 2683 */ 2684 MLXSW_ITEM32(reg, perpt, key_size, 0x04, 0, 4); 2685 2686 /* reg_perpt_bf_bypass 2687 * 0 - The eRP is used only if bloom filter state is set for the given 2688 * rule. 2689 * 1 - The eRP is used regardless of bloom filter state. 2690 * The bypass is an OR condition of region_id or eRP. See PERCR.bf_bypass 2691 * Access: RW 2692 */ 2693 MLXSW_ITEM32(reg, perpt, bf_bypass, 0x08, 8, 1); 2694 2695 /* reg_perpt_erp_id 2696 * eRP ID for use by the rules. 2697 * Access: RW 2698 */ 2699 MLXSW_ITEM32(reg, perpt, erp_id, 0x08, 0, 4); 2700 2701 /* reg_perpt_erpt_base_bank 2702 * Base eRP table bank, points to head of erp_vector 2703 * Range is 0 .. cap_max_erp_table_banks - 1 2704 * Access: OP 2705 */ 2706 MLXSW_ITEM32(reg, perpt, erpt_base_bank, 0x0C, 16, 4); 2707 2708 /* reg_perpt_erpt_base_index 2709 * Base index to eRP table within the eRP bank 2710 * Range is 0 .. cap_max_erp_table_bank_size - 1 2711 * Access: OP 2712 */ 2713 MLXSW_ITEM32(reg, perpt, erpt_base_index, 0x0C, 0, 8); 2714 2715 /* reg_perpt_erp_index_in_vector 2716 * eRP index in the vector. 2717 * Access: OP 2718 */ 2719 MLXSW_ITEM32(reg, perpt, erp_index_in_vector, 0x10, 0, 4); 2720 2721 /* reg_perpt_erp_vector 2722 * eRP vector. 2723 * Access: OP 2724 */ 2725 MLXSW_ITEM_BIT_ARRAY(reg, perpt, erp_vector, 0x14, 4, 1); 2726 2727 /* reg_perpt_mask 2728 * Mask 2729 * 0 - A-TCAM will ignore the bit in key 2730 * 1 - A-TCAM will compare the bit in key 2731 * Access: RW 2732 */ 2733 MLXSW_ITEM_BUF(reg, perpt, mask, 0x20, MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2734 2735 static inline void mlxsw_reg_perpt_erp_vector_pack(char *payload, 2736 unsigned long *erp_vector, 2737 unsigned long size) 2738 { 2739 unsigned long bit; 2740 2741 for_each_set_bit(bit, erp_vector, size) 2742 mlxsw_reg_perpt_erp_vector_set(payload, bit, true); 2743 } 2744 2745 static inline void 2746 mlxsw_reg_perpt_pack(char *payload, u8 erpt_bank, u8 erpt_index, 2747 enum mlxsw_reg_perpt_key_size key_size, u8 erp_id, 2748 u8 erpt_base_bank, u8 erpt_base_index, u8 erp_index, 2749 char *mask) 2750 { 2751 MLXSW_REG_ZERO(perpt, payload); 2752 mlxsw_reg_perpt_erpt_bank_set(payload, erpt_bank); 2753 mlxsw_reg_perpt_erpt_index_set(payload, erpt_index); 2754 mlxsw_reg_perpt_key_size_set(payload, key_size); 2755 mlxsw_reg_perpt_bf_bypass_set(payload, false); 2756 mlxsw_reg_perpt_erp_id_set(payload, erp_id); 2757 mlxsw_reg_perpt_erpt_base_bank_set(payload, erpt_base_bank); 2758 mlxsw_reg_perpt_erpt_base_index_set(payload, erpt_base_index); 2759 mlxsw_reg_perpt_erp_index_in_vector_set(payload, erp_index); 2760 mlxsw_reg_perpt_mask_memcpy_to(payload, mask); 2761 } 2762 2763 /* PERAR - Policy-Engine Region Association Register 2764 * ------------------------------------------------- 2765 * This register associates a hw region for region_id's. Changing on the fly 2766 * is supported by the device. 2767 */ 2768 #define MLXSW_REG_PERAR_ID 0x3026 2769 #define MLXSW_REG_PERAR_LEN 0x08 2770 2771 MLXSW_REG_DEFINE(perar, MLXSW_REG_PERAR_ID, MLXSW_REG_PERAR_LEN); 2772 2773 /* reg_perar_region_id 2774 * Region identifier 2775 * Range 0 .. cap_max_regions-1 2776 * Access: Index 2777 */ 2778 MLXSW_ITEM32(reg, perar, region_id, 0x00, 0, 16); 2779 2780 static inline unsigned int 2781 mlxsw_reg_perar_hw_regions_needed(unsigned int block_num) 2782 { 2783 return DIV_ROUND_UP(block_num, 4); 2784 } 2785 2786 /* reg_perar_hw_region 2787 * HW Region 2788 * Range 0 .. cap_max_regions-1 2789 * Default: hw_region = region_id 2790 * For a 8 key block region, 2 consecutive regions are used 2791 * For a 12 key block region, 3 consecutive regions are used 2792 * Access: RW 2793 */ 2794 MLXSW_ITEM32(reg, perar, hw_region, 0x04, 0, 16); 2795 2796 static inline void mlxsw_reg_perar_pack(char *payload, u16 region_id, 2797 u16 hw_region) 2798 { 2799 MLXSW_REG_ZERO(perar, payload); 2800 mlxsw_reg_perar_region_id_set(payload, region_id); 2801 mlxsw_reg_perar_hw_region_set(payload, hw_region); 2802 } 2803 2804 /* PTCE-V3 - Policy-Engine TCAM Entry Register Version 3 2805 * ----------------------------------------------------- 2806 * This register is a new version of PTCE-V2 in order to support the 2807 * A-TCAM. This register is not supported by SwitchX/-2 and Spectrum. 2808 */ 2809 #define MLXSW_REG_PTCE3_ID 0x3027 2810 #define MLXSW_REG_PTCE3_LEN 0xF0 2811 2812 MLXSW_REG_DEFINE(ptce3, MLXSW_REG_PTCE3_ID, MLXSW_REG_PTCE3_LEN); 2813 2814 /* reg_ptce3_v 2815 * Valid. 2816 * Access: RW 2817 */ 2818 MLXSW_ITEM32(reg, ptce3, v, 0x00, 31, 1); 2819 2820 enum mlxsw_reg_ptce3_op { 2821 /* Write operation. Used to write a new entry to the table. 2822 * All R/W fields are relevant for new entry. Activity bit is set 2823 * for new entries. Write with v = 0 will delete the entry. Must 2824 * not be used if an entry exists. 2825 */ 2826 MLXSW_REG_PTCE3_OP_WRITE_WRITE = 0, 2827 /* Update operation */ 2828 MLXSW_REG_PTCE3_OP_WRITE_UPDATE = 1, 2829 /* Read operation */ 2830 MLXSW_REG_PTCE3_OP_QUERY_READ = 0, 2831 }; 2832 2833 /* reg_ptce3_op 2834 * Access: OP 2835 */ 2836 MLXSW_ITEM32(reg, ptce3, op, 0x00, 20, 3); 2837 2838 /* reg_ptce3_priority 2839 * Priority of the rule. Higher values win. 2840 * For Spectrum-2 range is 1..cap_kvd_size - 1 2841 * Note: Priority does not have to be unique per rule. 2842 * Access: RW 2843 */ 2844 MLXSW_ITEM32(reg, ptce3, priority, 0x04, 0, 24); 2845 2846 /* reg_ptce3_tcam_region_info 2847 * Opaque object that represents the TCAM region. 2848 * Access: Index 2849 */ 2850 MLXSW_ITEM_BUF(reg, ptce3, tcam_region_info, 0x10, 2851 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN); 2852 2853 /* reg_ptce3_flex2_key_blocks 2854 * ACL key. The key must be masked according to eRP (if exists) or 2855 * according to master mask. 2856 * Access: Index 2857 */ 2858 MLXSW_ITEM_BUF(reg, ptce3, flex2_key_blocks, 0x20, 2859 MLXSW_REG_PTCEX_FLEX_KEY_BLOCKS_LEN); 2860 2861 /* reg_ptce3_erp_id 2862 * eRP ID. 2863 * Access: Index 2864 */ 2865 MLXSW_ITEM32(reg, ptce3, erp_id, 0x80, 0, 4); 2866 2867 /* reg_ptce3_delta_start 2868 * Start point of delta_value and delta_mask, in bits. Must not exceed 2869 * num_key_blocks * 36 - 8. Reserved when delta_mask = 0. 2870 * Access: Index 2871 */ 2872 MLXSW_ITEM32(reg, ptce3, delta_start, 0x84, 0, 10); 2873 2874 /* reg_ptce3_delta_mask 2875 * Delta mask. 2876 * 0 - Ignore relevant bit in delta_value 2877 * 1 - Compare relevant bit in delta_value 2878 * Delta mask must not be set for reserved fields in the key blocks. 2879 * Note: No delta when no eRPs. Thus, for regions with 2880 * PERERP.erpt_pointer_valid = 0 the delta mask must be 0. 2881 * Access: Index 2882 */ 2883 MLXSW_ITEM32(reg, ptce3, delta_mask, 0x88, 16, 8); 2884 2885 /* reg_ptce3_delta_value 2886 * Delta value. 2887 * Bits which are masked by delta_mask must be 0. 2888 * Access: Index 2889 */ 2890 MLXSW_ITEM32(reg, ptce3, delta_value, 0x88, 0, 8); 2891 2892 /* reg_ptce3_prune_vector 2893 * Pruning vector relative to the PERPT.erp_id. 2894 * Used for reducing lookups. 2895 * 0 - NEED: Do a lookup using the eRP. 2896 * 1 - PRUNE: Do not perform a lookup using the eRP. 2897 * Maybe be modified by PEAPBL and PEAPBM. 2898 * Note: In Spectrum-2, a region of 8 key blocks must be set to either 2899 * all 1's or all 0's. 2900 * Access: RW 2901 */ 2902 MLXSW_ITEM_BIT_ARRAY(reg, ptce3, prune_vector, 0x90, 4, 1); 2903 2904 /* reg_ptce3_prune_ctcam 2905 * Pruning on C-TCAM. Used for reducing lookups. 2906 * 0 - NEED: Do a lookup in the C-TCAM. 2907 * 1 - PRUNE: Do not perform a lookup in the C-TCAM. 2908 * Access: RW 2909 */ 2910 MLXSW_ITEM32(reg, ptce3, prune_ctcam, 0x94, 31, 1); 2911 2912 /* reg_ptce3_large_exists 2913 * Large entry key ID exists. 2914 * Within the region: 2915 * 0 - SINGLE: The large_entry_key_id is not currently in use. 2916 * For rule insert: The MSB of the key (blocks 6..11) will be added. 2917 * For rule delete: The MSB of the key will be removed. 2918 * 1 - NON_SINGLE: The large_entry_key_id is currently in use. 2919 * For rule insert: The MSB of the key (blocks 6..11) will not be added. 2920 * For rule delete: The MSB of the key will not be removed. 2921 * Access: WO 2922 */ 2923 MLXSW_ITEM32(reg, ptce3, large_exists, 0x98, 31, 1); 2924 2925 /* reg_ptce3_large_entry_key_id 2926 * Large entry key ID. 2927 * A key for 12 key blocks rules. Reserved when region has less than 12 key 2928 * blocks. Must be different for different keys which have the same common 2929 * 6 key blocks (MSB, blocks 6..11) key within a region. 2930 * Range is 0..cap_max_pe_large_key_id - 1 2931 * Access: RW 2932 */ 2933 MLXSW_ITEM32(reg, ptce3, large_entry_key_id, 0x98, 0, 24); 2934 2935 /* reg_ptce3_action_pointer 2936 * Pointer to action. 2937 * Range is 0..cap_max_kvd_action_sets - 1 2938 * Access: RW 2939 */ 2940 MLXSW_ITEM32(reg, ptce3, action_pointer, 0xA0, 0, 24); 2941 2942 static inline void mlxsw_reg_ptce3_pack(char *payload, bool valid, 2943 enum mlxsw_reg_ptce3_op op, 2944 u32 priority, 2945 const char *tcam_region_info, 2946 const char *key, u8 erp_id, 2947 u16 delta_start, u8 delta_mask, 2948 u8 delta_value, bool large_exists, 2949 u32 lkey_id, u32 action_pointer) 2950 { 2951 MLXSW_REG_ZERO(ptce3, payload); 2952 mlxsw_reg_ptce3_v_set(payload, valid); 2953 mlxsw_reg_ptce3_op_set(payload, op); 2954 mlxsw_reg_ptce3_priority_set(payload, priority); 2955 mlxsw_reg_ptce3_tcam_region_info_memcpy_to(payload, tcam_region_info); 2956 mlxsw_reg_ptce3_flex2_key_blocks_memcpy_to(payload, key); 2957 mlxsw_reg_ptce3_erp_id_set(payload, erp_id); 2958 mlxsw_reg_ptce3_delta_start_set(payload, delta_start); 2959 mlxsw_reg_ptce3_delta_mask_set(payload, delta_mask); 2960 mlxsw_reg_ptce3_delta_value_set(payload, delta_value); 2961 mlxsw_reg_ptce3_large_exists_set(payload, large_exists); 2962 mlxsw_reg_ptce3_large_entry_key_id_set(payload, lkey_id); 2963 mlxsw_reg_ptce3_action_pointer_set(payload, action_pointer); 2964 } 2965 2966 /* PERCR - Policy-Engine Region Configuration Register 2967 * --------------------------------------------------- 2968 * This register configures the region parameters. The region_id must be 2969 * allocated. 2970 */ 2971 #define MLXSW_REG_PERCR_ID 0x302A 2972 #define MLXSW_REG_PERCR_LEN 0x80 2973 2974 MLXSW_REG_DEFINE(percr, MLXSW_REG_PERCR_ID, MLXSW_REG_PERCR_LEN); 2975 2976 /* reg_percr_region_id 2977 * Region identifier. 2978 * Range 0..cap_max_regions-1 2979 * Access: Index 2980 */ 2981 MLXSW_ITEM32(reg, percr, region_id, 0x00, 0, 16); 2982 2983 /* reg_percr_atcam_ignore_prune 2984 * Ignore prune_vector by other A-TCAM rules. Used e.g., for a new rule. 2985 * Access: RW 2986 */ 2987 MLXSW_ITEM32(reg, percr, atcam_ignore_prune, 0x04, 25, 1); 2988 2989 /* reg_percr_ctcam_ignore_prune 2990 * Ignore prune_ctcam by other A-TCAM rules. Used e.g., for a new rule. 2991 * Access: RW 2992 */ 2993 MLXSW_ITEM32(reg, percr, ctcam_ignore_prune, 0x04, 24, 1); 2994 2995 /* reg_percr_bf_bypass 2996 * Bloom filter bypass. 2997 * 0 - Bloom filter is used (default) 2998 * 1 - Bloom filter is bypassed. The bypass is an OR condition of 2999 * region_id or eRP. See PERPT.bf_bypass 3000 * Access: RW 3001 */ 3002 MLXSW_ITEM32(reg, percr, bf_bypass, 0x04, 16, 1); 3003 3004 /* reg_percr_master_mask 3005 * Master mask. Logical OR mask of all masks of all rules of a region 3006 * (both A-TCAM and C-TCAM). When there are no eRPs 3007 * (erpt_pointer_valid = 0), then this provides the mask. 3008 * Access: RW 3009 */ 3010 MLXSW_ITEM_BUF(reg, percr, master_mask, 0x20, 96); 3011 3012 static inline void mlxsw_reg_percr_pack(char *payload, u16 region_id) 3013 { 3014 MLXSW_REG_ZERO(percr, payload); 3015 mlxsw_reg_percr_region_id_set(payload, region_id); 3016 mlxsw_reg_percr_atcam_ignore_prune_set(payload, false); 3017 mlxsw_reg_percr_ctcam_ignore_prune_set(payload, false); 3018 mlxsw_reg_percr_bf_bypass_set(payload, false); 3019 } 3020 3021 /* PERERP - Policy-Engine Region eRP Register 3022 * ------------------------------------------ 3023 * This register configures the region eRP. The region_id must be 3024 * allocated. 3025 */ 3026 #define MLXSW_REG_PERERP_ID 0x302B 3027 #define MLXSW_REG_PERERP_LEN 0x1C 3028 3029 MLXSW_REG_DEFINE(pererp, MLXSW_REG_PERERP_ID, MLXSW_REG_PERERP_LEN); 3030 3031 /* reg_pererp_region_id 3032 * Region identifier. 3033 * Range 0..cap_max_regions-1 3034 * Access: Index 3035 */ 3036 MLXSW_ITEM32(reg, pererp, region_id, 0x00, 0, 16); 3037 3038 /* reg_pererp_ctcam_le 3039 * C-TCAM lookup enable. Reserved when erpt_pointer_valid = 0. 3040 * Access: RW 3041 */ 3042 MLXSW_ITEM32(reg, pererp, ctcam_le, 0x04, 28, 1); 3043 3044 /* reg_pererp_erpt_pointer_valid 3045 * erpt_pointer is valid. 3046 * Access: RW 3047 */ 3048 MLXSW_ITEM32(reg, pererp, erpt_pointer_valid, 0x10, 31, 1); 3049 3050 /* reg_pererp_erpt_bank_pointer 3051 * Pointer to eRP table bank. May be modified at any time. 3052 * Range 0..cap_max_erp_table_banks-1 3053 * Reserved when erpt_pointer_valid = 0 3054 */ 3055 MLXSW_ITEM32(reg, pererp, erpt_bank_pointer, 0x10, 16, 4); 3056 3057 /* reg_pererp_erpt_pointer 3058 * Pointer to eRP table within the eRP bank. Can be changed for an 3059 * existing region. 3060 * Range 0..cap_max_erp_table_size-1 3061 * Reserved when erpt_pointer_valid = 0 3062 * Access: RW 3063 */ 3064 MLXSW_ITEM32(reg, pererp, erpt_pointer, 0x10, 0, 8); 3065 3066 /* reg_pererp_erpt_vector 3067 * Vector of allowed eRP indexes starting from erpt_pointer within the 3068 * erpt_bank_pointer. Next entries will be in next bank. 3069 * Note that eRP index is used and not eRP ID. 3070 * Reserved when erpt_pointer_valid = 0 3071 * Access: RW 3072 */ 3073 MLXSW_ITEM_BIT_ARRAY(reg, pererp, erpt_vector, 0x14, 4, 1); 3074 3075 /* reg_pererp_master_rp_id 3076 * Master RP ID. When there are no eRPs, then this provides the eRP ID 3077 * for the lookup. Can be changed for an existing region. 3078 * Reserved when erpt_pointer_valid = 1 3079 * Access: RW 3080 */ 3081 MLXSW_ITEM32(reg, pererp, master_rp_id, 0x18, 0, 4); 3082 3083 static inline void mlxsw_reg_pererp_erp_vector_pack(char *payload, 3084 unsigned long *erp_vector, 3085 unsigned long size) 3086 { 3087 unsigned long bit; 3088 3089 for_each_set_bit(bit, erp_vector, size) 3090 mlxsw_reg_pererp_erpt_vector_set(payload, bit, true); 3091 } 3092 3093 static inline void mlxsw_reg_pererp_pack(char *payload, u16 region_id, 3094 bool ctcam_le, bool erpt_pointer_valid, 3095 u8 erpt_bank_pointer, u8 erpt_pointer, 3096 u8 master_rp_id) 3097 { 3098 MLXSW_REG_ZERO(pererp, payload); 3099 mlxsw_reg_pererp_region_id_set(payload, region_id); 3100 mlxsw_reg_pererp_ctcam_le_set(payload, ctcam_le); 3101 mlxsw_reg_pererp_erpt_pointer_valid_set(payload, erpt_pointer_valid); 3102 mlxsw_reg_pererp_erpt_bank_pointer_set(payload, erpt_bank_pointer); 3103 mlxsw_reg_pererp_erpt_pointer_set(payload, erpt_pointer); 3104 mlxsw_reg_pererp_master_rp_id_set(payload, master_rp_id); 3105 } 3106 3107 /* PEABFE - Policy-Engine Algorithmic Bloom Filter Entries Register 3108 * ---------------------------------------------------------------- 3109 * This register configures the Bloom filter entries. 3110 */ 3111 #define MLXSW_REG_PEABFE_ID 0x3022 3112 #define MLXSW_REG_PEABFE_BASE_LEN 0x10 3113 #define MLXSW_REG_PEABFE_BF_REC_LEN 0x4 3114 #define MLXSW_REG_PEABFE_BF_REC_MAX_COUNT 256 3115 #define MLXSW_REG_PEABFE_LEN (MLXSW_REG_PEABFE_BASE_LEN + \ 3116 MLXSW_REG_PEABFE_BF_REC_LEN * \ 3117 MLXSW_REG_PEABFE_BF_REC_MAX_COUNT) 3118 3119 MLXSW_REG_DEFINE(peabfe, MLXSW_REG_PEABFE_ID, MLXSW_REG_PEABFE_LEN); 3120 3121 /* reg_peabfe_size 3122 * Number of BF entries to be updated. 3123 * Range 1..256 3124 * Access: Op 3125 */ 3126 MLXSW_ITEM32(reg, peabfe, size, 0x00, 0, 9); 3127 3128 /* reg_peabfe_bf_entry_state 3129 * Bloom filter state 3130 * 0 - Clear 3131 * 1 - Set 3132 * Access: RW 3133 */ 3134 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_state, 3135 MLXSW_REG_PEABFE_BASE_LEN, 31, 1, 3136 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3137 3138 /* reg_peabfe_bf_entry_bank 3139 * Bloom filter bank ID 3140 * Range 0..cap_max_erp_table_banks-1 3141 * Access: Index 3142 */ 3143 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_bank, 3144 MLXSW_REG_PEABFE_BASE_LEN, 24, 4, 3145 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3146 3147 /* reg_peabfe_bf_entry_index 3148 * Bloom filter entry index 3149 * Range 0..2^cap_max_bf_log-1 3150 * Access: Index 3151 */ 3152 MLXSW_ITEM32_INDEXED(reg, peabfe, bf_entry_index, 3153 MLXSW_REG_PEABFE_BASE_LEN, 0, 24, 3154 MLXSW_REG_PEABFE_BF_REC_LEN, 0x00, false); 3155 3156 static inline void mlxsw_reg_peabfe_pack(char *payload) 3157 { 3158 MLXSW_REG_ZERO(peabfe, payload); 3159 } 3160 3161 static inline void mlxsw_reg_peabfe_rec_pack(char *payload, int rec_index, 3162 u8 state, u8 bank, u32 bf_index) 3163 { 3164 u8 num_rec = mlxsw_reg_peabfe_size_get(payload); 3165 3166 if (rec_index >= num_rec) 3167 mlxsw_reg_peabfe_size_set(payload, rec_index + 1); 3168 mlxsw_reg_peabfe_bf_entry_state_set(payload, rec_index, state); 3169 mlxsw_reg_peabfe_bf_entry_bank_set(payload, rec_index, bank); 3170 mlxsw_reg_peabfe_bf_entry_index_set(payload, rec_index, bf_index); 3171 } 3172 3173 /* IEDR - Infrastructure Entry Delete Register 3174 * ---------------------------------------------------- 3175 * This register is used for deleting entries from the entry tables. 3176 * It is legitimate to attempt to delete a nonexisting entry (the device will 3177 * respond as a good flow). 3178 */ 3179 #define MLXSW_REG_IEDR_ID 0x3804 3180 #define MLXSW_REG_IEDR_BASE_LEN 0x10 /* base length, without records */ 3181 #define MLXSW_REG_IEDR_REC_LEN 0x8 /* record length */ 3182 #define MLXSW_REG_IEDR_REC_MAX_COUNT 64 3183 #define MLXSW_REG_IEDR_LEN (MLXSW_REG_IEDR_BASE_LEN + \ 3184 MLXSW_REG_IEDR_REC_LEN * \ 3185 MLXSW_REG_IEDR_REC_MAX_COUNT) 3186 3187 MLXSW_REG_DEFINE(iedr, MLXSW_REG_IEDR_ID, MLXSW_REG_IEDR_LEN); 3188 3189 /* reg_iedr_num_rec 3190 * Number of records. 3191 * Access: OP 3192 */ 3193 MLXSW_ITEM32(reg, iedr, num_rec, 0x00, 0, 8); 3194 3195 /* reg_iedr_rec_type 3196 * Resource type. 3197 * Access: OP 3198 */ 3199 MLXSW_ITEM32_INDEXED(reg, iedr, rec_type, MLXSW_REG_IEDR_BASE_LEN, 24, 8, 3200 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3201 3202 /* reg_iedr_rec_size 3203 * Size of entries do be deleted. The unit is 1 entry, regardless of entry type. 3204 * Access: OP 3205 */ 3206 MLXSW_ITEM32_INDEXED(reg, iedr, rec_size, MLXSW_REG_IEDR_BASE_LEN, 0, 13, 3207 MLXSW_REG_IEDR_REC_LEN, 0x00, false); 3208 3209 /* reg_iedr_rec_index_start 3210 * Resource index start. 3211 * Access: OP 3212 */ 3213 MLXSW_ITEM32_INDEXED(reg, iedr, rec_index_start, MLXSW_REG_IEDR_BASE_LEN, 0, 24, 3214 MLXSW_REG_IEDR_REC_LEN, 0x04, false); 3215 3216 static inline void mlxsw_reg_iedr_pack(char *payload) 3217 { 3218 MLXSW_REG_ZERO(iedr, payload); 3219 } 3220 3221 static inline void mlxsw_reg_iedr_rec_pack(char *payload, int rec_index, 3222 u8 rec_type, u16 rec_size, 3223 u32 rec_index_start) 3224 { 3225 u8 num_rec = mlxsw_reg_iedr_num_rec_get(payload); 3226 3227 if (rec_index >= num_rec) 3228 mlxsw_reg_iedr_num_rec_set(payload, rec_index + 1); 3229 mlxsw_reg_iedr_rec_type_set(payload, rec_index, rec_type); 3230 mlxsw_reg_iedr_rec_size_set(payload, rec_index, rec_size); 3231 mlxsw_reg_iedr_rec_index_start_set(payload, rec_index, rec_index_start); 3232 } 3233 3234 /* QPTS - QoS Priority Trust State Register 3235 * ---------------------------------------- 3236 * This register controls the port policy to calculate the switch priority and 3237 * packet color based on incoming packet fields. 3238 */ 3239 #define MLXSW_REG_QPTS_ID 0x4002 3240 #define MLXSW_REG_QPTS_LEN 0x8 3241 3242 MLXSW_REG_DEFINE(qpts, MLXSW_REG_QPTS_ID, MLXSW_REG_QPTS_LEN); 3243 3244 /* reg_qpts_local_port 3245 * Local port number. 3246 * Access: Index 3247 * 3248 * Note: CPU port is supported. 3249 */ 3250 MLXSW_ITEM32(reg, qpts, local_port, 0x00, 16, 8); 3251 3252 enum mlxsw_reg_qpts_trust_state { 3253 MLXSW_REG_QPTS_TRUST_STATE_PCP = 1, 3254 MLXSW_REG_QPTS_TRUST_STATE_DSCP = 2, /* For MPLS, trust EXP. */ 3255 }; 3256 3257 /* reg_qpts_trust_state 3258 * Trust state for a given port. 3259 * Access: RW 3260 */ 3261 MLXSW_ITEM32(reg, qpts, trust_state, 0x04, 0, 3); 3262 3263 static inline void mlxsw_reg_qpts_pack(char *payload, u8 local_port, 3264 enum mlxsw_reg_qpts_trust_state ts) 3265 { 3266 MLXSW_REG_ZERO(qpts, payload); 3267 3268 mlxsw_reg_qpts_local_port_set(payload, local_port); 3269 mlxsw_reg_qpts_trust_state_set(payload, ts); 3270 } 3271 3272 /* QPCR - QoS Policer Configuration Register 3273 * ----------------------------------------- 3274 * The QPCR register is used to create policers - that limit 3275 * the rate of bytes or packets via some trap group. 3276 */ 3277 #define MLXSW_REG_QPCR_ID 0x4004 3278 #define MLXSW_REG_QPCR_LEN 0x28 3279 3280 MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN); 3281 3282 enum mlxsw_reg_qpcr_g { 3283 MLXSW_REG_QPCR_G_GLOBAL = 2, 3284 MLXSW_REG_QPCR_G_STORM_CONTROL = 3, 3285 }; 3286 3287 /* reg_qpcr_g 3288 * The policer type. 3289 * Access: Index 3290 */ 3291 MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2); 3292 3293 /* reg_qpcr_pid 3294 * Policer ID. 3295 * Access: Index 3296 */ 3297 MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14); 3298 3299 /* reg_qpcr_clear_counter 3300 * Clear counters. 3301 * Access: OP 3302 */ 3303 MLXSW_ITEM32(reg, qpcr, clear_counter, 0x04, 31, 1); 3304 3305 /* reg_qpcr_color_aware 3306 * Is the policer aware of colors. 3307 * Must be 0 (unaware) for cpu port. 3308 * Access: RW for unbounded policer. RO for bounded policer. 3309 */ 3310 MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1); 3311 3312 /* reg_qpcr_bytes 3313 * Is policer limit is for bytes per sec or packets per sec. 3314 * 0 - packets 3315 * 1 - bytes 3316 * Access: RW for unbounded policer. RO for bounded policer. 3317 */ 3318 MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1); 3319 3320 enum mlxsw_reg_qpcr_ir_units { 3321 MLXSW_REG_QPCR_IR_UNITS_M, 3322 MLXSW_REG_QPCR_IR_UNITS_K, 3323 }; 3324 3325 /* reg_qpcr_ir_units 3326 * Policer's units for cir and eir fields (for bytes limits only) 3327 * 1 - 10^3 3328 * 0 - 10^6 3329 * Access: OP 3330 */ 3331 MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1); 3332 3333 enum mlxsw_reg_qpcr_rate_type { 3334 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1, 3335 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2, 3336 }; 3337 3338 /* reg_qpcr_rate_type 3339 * Policer can have one limit (single rate) or 2 limits with specific operation 3340 * for packets that exceed the lower rate but not the upper one. 3341 * (For cpu port must be single rate) 3342 * Access: RW for unbounded policer. RO for bounded policer. 3343 */ 3344 MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2); 3345 3346 /* reg_qpc_cbs 3347 * Policer's committed burst size. 3348 * The policer is working with time slices of 50 nano sec. By default every 3349 * slice is granted the proportionate share of the committed rate. If we want to 3350 * allow a slice to exceed that share (while still keeping the rate per sec) we 3351 * can allow burst. The burst size is between the default proportionate share 3352 * (and no lower than 8) to 32Gb. (Even though giving a number higher than the 3353 * committed rate will result in exceeding the rate). The burst size must be a 3354 * log of 2 and will be determined by 2^cbs. 3355 * Access: RW 3356 */ 3357 MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6); 3358 3359 /* reg_qpcr_cir 3360 * Policer's committed rate. 3361 * The rate used for sungle rate, the lower rate for double rate. 3362 * For bytes limits, the rate will be this value * the unit from ir_units. 3363 * (Resolution error is up to 1%). 3364 * Access: RW 3365 */ 3366 MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32); 3367 3368 /* reg_qpcr_eir 3369 * Policer's exceed rate. 3370 * The higher rate for double rate, reserved for single rate. 3371 * Lower rate for double rate policer. 3372 * For bytes limits, the rate will be this value * the unit from ir_units. 3373 * (Resolution error is up to 1%). 3374 * Access: RW 3375 */ 3376 MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32); 3377 3378 #define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2 3379 3380 /* reg_qpcr_exceed_action. 3381 * What to do with packets between the 2 limits for double rate. 3382 * Access: RW for unbounded policer. RO for bounded policer. 3383 */ 3384 MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4); 3385 3386 enum mlxsw_reg_qpcr_action { 3387 /* Discard */ 3388 MLXSW_REG_QPCR_ACTION_DISCARD = 1, 3389 /* Forward and set color to red. 3390 * If the packet is intended to cpu port, it will be dropped. 3391 */ 3392 MLXSW_REG_QPCR_ACTION_FORWARD = 2, 3393 }; 3394 3395 /* reg_qpcr_violate_action 3396 * What to do with packets that cross the cir limit (for single rate) or the eir 3397 * limit (for double rate). 3398 * Access: RW for unbounded policer. RO for bounded policer. 3399 */ 3400 MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4); 3401 3402 /* reg_qpcr_violate_count 3403 * Counts the number of times violate_action happened on this PID. 3404 * Access: RW 3405 */ 3406 MLXSW_ITEM64(reg, qpcr, violate_count, 0x20, 0, 64); 3407 3408 #define MLXSW_REG_QPCR_LOWEST_CIR 1 3409 #define MLXSW_REG_QPCR_HIGHEST_CIR (2 * 1000 * 1000 * 1000) /* 2Gpps */ 3410 #define MLXSW_REG_QPCR_LOWEST_CBS 4 3411 #define MLXSW_REG_QPCR_HIGHEST_CBS 24 3412 3413 static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid, 3414 enum mlxsw_reg_qpcr_ir_units ir_units, 3415 bool bytes, u32 cir, u16 cbs) 3416 { 3417 MLXSW_REG_ZERO(qpcr, payload); 3418 mlxsw_reg_qpcr_pid_set(payload, pid); 3419 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL); 3420 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE); 3421 mlxsw_reg_qpcr_violate_action_set(payload, 3422 MLXSW_REG_QPCR_ACTION_DISCARD); 3423 mlxsw_reg_qpcr_cir_set(payload, cir); 3424 mlxsw_reg_qpcr_ir_units_set(payload, ir_units); 3425 mlxsw_reg_qpcr_bytes_set(payload, bytes); 3426 mlxsw_reg_qpcr_cbs_set(payload, cbs); 3427 } 3428 3429 /* QTCT - QoS Switch Traffic Class Table 3430 * ------------------------------------- 3431 * Configures the mapping between the packet switch priority and the 3432 * traffic class on the transmit port. 3433 */ 3434 #define MLXSW_REG_QTCT_ID 0x400A 3435 #define MLXSW_REG_QTCT_LEN 0x08 3436 3437 MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN); 3438 3439 /* reg_qtct_local_port 3440 * Local port number. 3441 * Access: Index 3442 * 3443 * Note: CPU port is not supported. 3444 */ 3445 MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8); 3446 3447 /* reg_qtct_sub_port 3448 * Virtual port within the physical port. 3449 * Should be set to 0 when virtual ports are not enabled on the port. 3450 * Access: Index 3451 */ 3452 MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8); 3453 3454 /* reg_qtct_switch_prio 3455 * Switch priority. 3456 * Access: Index 3457 */ 3458 MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4); 3459 3460 /* reg_qtct_tclass 3461 * Traffic class. 3462 * Default values: 3463 * switch_prio 0 : tclass 1 3464 * switch_prio 1 : tclass 0 3465 * switch_prio i : tclass i, for i > 1 3466 * Access: RW 3467 */ 3468 MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4); 3469 3470 static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port, 3471 u8 switch_prio, u8 tclass) 3472 { 3473 MLXSW_REG_ZERO(qtct, payload); 3474 mlxsw_reg_qtct_local_port_set(payload, local_port); 3475 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio); 3476 mlxsw_reg_qtct_tclass_set(payload, tclass); 3477 } 3478 3479 /* QEEC - QoS ETS Element Configuration Register 3480 * --------------------------------------------- 3481 * Configures the ETS elements. 3482 */ 3483 #define MLXSW_REG_QEEC_ID 0x400D 3484 #define MLXSW_REG_QEEC_LEN 0x20 3485 3486 MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN); 3487 3488 /* reg_qeec_local_port 3489 * Local port number. 3490 * Access: Index 3491 * 3492 * Note: CPU port is supported. 3493 */ 3494 MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8); 3495 3496 enum mlxsw_reg_qeec_hr { 3497 MLXSW_REG_QEEC_HR_PORT, 3498 MLXSW_REG_QEEC_HR_GROUP, 3499 MLXSW_REG_QEEC_HR_SUBGROUP, 3500 MLXSW_REG_QEEC_HR_TC, 3501 }; 3502 3503 /* reg_qeec_element_hierarchy 3504 * 0 - Port 3505 * 1 - Group 3506 * 2 - Subgroup 3507 * 3 - Traffic Class 3508 * Access: Index 3509 */ 3510 MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4); 3511 3512 /* reg_qeec_element_index 3513 * The index of the element in the hierarchy. 3514 * Access: Index 3515 */ 3516 MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8); 3517 3518 /* reg_qeec_next_element_index 3519 * The index of the next (lower) element in the hierarchy. 3520 * Access: RW 3521 * 3522 * Note: Reserved for element_hierarchy 0. 3523 */ 3524 MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8); 3525 3526 /* reg_qeec_mise 3527 * Min shaper configuration enable. Enables configuration of the min 3528 * shaper on this ETS element 3529 * 0 - Disable 3530 * 1 - Enable 3531 * Access: RW 3532 */ 3533 MLXSW_ITEM32(reg, qeec, mise, 0x0C, 31, 1); 3534 3535 /* reg_qeec_ptps 3536 * PTP shaper 3537 * 0: regular shaper mode 3538 * 1: PTP oriented shaper 3539 * Allowed only for hierarchy 0 3540 * Not supported for CPU port 3541 * Note that ptps mode may affect the shaper rates of all hierarchies 3542 * Supported only on Spectrum-1 3543 * Access: RW 3544 */ 3545 MLXSW_ITEM32(reg, qeec, ptps, 0x0C, 29, 1); 3546 3547 enum { 3548 MLXSW_REG_QEEC_BYTES_MODE, 3549 MLXSW_REG_QEEC_PACKETS_MODE, 3550 }; 3551 3552 /* reg_qeec_pb 3553 * Packets or bytes mode. 3554 * 0 - Bytes mode 3555 * 1 - Packets mode 3556 * Access: RW 3557 * 3558 * Note: Used for max shaper configuration. For Spectrum, packets mode 3559 * is supported only for traffic classes of CPU port. 3560 */ 3561 MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1); 3562 3563 /* The smallest permitted min shaper rate. */ 3564 #define MLXSW_REG_QEEC_MIS_MIN 200000 /* Kbps */ 3565 3566 /* reg_qeec_min_shaper_rate 3567 * Min shaper information rate. 3568 * For CPU port, can only be configured for port hierarchy. 3569 * When in bytes mode, value is specified in units of 1000bps. 3570 * Access: RW 3571 */ 3572 MLXSW_ITEM32(reg, qeec, min_shaper_rate, 0x0C, 0, 28); 3573 3574 /* reg_qeec_mase 3575 * Max shaper configuration enable. Enables configuration of the max 3576 * shaper on this ETS element. 3577 * 0 - Disable 3578 * 1 - Enable 3579 * Access: RW 3580 */ 3581 MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1); 3582 3583 /* The largest max shaper value possible to disable the shaper. */ 3584 #define MLXSW_REG_QEEC_MAS_DIS ((1u << 31) - 1) /* Kbps */ 3585 3586 /* reg_qeec_max_shaper_rate 3587 * Max shaper information rate. 3588 * For CPU port, can only be configured for port hierarchy. 3589 * When in bytes mode, value is specified in units of 1000bps. 3590 * Access: RW 3591 */ 3592 MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 31); 3593 3594 /* reg_qeec_de 3595 * DWRR configuration enable. Enables configuration of the dwrr and 3596 * dwrr_weight. 3597 * 0 - Disable 3598 * 1 - Enable 3599 * Access: RW 3600 */ 3601 MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1); 3602 3603 /* reg_qeec_dwrr 3604 * Transmission selection algorithm to use on the link going down from 3605 * the ETS element. 3606 * 0 - Strict priority 3607 * 1 - DWRR 3608 * Access: RW 3609 */ 3610 MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1); 3611 3612 /* reg_qeec_dwrr_weight 3613 * DWRR weight on the link going down from the ETS element. The 3614 * percentage of bandwidth guaranteed to an ETS element within 3615 * its hierarchy. The sum of all weights across all ETS elements 3616 * within one hierarchy should be equal to 100. Reserved when 3617 * transmission selection algorithm is strict priority. 3618 * Access: RW 3619 */ 3620 MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8); 3621 3622 /* reg_qeec_max_shaper_bs 3623 * Max shaper burst size 3624 * Burst size is 2^max_shaper_bs * 512 bits 3625 * For Spectrum-1: Range is: 5..25 3626 * For Spectrum-2: Range is: 11..25 3627 * Reserved when ptps = 1 3628 * Access: RW 3629 */ 3630 MLXSW_ITEM32(reg, qeec, max_shaper_bs, 0x1C, 0, 6); 3631 3632 #define MLXSW_REG_QEEC_HIGHEST_SHAPER_BS 25 3633 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP1 5 3634 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP2 11 3635 #define MLXSW_REG_QEEC_LOWEST_SHAPER_BS_SP3 5 3636 3637 static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port, 3638 enum mlxsw_reg_qeec_hr hr, u8 index, 3639 u8 next_index) 3640 { 3641 MLXSW_REG_ZERO(qeec, payload); 3642 mlxsw_reg_qeec_local_port_set(payload, local_port); 3643 mlxsw_reg_qeec_element_hierarchy_set(payload, hr); 3644 mlxsw_reg_qeec_element_index_set(payload, index); 3645 mlxsw_reg_qeec_next_element_index_set(payload, next_index); 3646 } 3647 3648 static inline void mlxsw_reg_qeec_ptps_pack(char *payload, u8 local_port, 3649 bool ptps) 3650 { 3651 MLXSW_REG_ZERO(qeec, payload); 3652 mlxsw_reg_qeec_local_port_set(payload, local_port); 3653 mlxsw_reg_qeec_element_hierarchy_set(payload, MLXSW_REG_QEEC_HR_PORT); 3654 mlxsw_reg_qeec_ptps_set(payload, ptps); 3655 } 3656 3657 /* QRWE - QoS ReWrite Enable 3658 * ------------------------- 3659 * This register configures the rewrite enable per receive port. 3660 */ 3661 #define MLXSW_REG_QRWE_ID 0x400F 3662 #define MLXSW_REG_QRWE_LEN 0x08 3663 3664 MLXSW_REG_DEFINE(qrwe, MLXSW_REG_QRWE_ID, MLXSW_REG_QRWE_LEN); 3665 3666 /* reg_qrwe_local_port 3667 * Local port number. 3668 * Access: Index 3669 * 3670 * Note: CPU port is supported. No support for router port. 3671 */ 3672 MLXSW_ITEM32(reg, qrwe, local_port, 0x00, 16, 8); 3673 3674 /* reg_qrwe_dscp 3675 * Whether to enable DSCP rewrite (default is 0, don't rewrite). 3676 * Access: RW 3677 */ 3678 MLXSW_ITEM32(reg, qrwe, dscp, 0x04, 1, 1); 3679 3680 /* reg_qrwe_pcp 3681 * Whether to enable PCP and DEI rewrite (default is 0, don't rewrite). 3682 * Access: RW 3683 */ 3684 MLXSW_ITEM32(reg, qrwe, pcp, 0x04, 0, 1); 3685 3686 static inline void mlxsw_reg_qrwe_pack(char *payload, u8 local_port, 3687 bool rewrite_pcp, bool rewrite_dscp) 3688 { 3689 MLXSW_REG_ZERO(qrwe, payload); 3690 mlxsw_reg_qrwe_local_port_set(payload, local_port); 3691 mlxsw_reg_qrwe_pcp_set(payload, rewrite_pcp); 3692 mlxsw_reg_qrwe_dscp_set(payload, rewrite_dscp); 3693 } 3694 3695 /* QPDSM - QoS Priority to DSCP Mapping 3696 * ------------------------------------ 3697 * QoS Priority to DSCP Mapping Register 3698 */ 3699 #define MLXSW_REG_QPDSM_ID 0x4011 3700 #define MLXSW_REG_QPDSM_BASE_LEN 0x04 /* base length, without records */ 3701 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN 0x4 /* record length */ 3702 #define MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT 16 3703 #define MLXSW_REG_QPDSM_LEN (MLXSW_REG_QPDSM_BASE_LEN + \ 3704 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN * \ 3705 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_MAX_COUNT) 3706 3707 MLXSW_REG_DEFINE(qpdsm, MLXSW_REG_QPDSM_ID, MLXSW_REG_QPDSM_LEN); 3708 3709 /* reg_qpdsm_local_port 3710 * Local Port. Supported for data packets from CPU port. 3711 * Access: Index 3712 */ 3713 MLXSW_ITEM32(reg, qpdsm, local_port, 0x00, 16, 8); 3714 3715 /* reg_qpdsm_prio_entry_color0_e 3716 * Enable update of the entry for color 0 and a given port. 3717 * Access: WO 3718 */ 3719 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_e, 3720 MLXSW_REG_QPDSM_BASE_LEN, 31, 1, 3721 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3722 3723 /* reg_qpdsm_prio_entry_color0_dscp 3724 * DSCP field in the outer label of the packet for color 0 and a given port. 3725 * Reserved when e=0. 3726 * Access: RW 3727 */ 3728 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color0_dscp, 3729 MLXSW_REG_QPDSM_BASE_LEN, 24, 6, 3730 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3731 3732 /* reg_qpdsm_prio_entry_color1_e 3733 * Enable update of the entry for color 1 and a given port. 3734 * Access: WO 3735 */ 3736 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_e, 3737 MLXSW_REG_QPDSM_BASE_LEN, 23, 1, 3738 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3739 3740 /* reg_qpdsm_prio_entry_color1_dscp 3741 * DSCP field in the outer label of the packet for color 1 and a given port. 3742 * Reserved when e=0. 3743 * Access: RW 3744 */ 3745 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color1_dscp, 3746 MLXSW_REG_QPDSM_BASE_LEN, 16, 6, 3747 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3748 3749 /* reg_qpdsm_prio_entry_color2_e 3750 * Enable update of the entry for color 2 and a given port. 3751 * Access: WO 3752 */ 3753 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_e, 3754 MLXSW_REG_QPDSM_BASE_LEN, 15, 1, 3755 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3756 3757 /* reg_qpdsm_prio_entry_color2_dscp 3758 * DSCP field in the outer label of the packet for color 2 and a given port. 3759 * Reserved when e=0. 3760 * Access: RW 3761 */ 3762 MLXSW_ITEM32_INDEXED(reg, qpdsm, prio_entry_color2_dscp, 3763 MLXSW_REG_QPDSM_BASE_LEN, 8, 6, 3764 MLXSW_REG_QPDSM_PRIO_ENTRY_REC_LEN, 0x00, false); 3765 3766 static inline void mlxsw_reg_qpdsm_pack(char *payload, u8 local_port) 3767 { 3768 MLXSW_REG_ZERO(qpdsm, payload); 3769 mlxsw_reg_qpdsm_local_port_set(payload, local_port); 3770 } 3771 3772 static inline void 3773 mlxsw_reg_qpdsm_prio_pack(char *payload, unsigned short prio, u8 dscp) 3774 { 3775 mlxsw_reg_qpdsm_prio_entry_color0_e_set(payload, prio, 1); 3776 mlxsw_reg_qpdsm_prio_entry_color0_dscp_set(payload, prio, dscp); 3777 mlxsw_reg_qpdsm_prio_entry_color1_e_set(payload, prio, 1); 3778 mlxsw_reg_qpdsm_prio_entry_color1_dscp_set(payload, prio, dscp); 3779 mlxsw_reg_qpdsm_prio_entry_color2_e_set(payload, prio, 1); 3780 mlxsw_reg_qpdsm_prio_entry_color2_dscp_set(payload, prio, dscp); 3781 } 3782 3783 /* QPDP - QoS Port DSCP to Priority Mapping Register 3784 * ------------------------------------------------- 3785 * This register controls the port default Switch Priority and Color. The 3786 * default Switch Priority and Color are used for frames where the trust state 3787 * uses default values. All member ports of a LAG should be configured with the 3788 * same default values. 3789 */ 3790 #define MLXSW_REG_QPDP_ID 0x4007 3791 #define MLXSW_REG_QPDP_LEN 0x8 3792 3793 MLXSW_REG_DEFINE(qpdp, MLXSW_REG_QPDP_ID, MLXSW_REG_QPDP_LEN); 3794 3795 /* reg_qpdp_local_port 3796 * Local Port. Supported for data packets from CPU port. 3797 * Access: Index 3798 */ 3799 MLXSW_ITEM32(reg, qpdp, local_port, 0x00, 16, 8); 3800 3801 /* reg_qpdp_switch_prio 3802 * Default port Switch Priority (default 0) 3803 * Access: RW 3804 */ 3805 MLXSW_ITEM32(reg, qpdp, switch_prio, 0x04, 0, 4); 3806 3807 static inline void mlxsw_reg_qpdp_pack(char *payload, u8 local_port, 3808 u8 switch_prio) 3809 { 3810 MLXSW_REG_ZERO(qpdp, payload); 3811 mlxsw_reg_qpdp_local_port_set(payload, local_port); 3812 mlxsw_reg_qpdp_switch_prio_set(payload, switch_prio); 3813 } 3814 3815 /* QPDPM - QoS Port DSCP to Priority Mapping Register 3816 * -------------------------------------------------- 3817 * This register controls the mapping from DSCP field to 3818 * Switch Priority for IP packets. 3819 */ 3820 #define MLXSW_REG_QPDPM_ID 0x4013 3821 #define MLXSW_REG_QPDPM_BASE_LEN 0x4 /* base length, without records */ 3822 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN 0x2 /* record length */ 3823 #define MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT 64 3824 #define MLXSW_REG_QPDPM_LEN (MLXSW_REG_QPDPM_BASE_LEN + \ 3825 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN * \ 3826 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_MAX_COUNT) 3827 3828 MLXSW_REG_DEFINE(qpdpm, MLXSW_REG_QPDPM_ID, MLXSW_REG_QPDPM_LEN); 3829 3830 /* reg_qpdpm_local_port 3831 * Local Port. Supported for data packets from CPU port. 3832 * Access: Index 3833 */ 3834 MLXSW_ITEM32(reg, qpdpm, local_port, 0x00, 16, 8); 3835 3836 /* reg_qpdpm_dscp_e 3837 * Enable update of the specific entry. When cleared, the switch_prio and color 3838 * fields are ignored and the previous switch_prio and color values are 3839 * preserved. 3840 * Access: WO 3841 */ 3842 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_e, MLXSW_REG_QPDPM_BASE_LEN, 15, 1, 3843 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3844 3845 /* reg_qpdpm_dscp_prio 3846 * The new Switch Priority value for the relevant DSCP value. 3847 * Access: RW 3848 */ 3849 MLXSW_ITEM16_INDEXED(reg, qpdpm, dscp_entry_prio, 3850 MLXSW_REG_QPDPM_BASE_LEN, 0, 4, 3851 MLXSW_REG_QPDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 3852 3853 static inline void mlxsw_reg_qpdpm_pack(char *payload, u8 local_port) 3854 { 3855 MLXSW_REG_ZERO(qpdpm, payload); 3856 mlxsw_reg_qpdpm_local_port_set(payload, local_port); 3857 } 3858 3859 static inline void 3860 mlxsw_reg_qpdpm_dscp_pack(char *payload, unsigned short dscp, u8 prio) 3861 { 3862 mlxsw_reg_qpdpm_dscp_entry_e_set(payload, dscp, 1); 3863 mlxsw_reg_qpdpm_dscp_entry_prio_set(payload, dscp, prio); 3864 } 3865 3866 /* QTCTM - QoS Switch Traffic Class Table is Multicast-Aware Register 3867 * ------------------------------------------------------------------ 3868 * This register configures if the Switch Priority to Traffic Class mapping is 3869 * based on Multicast packet indication. If so, then multicast packets will get 3870 * a Traffic Class that is plus (cap_max_tclass_data/2) the value configured by 3871 * QTCT. 3872 * By default, Switch Priority to Traffic Class mapping is not based on 3873 * Multicast packet indication. 3874 */ 3875 #define MLXSW_REG_QTCTM_ID 0x401A 3876 #define MLXSW_REG_QTCTM_LEN 0x08 3877 3878 MLXSW_REG_DEFINE(qtctm, MLXSW_REG_QTCTM_ID, MLXSW_REG_QTCTM_LEN); 3879 3880 /* reg_qtctm_local_port 3881 * Local port number. 3882 * No support for CPU port. 3883 * Access: Index 3884 */ 3885 MLXSW_ITEM32(reg, qtctm, local_port, 0x00, 16, 8); 3886 3887 /* reg_qtctm_mc 3888 * Multicast Mode 3889 * Whether Switch Priority to Traffic Class mapping is based on Multicast packet 3890 * indication (default is 0, not based on Multicast packet indication). 3891 */ 3892 MLXSW_ITEM32(reg, qtctm, mc, 0x04, 0, 1); 3893 3894 static inline void 3895 mlxsw_reg_qtctm_pack(char *payload, u8 local_port, bool mc) 3896 { 3897 MLXSW_REG_ZERO(qtctm, payload); 3898 mlxsw_reg_qtctm_local_port_set(payload, local_port); 3899 mlxsw_reg_qtctm_mc_set(payload, mc); 3900 } 3901 3902 /* QPSC - QoS PTP Shaper Configuration Register 3903 * -------------------------------------------- 3904 * The QPSC allows advanced configuration of the shapers when QEEC.ptps=1. 3905 * Supported only on Spectrum-1. 3906 */ 3907 #define MLXSW_REG_QPSC_ID 0x401B 3908 #define MLXSW_REG_QPSC_LEN 0x28 3909 3910 MLXSW_REG_DEFINE(qpsc, MLXSW_REG_QPSC_ID, MLXSW_REG_QPSC_LEN); 3911 3912 enum mlxsw_reg_qpsc_port_speed { 3913 MLXSW_REG_QPSC_PORT_SPEED_100M, 3914 MLXSW_REG_QPSC_PORT_SPEED_1G, 3915 MLXSW_REG_QPSC_PORT_SPEED_10G, 3916 MLXSW_REG_QPSC_PORT_SPEED_25G, 3917 }; 3918 3919 /* reg_qpsc_port_speed 3920 * Port speed. 3921 * Access: Index 3922 */ 3923 MLXSW_ITEM32(reg, qpsc, port_speed, 0x00, 0, 4); 3924 3925 /* reg_qpsc_shaper_time_exp 3926 * The base-time-interval for updating the shapers tokens (for all hierarchies). 3927 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 3928 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 3929 * Access: RW 3930 */ 3931 MLXSW_ITEM32(reg, qpsc, shaper_time_exp, 0x04, 16, 4); 3932 3933 /* reg_qpsc_shaper_time_mantissa 3934 * The base-time-interval for updating the shapers tokens (for all hierarchies). 3935 * shaper_update_rate = 2 ^ shaper_time_exp * (1 + shaper_time_mantissa) * 32nSec 3936 * shaper_rate = 64bit * shaper_inc / shaper_update_rate 3937 * Access: RW 3938 */ 3939 MLXSW_ITEM32(reg, qpsc, shaper_time_mantissa, 0x04, 0, 5); 3940 3941 /* reg_qpsc_shaper_inc 3942 * Number of tokens added to shaper on each update. 3943 * Units of 8B. 3944 * Access: RW 3945 */ 3946 MLXSW_ITEM32(reg, qpsc, shaper_inc, 0x08, 0, 5); 3947 3948 /* reg_qpsc_shaper_bs 3949 * Max shaper Burst size. 3950 * Burst size is 2 ^ max_shaper_bs * 512 [bits] 3951 * Range is: 5..25 (from 2KB..2GB) 3952 * Access: RW 3953 */ 3954 MLXSW_ITEM32(reg, qpsc, shaper_bs, 0x0C, 0, 6); 3955 3956 /* reg_qpsc_ptsc_we 3957 * Write enable to port_to_shaper_credits. 3958 * Access: WO 3959 */ 3960 MLXSW_ITEM32(reg, qpsc, ptsc_we, 0x10, 31, 1); 3961 3962 /* reg_qpsc_port_to_shaper_credits 3963 * For split ports: range 1..57 3964 * For non-split ports: range 1..112 3965 * Written only when ptsc_we is set. 3966 * Access: RW 3967 */ 3968 MLXSW_ITEM32(reg, qpsc, port_to_shaper_credits, 0x10, 0, 8); 3969 3970 /* reg_qpsc_ing_timestamp_inc 3971 * Ingress timestamp increment. 3972 * 2's complement. 3973 * The timestamp of MTPPTR at ingress will be incremented by this value. Global 3974 * value for all ports. 3975 * Same units as used by MTPPTR. 3976 * Access: RW 3977 */ 3978 MLXSW_ITEM32(reg, qpsc, ing_timestamp_inc, 0x20, 0, 32); 3979 3980 /* reg_qpsc_egr_timestamp_inc 3981 * Egress timestamp increment. 3982 * 2's complement. 3983 * The timestamp of MTPPTR at egress will be incremented by this value. Global 3984 * value for all ports. 3985 * Same units as used by MTPPTR. 3986 * Access: RW 3987 */ 3988 MLXSW_ITEM32(reg, qpsc, egr_timestamp_inc, 0x24, 0, 32); 3989 3990 static inline void 3991 mlxsw_reg_qpsc_pack(char *payload, enum mlxsw_reg_qpsc_port_speed port_speed, 3992 u8 shaper_time_exp, u8 shaper_time_mantissa, u8 shaper_inc, 3993 u8 shaper_bs, u8 port_to_shaper_credits, 3994 int ing_timestamp_inc, int egr_timestamp_inc) 3995 { 3996 MLXSW_REG_ZERO(qpsc, payload); 3997 mlxsw_reg_qpsc_port_speed_set(payload, port_speed); 3998 mlxsw_reg_qpsc_shaper_time_exp_set(payload, shaper_time_exp); 3999 mlxsw_reg_qpsc_shaper_time_mantissa_set(payload, shaper_time_mantissa); 4000 mlxsw_reg_qpsc_shaper_inc_set(payload, shaper_inc); 4001 mlxsw_reg_qpsc_shaper_bs_set(payload, shaper_bs); 4002 mlxsw_reg_qpsc_ptsc_we_set(payload, true); 4003 mlxsw_reg_qpsc_port_to_shaper_credits_set(payload, port_to_shaper_credits); 4004 mlxsw_reg_qpsc_ing_timestamp_inc_set(payload, ing_timestamp_inc); 4005 mlxsw_reg_qpsc_egr_timestamp_inc_set(payload, egr_timestamp_inc); 4006 } 4007 4008 /* PMLP - Ports Module to Local Port Register 4009 * ------------------------------------------ 4010 * Configures the assignment of modules to local ports. 4011 */ 4012 #define MLXSW_REG_PMLP_ID 0x5002 4013 #define MLXSW_REG_PMLP_LEN 0x40 4014 4015 MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN); 4016 4017 /* reg_pmlp_rxtx 4018 * 0 - Tx value is used for both Tx and Rx. 4019 * 1 - Rx value is taken from a separte field. 4020 * Access: RW 4021 */ 4022 MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1); 4023 4024 /* reg_pmlp_local_port 4025 * Local port number. 4026 * Access: Index 4027 */ 4028 MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8); 4029 4030 /* reg_pmlp_width 4031 * 0 - Unmap local port. 4032 * 1 - Lane 0 is used. 4033 * 2 - Lanes 0 and 1 are used. 4034 * 4 - Lanes 0, 1, 2 and 3 are used. 4035 * 8 - Lanes 0-7 are used. 4036 * Access: RW 4037 */ 4038 MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8); 4039 4040 /* reg_pmlp_module 4041 * Module number. 4042 * Access: RW 4043 */ 4044 MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false); 4045 4046 /* reg_pmlp_tx_lane 4047 * Tx Lane. When rxtx field is cleared, this field is used for Rx as well. 4048 * Access: RW 4049 */ 4050 MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 4, 0x04, 0x00, false); 4051 4052 /* reg_pmlp_rx_lane 4053 * Rx Lane. When rxtx field is cleared, this field is ignored and Rx lane is 4054 * equal to Tx lane. 4055 * Access: RW 4056 */ 4057 MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 4, 0x04, 0x00, false); 4058 4059 static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port) 4060 { 4061 MLXSW_REG_ZERO(pmlp, payload); 4062 mlxsw_reg_pmlp_local_port_set(payload, local_port); 4063 } 4064 4065 /* PMTU - Port MTU Register 4066 * ------------------------ 4067 * Configures and reports the port MTU. 4068 */ 4069 #define MLXSW_REG_PMTU_ID 0x5003 4070 #define MLXSW_REG_PMTU_LEN 0x10 4071 4072 MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN); 4073 4074 /* reg_pmtu_local_port 4075 * Local port number. 4076 * Access: Index 4077 */ 4078 MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8); 4079 4080 /* reg_pmtu_max_mtu 4081 * Maximum MTU. 4082 * When port type (e.g. Ethernet) is configured, the relevant MTU is 4083 * reported, otherwise the minimum between the max_mtu of the different 4084 * types is reported. 4085 * Access: RO 4086 */ 4087 MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16); 4088 4089 /* reg_pmtu_admin_mtu 4090 * MTU value to set port to. Must be smaller or equal to max_mtu. 4091 * Note: If port type is Infiniband, then port must be disabled, when its 4092 * MTU is set. 4093 * Access: RW 4094 */ 4095 MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16); 4096 4097 /* reg_pmtu_oper_mtu 4098 * The actual MTU configured on the port. Packets exceeding this size 4099 * will be dropped. 4100 * Note: In Ethernet and FC oper_mtu == admin_mtu, however, in Infiniband 4101 * oper_mtu might be smaller than admin_mtu. 4102 * Access: RO 4103 */ 4104 MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16); 4105 4106 static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port, 4107 u16 new_mtu) 4108 { 4109 MLXSW_REG_ZERO(pmtu, payload); 4110 mlxsw_reg_pmtu_local_port_set(payload, local_port); 4111 mlxsw_reg_pmtu_max_mtu_set(payload, 0); 4112 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu); 4113 mlxsw_reg_pmtu_oper_mtu_set(payload, 0); 4114 } 4115 4116 /* PTYS - Port Type and Speed Register 4117 * ----------------------------------- 4118 * Configures and reports the port speed type. 4119 * 4120 * Note: When set while the link is up, the changes will not take effect 4121 * until the port transitions from down to up state. 4122 */ 4123 #define MLXSW_REG_PTYS_ID 0x5004 4124 #define MLXSW_REG_PTYS_LEN 0x40 4125 4126 MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN); 4127 4128 /* an_disable_admin 4129 * Auto negotiation disable administrative configuration 4130 * 0 - Device doesn't support AN disable. 4131 * 1 - Device supports AN disable. 4132 * Access: RW 4133 */ 4134 MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1); 4135 4136 /* reg_ptys_local_port 4137 * Local port number. 4138 * Access: Index 4139 */ 4140 MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8); 4141 4142 #define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0) 4143 #define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2) 4144 4145 /* reg_ptys_proto_mask 4146 * Protocol mask. Indicates which protocol is used. 4147 * 0 - Infiniband. 4148 * 1 - Fibre Channel. 4149 * 2 - Ethernet. 4150 * Access: Index 4151 */ 4152 MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3); 4153 4154 enum { 4155 MLXSW_REG_PTYS_AN_STATUS_NA, 4156 MLXSW_REG_PTYS_AN_STATUS_OK, 4157 MLXSW_REG_PTYS_AN_STATUS_FAIL, 4158 }; 4159 4160 /* reg_ptys_an_status 4161 * Autonegotiation status. 4162 * Access: RO 4163 */ 4164 MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4); 4165 4166 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_SGMII_100M BIT(0) 4167 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_1000BASE_X_SGMII BIT(1) 4168 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_2_5GBASE_X_2_5GMII BIT(2) 4169 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_5GBASE_R BIT(3) 4170 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XFI_XAUI_1_10G BIT(4) 4171 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_XLAUI_4_XLPPI_4_40G BIT(5) 4172 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_25GAUI_1_25GBASE_CR_KR BIT(6) 4173 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 BIT(7) 4174 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_50GAUI_1_LAUI_1_50GBASE_CR_KR BIT(8) 4175 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_CAUI_4_100GBASE_CR4_KR4 BIT(9) 4176 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10) 4177 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12) 4178 #define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15) 4179 4180 /* reg_ptys_ext_eth_proto_cap 4181 * Extended Ethernet port supported speeds and protocols. 4182 * Access: RO 4183 */ 4184 MLXSW_ITEM32(reg, ptys, ext_eth_proto_cap, 0x08, 0, 32); 4185 4186 #define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0) 4187 #define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1) 4188 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2) 4189 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3) 4190 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4) 4191 #define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5) 4192 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6) 4193 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7) 4194 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12) 4195 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13) 4196 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14) 4197 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15) 4198 #define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16) 4199 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18) 4200 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19) 4201 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20) 4202 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21) 4203 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22) 4204 #define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23) 4205 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24) 4206 #define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25) 4207 #define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26) 4208 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27) 4209 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28) 4210 #define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29) 4211 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30) 4212 #define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31) 4213 4214 /* reg_ptys_eth_proto_cap 4215 * Ethernet port supported speeds and protocols. 4216 * Access: RO 4217 */ 4218 MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32); 4219 4220 /* reg_ptys_ib_link_width_cap 4221 * IB port supported widths. 4222 * Access: RO 4223 */ 4224 MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16); 4225 4226 #define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0) 4227 #define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1) 4228 #define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2) 4229 #define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3) 4230 #define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4) 4231 #define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5) 4232 4233 /* reg_ptys_ib_proto_cap 4234 * IB port supported speeds and protocols. 4235 * Access: RO 4236 */ 4237 MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16); 4238 4239 /* reg_ptys_ext_eth_proto_admin 4240 * Extended speed and protocol to set port to. 4241 * Access: RW 4242 */ 4243 MLXSW_ITEM32(reg, ptys, ext_eth_proto_admin, 0x14, 0, 32); 4244 4245 /* reg_ptys_eth_proto_admin 4246 * Speed and protocol to set port to. 4247 * Access: RW 4248 */ 4249 MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32); 4250 4251 /* reg_ptys_ib_link_width_admin 4252 * IB width to set port to. 4253 * Access: RW 4254 */ 4255 MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16); 4256 4257 /* reg_ptys_ib_proto_admin 4258 * IB speeds and protocols to set port to. 4259 * Access: RW 4260 */ 4261 MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16); 4262 4263 /* reg_ptys_ext_eth_proto_oper 4264 * The extended current speed and protocol configured for the port. 4265 * Access: RO 4266 */ 4267 MLXSW_ITEM32(reg, ptys, ext_eth_proto_oper, 0x20, 0, 32); 4268 4269 /* reg_ptys_eth_proto_oper 4270 * The current speed and protocol configured for the port. 4271 * Access: RO 4272 */ 4273 MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32); 4274 4275 /* reg_ptys_ib_link_width_oper 4276 * The current IB width to set port to. 4277 * Access: RO 4278 */ 4279 MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16); 4280 4281 /* reg_ptys_ib_proto_oper 4282 * The current IB speed and protocol. 4283 * Access: RO 4284 */ 4285 MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16); 4286 4287 enum mlxsw_reg_ptys_connector_type { 4288 MLXSW_REG_PTYS_CONNECTOR_TYPE_UNKNOWN_OR_NO_CONNECTOR, 4289 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_NONE, 4290 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_TP, 4291 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_AUI, 4292 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_BNC, 4293 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_MII, 4294 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_FIBRE, 4295 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_DA, 4296 MLXSW_REG_PTYS_CONNECTOR_TYPE_PORT_OTHER, 4297 }; 4298 4299 /* reg_ptys_connector_type 4300 * Connector type indication. 4301 * Access: RO 4302 */ 4303 MLXSW_ITEM32(reg, ptys, connector_type, 0x2C, 0, 4); 4304 4305 static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port, 4306 u32 proto_admin, bool autoneg) 4307 { 4308 MLXSW_REG_ZERO(ptys, payload); 4309 mlxsw_reg_ptys_local_port_set(payload, local_port); 4310 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4311 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin); 4312 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4313 } 4314 4315 static inline void mlxsw_reg_ptys_ext_eth_pack(char *payload, u8 local_port, 4316 u32 proto_admin, bool autoneg) 4317 { 4318 MLXSW_REG_ZERO(ptys, payload); 4319 mlxsw_reg_ptys_local_port_set(payload, local_port); 4320 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH); 4321 mlxsw_reg_ptys_ext_eth_proto_admin_set(payload, proto_admin); 4322 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg); 4323 } 4324 4325 static inline void mlxsw_reg_ptys_eth_unpack(char *payload, 4326 u32 *p_eth_proto_cap, 4327 u32 *p_eth_proto_admin, 4328 u32 *p_eth_proto_oper) 4329 { 4330 if (p_eth_proto_cap) 4331 *p_eth_proto_cap = 4332 mlxsw_reg_ptys_eth_proto_cap_get(payload); 4333 if (p_eth_proto_admin) 4334 *p_eth_proto_admin = 4335 mlxsw_reg_ptys_eth_proto_admin_get(payload); 4336 if (p_eth_proto_oper) 4337 *p_eth_proto_oper = 4338 mlxsw_reg_ptys_eth_proto_oper_get(payload); 4339 } 4340 4341 static inline void mlxsw_reg_ptys_ext_eth_unpack(char *payload, 4342 u32 *p_eth_proto_cap, 4343 u32 *p_eth_proto_admin, 4344 u32 *p_eth_proto_oper) 4345 { 4346 if (p_eth_proto_cap) 4347 *p_eth_proto_cap = 4348 mlxsw_reg_ptys_ext_eth_proto_cap_get(payload); 4349 if (p_eth_proto_admin) 4350 *p_eth_proto_admin = 4351 mlxsw_reg_ptys_ext_eth_proto_admin_get(payload); 4352 if (p_eth_proto_oper) 4353 *p_eth_proto_oper = 4354 mlxsw_reg_ptys_ext_eth_proto_oper_get(payload); 4355 } 4356 4357 static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port, 4358 u16 proto_admin, u16 link_width) 4359 { 4360 MLXSW_REG_ZERO(ptys, payload); 4361 mlxsw_reg_ptys_local_port_set(payload, local_port); 4362 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB); 4363 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin); 4364 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width); 4365 } 4366 4367 static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap, 4368 u16 *p_ib_link_width_cap, 4369 u16 *p_ib_proto_oper, 4370 u16 *p_ib_link_width_oper) 4371 { 4372 if (p_ib_proto_cap) 4373 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload); 4374 if (p_ib_link_width_cap) 4375 *p_ib_link_width_cap = 4376 mlxsw_reg_ptys_ib_link_width_cap_get(payload); 4377 if (p_ib_proto_oper) 4378 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload); 4379 if (p_ib_link_width_oper) 4380 *p_ib_link_width_oper = 4381 mlxsw_reg_ptys_ib_link_width_oper_get(payload); 4382 } 4383 4384 /* PPAD - Port Physical Address Register 4385 * ------------------------------------- 4386 * The PPAD register configures the per port physical MAC address. 4387 */ 4388 #define MLXSW_REG_PPAD_ID 0x5005 4389 #define MLXSW_REG_PPAD_LEN 0x10 4390 4391 MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN); 4392 4393 /* reg_ppad_single_base_mac 4394 * 0: base_mac, local port should be 0 and mac[7:0] is 4395 * reserved. HW will set incremental 4396 * 1: single_mac - mac of the local_port 4397 * Access: RW 4398 */ 4399 MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1); 4400 4401 /* reg_ppad_local_port 4402 * port number, if single_base_mac = 0 then local_port is reserved 4403 * Access: RW 4404 */ 4405 MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8); 4406 4407 /* reg_ppad_mac 4408 * If single_base_mac = 0 - base MAC address, mac[7:0] is reserved. 4409 * If single_base_mac = 1 - the per port MAC address 4410 * Access: RW 4411 */ 4412 MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6); 4413 4414 static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac, 4415 u8 local_port) 4416 { 4417 MLXSW_REG_ZERO(ppad, payload); 4418 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac); 4419 mlxsw_reg_ppad_local_port_set(payload, local_port); 4420 } 4421 4422 /* PAOS - Ports Administrative and Operational Status Register 4423 * ----------------------------------------------------------- 4424 * Configures and retrieves per port administrative and operational status. 4425 */ 4426 #define MLXSW_REG_PAOS_ID 0x5006 4427 #define MLXSW_REG_PAOS_LEN 0x10 4428 4429 MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN); 4430 4431 /* reg_paos_swid 4432 * Switch partition ID with which to associate the port. 4433 * Note: while external ports uses unique local port numbers (and thus swid is 4434 * redundant), router ports use the same local port number where swid is the 4435 * only indication for the relevant port. 4436 * Access: Index 4437 */ 4438 MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8); 4439 4440 /* reg_paos_local_port 4441 * Local port number. 4442 * Access: Index 4443 */ 4444 MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8); 4445 4446 /* reg_paos_admin_status 4447 * Port administrative state (the desired state of the port): 4448 * 1 - Up. 4449 * 2 - Down. 4450 * 3 - Up once. This means that in case of link failure, the port won't go 4451 * into polling mode, but will wait to be re-enabled by software. 4452 * 4 - Disabled by system. Can only be set by hardware. 4453 * Access: RW 4454 */ 4455 MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4); 4456 4457 /* reg_paos_oper_status 4458 * Port operational state (the current state): 4459 * 1 - Up. 4460 * 2 - Down. 4461 * 3 - Down by port failure. This means that the device will not let the 4462 * port up again until explicitly specified by software. 4463 * Access: RO 4464 */ 4465 MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4); 4466 4467 /* reg_paos_ase 4468 * Admin state update enabled. 4469 * Access: WO 4470 */ 4471 MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1); 4472 4473 /* reg_paos_ee 4474 * Event update enable. If this bit is set, event generation will be 4475 * updated based on the e field. 4476 * Access: WO 4477 */ 4478 MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1); 4479 4480 /* reg_paos_e 4481 * Event generation on operational state change: 4482 * 0 - Do not generate event. 4483 * 1 - Generate Event. 4484 * 2 - Generate Single Event. 4485 * Access: RW 4486 */ 4487 MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2); 4488 4489 static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port, 4490 enum mlxsw_port_admin_status status) 4491 { 4492 MLXSW_REG_ZERO(paos, payload); 4493 mlxsw_reg_paos_swid_set(payload, 0); 4494 mlxsw_reg_paos_local_port_set(payload, local_port); 4495 mlxsw_reg_paos_admin_status_set(payload, status); 4496 mlxsw_reg_paos_oper_status_set(payload, 0); 4497 mlxsw_reg_paos_ase_set(payload, 1); 4498 mlxsw_reg_paos_ee_set(payload, 1); 4499 mlxsw_reg_paos_e_set(payload, 1); 4500 } 4501 4502 /* PFCC - Ports Flow Control Configuration Register 4503 * ------------------------------------------------ 4504 * Configures and retrieves the per port flow control configuration. 4505 */ 4506 #define MLXSW_REG_PFCC_ID 0x5007 4507 #define MLXSW_REG_PFCC_LEN 0x20 4508 4509 MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN); 4510 4511 /* reg_pfcc_local_port 4512 * Local port number. 4513 * Access: Index 4514 */ 4515 MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8); 4516 4517 /* reg_pfcc_pnat 4518 * Port number access type. Determines the way local_port is interpreted: 4519 * 0 - Local port number. 4520 * 1 - IB / label port number. 4521 * Access: Index 4522 */ 4523 MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2); 4524 4525 /* reg_pfcc_shl_cap 4526 * Send to higher layers capabilities: 4527 * 0 - No capability of sending Pause and PFC frames to higher layers. 4528 * 1 - Device has capability of sending Pause and PFC frames to higher 4529 * layers. 4530 * Access: RO 4531 */ 4532 MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1); 4533 4534 /* reg_pfcc_shl_opr 4535 * Send to higher layers operation: 4536 * 0 - Pause and PFC frames are handled by the port (default). 4537 * 1 - Pause and PFC frames are handled by the port and also sent to 4538 * higher layers. Only valid if shl_cap = 1. 4539 * Access: RW 4540 */ 4541 MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1); 4542 4543 /* reg_pfcc_ppan 4544 * Pause policy auto negotiation. 4545 * 0 - Disabled. Generate / ignore Pause frames based on pptx / pprtx. 4546 * 1 - Enabled. When auto-negotiation is performed, set the Pause policy 4547 * based on the auto-negotiation resolution. 4548 * Access: RW 4549 * 4550 * Note: The auto-negotiation advertisement is set according to pptx and 4551 * pprtx. When PFC is set on Tx / Rx, ppan must be set to 0. 4552 */ 4553 MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4); 4554 4555 /* reg_pfcc_prio_mask_tx 4556 * Bit per priority indicating if Tx flow control policy should be 4557 * updated based on bit pfctx. 4558 * Access: WO 4559 */ 4560 MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8); 4561 4562 /* reg_pfcc_prio_mask_rx 4563 * Bit per priority indicating if Rx flow control policy should be 4564 * updated based on bit pfcrx. 4565 * Access: WO 4566 */ 4567 MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8); 4568 4569 /* reg_pfcc_pptx 4570 * Admin Pause policy on Tx. 4571 * 0 - Never generate Pause frames (default). 4572 * 1 - Generate Pause frames according to Rx buffer threshold. 4573 * Access: RW 4574 */ 4575 MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1); 4576 4577 /* reg_pfcc_aptx 4578 * Active (operational) Pause policy on Tx. 4579 * 0 - Never generate Pause frames. 4580 * 1 - Generate Pause frames according to Rx buffer threshold. 4581 * Access: RO 4582 */ 4583 MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1); 4584 4585 /* reg_pfcc_pfctx 4586 * Priority based flow control policy on Tx[7:0]. Per-priority bit mask: 4587 * 0 - Never generate priority Pause frames on the specified priority 4588 * (default). 4589 * 1 - Generate priority Pause frames according to Rx buffer threshold on 4590 * the specified priority. 4591 * Access: RW 4592 * 4593 * Note: pfctx and pptx must be mutually exclusive. 4594 */ 4595 MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8); 4596 4597 /* reg_pfcc_pprx 4598 * Admin Pause policy on Rx. 4599 * 0 - Ignore received Pause frames (default). 4600 * 1 - Respect received Pause frames. 4601 * Access: RW 4602 */ 4603 MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1); 4604 4605 /* reg_pfcc_aprx 4606 * Active (operational) Pause policy on Rx. 4607 * 0 - Ignore received Pause frames. 4608 * 1 - Respect received Pause frames. 4609 * Access: RO 4610 */ 4611 MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1); 4612 4613 /* reg_pfcc_pfcrx 4614 * Priority based flow control policy on Rx[7:0]. Per-priority bit mask: 4615 * 0 - Ignore incoming priority Pause frames on the specified priority 4616 * (default). 4617 * 1 - Respect incoming priority Pause frames on the specified priority. 4618 * Access: RW 4619 */ 4620 MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8); 4621 4622 #define MLXSW_REG_PFCC_ALL_PRIO 0xFF 4623 4624 static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en) 4625 { 4626 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4627 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO); 4628 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en); 4629 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en); 4630 } 4631 4632 static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port) 4633 { 4634 MLXSW_REG_ZERO(pfcc, payload); 4635 mlxsw_reg_pfcc_local_port_set(payload, local_port); 4636 } 4637 4638 /* PPCNT - Ports Performance Counters Register 4639 * ------------------------------------------- 4640 * The PPCNT register retrieves per port performance counters. 4641 */ 4642 #define MLXSW_REG_PPCNT_ID 0x5008 4643 #define MLXSW_REG_PPCNT_LEN 0x100 4644 #define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08 4645 4646 MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN); 4647 4648 /* reg_ppcnt_swid 4649 * For HCA: must be always 0. 4650 * Switch partition ID to associate port with. 4651 * Switch partitions are numbered from 0 to 7 inclusively. 4652 * Switch partition 254 indicates stacking ports. 4653 * Switch partition 255 indicates all switch partitions. 4654 * Only valid on Set() operation with local_port=255. 4655 * Access: Index 4656 */ 4657 MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8); 4658 4659 /* reg_ppcnt_local_port 4660 * Local port number. 4661 * 255 indicates all ports on the device, and is only allowed 4662 * for Set() operation. 4663 * Access: Index 4664 */ 4665 MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8); 4666 4667 /* reg_ppcnt_pnat 4668 * Port number access type: 4669 * 0 - Local port number 4670 * 1 - IB port number 4671 * Access: Index 4672 */ 4673 MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2); 4674 4675 enum mlxsw_reg_ppcnt_grp { 4676 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0, 4677 MLXSW_REG_PPCNT_RFC_2863_CNT = 0x1, 4678 MLXSW_REG_PPCNT_RFC_2819_CNT = 0x2, 4679 MLXSW_REG_PPCNT_RFC_3635_CNT = 0x3, 4680 MLXSW_REG_PPCNT_EXT_CNT = 0x5, 4681 MLXSW_REG_PPCNT_DISCARD_CNT = 0x6, 4682 MLXSW_REG_PPCNT_PRIO_CNT = 0x10, 4683 MLXSW_REG_PPCNT_TC_CNT = 0x11, 4684 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13, 4685 }; 4686 4687 /* reg_ppcnt_grp 4688 * Performance counter group. 4689 * Group 63 indicates all groups. Only valid on Set() operation with 4690 * clr bit set. 4691 * 0x0: IEEE 802.3 Counters 4692 * 0x1: RFC 2863 Counters 4693 * 0x2: RFC 2819 Counters 4694 * 0x3: RFC 3635 Counters 4695 * 0x5: Ethernet Extended Counters 4696 * 0x6: Ethernet Discard Counters 4697 * 0x8: Link Level Retransmission Counters 4698 * 0x10: Per Priority Counters 4699 * 0x11: Per Traffic Class Counters 4700 * 0x12: Physical Layer Counters 4701 * 0x13: Per Traffic Class Congestion Counters 4702 * Access: Index 4703 */ 4704 MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6); 4705 4706 /* reg_ppcnt_clr 4707 * Clear counters. Setting the clr bit will reset the counter value 4708 * for all counters in the counter group. This bit can be set 4709 * for both Set() and Get() operation. 4710 * Access: OP 4711 */ 4712 MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1); 4713 4714 /* reg_ppcnt_prio_tc 4715 * Priority for counter set that support per priority, valid values: 0-7. 4716 * Traffic class for counter set that support per traffic class, 4717 * valid values: 0- cap_max_tclass-1 . 4718 * For HCA: cap_max_tclass is always 8. 4719 * Otherwise must be 0. 4720 * Access: Index 4721 */ 4722 MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5); 4723 4724 /* Ethernet IEEE 802.3 Counter Group */ 4725 4726 /* reg_ppcnt_a_frames_transmitted_ok 4727 * Access: RO 4728 */ 4729 MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok, 4730 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4731 4732 /* reg_ppcnt_a_frames_received_ok 4733 * Access: RO 4734 */ 4735 MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok, 4736 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4737 4738 /* reg_ppcnt_a_frame_check_sequence_errors 4739 * Access: RO 4740 */ 4741 MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors, 4742 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4743 4744 /* reg_ppcnt_a_alignment_errors 4745 * Access: RO 4746 */ 4747 MLXSW_ITEM64(reg, ppcnt, a_alignment_errors, 4748 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4749 4750 /* reg_ppcnt_a_octets_transmitted_ok 4751 * Access: RO 4752 */ 4753 MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok, 4754 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 4755 4756 /* reg_ppcnt_a_octets_received_ok 4757 * Access: RO 4758 */ 4759 MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok, 4760 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 4761 4762 /* reg_ppcnt_a_multicast_frames_xmitted_ok 4763 * Access: RO 4764 */ 4765 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok, 4766 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4767 4768 /* reg_ppcnt_a_broadcast_frames_xmitted_ok 4769 * Access: RO 4770 */ 4771 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok, 4772 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4773 4774 /* reg_ppcnt_a_multicast_frames_received_ok 4775 * Access: RO 4776 */ 4777 MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok, 4778 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4779 4780 /* reg_ppcnt_a_broadcast_frames_received_ok 4781 * Access: RO 4782 */ 4783 MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok, 4784 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 4785 4786 /* reg_ppcnt_a_in_range_length_errors 4787 * Access: RO 4788 */ 4789 MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors, 4790 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 4791 4792 /* reg_ppcnt_a_out_of_range_length_field 4793 * Access: RO 4794 */ 4795 MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field, 4796 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4797 4798 /* reg_ppcnt_a_frame_too_long_errors 4799 * Access: RO 4800 */ 4801 MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors, 4802 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4803 4804 /* reg_ppcnt_a_symbol_error_during_carrier 4805 * Access: RO 4806 */ 4807 MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier, 4808 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4809 4810 /* reg_ppcnt_a_mac_control_frames_transmitted 4811 * Access: RO 4812 */ 4813 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted, 4814 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4815 4816 /* reg_ppcnt_a_mac_control_frames_received 4817 * Access: RO 4818 */ 4819 MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received, 4820 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4821 4822 /* reg_ppcnt_a_unsupported_opcodes_received 4823 * Access: RO 4824 */ 4825 MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received, 4826 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4827 4828 /* reg_ppcnt_a_pause_mac_ctrl_frames_received 4829 * Access: RO 4830 */ 4831 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received, 4832 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4833 4834 /* reg_ppcnt_a_pause_mac_ctrl_frames_transmitted 4835 * Access: RO 4836 */ 4837 MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted, 4838 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4839 4840 /* Ethernet RFC 2863 Counter Group */ 4841 4842 /* reg_ppcnt_if_in_discards 4843 * Access: RO 4844 */ 4845 MLXSW_ITEM64(reg, ppcnt, if_in_discards, 4846 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4847 4848 /* reg_ppcnt_if_out_discards 4849 * Access: RO 4850 */ 4851 MLXSW_ITEM64(reg, ppcnt, if_out_discards, 4852 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4853 4854 /* reg_ppcnt_if_out_errors 4855 * Access: RO 4856 */ 4857 MLXSW_ITEM64(reg, ppcnt, if_out_errors, 4858 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4859 4860 /* Ethernet RFC 2819 Counter Group */ 4861 4862 /* reg_ppcnt_ether_stats_undersize_pkts 4863 * Access: RO 4864 */ 4865 MLXSW_ITEM64(reg, ppcnt, ether_stats_undersize_pkts, 4866 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 4867 4868 /* reg_ppcnt_ether_stats_oversize_pkts 4869 * Access: RO 4870 */ 4871 MLXSW_ITEM64(reg, ppcnt, ether_stats_oversize_pkts, 4872 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64); 4873 4874 /* reg_ppcnt_ether_stats_fragments 4875 * Access: RO 4876 */ 4877 MLXSW_ITEM64(reg, ppcnt, ether_stats_fragments, 4878 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 4879 4880 /* reg_ppcnt_ether_stats_pkts64octets 4881 * Access: RO 4882 */ 4883 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts64octets, 4884 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 4885 4886 /* reg_ppcnt_ether_stats_pkts65to127octets 4887 * Access: RO 4888 */ 4889 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts65to127octets, 4890 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4891 4892 /* reg_ppcnt_ether_stats_pkts128to255octets 4893 * Access: RO 4894 */ 4895 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts128to255octets, 4896 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4897 4898 /* reg_ppcnt_ether_stats_pkts256to511octets 4899 * Access: RO 4900 */ 4901 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts256to511octets, 4902 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4903 4904 /* reg_ppcnt_ether_stats_pkts512to1023octets 4905 * Access: RO 4906 */ 4907 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts512to1023octets, 4908 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64); 4909 4910 /* reg_ppcnt_ether_stats_pkts1024to1518octets 4911 * Access: RO 4912 */ 4913 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1024to1518octets, 4914 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64); 4915 4916 /* reg_ppcnt_ether_stats_pkts1519to2047octets 4917 * Access: RO 4918 */ 4919 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts1519to2047octets, 4920 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64); 4921 4922 /* reg_ppcnt_ether_stats_pkts2048to4095octets 4923 * Access: RO 4924 */ 4925 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts2048to4095octets, 4926 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64); 4927 4928 /* reg_ppcnt_ether_stats_pkts4096to8191octets 4929 * Access: RO 4930 */ 4931 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts4096to8191octets, 4932 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x98, 0, 64); 4933 4934 /* reg_ppcnt_ether_stats_pkts8192to10239octets 4935 * Access: RO 4936 */ 4937 MLXSW_ITEM64(reg, ppcnt, ether_stats_pkts8192to10239octets, 4938 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0xA0, 0, 64); 4939 4940 /* Ethernet RFC 3635 Counter Group */ 4941 4942 /* reg_ppcnt_dot3stats_fcs_errors 4943 * Access: RO 4944 */ 4945 MLXSW_ITEM64(reg, ppcnt, dot3stats_fcs_errors, 4946 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4947 4948 /* reg_ppcnt_dot3stats_symbol_errors 4949 * Access: RO 4950 */ 4951 MLXSW_ITEM64(reg, ppcnt, dot3stats_symbol_errors, 4952 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 4953 4954 /* reg_ppcnt_dot3control_in_unknown_opcodes 4955 * Access: RO 4956 */ 4957 MLXSW_ITEM64(reg, ppcnt, dot3control_in_unknown_opcodes, 4958 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 4959 4960 /* reg_ppcnt_dot3in_pause_frames 4961 * Access: RO 4962 */ 4963 MLXSW_ITEM64(reg, ppcnt, dot3in_pause_frames, 4964 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 4965 4966 /* Ethernet Extended Counter Group Counters */ 4967 4968 /* reg_ppcnt_ecn_marked 4969 * Access: RO 4970 */ 4971 MLXSW_ITEM64(reg, ppcnt, ecn_marked, 4972 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4973 4974 /* Ethernet Discard Counter Group Counters */ 4975 4976 /* reg_ppcnt_ingress_general 4977 * Access: RO 4978 */ 4979 MLXSW_ITEM64(reg, ppcnt, ingress_general, 4980 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 4981 4982 /* reg_ppcnt_ingress_policy_engine 4983 * Access: RO 4984 */ 4985 MLXSW_ITEM64(reg, ppcnt, ingress_policy_engine, 4986 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 4987 4988 /* reg_ppcnt_ingress_vlan_membership 4989 * Access: RO 4990 */ 4991 MLXSW_ITEM64(reg, ppcnt, ingress_vlan_membership, 4992 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64); 4993 4994 /* reg_ppcnt_ingress_tag_frame_type 4995 * Access: RO 4996 */ 4997 MLXSW_ITEM64(reg, ppcnt, ingress_tag_frame_type, 4998 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64); 4999 5000 /* reg_ppcnt_egress_vlan_membership 5001 * Access: RO 5002 */ 5003 MLXSW_ITEM64(reg, ppcnt, egress_vlan_membership, 5004 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5005 5006 /* reg_ppcnt_loopback_filter 5007 * Access: RO 5008 */ 5009 MLXSW_ITEM64(reg, ppcnt, loopback_filter, 5010 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5011 5012 /* reg_ppcnt_egress_general 5013 * Access: RO 5014 */ 5015 MLXSW_ITEM64(reg, ppcnt, egress_general, 5016 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64); 5017 5018 /* reg_ppcnt_egress_hoq 5019 * Access: RO 5020 */ 5021 MLXSW_ITEM64(reg, ppcnt, egress_hoq, 5022 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64); 5023 5024 /* reg_ppcnt_egress_policy_engine 5025 * Access: RO 5026 */ 5027 MLXSW_ITEM64(reg, ppcnt, egress_policy_engine, 5028 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5029 5030 /* reg_ppcnt_ingress_tx_link_down 5031 * Access: RO 5032 */ 5033 MLXSW_ITEM64(reg, ppcnt, ingress_tx_link_down, 5034 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5035 5036 /* reg_ppcnt_egress_stp_filter 5037 * Access: RO 5038 */ 5039 MLXSW_ITEM64(reg, ppcnt, egress_stp_filter, 5040 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5041 5042 /* reg_ppcnt_egress_sll 5043 * Access: RO 5044 */ 5045 MLXSW_ITEM64(reg, ppcnt, egress_sll, 5046 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5047 5048 /* Ethernet Per Priority Group Counters */ 5049 5050 /* reg_ppcnt_rx_octets 5051 * Access: RO 5052 */ 5053 MLXSW_ITEM64(reg, ppcnt, rx_octets, 5054 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5055 5056 /* reg_ppcnt_rx_frames 5057 * Access: RO 5058 */ 5059 MLXSW_ITEM64(reg, ppcnt, rx_frames, 5060 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64); 5061 5062 /* reg_ppcnt_tx_octets 5063 * Access: RO 5064 */ 5065 MLXSW_ITEM64(reg, ppcnt, tx_octets, 5066 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64); 5067 5068 /* reg_ppcnt_tx_frames 5069 * Access: RO 5070 */ 5071 MLXSW_ITEM64(reg, ppcnt, tx_frames, 5072 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64); 5073 5074 /* reg_ppcnt_rx_pause 5075 * Access: RO 5076 */ 5077 MLXSW_ITEM64(reg, ppcnt, rx_pause, 5078 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64); 5079 5080 /* reg_ppcnt_rx_pause_duration 5081 * Access: RO 5082 */ 5083 MLXSW_ITEM64(reg, ppcnt, rx_pause_duration, 5084 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64); 5085 5086 /* reg_ppcnt_tx_pause 5087 * Access: RO 5088 */ 5089 MLXSW_ITEM64(reg, ppcnt, tx_pause, 5090 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64); 5091 5092 /* reg_ppcnt_tx_pause_duration 5093 * Access: RO 5094 */ 5095 MLXSW_ITEM64(reg, ppcnt, tx_pause_duration, 5096 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64); 5097 5098 /* reg_ppcnt_rx_pause_transition 5099 * Access: RO 5100 */ 5101 MLXSW_ITEM64(reg, ppcnt, tx_pause_transition, 5102 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64); 5103 5104 /* Ethernet Per Traffic Group Counters */ 5105 5106 /* reg_ppcnt_tc_transmit_queue 5107 * Contains the transmit queue depth in cells of traffic class 5108 * selected by prio_tc and the port selected by local_port. 5109 * The field cannot be cleared. 5110 * Access: RO 5111 */ 5112 MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue, 5113 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5114 5115 /* reg_ppcnt_tc_no_buffer_discard_uc 5116 * The number of unicast packets dropped due to lack of shared 5117 * buffer resources. 5118 * Access: RO 5119 */ 5120 MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc, 5121 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64); 5122 5123 /* Ethernet Per Traffic Class Congestion Group Counters */ 5124 5125 /* reg_ppcnt_wred_discard 5126 * Access: RO 5127 */ 5128 MLXSW_ITEM64(reg, ppcnt, wred_discard, 5129 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64); 5130 5131 static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port, 5132 enum mlxsw_reg_ppcnt_grp grp, 5133 u8 prio_tc) 5134 { 5135 MLXSW_REG_ZERO(ppcnt, payload); 5136 mlxsw_reg_ppcnt_swid_set(payload, 0); 5137 mlxsw_reg_ppcnt_local_port_set(payload, local_port); 5138 mlxsw_reg_ppcnt_pnat_set(payload, 0); 5139 mlxsw_reg_ppcnt_grp_set(payload, grp); 5140 mlxsw_reg_ppcnt_clr_set(payload, 0); 5141 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc); 5142 } 5143 5144 /* PLIB - Port Local to InfiniBand Port 5145 * ------------------------------------ 5146 * The PLIB register performs mapping from Local Port into InfiniBand Port. 5147 */ 5148 #define MLXSW_REG_PLIB_ID 0x500A 5149 #define MLXSW_REG_PLIB_LEN 0x10 5150 5151 MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN); 5152 5153 /* reg_plib_local_port 5154 * Local port number. 5155 * Access: Index 5156 */ 5157 MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8); 5158 5159 /* reg_plib_ib_port 5160 * InfiniBand port remapping for local_port. 5161 * Access: RW 5162 */ 5163 MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8); 5164 5165 /* PPTB - Port Prio To Buffer Register 5166 * ----------------------------------- 5167 * Configures the switch priority to buffer table. 5168 */ 5169 #define MLXSW_REG_PPTB_ID 0x500B 5170 #define MLXSW_REG_PPTB_LEN 0x10 5171 5172 MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN); 5173 5174 enum { 5175 MLXSW_REG_PPTB_MM_UM, 5176 MLXSW_REG_PPTB_MM_UNICAST, 5177 MLXSW_REG_PPTB_MM_MULTICAST, 5178 }; 5179 5180 /* reg_pptb_mm 5181 * Mapping mode. 5182 * 0 - Map both unicast and multicast packets to the same buffer. 5183 * 1 - Map only unicast packets. 5184 * 2 - Map only multicast packets. 5185 * Access: Index 5186 * 5187 * Note: SwitchX-2 only supports the first option. 5188 */ 5189 MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2); 5190 5191 /* reg_pptb_local_port 5192 * Local port number. 5193 * Access: Index 5194 */ 5195 MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8); 5196 5197 /* reg_pptb_um 5198 * Enables the update of the untagged_buf field. 5199 * Access: RW 5200 */ 5201 MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1); 5202 5203 /* reg_pptb_pm 5204 * Enables the update of the prio_to_buff field. 5205 * Bit <i> is a flag for updating the mapping for switch priority <i>. 5206 * Access: RW 5207 */ 5208 MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8); 5209 5210 /* reg_pptb_prio_to_buff 5211 * Mapping of switch priority <i> to one of the allocated receive port 5212 * buffers. 5213 * Access: RW 5214 */ 5215 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4); 5216 5217 /* reg_pptb_pm_msb 5218 * Enables the update of the prio_to_buff field. 5219 * Bit <i> is a flag for updating the mapping for switch priority <i+8>. 5220 * Access: RW 5221 */ 5222 MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8); 5223 5224 /* reg_pptb_untagged_buff 5225 * Mapping of untagged frames to one of the allocated receive port buffers. 5226 * Access: RW 5227 * 5228 * Note: In SwitchX-2 this field must be mapped to buffer 8. Reserved for 5229 * Spectrum, as it maps untagged packets based on the default switch priority. 5230 */ 5231 MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4); 5232 5233 /* reg_pptb_prio_to_buff_msb 5234 * Mapping of switch priority <i+8> to one of the allocated receive port 5235 * buffers. 5236 * Access: RW 5237 */ 5238 MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4); 5239 5240 #define MLXSW_REG_PPTB_ALL_PRIO 0xFF 5241 5242 static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port) 5243 { 5244 MLXSW_REG_ZERO(pptb, payload); 5245 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM); 5246 mlxsw_reg_pptb_local_port_set(payload, local_port); 5247 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5248 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO); 5249 } 5250 5251 static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio, 5252 u8 buff) 5253 { 5254 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff); 5255 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff); 5256 } 5257 5258 /* PBMC - Port Buffer Management Control Register 5259 * ---------------------------------------------- 5260 * The PBMC register configures and retrieves the port packet buffer 5261 * allocation for different Prios, and the Pause threshold management. 5262 */ 5263 #define MLXSW_REG_PBMC_ID 0x500C 5264 #define MLXSW_REG_PBMC_LEN 0x6C 5265 5266 MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN); 5267 5268 /* reg_pbmc_local_port 5269 * Local port number. 5270 * Access: Index 5271 */ 5272 MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8); 5273 5274 /* reg_pbmc_xoff_timer_value 5275 * When device generates a pause frame, it uses this value as the pause 5276 * timer (time for the peer port to pause in quota-512 bit time). 5277 * Access: RW 5278 */ 5279 MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16); 5280 5281 /* reg_pbmc_xoff_refresh 5282 * The time before a new pause frame should be sent to refresh the pause RW 5283 * state. Using the same units as xoff_timer_value above (in quota-512 bit 5284 * time). 5285 * Access: RW 5286 */ 5287 MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16); 5288 5289 #define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11 5290 5291 /* reg_pbmc_buf_lossy 5292 * The field indicates if the buffer is lossy. 5293 * 0 - Lossless 5294 * 1 - Lossy 5295 * Access: RW 5296 */ 5297 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false); 5298 5299 /* reg_pbmc_buf_epsb 5300 * Eligible for Port Shared buffer. 5301 * If epsb is set, packets assigned to buffer are allowed to insert the port 5302 * shared buffer. 5303 * When buf_lossy is MLXSW_REG_PBMC_LOSSY_LOSSY this field is reserved. 5304 * Access: RW 5305 */ 5306 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false); 5307 5308 /* reg_pbmc_buf_size 5309 * The part of the packet buffer array is allocated for the specific buffer. 5310 * Units are represented in cells. 5311 * Access: RW 5312 */ 5313 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false); 5314 5315 /* reg_pbmc_buf_xoff_threshold 5316 * Once the amount of data in the buffer goes above this value, device 5317 * starts sending PFC frames for all priorities associated with the 5318 * buffer. Units are represented in cells. Reserved in case of lossy 5319 * buffer. 5320 * Access: RW 5321 * 5322 * Note: In Spectrum, reserved for buffer[9]. 5323 */ 5324 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16, 5325 0x08, 0x04, false); 5326 5327 /* reg_pbmc_buf_xon_threshold 5328 * When the amount of data in the buffer goes below this value, device 5329 * stops sending PFC frames for the priorities associated with the 5330 * buffer. Units are represented in cells. Reserved in case of lossy 5331 * buffer. 5332 * Access: RW 5333 * 5334 * Note: In Spectrum, reserved for buffer[9]. 5335 */ 5336 MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16, 5337 0x08, 0x04, false); 5338 5339 static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port, 5340 u16 xoff_timer_value, u16 xoff_refresh) 5341 { 5342 MLXSW_REG_ZERO(pbmc, payload); 5343 mlxsw_reg_pbmc_local_port_set(payload, local_port); 5344 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value); 5345 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh); 5346 } 5347 5348 static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload, 5349 int buf_index, 5350 u16 size) 5351 { 5352 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1); 5353 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5354 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5355 } 5356 5357 static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload, 5358 int buf_index, u16 size, 5359 u16 threshold) 5360 { 5361 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0); 5362 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0); 5363 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size); 5364 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold); 5365 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold); 5366 } 5367 5368 /* PSPA - Port Switch Partition Allocation 5369 * --------------------------------------- 5370 * Controls the association of a port with a switch partition and enables 5371 * configuring ports as stacking ports. 5372 */ 5373 #define MLXSW_REG_PSPA_ID 0x500D 5374 #define MLXSW_REG_PSPA_LEN 0x8 5375 5376 MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN); 5377 5378 /* reg_pspa_swid 5379 * Switch partition ID. 5380 * Access: RW 5381 */ 5382 MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8); 5383 5384 /* reg_pspa_local_port 5385 * Local port number. 5386 * Access: Index 5387 */ 5388 MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8); 5389 5390 /* reg_pspa_sub_port 5391 * Virtual port within the local port. Set to 0 when virtual ports are 5392 * disabled on the local port. 5393 * Access: Index 5394 */ 5395 MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8); 5396 5397 static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port) 5398 { 5399 MLXSW_REG_ZERO(pspa, payload); 5400 mlxsw_reg_pspa_swid_set(payload, swid); 5401 mlxsw_reg_pspa_local_port_set(payload, local_port); 5402 mlxsw_reg_pspa_sub_port_set(payload, 0); 5403 } 5404 5405 /* PPLR - Port Physical Loopback Register 5406 * -------------------------------------- 5407 * This register allows configuration of the port's loopback mode. 5408 */ 5409 #define MLXSW_REG_PPLR_ID 0x5018 5410 #define MLXSW_REG_PPLR_LEN 0x8 5411 5412 MLXSW_REG_DEFINE(pplr, MLXSW_REG_PPLR_ID, MLXSW_REG_PPLR_LEN); 5413 5414 /* reg_pplr_local_port 5415 * Local port number. 5416 * Access: Index 5417 */ 5418 MLXSW_ITEM32(reg, pplr, local_port, 0x00, 16, 8); 5419 5420 /* Phy local loopback. When set the port's egress traffic is looped back 5421 * to the receiver and the port transmitter is disabled. 5422 */ 5423 #define MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL BIT(1) 5424 5425 /* reg_pplr_lb_en 5426 * Loopback enable. 5427 * Access: RW 5428 */ 5429 MLXSW_ITEM32(reg, pplr, lb_en, 0x04, 0, 8); 5430 5431 static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port, 5432 bool phy_local) 5433 { 5434 MLXSW_REG_ZERO(pplr, payload); 5435 mlxsw_reg_pplr_local_port_set(payload, local_port); 5436 mlxsw_reg_pplr_lb_en_set(payload, 5437 phy_local ? 5438 MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0); 5439 } 5440 5441 /* PMTM - Port Module Type Mapping Register 5442 * ---------------------------------------- 5443 * The PMTM allows query or configuration of module types. 5444 */ 5445 #define MLXSW_REG_PMTM_ID 0x5067 5446 #define MLXSW_REG_PMTM_LEN 0x10 5447 5448 MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN); 5449 5450 /* reg_pmtm_module 5451 * Module number. 5452 * Access: Index 5453 */ 5454 MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8); 5455 5456 enum mlxsw_reg_pmtm_module_type { 5457 /* Backplane with 4 lanes */ 5458 MLXSW_REG_PMTM_MODULE_TYPE_BP_4X, 5459 /* QSFP */ 5460 MLXSW_REG_PMTM_MODULE_TYPE_QSFP, 5461 /* SFP */ 5462 MLXSW_REG_PMTM_MODULE_TYPE_SFP, 5463 /* Backplane with single lane */ 5464 MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4, 5465 /* Backplane with two lane */ 5466 MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8, 5467 /* Chip2Chip4x */ 5468 MLXSW_REG_PMTM_MODULE_TYPE_C2C4X = 10, 5469 /* Chip2Chip2x */ 5470 MLXSW_REG_PMTM_MODULE_TYPE_C2C2X, 5471 /* Chip2Chip1x */ 5472 MLXSW_REG_PMTM_MODULE_TYPE_C2C1X, 5473 /* QSFP-DD */ 5474 MLXSW_REG_PMTM_MODULE_TYPE_QSFP_DD = 14, 5475 /* OSFP */ 5476 MLXSW_REG_PMTM_MODULE_TYPE_OSFP, 5477 /* SFP-DD */ 5478 MLXSW_REG_PMTM_MODULE_TYPE_SFP_DD, 5479 /* DSFP */ 5480 MLXSW_REG_PMTM_MODULE_TYPE_DSFP, 5481 /* Chip2Chip8x */ 5482 MLXSW_REG_PMTM_MODULE_TYPE_C2C8X, 5483 }; 5484 5485 /* reg_pmtm_module_type 5486 * Module type. 5487 * Access: RW 5488 */ 5489 MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4); 5490 5491 static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module) 5492 { 5493 MLXSW_REG_ZERO(pmtm, payload); 5494 mlxsw_reg_pmtm_module_set(payload, module); 5495 } 5496 5497 static inline void 5498 mlxsw_reg_pmtm_unpack(char *payload, 5499 enum mlxsw_reg_pmtm_module_type *module_type) 5500 { 5501 *module_type = mlxsw_reg_pmtm_module_type_get(payload); 5502 } 5503 5504 /* HTGT - Host Trap Group Table 5505 * ---------------------------- 5506 * Configures the properties for forwarding to CPU. 5507 */ 5508 #define MLXSW_REG_HTGT_ID 0x7002 5509 #define MLXSW_REG_HTGT_LEN 0x20 5510 5511 MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN); 5512 5513 /* reg_htgt_swid 5514 * Switch partition ID. 5515 * Access: Index 5516 */ 5517 MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8); 5518 5519 #define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0 /* For locally attached CPU */ 5520 5521 /* reg_htgt_type 5522 * CPU path type. 5523 * Access: RW 5524 */ 5525 MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4); 5526 5527 enum mlxsw_reg_htgt_trap_group { 5528 MLXSW_REG_HTGT_TRAP_GROUP_EMAD, 5529 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP, 5530 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP, 5531 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP, 5532 MLXSW_REG_HTGT_TRAP_GROUP_SP_MC_SNOOPING, 5533 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP, 5534 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF, 5535 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM, 5536 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST, 5537 MLXSW_REG_HTGT_TRAP_GROUP_SP_NEIGH_DISCOVERY, 5538 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP, 5539 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME, 5540 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP, 5541 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT, 5542 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6, 5543 MLXSW_REG_HTGT_TRAP_GROUP_SP_LBERROR, 5544 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP0, 5545 MLXSW_REG_HTGT_TRAP_GROUP_SP_PTP1, 5546 MLXSW_REG_HTGT_TRAP_GROUP_SP_VRRP, 5547 MLXSW_REG_HTGT_TRAP_GROUP_SP_PKT_SAMPLE, 5548 MLXSW_REG_HTGT_TRAP_GROUP_SP_FLOW_LOGGING, 5549 MLXSW_REG_HTGT_TRAP_GROUP_SP_FID_MISS, 5550 MLXSW_REG_HTGT_TRAP_GROUP_SP_BFD, 5551 MLXSW_REG_HTGT_TRAP_GROUP_SP_DUMMY, 5552 MLXSW_REG_HTGT_TRAP_GROUP_SP_L2_DISCARDS, 5553 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_DISCARDS, 5554 MLXSW_REG_HTGT_TRAP_GROUP_SP_L3_EXCEPTIONS, 5555 MLXSW_REG_HTGT_TRAP_GROUP_SP_TUNNEL_DISCARDS, 5556 MLXSW_REG_HTGT_TRAP_GROUP_SP_ACL_DISCARDS, 5557 5558 __MLXSW_REG_HTGT_TRAP_GROUP_MAX, 5559 MLXSW_REG_HTGT_TRAP_GROUP_MAX = __MLXSW_REG_HTGT_TRAP_GROUP_MAX - 1 5560 }; 5561 5562 /* reg_htgt_trap_group 5563 * Trap group number. User defined number specifying which trap groups 5564 * should be forwarded to the CPU. The mapping between trap IDs and trap 5565 * groups is configured using HPKT register. 5566 * Access: Index 5567 */ 5568 MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8); 5569 5570 enum { 5571 MLXSW_REG_HTGT_POLICER_DISABLE, 5572 MLXSW_REG_HTGT_POLICER_ENABLE, 5573 }; 5574 5575 /* reg_htgt_pide 5576 * Enable policer ID specified using 'pid' field. 5577 * Access: RW 5578 */ 5579 MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1); 5580 5581 #define MLXSW_REG_HTGT_INVALID_POLICER 0xff 5582 5583 /* reg_htgt_pid 5584 * Policer ID for the trap group. 5585 * Access: RW 5586 */ 5587 MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8); 5588 5589 #define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0 5590 5591 /* reg_htgt_mirror_action 5592 * Mirror action to use. 5593 * 0 - Trap to CPU. 5594 * 1 - Trap to CPU and mirror to a mirroring agent. 5595 * 2 - Mirror to a mirroring agent and do not trap to CPU. 5596 * Access: RW 5597 * 5598 * Note: Mirroring to a mirroring agent is only supported in Spectrum. 5599 */ 5600 MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2); 5601 5602 /* reg_htgt_mirroring_agent 5603 * Mirroring agent. 5604 * Access: RW 5605 */ 5606 MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3); 5607 5608 #define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0 5609 5610 /* reg_htgt_priority 5611 * Trap group priority. 5612 * In case a packet matches multiple classification rules, the packet will 5613 * only be trapped once, based on the trap ID associated with the group (via 5614 * register HPKT) with the highest priority. 5615 * Supported values are 0-7, with 7 represnting the highest priority. 5616 * Access: RW 5617 * 5618 * Note: In SwitchX-2 this field is ignored and the priority value is replaced 5619 * by the 'trap_group' field. 5620 */ 5621 MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4); 5622 5623 #define MLXSW_REG_HTGT_DEFAULT_TC 7 5624 5625 /* reg_htgt_local_path_cpu_tclass 5626 * CPU ingress traffic class for the trap group. 5627 * Access: RW 5628 */ 5629 MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6); 5630 5631 enum mlxsw_reg_htgt_local_path_rdq { 5632 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13, 5633 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14, 5634 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15, 5635 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15, 5636 }; 5637 /* reg_htgt_local_path_rdq 5638 * Receive descriptor queue (RDQ) to use for the trap group. 5639 * Access: RW 5640 */ 5641 MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6); 5642 5643 static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id, 5644 u8 priority, u8 tc) 5645 { 5646 MLXSW_REG_ZERO(htgt, payload); 5647 5648 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) { 5649 mlxsw_reg_htgt_pide_set(payload, 5650 MLXSW_REG_HTGT_POLICER_DISABLE); 5651 } else { 5652 mlxsw_reg_htgt_pide_set(payload, 5653 MLXSW_REG_HTGT_POLICER_ENABLE); 5654 mlxsw_reg_htgt_pid_set(payload, policer_id); 5655 } 5656 5657 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL); 5658 mlxsw_reg_htgt_trap_group_set(payload, group); 5659 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU); 5660 mlxsw_reg_htgt_mirroring_agent_set(payload, 0); 5661 mlxsw_reg_htgt_priority_set(payload, priority); 5662 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc); 5663 mlxsw_reg_htgt_local_path_rdq_set(payload, group); 5664 } 5665 5666 /* HPKT - Host Packet Trap 5667 * ----------------------- 5668 * Configures trap IDs inside trap groups. 5669 */ 5670 #define MLXSW_REG_HPKT_ID 0x7003 5671 #define MLXSW_REG_HPKT_LEN 0x10 5672 5673 MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN); 5674 5675 enum { 5676 MLXSW_REG_HPKT_ACK_NOT_REQUIRED, 5677 MLXSW_REG_HPKT_ACK_REQUIRED, 5678 }; 5679 5680 /* reg_hpkt_ack 5681 * Require acknowledgements from the host for events. 5682 * If set, then the device will wait for the event it sent to be acknowledged 5683 * by the host. This option is only relevant for event trap IDs. 5684 * Access: RW 5685 * 5686 * Note: Currently not supported by firmware. 5687 */ 5688 MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1); 5689 5690 enum mlxsw_reg_hpkt_action { 5691 MLXSW_REG_HPKT_ACTION_FORWARD, 5692 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU, 5693 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU, 5694 MLXSW_REG_HPKT_ACTION_DISCARD, 5695 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD, 5696 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD, 5697 MLXSW_REG_HPKT_ACTION_TRAP_EXCEPTION_TO_CPU, 5698 MLXSW_REG_HPKT_ACTION_SET_FW_DEFAULT = 15, 5699 }; 5700 5701 /* reg_hpkt_action 5702 * Action to perform on packet when trapped. 5703 * 0 - No action. Forward to CPU based on switching rules. 5704 * 1 - Trap to CPU (CPU receives sole copy). 5705 * 2 - Mirror to CPU (CPU receives a replica of the packet). 5706 * 3 - Discard. 5707 * 4 - Soft discard (allow other traps to act on the packet). 5708 * 5 - Trap and soft discard (allow other traps to overwrite this trap). 5709 * 6 - Trap to CPU (CPU receives sole copy) and count it as error. 5710 * 15 - Restore the firmware's default action. 5711 * Access: RW 5712 * 5713 * Note: Must be set to 0 (forward) for event trap IDs, as they are already 5714 * addressed to the CPU. 5715 */ 5716 MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3); 5717 5718 /* reg_hpkt_trap_group 5719 * Trap group to associate the trap with. 5720 * Access: RW 5721 */ 5722 MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6); 5723 5724 /* reg_hpkt_trap_id 5725 * Trap ID. 5726 * Access: Index 5727 * 5728 * Note: A trap ID can only be associated with a single trap group. The device 5729 * will associate the trap ID with the last trap group configured. 5730 */ 5731 MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9); 5732 5733 enum { 5734 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT, 5735 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER, 5736 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER, 5737 }; 5738 5739 /* reg_hpkt_ctrl 5740 * Configure dedicated buffer resources for control packets. 5741 * Ignored by SwitchX-2. 5742 * 0 - Keep factory defaults. 5743 * 1 - Do not use control buffer for this trap ID. 5744 * 2 - Use control buffer for this trap ID. 5745 * Access: RW 5746 */ 5747 MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2); 5748 5749 static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id, 5750 enum mlxsw_reg_htgt_trap_group trap_group, 5751 bool is_ctrl) 5752 { 5753 MLXSW_REG_ZERO(hpkt, payload); 5754 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED); 5755 mlxsw_reg_hpkt_action_set(payload, action); 5756 mlxsw_reg_hpkt_trap_group_set(payload, trap_group); 5757 mlxsw_reg_hpkt_trap_id_set(payload, trap_id); 5758 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ? 5759 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER : 5760 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER); 5761 } 5762 5763 /* RGCR - Router General Configuration Register 5764 * -------------------------------------------- 5765 * The register is used for setting up the router configuration. 5766 */ 5767 #define MLXSW_REG_RGCR_ID 0x8001 5768 #define MLXSW_REG_RGCR_LEN 0x28 5769 5770 MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN); 5771 5772 /* reg_rgcr_ipv4_en 5773 * IPv4 router enable. 5774 * Access: RW 5775 */ 5776 MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1); 5777 5778 /* reg_rgcr_ipv6_en 5779 * IPv6 router enable. 5780 * Access: RW 5781 */ 5782 MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1); 5783 5784 /* reg_rgcr_max_router_interfaces 5785 * Defines the maximum number of active router interfaces for all virtual 5786 * routers. 5787 * Access: RW 5788 */ 5789 MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16); 5790 5791 /* reg_rgcr_usp 5792 * Update switch priority and packet color. 5793 * 0 - Preserve the value of Switch Priority and packet color. 5794 * 1 - Recalculate the value of Switch Priority and packet color. 5795 * Access: RW 5796 * 5797 * Note: Not supported by SwitchX and SwitchX-2. 5798 */ 5799 MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1); 5800 5801 /* reg_rgcr_pcp_rw 5802 * Indicates how to handle the pcp_rewrite_en value: 5803 * 0 - Preserve the value of pcp_rewrite_en. 5804 * 2 - Disable PCP rewrite. 5805 * 3 - Enable PCP rewrite. 5806 * Access: RW 5807 * 5808 * Note: Not supported by SwitchX and SwitchX-2. 5809 */ 5810 MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2); 5811 5812 /* reg_rgcr_activity_dis 5813 * Activity disable: 5814 * 0 - Activity will be set when an entry is hit (default). 5815 * 1 - Activity will not be set when an entry is hit. 5816 * 5817 * Bit 0 - Disable activity bit in Router Algorithmic LPM Unicast Entry 5818 * (RALUE). 5819 * Bit 1 - Disable activity bit in Router Algorithmic LPM Unicast Host 5820 * Entry (RAUHT). 5821 * Bits 2:7 are reserved. 5822 * Access: RW 5823 * 5824 * Note: Not supported by SwitchX, SwitchX-2 and Switch-IB. 5825 */ 5826 MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8); 5827 5828 static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en, 5829 bool ipv6_en) 5830 { 5831 MLXSW_REG_ZERO(rgcr, payload); 5832 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en); 5833 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en); 5834 } 5835 5836 /* RITR - Router Interface Table Register 5837 * -------------------------------------- 5838 * The register is used to configure the router interface table. 5839 */ 5840 #define MLXSW_REG_RITR_ID 0x8002 5841 #define MLXSW_REG_RITR_LEN 0x40 5842 5843 MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN); 5844 5845 /* reg_ritr_enable 5846 * Enables routing on the router interface. 5847 * Access: RW 5848 */ 5849 MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1); 5850 5851 /* reg_ritr_ipv4 5852 * IPv4 routing enable. Enables routing of IPv4 traffic on the router 5853 * interface. 5854 * Access: RW 5855 */ 5856 MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1); 5857 5858 /* reg_ritr_ipv6 5859 * IPv6 routing enable. Enables routing of IPv6 traffic on the router 5860 * interface. 5861 * Access: RW 5862 */ 5863 MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1); 5864 5865 /* reg_ritr_ipv4_mc 5866 * IPv4 multicast routing enable. 5867 * Access: RW 5868 */ 5869 MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1); 5870 5871 /* reg_ritr_ipv6_mc 5872 * IPv6 multicast routing enable. 5873 * Access: RW 5874 */ 5875 MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1); 5876 5877 enum mlxsw_reg_ritr_if_type { 5878 /* VLAN interface. */ 5879 MLXSW_REG_RITR_VLAN_IF, 5880 /* FID interface. */ 5881 MLXSW_REG_RITR_FID_IF, 5882 /* Sub-port interface. */ 5883 MLXSW_REG_RITR_SP_IF, 5884 /* Loopback Interface. */ 5885 MLXSW_REG_RITR_LOOPBACK_IF, 5886 }; 5887 5888 /* reg_ritr_type 5889 * Router interface type as per enum mlxsw_reg_ritr_if_type. 5890 * Access: RW 5891 */ 5892 MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3); 5893 5894 enum { 5895 MLXSW_REG_RITR_RIF_CREATE, 5896 MLXSW_REG_RITR_RIF_DEL, 5897 }; 5898 5899 /* reg_ritr_op 5900 * Opcode: 5901 * 0 - Create or edit RIF. 5902 * 1 - Delete RIF. 5903 * Reserved for SwitchX-2. For Spectrum, editing of interface properties 5904 * is not supported. An interface must be deleted and re-created in order 5905 * to update properties. 5906 * Access: WO 5907 */ 5908 MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2); 5909 5910 /* reg_ritr_rif 5911 * Router interface index. A pointer to the Router Interface Table. 5912 * Access: Index 5913 */ 5914 MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16); 5915 5916 /* reg_ritr_ipv4_fe 5917 * IPv4 Forwarding Enable. 5918 * Enables routing of IPv4 traffic on the router interface. When disabled, 5919 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5920 * Not supported in SwitchX-2. 5921 * Access: RW 5922 */ 5923 MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1); 5924 5925 /* reg_ritr_ipv6_fe 5926 * IPv6 Forwarding Enable. 5927 * Enables routing of IPv6 traffic on the router interface. When disabled, 5928 * forwarding is blocked but local traffic (traps and IP2ME) will be enabled. 5929 * Not supported in SwitchX-2. 5930 * Access: RW 5931 */ 5932 MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1); 5933 5934 /* reg_ritr_ipv4_mc_fe 5935 * IPv4 Multicast Forwarding Enable. 5936 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5937 * will be enabled. 5938 * Access: RW 5939 */ 5940 MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1); 5941 5942 /* reg_ritr_ipv6_mc_fe 5943 * IPv6 Multicast Forwarding Enable. 5944 * When disabled, forwarding is blocked but local traffic (traps and IP to me) 5945 * will be enabled. 5946 * Access: RW 5947 */ 5948 MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1); 5949 5950 /* reg_ritr_lb_en 5951 * Loop-back filter enable for unicast packets. 5952 * If the flag is set then loop-back filter for unicast packets is 5953 * implemented on the RIF. Multicast packets are always subject to 5954 * loop-back filtering. 5955 * Access: RW 5956 */ 5957 MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1); 5958 5959 /* reg_ritr_virtual_router 5960 * Virtual router ID associated with the router interface. 5961 * Access: RW 5962 */ 5963 MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16); 5964 5965 /* reg_ritr_mtu 5966 * Router interface MTU. 5967 * Access: RW 5968 */ 5969 MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16); 5970 5971 /* reg_ritr_if_swid 5972 * Switch partition ID. 5973 * Access: RW 5974 */ 5975 MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8); 5976 5977 /* reg_ritr_if_mac 5978 * Router interface MAC address. 5979 * In Spectrum, all MAC addresses must have the same 38 MSBits. 5980 * Access: RW 5981 */ 5982 MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6); 5983 5984 /* reg_ritr_if_vrrp_id_ipv6 5985 * VRRP ID for IPv6 5986 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5987 * Access: RW 5988 */ 5989 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv6, 0x1C, 8, 8); 5990 5991 /* reg_ritr_if_vrrp_id_ipv4 5992 * VRRP ID for IPv4 5993 * Note: Reserved for RIF types other than VLAN, FID and Sub-port. 5994 * Access: RW 5995 */ 5996 MLXSW_ITEM32(reg, ritr, if_vrrp_id_ipv4, 0x1C, 0, 8); 5997 5998 /* VLAN Interface */ 5999 6000 /* reg_ritr_vlan_if_vid 6001 * VLAN ID. 6002 * Access: RW 6003 */ 6004 MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12); 6005 6006 /* FID Interface */ 6007 6008 /* reg_ritr_fid_if_fid 6009 * Filtering ID. Used to connect a bridge to the router. Only FIDs from 6010 * the vFID range are supported. 6011 * Access: RW 6012 */ 6013 MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16); 6014 6015 static inline void mlxsw_reg_ritr_fid_set(char *payload, 6016 enum mlxsw_reg_ritr_if_type rif_type, 6017 u16 fid) 6018 { 6019 if (rif_type == MLXSW_REG_RITR_FID_IF) 6020 mlxsw_reg_ritr_fid_if_fid_set(payload, fid); 6021 else 6022 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid); 6023 } 6024 6025 /* Sub-port Interface */ 6026 6027 /* reg_ritr_sp_if_lag 6028 * LAG indication. When this bit is set the system_port field holds the 6029 * LAG identifier. 6030 * Access: RW 6031 */ 6032 MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1); 6033 6034 /* reg_ritr_sp_system_port 6035 * Port unique indentifier. When lag bit is set, this field holds the 6036 * lag_id in bits 0:9. 6037 * Access: RW 6038 */ 6039 MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16); 6040 6041 /* reg_ritr_sp_if_vid 6042 * VLAN ID. 6043 * Access: RW 6044 */ 6045 MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12); 6046 6047 /* Loopback Interface */ 6048 6049 enum mlxsw_reg_ritr_loopback_protocol { 6050 /* IPinIP IPv4 underlay Unicast */ 6051 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4, 6052 /* IPinIP IPv6 underlay Unicast */ 6053 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6, 6054 /* IPinIP generic - used for Spectrum-2 underlay RIF */ 6055 MLXSW_REG_RITR_LOOPBACK_GENERIC, 6056 }; 6057 6058 /* reg_ritr_loopback_protocol 6059 * Access: RW 6060 */ 6061 MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4); 6062 6063 enum mlxsw_reg_ritr_loopback_ipip_type { 6064 /* Tunnel is IPinIP. */ 6065 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP, 6066 /* Tunnel is GRE, no key. */ 6067 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP, 6068 /* Tunnel is GRE, with a key. */ 6069 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP, 6070 }; 6071 6072 /* reg_ritr_loopback_ipip_type 6073 * Encapsulation type. 6074 * Access: RW 6075 */ 6076 MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4); 6077 6078 enum mlxsw_reg_ritr_loopback_ipip_options { 6079 /* The key is defined by gre_key. */ 6080 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET, 6081 }; 6082 6083 /* reg_ritr_loopback_ipip_options 6084 * Access: RW 6085 */ 6086 MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4); 6087 6088 /* reg_ritr_loopback_ipip_uvr 6089 * Underlay Virtual Router ID. 6090 * Range is 0..cap_max_virtual_routers-1. 6091 * Reserved for Spectrum-2. 6092 * Access: RW 6093 */ 6094 MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16); 6095 6096 /* reg_ritr_loopback_ipip_underlay_rif 6097 * Underlay ingress router interface. 6098 * Reserved for Spectrum. 6099 * Access: RW 6100 */ 6101 MLXSW_ITEM32(reg, ritr, loopback_ipip_underlay_rif, 0x14, 0, 16); 6102 6103 /* reg_ritr_loopback_ipip_usip* 6104 * Encapsulation Underlay source IP. 6105 * Access: RW 6106 */ 6107 MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16); 6108 MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32); 6109 6110 /* reg_ritr_loopback_ipip_gre_key 6111 * GRE Key. 6112 * Reserved when ipip_type is not IP_IN_GRE_KEY_IN_IP. 6113 * Access: RW 6114 */ 6115 MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32); 6116 6117 /* Shared between ingress/egress */ 6118 enum mlxsw_reg_ritr_counter_set_type { 6119 /* No Count. */ 6120 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0, 6121 /* Basic. Used for router interfaces, counting the following: 6122 * - Error and Discard counters. 6123 * - Unicast, Multicast and Broadcast counters. Sharing the 6124 * same set of counters for the different type of traffic 6125 * (IPv4, IPv6 and mpls). 6126 */ 6127 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9, 6128 }; 6129 6130 /* reg_ritr_ingress_counter_index 6131 * Counter Index for flow counter. 6132 * Access: RW 6133 */ 6134 MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24); 6135 6136 /* reg_ritr_ingress_counter_set_type 6137 * Igress Counter Set Type for router interface counter. 6138 * Access: RW 6139 */ 6140 MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8); 6141 6142 /* reg_ritr_egress_counter_index 6143 * Counter Index for flow counter. 6144 * Access: RW 6145 */ 6146 MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24); 6147 6148 /* reg_ritr_egress_counter_set_type 6149 * Egress Counter Set Type for router interface counter. 6150 * Access: RW 6151 */ 6152 MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8); 6153 6154 static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index, 6155 bool enable, bool egress) 6156 { 6157 enum mlxsw_reg_ritr_counter_set_type set_type; 6158 6159 if (enable) 6160 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC; 6161 else 6162 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT; 6163 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type); 6164 6165 if (egress) 6166 mlxsw_reg_ritr_egress_counter_index_set(payload, index); 6167 else 6168 mlxsw_reg_ritr_ingress_counter_index_set(payload, index); 6169 } 6170 6171 static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif) 6172 { 6173 MLXSW_REG_ZERO(ritr, payload); 6174 mlxsw_reg_ritr_rif_set(payload, rif); 6175 } 6176 6177 static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag, 6178 u16 system_port, u16 vid) 6179 { 6180 mlxsw_reg_ritr_sp_if_lag_set(payload, lag); 6181 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port); 6182 mlxsw_reg_ritr_sp_if_vid_set(payload, vid); 6183 } 6184 6185 static inline void mlxsw_reg_ritr_pack(char *payload, bool enable, 6186 enum mlxsw_reg_ritr_if_type type, 6187 u16 rif, u16 vr_id, u16 mtu) 6188 { 6189 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL; 6190 6191 MLXSW_REG_ZERO(ritr, payload); 6192 mlxsw_reg_ritr_enable_set(payload, enable); 6193 mlxsw_reg_ritr_ipv4_set(payload, 1); 6194 mlxsw_reg_ritr_ipv6_set(payload, 1); 6195 mlxsw_reg_ritr_ipv4_mc_set(payload, 1); 6196 mlxsw_reg_ritr_ipv6_mc_set(payload, 1); 6197 mlxsw_reg_ritr_type_set(payload, type); 6198 mlxsw_reg_ritr_op_set(payload, op); 6199 mlxsw_reg_ritr_rif_set(payload, rif); 6200 mlxsw_reg_ritr_ipv4_fe_set(payload, 1); 6201 mlxsw_reg_ritr_ipv6_fe_set(payload, 1); 6202 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1); 6203 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1); 6204 mlxsw_reg_ritr_lb_en_set(payload, 1); 6205 mlxsw_reg_ritr_virtual_router_set(payload, vr_id); 6206 mlxsw_reg_ritr_mtu_set(payload, mtu); 6207 } 6208 6209 static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac) 6210 { 6211 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac); 6212 } 6213 6214 static inline void 6215 mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload, 6216 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6217 enum mlxsw_reg_ritr_loopback_ipip_options options, 6218 u16 uvr_id, u16 underlay_rif, u32 gre_key) 6219 { 6220 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type); 6221 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options); 6222 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id); 6223 mlxsw_reg_ritr_loopback_ipip_underlay_rif_set(payload, underlay_rif); 6224 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key); 6225 } 6226 6227 static inline void 6228 mlxsw_reg_ritr_loopback_ipip4_pack(char *payload, 6229 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type, 6230 enum mlxsw_reg_ritr_loopback_ipip_options options, 6231 u16 uvr_id, u16 underlay_rif, u32 usip, u32 gre_key) 6232 { 6233 mlxsw_reg_ritr_loopback_protocol_set(payload, 6234 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4); 6235 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options, 6236 uvr_id, underlay_rif, gre_key); 6237 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip); 6238 } 6239 6240 /* RTAR - Router TCAM Allocation Register 6241 * -------------------------------------- 6242 * This register is used for allocation of regions in the TCAM table. 6243 */ 6244 #define MLXSW_REG_RTAR_ID 0x8004 6245 #define MLXSW_REG_RTAR_LEN 0x20 6246 6247 MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN); 6248 6249 enum mlxsw_reg_rtar_op { 6250 MLXSW_REG_RTAR_OP_ALLOCATE, 6251 MLXSW_REG_RTAR_OP_RESIZE, 6252 MLXSW_REG_RTAR_OP_DEALLOCATE, 6253 }; 6254 6255 /* reg_rtar_op 6256 * Access: WO 6257 */ 6258 MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4); 6259 6260 enum mlxsw_reg_rtar_key_type { 6261 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1, 6262 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3 6263 }; 6264 6265 /* reg_rtar_key_type 6266 * TCAM key type for the region. 6267 * Access: WO 6268 */ 6269 MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8); 6270 6271 /* reg_rtar_region_size 6272 * TCAM region size. When allocating/resizing this is the requested 6273 * size, the response is the actual size. 6274 * Note: Actual size may be larger than requested. 6275 * Reserved for op = Deallocate 6276 * Access: WO 6277 */ 6278 MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16); 6279 6280 static inline void mlxsw_reg_rtar_pack(char *payload, 6281 enum mlxsw_reg_rtar_op op, 6282 enum mlxsw_reg_rtar_key_type key_type, 6283 u16 region_size) 6284 { 6285 MLXSW_REG_ZERO(rtar, payload); 6286 mlxsw_reg_rtar_op_set(payload, op); 6287 mlxsw_reg_rtar_key_type_set(payload, key_type); 6288 mlxsw_reg_rtar_region_size_set(payload, region_size); 6289 } 6290 6291 /* RATR - Router Adjacency Table Register 6292 * -------------------------------------- 6293 * The RATR register is used to configure the Router Adjacency (next-hop) 6294 * Table. 6295 */ 6296 #define MLXSW_REG_RATR_ID 0x8008 6297 #define MLXSW_REG_RATR_LEN 0x2C 6298 6299 MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN); 6300 6301 enum mlxsw_reg_ratr_op { 6302 /* Read */ 6303 MLXSW_REG_RATR_OP_QUERY_READ = 0, 6304 /* Read and clear activity */ 6305 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2, 6306 /* Write Adjacency entry */ 6307 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1, 6308 /* Write Adjacency entry only if the activity is cleared. 6309 * The write may not succeed if the activity is set. There is not 6310 * direct feedback if the write has succeeded or not, however 6311 * the get will reveal the actual entry (SW can compare the get 6312 * response to the set command). 6313 */ 6314 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3, 6315 }; 6316 6317 /* reg_ratr_op 6318 * Note that Write operation may also be used for updating 6319 * counter_set_type and counter_index. In this case all other 6320 * fields must not be updated. 6321 * Access: OP 6322 */ 6323 MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4); 6324 6325 /* reg_ratr_v 6326 * Valid bit. Indicates if the adjacency entry is valid. 6327 * Note: the device may need some time before reusing an invalidated 6328 * entry. During this time the entry can not be reused. It is 6329 * recommended to use another entry before reusing an invalidated 6330 * entry (e.g. software can put it at the end of the list for 6331 * reusing). Trying to access an invalidated entry not yet cleared 6332 * by the device results with failure indicating "Try Again" status. 6333 * When valid is '0' then egress_router_interface,trap_action, 6334 * adjacency_parameters and counters are reserved 6335 * Access: RW 6336 */ 6337 MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1); 6338 6339 /* reg_ratr_a 6340 * Activity. Set for new entries. Set if a packet lookup has hit on 6341 * the specific entry. To clear the a bit, use "clear activity". 6342 * Access: RO 6343 */ 6344 MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1); 6345 6346 enum mlxsw_reg_ratr_type { 6347 /* Ethernet */ 6348 MLXSW_REG_RATR_TYPE_ETHERNET, 6349 /* IPoIB Unicast without GRH. 6350 * Reserved for Spectrum. 6351 */ 6352 MLXSW_REG_RATR_TYPE_IPOIB_UC, 6353 /* IPoIB Unicast with GRH. Supported only in table 0 (Ethernet unicast 6354 * adjacency). 6355 * Reserved for Spectrum. 6356 */ 6357 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH, 6358 /* IPoIB Multicast. 6359 * Reserved for Spectrum. 6360 */ 6361 MLXSW_REG_RATR_TYPE_IPOIB_MC, 6362 /* MPLS. 6363 * Reserved for SwitchX/-2. 6364 */ 6365 MLXSW_REG_RATR_TYPE_MPLS, 6366 /* IPinIP Encap. 6367 * Reserved for SwitchX/-2. 6368 */ 6369 MLXSW_REG_RATR_TYPE_IPIP, 6370 }; 6371 6372 /* reg_ratr_type 6373 * Adjacency entry type. 6374 * Access: RW 6375 */ 6376 MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4); 6377 6378 /* reg_ratr_adjacency_index_low 6379 * Bits 15:0 of index into the adjacency table. 6380 * For SwitchX and SwitchX-2, the adjacency table is linear and 6381 * used for adjacency entries only. 6382 * For Spectrum, the index is to the KVD linear. 6383 * Access: Index 6384 */ 6385 MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16); 6386 6387 /* reg_ratr_egress_router_interface 6388 * Range is 0 .. cap_max_router_interfaces - 1 6389 * Access: RW 6390 */ 6391 MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16); 6392 6393 enum mlxsw_reg_ratr_trap_action { 6394 MLXSW_REG_RATR_TRAP_ACTION_NOP, 6395 MLXSW_REG_RATR_TRAP_ACTION_TRAP, 6396 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU, 6397 MLXSW_REG_RATR_TRAP_ACTION_MIRROR, 6398 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS, 6399 }; 6400 6401 /* reg_ratr_trap_action 6402 * see mlxsw_reg_ratr_trap_action 6403 * Access: RW 6404 */ 6405 MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4); 6406 6407 /* reg_ratr_adjacency_index_high 6408 * Bits 23:16 of the adjacency_index. 6409 * Access: Index 6410 */ 6411 MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8); 6412 6413 enum mlxsw_reg_ratr_trap_id { 6414 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0, 6415 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1, 6416 }; 6417 6418 /* reg_ratr_trap_id 6419 * Trap ID to be reported to CPU. 6420 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 6421 * For trap_action of NOP, MIRROR and DISCARD_ERROR 6422 * Access: RW 6423 */ 6424 MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8); 6425 6426 /* reg_ratr_eth_destination_mac 6427 * MAC address of the destination next-hop. 6428 * Access: RW 6429 */ 6430 MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6); 6431 6432 enum mlxsw_reg_ratr_ipip_type { 6433 /* IPv4, address set by mlxsw_reg_ratr_ipip_ipv4_udip. */ 6434 MLXSW_REG_RATR_IPIP_TYPE_IPV4, 6435 /* IPv6, address set by mlxsw_reg_ratr_ipip_ipv6_ptr. */ 6436 MLXSW_REG_RATR_IPIP_TYPE_IPV6, 6437 }; 6438 6439 /* reg_ratr_ipip_type 6440 * Underlay destination ip type. 6441 * Note: the type field must match the protocol of the router interface. 6442 * Access: RW 6443 */ 6444 MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4); 6445 6446 /* reg_ratr_ipip_ipv4_udip 6447 * Underlay ipv4 dip. 6448 * Reserved when ipip_type is IPv6. 6449 * Access: RW 6450 */ 6451 MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32); 6452 6453 /* reg_ratr_ipip_ipv6_ptr 6454 * Pointer to IPv6 underlay destination ip address. 6455 * For Spectrum: Pointer to KVD linear space. 6456 * Access: RW 6457 */ 6458 MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24); 6459 6460 enum mlxsw_reg_flow_counter_set_type { 6461 /* No count */ 6462 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6463 /* Count packets and bytes */ 6464 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03, 6465 /* Count only packets */ 6466 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05, 6467 }; 6468 6469 /* reg_ratr_counter_set_type 6470 * Counter set type for flow counters 6471 * Access: RW 6472 */ 6473 MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8); 6474 6475 /* reg_ratr_counter_index 6476 * Counter index for flow counters 6477 * Access: RW 6478 */ 6479 MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24); 6480 6481 static inline void 6482 mlxsw_reg_ratr_pack(char *payload, 6483 enum mlxsw_reg_ratr_op op, bool valid, 6484 enum mlxsw_reg_ratr_type type, 6485 u32 adjacency_index, u16 egress_rif) 6486 { 6487 MLXSW_REG_ZERO(ratr, payload); 6488 mlxsw_reg_ratr_op_set(payload, op); 6489 mlxsw_reg_ratr_v_set(payload, valid); 6490 mlxsw_reg_ratr_type_set(payload, type); 6491 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index); 6492 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16); 6493 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif); 6494 } 6495 6496 static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload, 6497 const char *dest_mac) 6498 { 6499 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac); 6500 } 6501 6502 static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip) 6503 { 6504 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4); 6505 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip); 6506 } 6507 6508 static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index, 6509 bool counter_enable) 6510 { 6511 enum mlxsw_reg_flow_counter_set_type set_type; 6512 6513 if (counter_enable) 6514 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES; 6515 else 6516 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT; 6517 6518 mlxsw_reg_ratr_counter_index_set(payload, counter_index); 6519 mlxsw_reg_ratr_counter_set_type_set(payload, set_type); 6520 } 6521 6522 /* RDPM - Router DSCP to Priority Mapping 6523 * -------------------------------------- 6524 * Controls the mapping from DSCP field to switch priority on routed packets 6525 */ 6526 #define MLXSW_REG_RDPM_ID 0x8009 6527 #define MLXSW_REG_RDPM_BASE_LEN 0x00 6528 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01 6529 #define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64 6530 #define MLXSW_REG_RDPM_LEN 0x40 6531 #define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \ 6532 MLXSW_REG_RDPM_LEN - \ 6533 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN) 6534 6535 MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN); 6536 6537 /* reg_dscp_entry_e 6538 * Enable update of the specific entry 6539 * Access: Index 6540 */ 6541 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1, 6542 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6543 6544 /* reg_dscp_entry_prio 6545 * Switch Priority 6546 * Access: RW 6547 */ 6548 MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4, 6549 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false); 6550 6551 static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index, 6552 u8 prio) 6553 { 6554 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1); 6555 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio); 6556 } 6557 6558 /* RICNT - Router Interface Counter Register 6559 * ----------------------------------------- 6560 * The RICNT register retrieves per port performance counters 6561 */ 6562 #define MLXSW_REG_RICNT_ID 0x800B 6563 #define MLXSW_REG_RICNT_LEN 0x100 6564 6565 MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN); 6566 6567 /* reg_ricnt_counter_index 6568 * Counter index 6569 * Access: RW 6570 */ 6571 MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24); 6572 6573 enum mlxsw_reg_ricnt_counter_set_type { 6574 /* No Count. */ 6575 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00, 6576 /* Basic. Used for router interfaces, counting the following: 6577 * - Error and Discard counters. 6578 * - Unicast, Multicast and Broadcast counters. Sharing the 6579 * same set of counters for the different type of traffic 6580 * (IPv4, IPv6 and mpls). 6581 */ 6582 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09, 6583 }; 6584 6585 /* reg_ricnt_counter_set_type 6586 * Counter Set Type for router interface counter 6587 * Access: RW 6588 */ 6589 MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8); 6590 6591 enum mlxsw_reg_ricnt_opcode { 6592 /* Nop. Supported only for read access*/ 6593 MLXSW_REG_RICNT_OPCODE_NOP = 0x00, 6594 /* Clear. Setting the clr bit will reset the counter value for 6595 * all counters of the specified Router Interface. 6596 */ 6597 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08, 6598 }; 6599 6600 /* reg_ricnt_opcode 6601 * Opcode 6602 * Access: RW 6603 */ 6604 MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4); 6605 6606 /* reg_ricnt_good_unicast_packets 6607 * good unicast packets. 6608 * Access: RW 6609 */ 6610 MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64); 6611 6612 /* reg_ricnt_good_multicast_packets 6613 * good multicast packets. 6614 * Access: RW 6615 */ 6616 MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64); 6617 6618 /* reg_ricnt_good_broadcast_packets 6619 * good broadcast packets 6620 * Access: RW 6621 */ 6622 MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64); 6623 6624 /* reg_ricnt_good_unicast_bytes 6625 * A count of L3 data and padding octets not including L2 headers 6626 * for good unicast frames. 6627 * Access: RW 6628 */ 6629 MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64); 6630 6631 /* reg_ricnt_good_multicast_bytes 6632 * A count of L3 data and padding octets not including L2 headers 6633 * for good multicast frames. 6634 * Access: RW 6635 */ 6636 MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64); 6637 6638 /* reg_ritr_good_broadcast_bytes 6639 * A count of L3 data and padding octets not including L2 headers 6640 * for good broadcast frames. 6641 * Access: RW 6642 */ 6643 MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64); 6644 6645 /* reg_ricnt_error_packets 6646 * A count of errored frames that do not pass the router checks. 6647 * Access: RW 6648 */ 6649 MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64); 6650 6651 /* reg_ricnt_discrad_packets 6652 * A count of non-errored frames that do not pass the router checks. 6653 * Access: RW 6654 */ 6655 MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64); 6656 6657 /* reg_ricnt_error_bytes 6658 * A count of L3 data and padding octets not including L2 headers 6659 * for errored frames. 6660 * Access: RW 6661 */ 6662 MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64); 6663 6664 /* reg_ricnt_discard_bytes 6665 * A count of L3 data and padding octets not including L2 headers 6666 * for non-errored frames that do not pass the router checks. 6667 * Access: RW 6668 */ 6669 MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64); 6670 6671 static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index, 6672 enum mlxsw_reg_ricnt_opcode op) 6673 { 6674 MLXSW_REG_ZERO(ricnt, payload); 6675 mlxsw_reg_ricnt_op_set(payload, op); 6676 mlxsw_reg_ricnt_counter_index_set(payload, index); 6677 mlxsw_reg_ricnt_counter_set_type_set(payload, 6678 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC); 6679 } 6680 6681 /* RRCR - Router Rules Copy Register Layout 6682 * ---------------------------------------- 6683 * This register is used for moving and copying route entry rules. 6684 */ 6685 #define MLXSW_REG_RRCR_ID 0x800F 6686 #define MLXSW_REG_RRCR_LEN 0x24 6687 6688 MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN); 6689 6690 enum mlxsw_reg_rrcr_op { 6691 /* Move rules */ 6692 MLXSW_REG_RRCR_OP_MOVE, 6693 /* Copy rules */ 6694 MLXSW_REG_RRCR_OP_COPY, 6695 }; 6696 6697 /* reg_rrcr_op 6698 * Access: WO 6699 */ 6700 MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4); 6701 6702 /* reg_rrcr_offset 6703 * Offset within the region from which to copy/move. 6704 * Access: Index 6705 */ 6706 MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16); 6707 6708 /* reg_rrcr_size 6709 * The number of rules to copy/move. 6710 * Access: WO 6711 */ 6712 MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16); 6713 6714 /* reg_rrcr_table_id 6715 * Identifier of the table on which to perform the operation. Encoding is the 6716 * same as in RTAR.key_type 6717 * Access: Index 6718 */ 6719 MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4); 6720 6721 /* reg_rrcr_dest_offset 6722 * Offset within the region to which to copy/move 6723 * Access: Index 6724 */ 6725 MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16); 6726 6727 static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op, 6728 u16 offset, u16 size, 6729 enum mlxsw_reg_rtar_key_type table_id, 6730 u16 dest_offset) 6731 { 6732 MLXSW_REG_ZERO(rrcr, payload); 6733 mlxsw_reg_rrcr_op_set(payload, op); 6734 mlxsw_reg_rrcr_offset_set(payload, offset); 6735 mlxsw_reg_rrcr_size_set(payload, size); 6736 mlxsw_reg_rrcr_table_id_set(payload, table_id); 6737 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset); 6738 } 6739 6740 /* RALTA - Router Algorithmic LPM Tree Allocation Register 6741 * ------------------------------------------------------- 6742 * RALTA is used to allocate the LPM trees of the SHSPM method. 6743 */ 6744 #define MLXSW_REG_RALTA_ID 0x8010 6745 #define MLXSW_REG_RALTA_LEN 0x04 6746 6747 MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN); 6748 6749 /* reg_ralta_op 6750 * opcode (valid for Write, must be 0 on Read) 6751 * 0 - allocate a tree 6752 * 1 - deallocate a tree 6753 * Access: OP 6754 */ 6755 MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2); 6756 6757 enum mlxsw_reg_ralxx_protocol { 6758 MLXSW_REG_RALXX_PROTOCOL_IPV4, 6759 MLXSW_REG_RALXX_PROTOCOL_IPV6, 6760 }; 6761 6762 /* reg_ralta_protocol 6763 * Protocol. 6764 * Deallocation opcode: Reserved. 6765 * Access: RW 6766 */ 6767 MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4); 6768 6769 /* reg_ralta_tree_id 6770 * An identifier (numbered from 1..cap_shspm_max_trees-1) representing 6771 * the tree identifier (managed by software). 6772 * Note that tree_id 0 is allocated for a default-route tree. 6773 * Access: Index 6774 */ 6775 MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8); 6776 6777 static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc, 6778 enum mlxsw_reg_ralxx_protocol protocol, 6779 u8 tree_id) 6780 { 6781 MLXSW_REG_ZERO(ralta, payload); 6782 mlxsw_reg_ralta_op_set(payload, !alloc); 6783 mlxsw_reg_ralta_protocol_set(payload, protocol); 6784 mlxsw_reg_ralta_tree_id_set(payload, tree_id); 6785 } 6786 6787 /* RALST - Router Algorithmic LPM Structure Tree Register 6788 * ------------------------------------------------------ 6789 * RALST is used to set and query the structure of an LPM tree. 6790 * The structure of the tree must be sorted as a sorted binary tree, while 6791 * each node is a bin that is tagged as the length of the prefixes the lookup 6792 * will refer to. Therefore, bin X refers to a set of entries with prefixes 6793 * of X bits to match with the destination address. The bin 0 indicates 6794 * the default action, when there is no match of any prefix. 6795 */ 6796 #define MLXSW_REG_RALST_ID 0x8011 6797 #define MLXSW_REG_RALST_LEN 0x104 6798 6799 MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN); 6800 6801 /* reg_ralst_root_bin 6802 * The bin number of the root bin. 6803 * 0<root_bin=<(length of IP address) 6804 * For a default-route tree configure 0xff 6805 * Access: RW 6806 */ 6807 MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8); 6808 6809 /* reg_ralst_tree_id 6810 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6811 * Access: Index 6812 */ 6813 MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8); 6814 6815 #define MLXSW_REG_RALST_BIN_NO_CHILD 0xff 6816 #define MLXSW_REG_RALST_BIN_OFFSET 0x04 6817 #define MLXSW_REG_RALST_BIN_COUNT 128 6818 6819 /* reg_ralst_left_child_bin 6820 * Holding the children of the bin according to the stored tree's structure. 6821 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6822 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6823 * Access: RW 6824 */ 6825 MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false); 6826 6827 /* reg_ralst_right_child_bin 6828 * Holding the children of the bin according to the stored tree's structure. 6829 * For trees composed of less than 4 blocks, the bins in excess are reserved. 6830 * Note that tree_id 0 is allocated for a default-route tree, bins are 0xff 6831 * Access: RW 6832 */ 6833 MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00, 6834 false); 6835 6836 static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id) 6837 { 6838 MLXSW_REG_ZERO(ralst, payload); 6839 6840 /* Initialize all bins to have no left or right child */ 6841 memset(payload + MLXSW_REG_RALST_BIN_OFFSET, 6842 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2); 6843 6844 mlxsw_reg_ralst_root_bin_set(payload, root_bin); 6845 mlxsw_reg_ralst_tree_id_set(payload, tree_id); 6846 } 6847 6848 static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number, 6849 u8 left_child_bin, 6850 u8 right_child_bin) 6851 { 6852 int bin_index = bin_number - 1; 6853 6854 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin); 6855 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index, 6856 right_child_bin); 6857 } 6858 6859 /* RALTB - Router Algorithmic LPM Tree Binding Register 6860 * ---------------------------------------------------- 6861 * RALTB is used to bind virtual router and protocol to an allocated LPM tree. 6862 */ 6863 #define MLXSW_REG_RALTB_ID 0x8012 6864 #define MLXSW_REG_RALTB_LEN 0x04 6865 6866 MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN); 6867 6868 /* reg_raltb_virtual_router 6869 * Virtual Router ID 6870 * Range is 0..cap_max_virtual_routers-1 6871 * Access: Index 6872 */ 6873 MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16); 6874 6875 /* reg_raltb_protocol 6876 * Protocol. 6877 * Access: Index 6878 */ 6879 MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4); 6880 6881 /* reg_raltb_tree_id 6882 * Tree to be used for the {virtual_router, protocol} 6883 * Tree identifier numbered from 1..(cap_shspm_max_trees-1). 6884 * By default, all Unicast IPv4 and IPv6 are bound to tree_id 0. 6885 * Access: RW 6886 */ 6887 MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8); 6888 6889 static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router, 6890 enum mlxsw_reg_ralxx_protocol protocol, 6891 u8 tree_id) 6892 { 6893 MLXSW_REG_ZERO(raltb, payload); 6894 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router); 6895 mlxsw_reg_raltb_protocol_set(payload, protocol); 6896 mlxsw_reg_raltb_tree_id_set(payload, tree_id); 6897 } 6898 6899 /* RALUE - Router Algorithmic LPM Unicast Entry Register 6900 * ----------------------------------------------------- 6901 * RALUE is used to configure and query LPM entries that serve 6902 * the Unicast protocols. 6903 */ 6904 #define MLXSW_REG_RALUE_ID 0x8013 6905 #define MLXSW_REG_RALUE_LEN 0x38 6906 6907 MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN); 6908 6909 /* reg_ralue_protocol 6910 * Protocol. 6911 * Access: Index 6912 */ 6913 MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4); 6914 6915 enum mlxsw_reg_ralue_op { 6916 /* Read operation. If entry doesn't exist, the operation fails. */ 6917 MLXSW_REG_RALUE_OP_QUERY_READ = 0, 6918 /* Clear on read operation. Used to read entry and 6919 * clear Activity bit. 6920 */ 6921 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1, 6922 /* Write operation. Used to write a new entry to the table. All RW 6923 * fields are written for new entry. Activity bit is set 6924 * for new entries. 6925 */ 6926 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0, 6927 /* Update operation. Used to update an existing route entry and 6928 * only update the RW fields that are detailed in the field 6929 * op_u_mask. If entry doesn't exist, the operation fails. 6930 */ 6931 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1, 6932 /* Clear activity. The Activity bit (the field a) is cleared 6933 * for the entry. 6934 */ 6935 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2, 6936 /* Delete operation. Used to delete an existing entry. If entry 6937 * doesn't exist, the operation fails. 6938 */ 6939 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3, 6940 }; 6941 6942 /* reg_ralue_op 6943 * Operation. 6944 * Access: OP 6945 */ 6946 MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3); 6947 6948 /* reg_ralue_a 6949 * Activity. Set for new entries. Set if a packet lookup has hit on the 6950 * specific entry, only if the entry is a route. To clear the a bit, use 6951 * "clear activity" op. 6952 * Enabled by activity_dis in RGCR 6953 * Access: RO 6954 */ 6955 MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1); 6956 6957 /* reg_ralue_virtual_router 6958 * Virtual Router ID 6959 * Range is 0..cap_max_virtual_routers-1 6960 * Access: Index 6961 */ 6962 MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16); 6963 6964 #define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0) 6965 #define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1) 6966 #define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2) 6967 6968 /* reg_ralue_op_u_mask 6969 * opcode update mask. 6970 * On read operation, this field is reserved. 6971 * This field is valid for update opcode, otherwise - reserved. 6972 * This field is a bitmask of the fields that should be updated. 6973 * Access: WO 6974 */ 6975 MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3); 6976 6977 /* reg_ralue_prefix_len 6978 * Number of bits in the prefix of the LPM route. 6979 * Note that for IPv6 prefixes, if prefix_len>64 the entry consumes 6980 * two entries in the physical HW table. 6981 * Access: Index 6982 */ 6983 MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8); 6984 6985 /* reg_ralue_dip* 6986 * The prefix of the route or of the marker that the object of the LPM 6987 * is compared with. The most significant bits of the dip are the prefix. 6988 * The least significant bits must be '0' if the prefix_len is smaller 6989 * than 128 for IPv6 or smaller than 32 for IPv4. 6990 * IPv4 address uses bits dip[31:0] and bits dip[127:32] are reserved. 6991 * Access: Index 6992 */ 6993 MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32); 6994 MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16); 6995 6996 enum mlxsw_reg_ralue_entry_type { 6997 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1, 6998 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2, 6999 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3, 7000 }; 7001 7002 /* reg_ralue_entry_type 7003 * Entry type. 7004 * Note - for Marker entries, the action_type and action fields are reserved. 7005 * Access: RW 7006 */ 7007 MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2); 7008 7009 /* reg_ralue_bmp_len 7010 * The best match prefix length in the case that there is no match for 7011 * longer prefixes. 7012 * If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len 7013 * Note for any update operation with entry_type modification this 7014 * field must be set. 7015 * Access: RW 7016 */ 7017 MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8); 7018 7019 enum mlxsw_reg_ralue_action_type { 7020 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE, 7021 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL, 7022 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME, 7023 }; 7024 7025 /* reg_ralue_action_type 7026 * Action Type 7027 * Indicates how the IP address is connected. 7028 * It can be connected to a local subnet through local_erif or can be 7029 * on a remote subnet connected through a next-hop router, 7030 * or transmitted to the CPU. 7031 * Reserved when entry_type = MARKER_ENTRY 7032 * Access: RW 7033 */ 7034 MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2); 7035 7036 enum mlxsw_reg_ralue_trap_action { 7037 MLXSW_REG_RALUE_TRAP_ACTION_NOP, 7038 MLXSW_REG_RALUE_TRAP_ACTION_TRAP, 7039 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU, 7040 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR, 7041 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR, 7042 }; 7043 7044 /* reg_ralue_trap_action 7045 * Trap action. 7046 * For IP2ME action, only NOP and MIRROR are possible. 7047 * Access: RW 7048 */ 7049 MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4); 7050 7051 /* reg_ralue_trap_id 7052 * Trap ID to be reported to CPU. 7053 * Trap ID is RTR_INGRESS0 or RTR_INGRESS1. 7054 * For trap_action of NOP, MIRROR and DISCARD_ERROR, trap_id is reserved. 7055 * Access: RW 7056 */ 7057 MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9); 7058 7059 /* reg_ralue_adjacency_index 7060 * Points to the first entry of the group-based ECMP. 7061 * Only relevant in case of REMOTE action. 7062 * Access: RW 7063 */ 7064 MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24); 7065 7066 /* reg_ralue_ecmp_size 7067 * Amount of sequential entries starting 7068 * from the adjacency_index (the number of ECMPs). 7069 * The valid range is 1-64, 512, 1024, 2048 and 4096. 7070 * Reserved when trap_action is TRAP or DISCARD_ERROR. 7071 * Only relevant in case of REMOTE action. 7072 * Access: RW 7073 */ 7074 MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13); 7075 7076 /* reg_ralue_local_erif 7077 * Egress Router Interface. 7078 * Only relevant in case of LOCAL action. 7079 * Access: RW 7080 */ 7081 MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16); 7082 7083 /* reg_ralue_ip2me_v 7084 * Valid bit for the tunnel_ptr field. 7085 * If valid = 0 then trap to CPU as IP2ME trap ID. 7086 * If valid = 1 and the packet format allows NVE or IPinIP tunnel 7087 * decapsulation then tunnel decapsulation is done. 7088 * If valid = 1 and packet format does not allow NVE or IPinIP tunnel 7089 * decapsulation then trap as IP2ME trap ID. 7090 * Only relevant in case of IP2ME action. 7091 * Access: RW 7092 */ 7093 MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1); 7094 7095 /* reg_ralue_ip2me_tunnel_ptr 7096 * Tunnel Pointer for NVE or IPinIP tunnel decapsulation. 7097 * For Spectrum, pointer to KVD Linear. 7098 * Only relevant in case of IP2ME action. 7099 * Access: RW 7100 */ 7101 MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24); 7102 7103 static inline void mlxsw_reg_ralue_pack(char *payload, 7104 enum mlxsw_reg_ralxx_protocol protocol, 7105 enum mlxsw_reg_ralue_op op, 7106 u16 virtual_router, u8 prefix_len) 7107 { 7108 MLXSW_REG_ZERO(ralue, payload); 7109 mlxsw_reg_ralue_protocol_set(payload, protocol); 7110 mlxsw_reg_ralue_op_set(payload, op); 7111 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router); 7112 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len); 7113 mlxsw_reg_ralue_entry_type_set(payload, 7114 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY); 7115 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len); 7116 } 7117 7118 static inline void mlxsw_reg_ralue_pack4(char *payload, 7119 enum mlxsw_reg_ralxx_protocol protocol, 7120 enum mlxsw_reg_ralue_op op, 7121 u16 virtual_router, u8 prefix_len, 7122 u32 dip) 7123 { 7124 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7125 mlxsw_reg_ralue_dip4_set(payload, dip); 7126 } 7127 7128 static inline void mlxsw_reg_ralue_pack6(char *payload, 7129 enum mlxsw_reg_ralxx_protocol protocol, 7130 enum mlxsw_reg_ralue_op op, 7131 u16 virtual_router, u8 prefix_len, 7132 const void *dip) 7133 { 7134 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len); 7135 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip); 7136 } 7137 7138 static inline void 7139 mlxsw_reg_ralue_act_remote_pack(char *payload, 7140 enum mlxsw_reg_ralue_trap_action trap_action, 7141 u16 trap_id, u32 adjacency_index, u16 ecmp_size) 7142 { 7143 mlxsw_reg_ralue_action_type_set(payload, 7144 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE); 7145 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7146 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7147 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index); 7148 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size); 7149 } 7150 7151 static inline void 7152 mlxsw_reg_ralue_act_local_pack(char *payload, 7153 enum mlxsw_reg_ralue_trap_action trap_action, 7154 u16 trap_id, u16 local_erif) 7155 { 7156 mlxsw_reg_ralue_action_type_set(payload, 7157 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL); 7158 mlxsw_reg_ralue_trap_action_set(payload, trap_action); 7159 mlxsw_reg_ralue_trap_id_set(payload, trap_id); 7160 mlxsw_reg_ralue_local_erif_set(payload, local_erif); 7161 } 7162 7163 static inline void 7164 mlxsw_reg_ralue_act_ip2me_pack(char *payload) 7165 { 7166 mlxsw_reg_ralue_action_type_set(payload, 7167 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7168 } 7169 7170 static inline void 7171 mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr) 7172 { 7173 mlxsw_reg_ralue_action_type_set(payload, 7174 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME); 7175 mlxsw_reg_ralue_ip2me_v_set(payload, 1); 7176 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr); 7177 } 7178 7179 /* RAUHT - Router Algorithmic LPM Unicast Host Table Register 7180 * ---------------------------------------------------------- 7181 * The RAUHT register is used to configure and query the Unicast Host table in 7182 * devices that implement the Algorithmic LPM. 7183 */ 7184 #define MLXSW_REG_RAUHT_ID 0x8014 7185 #define MLXSW_REG_RAUHT_LEN 0x74 7186 7187 MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN); 7188 7189 enum mlxsw_reg_rauht_type { 7190 MLXSW_REG_RAUHT_TYPE_IPV4, 7191 MLXSW_REG_RAUHT_TYPE_IPV6, 7192 }; 7193 7194 /* reg_rauht_type 7195 * Access: Index 7196 */ 7197 MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2); 7198 7199 enum mlxsw_reg_rauht_op { 7200 MLXSW_REG_RAUHT_OP_QUERY_READ = 0, 7201 /* Read operation */ 7202 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1, 7203 /* Clear on read operation. Used to read entry and clear 7204 * activity bit. 7205 */ 7206 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0, 7207 /* Add. Used to write a new entry to the table. All R/W fields are 7208 * relevant for new entry. Activity bit is set for new entries. 7209 */ 7210 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1, 7211 /* Update action. Used to update an existing route entry and 7212 * only update the following fields: 7213 * trap_action, trap_id, mac, counter_set_type, counter_index 7214 */ 7215 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2, 7216 /* Clear activity. A bit is cleared for the entry. */ 7217 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3, 7218 /* Delete entry */ 7219 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4, 7220 /* Delete all host entries on a RIF. In this command, dip 7221 * field is reserved. 7222 */ 7223 }; 7224 7225 /* reg_rauht_op 7226 * Access: OP 7227 */ 7228 MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3); 7229 7230 /* reg_rauht_a 7231 * Activity. Set for new entries. Set if a packet lookup has hit on 7232 * the specific entry. 7233 * To clear the a bit, use "clear activity" op. 7234 * Enabled by activity_dis in RGCR 7235 * Access: RO 7236 */ 7237 MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1); 7238 7239 /* reg_rauht_rif 7240 * Router Interface 7241 * Access: Index 7242 */ 7243 MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16); 7244 7245 /* reg_rauht_dip* 7246 * Destination address. 7247 * Access: Index 7248 */ 7249 MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32); 7250 MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16); 7251 7252 enum mlxsw_reg_rauht_trap_action { 7253 MLXSW_REG_RAUHT_TRAP_ACTION_NOP, 7254 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP, 7255 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU, 7256 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR, 7257 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS, 7258 }; 7259 7260 /* reg_rauht_trap_action 7261 * Access: RW 7262 */ 7263 MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4); 7264 7265 enum mlxsw_reg_rauht_trap_id { 7266 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0, 7267 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1, 7268 }; 7269 7270 /* reg_rauht_trap_id 7271 * Trap ID to be reported to CPU. 7272 * Trap-ID is RTR_EGRESS0 or RTR_EGRESS1. 7273 * For trap_action of NOP, MIRROR and DISCARD_ERROR, 7274 * trap_id is reserved. 7275 * Access: RW 7276 */ 7277 MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9); 7278 7279 /* reg_rauht_counter_set_type 7280 * Counter set type for flow counters 7281 * Access: RW 7282 */ 7283 MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8); 7284 7285 /* reg_rauht_counter_index 7286 * Counter index for flow counters 7287 * Access: RW 7288 */ 7289 MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24); 7290 7291 /* reg_rauht_mac 7292 * MAC address. 7293 * Access: RW 7294 */ 7295 MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6); 7296 7297 static inline void mlxsw_reg_rauht_pack(char *payload, 7298 enum mlxsw_reg_rauht_op op, u16 rif, 7299 const char *mac) 7300 { 7301 MLXSW_REG_ZERO(rauht, payload); 7302 mlxsw_reg_rauht_op_set(payload, op); 7303 mlxsw_reg_rauht_rif_set(payload, rif); 7304 mlxsw_reg_rauht_mac_memcpy_to(payload, mac); 7305 } 7306 7307 static inline void mlxsw_reg_rauht_pack4(char *payload, 7308 enum mlxsw_reg_rauht_op op, u16 rif, 7309 const char *mac, u32 dip) 7310 { 7311 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7312 mlxsw_reg_rauht_dip4_set(payload, dip); 7313 } 7314 7315 static inline void mlxsw_reg_rauht_pack6(char *payload, 7316 enum mlxsw_reg_rauht_op op, u16 rif, 7317 const char *mac, const char *dip) 7318 { 7319 mlxsw_reg_rauht_pack(payload, op, rif, mac); 7320 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6); 7321 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip); 7322 } 7323 7324 static inline void mlxsw_reg_rauht_pack_counter(char *payload, 7325 u64 counter_index) 7326 { 7327 mlxsw_reg_rauht_counter_index_set(payload, counter_index); 7328 mlxsw_reg_rauht_counter_set_type_set(payload, 7329 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES); 7330 } 7331 7332 /* RALEU - Router Algorithmic LPM ECMP Update Register 7333 * --------------------------------------------------- 7334 * The register enables updating the ECMP section in the action for multiple 7335 * LPM Unicast entries in a single operation. The update is executed to 7336 * all entries of a {virtual router, protocol} tuple using the same ECMP group. 7337 */ 7338 #define MLXSW_REG_RALEU_ID 0x8015 7339 #define MLXSW_REG_RALEU_LEN 0x28 7340 7341 MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN); 7342 7343 /* reg_raleu_protocol 7344 * Protocol. 7345 * Access: Index 7346 */ 7347 MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4); 7348 7349 /* reg_raleu_virtual_router 7350 * Virtual Router ID 7351 * Range is 0..cap_max_virtual_routers-1 7352 * Access: Index 7353 */ 7354 MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16); 7355 7356 /* reg_raleu_adjacency_index 7357 * Adjacency Index used for matching on the existing entries. 7358 * Access: Index 7359 */ 7360 MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24); 7361 7362 /* reg_raleu_ecmp_size 7363 * ECMP Size used for matching on the existing entries. 7364 * Access: Index 7365 */ 7366 MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13); 7367 7368 /* reg_raleu_new_adjacency_index 7369 * New Adjacency Index. 7370 * Access: WO 7371 */ 7372 MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24); 7373 7374 /* reg_raleu_new_ecmp_size 7375 * New ECMP Size. 7376 * Access: WO 7377 */ 7378 MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13); 7379 7380 static inline void mlxsw_reg_raleu_pack(char *payload, 7381 enum mlxsw_reg_ralxx_protocol protocol, 7382 u16 virtual_router, 7383 u32 adjacency_index, u16 ecmp_size, 7384 u32 new_adjacency_index, 7385 u16 new_ecmp_size) 7386 { 7387 MLXSW_REG_ZERO(raleu, payload); 7388 mlxsw_reg_raleu_protocol_set(payload, protocol); 7389 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router); 7390 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index); 7391 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size); 7392 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index); 7393 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size); 7394 } 7395 7396 /* RAUHTD - Router Algorithmic LPM Unicast Host Table Dump Register 7397 * ---------------------------------------------------------------- 7398 * The RAUHTD register allows dumping entries from the Router Unicast Host 7399 * Table. For a given session an entry is dumped no more than one time. The 7400 * first RAUHTD access after reset is a new session. A session ends when the 7401 * num_rec response is smaller than num_rec request or for IPv4 when the 7402 * num_entries is smaller than 4. The clear activity affect the current session 7403 * or the last session if a new session has not started. 7404 */ 7405 #define MLXSW_REG_RAUHTD_ID 0x8018 7406 #define MLXSW_REG_RAUHTD_BASE_LEN 0x20 7407 #define MLXSW_REG_RAUHTD_REC_LEN 0x20 7408 #define MLXSW_REG_RAUHTD_REC_MAX_NUM 32 7409 #define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \ 7410 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN) 7411 #define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4 7412 7413 MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN); 7414 7415 #define MLXSW_REG_RAUHTD_FILTER_A BIT(0) 7416 #define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3) 7417 7418 /* reg_rauhtd_filter_fields 7419 * if a bit is '0' then the relevant field is ignored and dump is done 7420 * regardless of the field value 7421 * Bit0 - filter by activity: entry_a 7422 * Bit3 - filter by entry rip: entry_rif 7423 * Access: Index 7424 */ 7425 MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8); 7426 7427 enum mlxsw_reg_rauhtd_op { 7428 MLXSW_REG_RAUHTD_OP_DUMP, 7429 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR, 7430 }; 7431 7432 /* reg_rauhtd_op 7433 * Access: OP 7434 */ 7435 MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2); 7436 7437 /* reg_rauhtd_num_rec 7438 * At request: number of records requested 7439 * At response: number of records dumped 7440 * For IPv4, each record has 4 entries at request and up to 4 entries 7441 * at response 7442 * Range is 0..MLXSW_REG_RAUHTD_REC_MAX_NUM 7443 * Access: Index 7444 */ 7445 MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8); 7446 7447 /* reg_rauhtd_entry_a 7448 * Dump only if activity has value of entry_a 7449 * Reserved if filter_fields bit0 is '0' 7450 * Access: Index 7451 */ 7452 MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1); 7453 7454 enum mlxsw_reg_rauhtd_type { 7455 MLXSW_REG_RAUHTD_TYPE_IPV4, 7456 MLXSW_REG_RAUHTD_TYPE_IPV6, 7457 }; 7458 7459 /* reg_rauhtd_type 7460 * Dump only if record type is: 7461 * 0 - IPv4 7462 * 1 - IPv6 7463 * Access: Index 7464 */ 7465 MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4); 7466 7467 /* reg_rauhtd_entry_rif 7468 * Dump only if RIF has value of entry_rif 7469 * Reserved if filter_fields bit3 is '0' 7470 * Access: Index 7471 */ 7472 MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16); 7473 7474 static inline void mlxsw_reg_rauhtd_pack(char *payload, 7475 enum mlxsw_reg_rauhtd_type type) 7476 { 7477 MLXSW_REG_ZERO(rauhtd, payload); 7478 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A); 7479 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR); 7480 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM); 7481 mlxsw_reg_rauhtd_entry_a_set(payload, 1); 7482 mlxsw_reg_rauhtd_type_set(payload, type); 7483 } 7484 7485 /* reg_rauhtd_ipv4_rec_num_entries 7486 * Number of valid entries in this record: 7487 * 0 - 1 valid entry 7488 * 1 - 2 valid entries 7489 * 2 - 3 valid entries 7490 * 3 - 4 valid entries 7491 * Access: RO 7492 */ 7493 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries, 7494 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2, 7495 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7496 7497 /* reg_rauhtd_rec_type 7498 * Record type. 7499 * 0 - IPv4 7500 * 1 - IPv6 7501 * Access: RO 7502 */ 7503 MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2, 7504 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false); 7505 7506 #define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8 7507 7508 /* reg_rauhtd_ipv4_ent_a 7509 * Activity. Set for new entries. Set if a packet lookup has hit on the 7510 * specific entry. 7511 * Access: RO 7512 */ 7513 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7514 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7515 7516 /* reg_rauhtd_ipv4_ent_rif 7517 * Router interface. 7518 * Access: RO 7519 */ 7520 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7521 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false); 7522 7523 /* reg_rauhtd_ipv4_ent_dip 7524 * Destination IPv4 address. 7525 * Access: RO 7526 */ 7527 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7528 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false); 7529 7530 #define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20 7531 7532 /* reg_rauhtd_ipv6_ent_a 7533 * Activity. Set for new entries. Set if a packet lookup has hit on the 7534 * specific entry. 7535 * Access: RO 7536 */ 7537 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1, 7538 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7539 7540 /* reg_rauhtd_ipv6_ent_rif 7541 * Router interface. 7542 * Access: RO 7543 */ 7544 MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0, 7545 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false); 7546 7547 /* reg_rauhtd_ipv6_ent_dip 7548 * Destination IPv6 address. 7549 * Access: RO 7550 */ 7551 MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 7552 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10); 7553 7554 static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload, 7555 int ent_index, u16 *p_rif, 7556 u32 *p_dip) 7557 { 7558 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index); 7559 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index); 7560 } 7561 7562 static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload, 7563 int rec_index, u16 *p_rif, 7564 char *p_dip) 7565 { 7566 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index); 7567 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip); 7568 } 7569 7570 /* RTDP - Routing Tunnel Decap Properties Register 7571 * ----------------------------------------------- 7572 * The RTDP register is used for configuring the tunnel decap properties of NVE 7573 * and IPinIP. 7574 */ 7575 #define MLXSW_REG_RTDP_ID 0x8020 7576 #define MLXSW_REG_RTDP_LEN 0x44 7577 7578 MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN); 7579 7580 enum mlxsw_reg_rtdp_type { 7581 MLXSW_REG_RTDP_TYPE_NVE, 7582 MLXSW_REG_RTDP_TYPE_IPIP, 7583 }; 7584 7585 /* reg_rtdp_type 7586 * Type of the RTDP entry as per enum mlxsw_reg_rtdp_type. 7587 * Access: RW 7588 */ 7589 MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4); 7590 7591 /* reg_rtdp_tunnel_index 7592 * Index to the Decap entry. 7593 * For Spectrum, Index to KVD Linear. 7594 * Access: Index 7595 */ 7596 MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24); 7597 7598 /* reg_rtdp_egress_router_interface 7599 * Underlay egress router interface. 7600 * Valid range is from 0 to cap_max_router_interfaces - 1 7601 * Access: RW 7602 */ 7603 MLXSW_ITEM32(reg, rtdp, egress_router_interface, 0x40, 0, 16); 7604 7605 /* IPinIP */ 7606 7607 /* reg_rtdp_ipip_irif 7608 * Ingress Router Interface for the overlay router 7609 * Access: RW 7610 */ 7611 MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16); 7612 7613 enum mlxsw_reg_rtdp_ipip_sip_check { 7614 /* No sip checks. */ 7615 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO, 7616 /* Filter packet if underlay is not IPv4 or if underlay SIP does not 7617 * equal ipv4_usip. 7618 */ 7619 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4, 7620 /* Filter packet if underlay is not IPv6 or if underlay SIP does not 7621 * equal ipv6_usip. 7622 */ 7623 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3, 7624 }; 7625 7626 /* reg_rtdp_ipip_sip_check 7627 * SIP check to perform. If decapsulation failed due to these configurations 7628 * then trap_id is IPIP_DECAP_ERROR. 7629 * Access: RW 7630 */ 7631 MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3); 7632 7633 /* If set, allow decapsulation of IPinIP (without GRE). */ 7634 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0) 7635 /* If set, allow decapsulation of IPinGREinIP without a key. */ 7636 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1) 7637 /* If set, allow decapsulation of IPinGREinIP with a key. */ 7638 #define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2) 7639 7640 /* reg_rtdp_ipip_type_check 7641 * Flags as per MLXSW_REG_RTDP_IPIP_TYPE_CHECK_*. If decapsulation failed due to 7642 * these configurations then trap_id is IPIP_DECAP_ERROR. 7643 * Access: RW 7644 */ 7645 MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3); 7646 7647 /* reg_rtdp_ipip_gre_key_check 7648 * Whether GRE key should be checked. When check is enabled: 7649 * - A packet received as IPinIP (without GRE) will always pass. 7650 * - A packet received as IPinGREinIP without a key will not pass the check. 7651 * - A packet received as IPinGREinIP with a key will pass the check only if the 7652 * key in the packet is equal to expected_gre_key. 7653 * If decapsulation failed due to GRE key then trap_id is IPIP_DECAP_ERROR. 7654 * Access: RW 7655 */ 7656 MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1); 7657 7658 /* reg_rtdp_ipip_ipv4_usip 7659 * Underlay IPv4 address for ipv4 source address check. 7660 * Reserved when sip_check is not '1'. 7661 * Access: RW 7662 */ 7663 MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32); 7664 7665 /* reg_rtdp_ipip_ipv6_usip_ptr 7666 * This field is valid when sip_check is "sipv6 check explicitly". This is a 7667 * pointer to the IPv6 DIP which is configured by RIPS. For Spectrum, the index 7668 * is to the KVD linear. 7669 * Reserved when sip_check is not MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6. 7670 * Access: RW 7671 */ 7672 MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24); 7673 7674 /* reg_rtdp_ipip_expected_gre_key 7675 * GRE key for checking. 7676 * Reserved when gre_key_check is '0'. 7677 * Access: RW 7678 */ 7679 MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32); 7680 7681 static inline void mlxsw_reg_rtdp_pack(char *payload, 7682 enum mlxsw_reg_rtdp_type type, 7683 u32 tunnel_index) 7684 { 7685 MLXSW_REG_ZERO(rtdp, payload); 7686 mlxsw_reg_rtdp_type_set(payload, type); 7687 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index); 7688 } 7689 7690 static inline void 7691 mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif, 7692 enum mlxsw_reg_rtdp_ipip_sip_check sip_check, 7693 unsigned int type_check, bool gre_key_check, 7694 u32 ipv4_usip, u32 expected_gre_key) 7695 { 7696 mlxsw_reg_rtdp_ipip_irif_set(payload, irif); 7697 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check); 7698 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check); 7699 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check); 7700 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip); 7701 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key); 7702 } 7703 7704 /* RIGR-V2 - Router Interface Group Register Version 2 7705 * --------------------------------------------------- 7706 * The RIGR_V2 register is used to add, remove and query egress interface list 7707 * of a multicast forwarding entry. 7708 */ 7709 #define MLXSW_REG_RIGR2_ID 0x8023 7710 #define MLXSW_REG_RIGR2_LEN 0xB0 7711 7712 #define MLXSW_REG_RIGR2_MAX_ERIFS 32 7713 7714 MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN); 7715 7716 /* reg_rigr2_rigr_index 7717 * KVD Linear index. 7718 * Access: Index 7719 */ 7720 MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24); 7721 7722 /* reg_rigr2_vnext 7723 * Next RIGR Index is valid. 7724 * Access: RW 7725 */ 7726 MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1); 7727 7728 /* reg_rigr2_next_rigr_index 7729 * Next RIGR Index. The index is to the KVD linear. 7730 * Reserved when vnxet = '0'. 7731 * Access: RW 7732 */ 7733 MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24); 7734 7735 /* reg_rigr2_vrmid 7736 * RMID Index is valid. 7737 * Access: RW 7738 */ 7739 MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1); 7740 7741 /* reg_rigr2_rmid_index 7742 * RMID Index. 7743 * Range 0 .. max_mid - 1 7744 * Reserved when vrmid = '0'. 7745 * The index is to the Port Group Table (PGT) 7746 * Access: RW 7747 */ 7748 MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16); 7749 7750 /* reg_rigr2_erif_entry_v 7751 * Egress Router Interface is valid. 7752 * Note that low-entries must be set if high-entries are set. For 7753 * example: if erif_entry[2].v is set then erif_entry[1].v and 7754 * erif_entry[0].v must be set. 7755 * Index can be from 0 to cap_mc_erif_list_entries-1 7756 * Access: RW 7757 */ 7758 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false); 7759 7760 /* reg_rigr2_erif_entry_erif 7761 * Egress Router Interface. 7762 * Valid range is from 0 to cap_max_router_interfaces - 1 7763 * Index can be from 0 to MLXSW_REG_RIGR2_MAX_ERIFS - 1 7764 * Access: RW 7765 */ 7766 MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false); 7767 7768 static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index, 7769 bool vnext, u32 next_rigr_index) 7770 { 7771 MLXSW_REG_ZERO(rigr2, payload); 7772 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index); 7773 mlxsw_reg_rigr2_vnext_set(payload, vnext); 7774 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index); 7775 mlxsw_reg_rigr2_vrmid_set(payload, 0); 7776 mlxsw_reg_rigr2_rmid_index_set(payload, 0); 7777 } 7778 7779 static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index, 7780 bool v, u16 erif) 7781 { 7782 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v); 7783 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif); 7784 } 7785 7786 /* RECR-V2 - Router ECMP Configuration Version 2 Register 7787 * ------------------------------------------------------ 7788 */ 7789 #define MLXSW_REG_RECR2_ID 0x8025 7790 #define MLXSW_REG_RECR2_LEN 0x38 7791 7792 MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN); 7793 7794 /* reg_recr2_pp 7795 * Per-port configuration 7796 * Access: Index 7797 */ 7798 MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1); 7799 7800 /* reg_recr2_sh 7801 * Symmetric hash 7802 * Access: RW 7803 */ 7804 MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1); 7805 7806 /* reg_recr2_seed 7807 * Seed 7808 * Access: RW 7809 */ 7810 MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32); 7811 7812 enum { 7813 /* Enable IPv4 fields if packet is not TCP and not UDP */ 7814 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3, 7815 /* Enable IPv4 fields if packet is TCP or UDP */ 7816 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4, 7817 /* Enable IPv6 fields if packet is not TCP and not UDP */ 7818 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5, 7819 /* Enable IPv6 fields if packet is TCP or UDP */ 7820 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6, 7821 /* Enable TCP/UDP header fields if packet is IPv4 */ 7822 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7, 7823 /* Enable TCP/UDP header fields if packet is IPv6 */ 7824 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8, 7825 }; 7826 7827 /* reg_recr2_outer_header_enables 7828 * Bit mask where each bit enables a specific layer to be included in 7829 * the hash calculation. 7830 * Access: RW 7831 */ 7832 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1); 7833 7834 enum { 7835 /* IPv4 Source IP */ 7836 MLXSW_REG_RECR2_IPV4_SIP0 = 9, 7837 MLXSW_REG_RECR2_IPV4_SIP3 = 12, 7838 /* IPv4 Destination IP */ 7839 MLXSW_REG_RECR2_IPV4_DIP0 = 13, 7840 MLXSW_REG_RECR2_IPV4_DIP3 = 16, 7841 /* IP Protocol */ 7842 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17, 7843 /* IPv6 Source IP */ 7844 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21, 7845 MLXSW_REG_RECR2_IPV6_SIP8 = 29, 7846 MLXSW_REG_RECR2_IPV6_SIP15 = 36, 7847 /* IPv6 Destination IP */ 7848 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37, 7849 MLXSW_REG_RECR2_IPV6_DIP8 = 45, 7850 MLXSW_REG_RECR2_IPV6_DIP15 = 52, 7851 /* IPv6 Next Header */ 7852 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53, 7853 /* IPv6 Flow Label */ 7854 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57, 7855 /* TCP/UDP Source Port */ 7856 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74, 7857 /* TCP/UDP Destination Port */ 7858 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75, 7859 }; 7860 7861 /* reg_recr2_outer_header_fields_enable 7862 * Packet fields to enable for ECMP hash subject to outer_header_enable. 7863 * Access: RW 7864 */ 7865 MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1); 7866 7867 static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload) 7868 { 7869 int i; 7870 7871 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++) 7872 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7873 true); 7874 } 7875 7876 static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload) 7877 { 7878 int i; 7879 7880 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++) 7881 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7882 true); 7883 } 7884 7885 static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload) 7886 { 7887 int i = MLXSW_REG_RECR2_IPV6_SIP0_7; 7888 7889 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7890 7891 i = MLXSW_REG_RECR2_IPV6_SIP8; 7892 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++) 7893 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7894 true); 7895 } 7896 7897 static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload) 7898 { 7899 int i = MLXSW_REG_RECR2_IPV6_DIP0_7; 7900 7901 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true); 7902 7903 i = MLXSW_REG_RECR2_IPV6_DIP8; 7904 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++) 7905 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, 7906 true); 7907 } 7908 7909 static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed) 7910 { 7911 MLXSW_REG_ZERO(recr2, payload); 7912 mlxsw_reg_recr2_pp_set(payload, false); 7913 mlxsw_reg_recr2_sh_set(payload, true); 7914 mlxsw_reg_recr2_seed_set(payload, seed); 7915 } 7916 7917 /* RMFT-V2 - Router Multicast Forwarding Table Version 2 Register 7918 * -------------------------------------------------------------- 7919 * The RMFT_V2 register is used to configure and query the multicast table. 7920 */ 7921 #define MLXSW_REG_RMFT2_ID 0x8027 7922 #define MLXSW_REG_RMFT2_LEN 0x174 7923 7924 MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN); 7925 7926 /* reg_rmft2_v 7927 * Valid 7928 * Access: RW 7929 */ 7930 MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1); 7931 7932 enum mlxsw_reg_rmft2_type { 7933 MLXSW_REG_RMFT2_TYPE_IPV4, 7934 MLXSW_REG_RMFT2_TYPE_IPV6 7935 }; 7936 7937 /* reg_rmft2_type 7938 * Access: Index 7939 */ 7940 MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2); 7941 7942 enum mlxsw_sp_reg_rmft2_op { 7943 /* For Write: 7944 * Write operation. Used to write a new entry to the table. All RW 7945 * fields are relevant for new entry. Activity bit is set for new 7946 * entries - Note write with v (Valid) 0 will delete the entry. 7947 * For Query: 7948 * Read operation 7949 */ 7950 MLXSW_REG_RMFT2_OP_READ_WRITE, 7951 }; 7952 7953 /* reg_rmft2_op 7954 * Operation. 7955 * Access: OP 7956 */ 7957 MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2); 7958 7959 /* reg_rmft2_a 7960 * Activity. Set for new entries. Set if a packet lookup has hit on the specific 7961 * entry. 7962 * Access: RO 7963 */ 7964 MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1); 7965 7966 /* reg_rmft2_offset 7967 * Offset within the multicast forwarding table to write to. 7968 * Access: Index 7969 */ 7970 MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16); 7971 7972 /* reg_rmft2_virtual_router 7973 * Virtual Router ID. Range from 0..cap_max_virtual_routers-1 7974 * Access: RW 7975 */ 7976 MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16); 7977 7978 enum mlxsw_reg_rmft2_irif_mask { 7979 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE, 7980 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE 7981 }; 7982 7983 /* reg_rmft2_irif_mask 7984 * Ingress RIF mask. 7985 * Access: RW 7986 */ 7987 MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1); 7988 7989 /* reg_rmft2_irif 7990 * Ingress RIF index. 7991 * Access: RW 7992 */ 7993 MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16); 7994 7995 /* reg_rmft2_dip{4,6} 7996 * Destination IPv4/6 address 7997 * Access: RW 7998 */ 7999 MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16); 8000 MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32); 8001 8002 /* reg_rmft2_dip{4,6}_mask 8003 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8004 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8005 * Access: RW 8006 */ 8007 MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16); 8008 MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32); 8009 8010 /* reg_rmft2_sip{4,6} 8011 * Source IPv4/6 address 8012 * Access: RW 8013 */ 8014 MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16); 8015 MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32); 8016 8017 /* reg_rmft2_sip{4,6}_mask 8018 * A bit that is set directs the TCAM to compare the corresponding bit in key. A 8019 * bit that is clear directs the TCAM to ignore the corresponding bit in key. 8020 * Access: RW 8021 */ 8022 MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16); 8023 MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32); 8024 8025 /* reg_rmft2_flexible_action_set 8026 * ACL action set. The only supported action types in this field and in any 8027 * action-set pointed from here are as follows: 8028 * 00h: ACTION_NULL 8029 * 01h: ACTION_MAC_TTL, only TTL configuration is supported. 8030 * 03h: ACTION_TRAP 8031 * 06h: ACTION_QOS 8032 * 08h: ACTION_POLICING_MONITORING 8033 * 10h: ACTION_ROUTER_MC 8034 * Access: RW 8035 */ 8036 MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80, 8037 MLXSW_REG_FLEX_ACTION_SET_LEN); 8038 8039 static inline void 8040 mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset, 8041 u16 virtual_router, 8042 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8043 const char *flex_action_set) 8044 { 8045 MLXSW_REG_ZERO(rmft2, payload); 8046 mlxsw_reg_rmft2_v_set(payload, v); 8047 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE); 8048 mlxsw_reg_rmft2_offset_set(payload, offset); 8049 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router); 8050 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask); 8051 mlxsw_reg_rmft2_irif_set(payload, irif); 8052 if (flex_action_set) 8053 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload, 8054 flex_action_set); 8055 } 8056 8057 static inline void 8058 mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8059 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8060 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask, 8061 const char *flexible_action_set) 8062 { 8063 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8064 irif_mask, irif, flexible_action_set); 8065 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4); 8066 mlxsw_reg_rmft2_dip4_set(payload, dip4); 8067 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask); 8068 mlxsw_reg_rmft2_sip4_set(payload, sip4); 8069 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask); 8070 } 8071 8072 static inline void 8073 mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router, 8074 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif, 8075 struct in6_addr dip6, struct in6_addr dip6_mask, 8076 struct in6_addr sip6, struct in6_addr sip6_mask, 8077 const char *flexible_action_set) 8078 { 8079 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router, 8080 irif_mask, irif, flexible_action_set); 8081 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6); 8082 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6); 8083 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask); 8084 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6); 8085 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask); 8086 } 8087 8088 /* MFCR - Management Fan Control Register 8089 * -------------------------------------- 8090 * This register controls the settings of the Fan Speed PWM mechanism. 8091 */ 8092 #define MLXSW_REG_MFCR_ID 0x9001 8093 #define MLXSW_REG_MFCR_LEN 0x08 8094 8095 MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN); 8096 8097 enum mlxsw_reg_mfcr_pwm_frequency { 8098 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00, 8099 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01, 8100 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02, 8101 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40, 8102 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41, 8103 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42, 8104 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43, 8105 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44, 8106 }; 8107 8108 /* reg_mfcr_pwm_frequency 8109 * Controls the frequency of the PWM signal. 8110 * Access: RW 8111 */ 8112 MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7); 8113 8114 #define MLXSW_MFCR_TACHOS_MAX 10 8115 8116 /* reg_mfcr_tacho_active 8117 * Indicates which of the tachometer is active (bit per tachometer). 8118 * Access: RO 8119 */ 8120 MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX); 8121 8122 #define MLXSW_MFCR_PWMS_MAX 5 8123 8124 /* reg_mfcr_pwm_active 8125 * Indicates which of the PWM control is active (bit per PWM). 8126 * Access: RO 8127 */ 8128 MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX); 8129 8130 static inline void 8131 mlxsw_reg_mfcr_pack(char *payload, 8132 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency) 8133 { 8134 MLXSW_REG_ZERO(mfcr, payload); 8135 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency); 8136 } 8137 8138 static inline void 8139 mlxsw_reg_mfcr_unpack(char *payload, 8140 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency, 8141 u16 *p_tacho_active, u8 *p_pwm_active) 8142 { 8143 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload); 8144 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload); 8145 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload); 8146 } 8147 8148 /* MFSC - Management Fan Speed Control Register 8149 * -------------------------------------------- 8150 * This register controls the settings of the Fan Speed PWM mechanism. 8151 */ 8152 #define MLXSW_REG_MFSC_ID 0x9002 8153 #define MLXSW_REG_MFSC_LEN 0x08 8154 8155 MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN); 8156 8157 /* reg_mfsc_pwm 8158 * Fan pwm to control / monitor. 8159 * Access: Index 8160 */ 8161 MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3); 8162 8163 /* reg_mfsc_pwm_duty_cycle 8164 * Controls the duty cycle of the PWM. Value range from 0..255 to 8165 * represent duty cycle of 0%...100%. 8166 * Access: RW 8167 */ 8168 MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8); 8169 8170 static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm, 8171 u8 pwm_duty_cycle) 8172 { 8173 MLXSW_REG_ZERO(mfsc, payload); 8174 mlxsw_reg_mfsc_pwm_set(payload, pwm); 8175 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle); 8176 } 8177 8178 /* MFSM - Management Fan Speed Measurement 8179 * --------------------------------------- 8180 * This register controls the settings of the Tacho measurements and 8181 * enables reading the Tachometer measurements. 8182 */ 8183 #define MLXSW_REG_MFSM_ID 0x9003 8184 #define MLXSW_REG_MFSM_LEN 0x08 8185 8186 MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN); 8187 8188 /* reg_mfsm_tacho 8189 * Fan tachometer index. 8190 * Access: Index 8191 */ 8192 MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4); 8193 8194 /* reg_mfsm_rpm 8195 * Fan speed (round per minute). 8196 * Access: RO 8197 */ 8198 MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16); 8199 8200 static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho) 8201 { 8202 MLXSW_REG_ZERO(mfsm, payload); 8203 mlxsw_reg_mfsm_tacho_set(payload, tacho); 8204 } 8205 8206 /* MFSL - Management Fan Speed Limit Register 8207 * ------------------------------------------ 8208 * The Fan Speed Limit register is used to configure the fan speed 8209 * event / interrupt notification mechanism. Fan speed threshold are 8210 * defined for both under-speed and over-speed. 8211 */ 8212 #define MLXSW_REG_MFSL_ID 0x9004 8213 #define MLXSW_REG_MFSL_LEN 0x0C 8214 8215 MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN); 8216 8217 /* reg_mfsl_tacho 8218 * Fan tachometer index. 8219 * Access: Index 8220 */ 8221 MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4); 8222 8223 /* reg_mfsl_tach_min 8224 * Tachometer minimum value (minimum RPM). 8225 * Access: RW 8226 */ 8227 MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16); 8228 8229 /* reg_mfsl_tach_max 8230 * Tachometer maximum value (maximum RPM). 8231 * Access: RW 8232 */ 8233 MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16); 8234 8235 static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho, 8236 u16 tach_min, u16 tach_max) 8237 { 8238 MLXSW_REG_ZERO(mfsl, payload); 8239 mlxsw_reg_mfsl_tacho_set(payload, tacho); 8240 mlxsw_reg_mfsl_tach_min_set(payload, tach_min); 8241 mlxsw_reg_mfsl_tach_max_set(payload, tach_max); 8242 } 8243 8244 static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho, 8245 u16 *p_tach_min, u16 *p_tach_max) 8246 { 8247 if (p_tach_min) 8248 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload); 8249 8250 if (p_tach_max) 8251 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload); 8252 } 8253 8254 /* FORE - Fan Out of Range Event Register 8255 * -------------------------------------- 8256 * This register reports the status of the controlled fans compared to the 8257 * range defined by the MFSL register. 8258 */ 8259 #define MLXSW_REG_FORE_ID 0x9007 8260 #define MLXSW_REG_FORE_LEN 0x0C 8261 8262 MLXSW_REG_DEFINE(fore, MLXSW_REG_FORE_ID, MLXSW_REG_FORE_LEN); 8263 8264 /* fan_under_limit 8265 * Fan speed is below the low limit defined in MFSL register. Each bit relates 8266 * to a single tachometer and indicates the specific tachometer reading is 8267 * below the threshold. 8268 * Access: RO 8269 */ 8270 MLXSW_ITEM32(reg, fore, fan_under_limit, 0x00, 16, 10); 8271 8272 static inline void mlxsw_reg_fore_unpack(char *payload, u8 tacho, 8273 bool *fault) 8274 { 8275 u16 limit; 8276 8277 if (fault) { 8278 limit = mlxsw_reg_fore_fan_under_limit_get(payload); 8279 *fault = limit & BIT(tacho); 8280 } 8281 } 8282 8283 /* MTCAP - Management Temperature Capabilities 8284 * ------------------------------------------- 8285 * This register exposes the capabilities of the device and 8286 * system temperature sensing. 8287 */ 8288 #define MLXSW_REG_MTCAP_ID 0x9009 8289 #define MLXSW_REG_MTCAP_LEN 0x08 8290 8291 MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN); 8292 8293 /* reg_mtcap_sensor_count 8294 * Number of sensors supported by the device. 8295 * This includes the QSFP module sensors (if exists in the QSFP module). 8296 * Access: RO 8297 */ 8298 MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7); 8299 8300 /* MTMP - Management Temperature 8301 * ----------------------------- 8302 * This register controls the settings of the temperature measurements 8303 * and enables reading the temperature measurements. Note that temperature 8304 * is in 0.125 degrees Celsius. 8305 */ 8306 #define MLXSW_REG_MTMP_ID 0x900A 8307 #define MLXSW_REG_MTMP_LEN 0x20 8308 8309 MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN); 8310 8311 #define MLXSW_REG_MTMP_MODULE_INDEX_MIN 64 8312 #define MLXSW_REG_MTMP_GBOX_INDEX_MIN 256 8313 /* reg_mtmp_sensor_index 8314 * Sensors index to access. 8315 * 64-127 of sensor_index are mapped to the SFP+/QSFP modules sequentially 8316 * (module 0 is mapped to sensor_index 64). 8317 * Access: Index 8318 */ 8319 MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 12); 8320 8321 /* Convert to milli degrees Celsius */ 8322 #define MLXSW_REG_MTMP_TEMP_TO_MC(val) ({ typeof(val) v_ = (val); \ 8323 ((v_) >= 0) ? ((v_) * 125) : \ 8324 ((s16)((GENMASK(15, 0) + (v_) + 1) \ 8325 * 125)); }) 8326 8327 /* reg_mtmp_temperature 8328 * Temperature reading from the sensor. Reading is in 0.125 Celsius 8329 * degrees units. 8330 * Access: RO 8331 */ 8332 MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16); 8333 8334 /* reg_mtmp_mte 8335 * Max Temperature Enable - enables measuring the max temperature on a sensor. 8336 * Access: RW 8337 */ 8338 MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1); 8339 8340 /* reg_mtmp_mtr 8341 * Max Temperature Reset - clears the value of the max temperature register. 8342 * Access: WO 8343 */ 8344 MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1); 8345 8346 /* reg_mtmp_max_temperature 8347 * The highest measured temperature from the sensor. 8348 * When the bit mte is cleared, the field max_temperature is reserved. 8349 * Access: RO 8350 */ 8351 MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16); 8352 8353 /* reg_mtmp_tee 8354 * Temperature Event Enable. 8355 * 0 - Do not generate event 8356 * 1 - Generate event 8357 * 2 - Generate single event 8358 * Access: RW 8359 */ 8360 MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2); 8361 8362 #define MLXSW_REG_MTMP_THRESH_HI 0x348 /* 105 Celsius */ 8363 8364 /* reg_mtmp_temperature_threshold_hi 8365 * High threshold for Temperature Warning Event. In 0.125 Celsius. 8366 * Access: RW 8367 */ 8368 MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16); 8369 8370 /* reg_mtmp_temperature_threshold_lo 8371 * Low threshold for Temperature Warning Event. In 0.125 Celsius. 8372 * Access: RW 8373 */ 8374 MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16); 8375 8376 #define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8 8377 8378 /* reg_mtmp_sensor_name 8379 * Sensor Name 8380 * Access: RO 8381 */ 8382 MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE); 8383 8384 static inline void mlxsw_reg_mtmp_pack(char *payload, u16 sensor_index, 8385 bool max_temp_enable, 8386 bool max_temp_reset) 8387 { 8388 MLXSW_REG_ZERO(mtmp, payload); 8389 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index); 8390 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable); 8391 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset); 8392 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload, 8393 MLXSW_REG_MTMP_THRESH_HI); 8394 } 8395 8396 static inline void mlxsw_reg_mtmp_unpack(char *payload, int *p_temp, 8397 int *p_max_temp, char *sensor_name) 8398 { 8399 s16 temp; 8400 8401 if (p_temp) { 8402 temp = mlxsw_reg_mtmp_temperature_get(payload); 8403 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8404 } 8405 if (p_max_temp) { 8406 temp = mlxsw_reg_mtmp_max_temperature_get(payload); 8407 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp); 8408 } 8409 if (sensor_name) 8410 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name); 8411 } 8412 8413 /* MTBR - Management Temperature Bulk Register 8414 * ------------------------------------------- 8415 * This register is used for bulk temperature reading. 8416 */ 8417 #define MLXSW_REG_MTBR_ID 0x900F 8418 #define MLXSW_REG_MTBR_BASE_LEN 0x10 /* base length, without records */ 8419 #define MLXSW_REG_MTBR_REC_LEN 0x04 /* record length */ 8420 #define MLXSW_REG_MTBR_REC_MAX_COUNT 47 /* firmware limitation */ 8421 #define MLXSW_REG_MTBR_LEN (MLXSW_REG_MTBR_BASE_LEN + \ 8422 MLXSW_REG_MTBR_REC_LEN * \ 8423 MLXSW_REG_MTBR_REC_MAX_COUNT) 8424 8425 MLXSW_REG_DEFINE(mtbr, MLXSW_REG_MTBR_ID, MLXSW_REG_MTBR_LEN); 8426 8427 /* reg_mtbr_base_sensor_index 8428 * Base sensors index to access (0 - ASIC sensor, 1-63 - ambient sensors, 8429 * 64-127 are mapped to the SFP+/QSFP modules sequentially). 8430 * Access: Index 8431 */ 8432 MLXSW_ITEM32(reg, mtbr, base_sensor_index, 0x00, 0, 12); 8433 8434 /* reg_mtbr_num_rec 8435 * Request: Number of records to read 8436 * Response: Number of records read 8437 * See above description for more details. 8438 * Range 1..255 8439 * Access: RW 8440 */ 8441 MLXSW_ITEM32(reg, mtbr, num_rec, 0x04, 0, 8); 8442 8443 /* reg_mtbr_rec_max_temp 8444 * The highest measured temperature from the sensor. 8445 * When the bit mte is cleared, the field max_temperature is reserved. 8446 * Access: RO 8447 */ 8448 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_max_temp, MLXSW_REG_MTBR_BASE_LEN, 16, 8449 16, MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8450 8451 /* reg_mtbr_rec_temp 8452 * Temperature reading from the sensor. Reading is in 0..125 Celsius 8453 * degrees units. 8454 * Access: RO 8455 */ 8456 MLXSW_ITEM32_INDEXED(reg, mtbr, rec_temp, MLXSW_REG_MTBR_BASE_LEN, 0, 16, 8457 MLXSW_REG_MTBR_REC_LEN, 0x00, false); 8458 8459 static inline void mlxsw_reg_mtbr_pack(char *payload, u16 base_sensor_index, 8460 u8 num_rec) 8461 { 8462 MLXSW_REG_ZERO(mtbr, payload); 8463 mlxsw_reg_mtbr_base_sensor_index_set(payload, base_sensor_index); 8464 mlxsw_reg_mtbr_num_rec_set(payload, num_rec); 8465 } 8466 8467 /* Error codes from temperatute reading */ 8468 enum mlxsw_reg_mtbr_temp_status { 8469 MLXSW_REG_MTBR_NO_CONN = 0x8000, 8470 MLXSW_REG_MTBR_NO_TEMP_SENS = 0x8001, 8471 MLXSW_REG_MTBR_INDEX_NA = 0x8002, 8472 MLXSW_REG_MTBR_BAD_SENS_INFO = 0x8003, 8473 }; 8474 8475 /* Base index for reading modules temperature */ 8476 #define MLXSW_REG_MTBR_BASE_MODULE_INDEX 64 8477 8478 static inline void mlxsw_reg_mtbr_temp_unpack(char *payload, int rec_ind, 8479 u16 *p_temp, u16 *p_max_temp) 8480 { 8481 if (p_temp) 8482 *p_temp = mlxsw_reg_mtbr_rec_temp_get(payload, rec_ind); 8483 if (p_max_temp) 8484 *p_max_temp = mlxsw_reg_mtbr_rec_max_temp_get(payload, rec_ind); 8485 } 8486 8487 /* MCIA - Management Cable Info Access 8488 * ----------------------------------- 8489 * MCIA register is used to access the SFP+ and QSFP connector's EPROM. 8490 */ 8491 8492 #define MLXSW_REG_MCIA_ID 0x9014 8493 #define MLXSW_REG_MCIA_LEN 0x40 8494 8495 MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN); 8496 8497 /* reg_mcia_l 8498 * Lock bit. Setting this bit will lock the access to the specific 8499 * cable. Used for updating a full page in a cable EPROM. Any access 8500 * other then subsequence writes will fail while the port is locked. 8501 * Access: RW 8502 */ 8503 MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1); 8504 8505 /* reg_mcia_module 8506 * Module number. 8507 * Access: Index 8508 */ 8509 MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8); 8510 8511 /* reg_mcia_status 8512 * Module status. 8513 * Access: RO 8514 */ 8515 MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8); 8516 8517 /* reg_mcia_i2c_device_address 8518 * I2C device address. 8519 * Access: RW 8520 */ 8521 MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8); 8522 8523 /* reg_mcia_page_number 8524 * Page number. 8525 * Access: RW 8526 */ 8527 MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8); 8528 8529 /* reg_mcia_device_address 8530 * Device address. 8531 * Access: RW 8532 */ 8533 MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16); 8534 8535 /* reg_mcia_size 8536 * Number of bytes to read/write (up to 48 bytes). 8537 * Access: RW 8538 */ 8539 MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16); 8540 8541 #define MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH 256 8542 #define MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH 128 8543 #define MLXSW_REG_MCIA_EEPROM_SIZE 48 8544 #define MLXSW_REG_MCIA_I2C_ADDR_LOW 0x50 8545 #define MLXSW_REG_MCIA_I2C_ADDR_HIGH 0x51 8546 #define MLXSW_REG_MCIA_PAGE0_LO_OFF 0xa0 8547 #define MLXSW_REG_MCIA_TH_ITEM_SIZE 2 8548 #define MLXSW_REG_MCIA_TH_PAGE_NUM 3 8549 #define MLXSW_REG_MCIA_PAGE0_LO 0 8550 #define MLXSW_REG_MCIA_TH_PAGE_OFF 0x80 8551 8552 enum mlxsw_reg_mcia_eeprom_module_info_rev_id { 8553 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_UNSPC = 0x00, 8554 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8436 = 0x01, 8555 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID_8636 = 0x03, 8556 }; 8557 8558 enum mlxsw_reg_mcia_eeprom_module_info_id { 8559 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_SFP = 0x03, 8560 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP = 0x0C, 8561 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_PLUS = 0x0D, 8562 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP28 = 0x11, 8563 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID_QSFP_DD = 0x18, 8564 }; 8565 8566 enum mlxsw_reg_mcia_eeprom_module_info { 8567 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_ID, 8568 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_REV_ID, 8569 MLXSW_REG_MCIA_EEPROM_MODULE_INFO_SIZE, 8570 }; 8571 8572 /* reg_mcia_eeprom 8573 * Bytes to read/write. 8574 * Access: RW 8575 */ 8576 MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_REG_MCIA_EEPROM_SIZE); 8577 8578 /* This is used to access the optional upper pages (1-3) in the QSFP+ 8579 * memory map. Page 1 is available on offset 256 through 383, page 2 - 8580 * on offset 384 through 511, page 3 - on offset 512 through 639. 8581 */ 8582 #define MLXSW_REG_MCIA_PAGE_GET(off) (((off) - \ 8583 MLXSW_REG_MCIA_EEPROM_PAGE_LENGTH) / \ 8584 MLXSW_REG_MCIA_EEPROM_UP_PAGE_LENGTH + 1) 8585 8586 static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock, 8587 u8 page_number, u16 device_addr, 8588 u8 size, u8 i2c_device_addr) 8589 { 8590 MLXSW_REG_ZERO(mcia, payload); 8591 mlxsw_reg_mcia_module_set(payload, module); 8592 mlxsw_reg_mcia_l_set(payload, lock); 8593 mlxsw_reg_mcia_page_number_set(payload, page_number); 8594 mlxsw_reg_mcia_device_address_set(payload, device_addr); 8595 mlxsw_reg_mcia_size_set(payload, size); 8596 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr); 8597 } 8598 8599 /* MPAT - Monitoring Port Analyzer Table 8600 * ------------------------------------- 8601 * MPAT Register is used to query and configure the Switch PortAnalyzer Table. 8602 * For an enabled analyzer, all fields except e (enable) cannot be modified. 8603 */ 8604 #define MLXSW_REG_MPAT_ID 0x901A 8605 #define MLXSW_REG_MPAT_LEN 0x78 8606 8607 MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN); 8608 8609 /* reg_mpat_pa_id 8610 * Port Analyzer ID. 8611 * Access: Index 8612 */ 8613 MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4); 8614 8615 /* reg_mpat_system_port 8616 * A unique port identifier for the final destination of the packet. 8617 * Access: RW 8618 */ 8619 MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16); 8620 8621 /* reg_mpat_e 8622 * Enable. Indicating the Port Analyzer is enabled. 8623 * Access: RW 8624 */ 8625 MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1); 8626 8627 /* reg_mpat_qos 8628 * Quality Of Service Mode. 8629 * 0: CONFIGURED - QoS parameters (Switch Priority, and encapsulation 8630 * PCP, DEI, DSCP or VL) are configured. 8631 * 1: MAINTAIN - QoS parameters (Switch Priority, Color) are the 8632 * same as in the original packet that has triggered the mirroring. For 8633 * SPAN also the pcp,dei are maintained. 8634 * Access: RW 8635 */ 8636 MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1); 8637 8638 /* reg_mpat_be 8639 * Best effort mode. Indicates mirroring traffic should not cause packet 8640 * drop or back pressure, but will discard the mirrored packets. Mirrored 8641 * packets will be forwarded on a best effort manner. 8642 * 0: Do not discard mirrored packets 8643 * 1: Discard mirrored packets if causing congestion 8644 * Access: RW 8645 */ 8646 MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1); 8647 8648 enum mlxsw_reg_mpat_span_type { 8649 /* Local SPAN Ethernet. 8650 * The original packet is not encapsulated. 8651 */ 8652 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0, 8653 8654 /* Remote SPAN Ethernet VLAN. 8655 * The packet is forwarded to the monitoring port on the monitoring 8656 * VLAN. 8657 */ 8658 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH = 0x1, 8659 8660 /* Encapsulated Remote SPAN Ethernet L3 GRE. 8661 * The packet is encapsulated with GRE header. 8662 */ 8663 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3, 8664 }; 8665 8666 /* reg_mpat_span_type 8667 * SPAN type. 8668 * Access: RW 8669 */ 8670 MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4); 8671 8672 /* Remote SPAN - Ethernet VLAN 8673 * - - - - - - - - - - - - - - 8674 */ 8675 8676 /* reg_mpat_eth_rspan_vid 8677 * Encapsulation header VLAN ID. 8678 * Access: RW 8679 */ 8680 MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12); 8681 8682 /* Encapsulated Remote SPAN - Ethernet L2 8683 * - - - - - - - - - - - - - - - - - - - 8684 */ 8685 8686 enum mlxsw_reg_mpat_eth_rspan_version { 8687 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15, 8688 }; 8689 8690 /* reg_mpat_eth_rspan_version 8691 * RSPAN mirror header version. 8692 * Access: RW 8693 */ 8694 MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4); 8695 8696 /* reg_mpat_eth_rspan_mac 8697 * Destination MAC address. 8698 * Access: RW 8699 */ 8700 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6); 8701 8702 /* reg_mpat_eth_rspan_tp 8703 * Tag Packet. Indicates whether the mirroring header should be VLAN tagged. 8704 * Access: RW 8705 */ 8706 MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1); 8707 8708 /* Encapsulated Remote SPAN - Ethernet L3 8709 * - - - - - - - - - - - - - - - - - - - 8710 */ 8711 8712 enum mlxsw_reg_mpat_eth_rspan_protocol { 8713 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4, 8714 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6, 8715 }; 8716 8717 /* reg_mpat_eth_rspan_protocol 8718 * SPAN encapsulation protocol. 8719 * Access: RW 8720 */ 8721 MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4); 8722 8723 /* reg_mpat_eth_rspan_ttl 8724 * Encapsulation header Time-to-Live/HopLimit. 8725 * Access: RW 8726 */ 8727 MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8); 8728 8729 /* reg_mpat_eth_rspan_smac 8730 * Source MAC address 8731 * Access: RW 8732 */ 8733 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6); 8734 8735 /* reg_mpat_eth_rspan_dip* 8736 * Destination IP address. The IP version is configured by protocol. 8737 * Access: RW 8738 */ 8739 MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32); 8740 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16); 8741 8742 /* reg_mpat_eth_rspan_sip* 8743 * Source IP address. The IP version is configured by protocol. 8744 * Access: RW 8745 */ 8746 MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32); 8747 MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16); 8748 8749 static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id, 8750 u16 system_port, bool e, 8751 enum mlxsw_reg_mpat_span_type span_type) 8752 { 8753 MLXSW_REG_ZERO(mpat, payload); 8754 mlxsw_reg_mpat_pa_id_set(payload, pa_id); 8755 mlxsw_reg_mpat_system_port_set(payload, system_port); 8756 mlxsw_reg_mpat_e_set(payload, e); 8757 mlxsw_reg_mpat_qos_set(payload, 1); 8758 mlxsw_reg_mpat_be_set(payload, 1); 8759 mlxsw_reg_mpat_span_type_set(payload, span_type); 8760 } 8761 8762 static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid) 8763 { 8764 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid); 8765 } 8766 8767 static inline void 8768 mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload, 8769 enum mlxsw_reg_mpat_eth_rspan_version version, 8770 const char *mac, 8771 bool tp) 8772 { 8773 mlxsw_reg_mpat_eth_rspan_version_set(payload, version); 8774 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac); 8775 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp); 8776 } 8777 8778 static inline void 8779 mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl, 8780 const char *smac, 8781 u32 sip, u32 dip) 8782 { 8783 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8784 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8785 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8786 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4); 8787 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip); 8788 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip); 8789 } 8790 8791 static inline void 8792 mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl, 8793 const char *smac, 8794 struct in6_addr sip, struct in6_addr dip) 8795 { 8796 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl); 8797 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac); 8798 mlxsw_reg_mpat_eth_rspan_protocol_set(payload, 8799 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6); 8800 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip); 8801 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip); 8802 } 8803 8804 /* MPAR - Monitoring Port Analyzer Register 8805 * ---------------------------------------- 8806 * MPAR register is used to query and configure the port analyzer port mirroring 8807 * properties. 8808 */ 8809 #define MLXSW_REG_MPAR_ID 0x901B 8810 #define MLXSW_REG_MPAR_LEN 0x0C 8811 8812 MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN); 8813 8814 /* reg_mpar_local_port 8815 * The local port to mirror the packets from. 8816 * Access: Index 8817 */ 8818 MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8); 8819 8820 enum mlxsw_reg_mpar_i_e { 8821 MLXSW_REG_MPAR_TYPE_EGRESS, 8822 MLXSW_REG_MPAR_TYPE_INGRESS, 8823 }; 8824 8825 /* reg_mpar_i_e 8826 * Ingress/Egress 8827 * Access: Index 8828 */ 8829 MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4); 8830 8831 /* reg_mpar_enable 8832 * Enable mirroring 8833 * By default, port mirroring is disabled for all ports. 8834 * Access: RW 8835 */ 8836 MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1); 8837 8838 /* reg_mpar_pa_id 8839 * Port Analyzer ID. 8840 * Access: RW 8841 */ 8842 MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4); 8843 8844 static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port, 8845 enum mlxsw_reg_mpar_i_e i_e, 8846 bool enable, u8 pa_id) 8847 { 8848 MLXSW_REG_ZERO(mpar, payload); 8849 mlxsw_reg_mpar_local_port_set(payload, local_port); 8850 mlxsw_reg_mpar_enable_set(payload, enable); 8851 mlxsw_reg_mpar_i_e_set(payload, i_e); 8852 mlxsw_reg_mpar_pa_id_set(payload, pa_id); 8853 } 8854 8855 /* MGIR - Management General Information Register 8856 * ---------------------------------------------- 8857 * MGIR register allows software to query the hardware and firmware general 8858 * information. 8859 */ 8860 #define MLXSW_REG_MGIR_ID 0x9020 8861 #define MLXSW_REG_MGIR_LEN 0x9C 8862 8863 MLXSW_REG_DEFINE(mgir, MLXSW_REG_MGIR_ID, MLXSW_REG_MGIR_LEN); 8864 8865 /* reg_mgir_hw_info_device_hw_revision 8866 * Access: RO 8867 */ 8868 MLXSW_ITEM32(reg, mgir, hw_info_device_hw_revision, 0x0, 16, 16); 8869 8870 #define MLXSW_REG_MGIR_FW_INFO_PSID_SIZE 16 8871 8872 /* reg_mgir_fw_info_psid 8873 * PSID (ASCII string). 8874 * Access: RO 8875 */ 8876 MLXSW_ITEM_BUF(reg, mgir, fw_info_psid, 0x30, MLXSW_REG_MGIR_FW_INFO_PSID_SIZE); 8877 8878 /* reg_mgir_fw_info_extended_major 8879 * Access: RO 8880 */ 8881 MLXSW_ITEM32(reg, mgir, fw_info_extended_major, 0x44, 0, 32); 8882 8883 /* reg_mgir_fw_info_extended_minor 8884 * Access: RO 8885 */ 8886 MLXSW_ITEM32(reg, mgir, fw_info_extended_minor, 0x48, 0, 32); 8887 8888 /* reg_mgir_fw_info_extended_sub_minor 8889 * Access: RO 8890 */ 8891 MLXSW_ITEM32(reg, mgir, fw_info_extended_sub_minor, 0x4C, 0, 32); 8892 8893 static inline void mlxsw_reg_mgir_pack(char *payload) 8894 { 8895 MLXSW_REG_ZERO(mgir, payload); 8896 } 8897 8898 static inline void 8899 mlxsw_reg_mgir_unpack(char *payload, u32 *hw_rev, char *fw_info_psid, 8900 u32 *fw_major, u32 *fw_minor, u32 *fw_sub_minor) 8901 { 8902 *hw_rev = mlxsw_reg_mgir_hw_info_device_hw_revision_get(payload); 8903 mlxsw_reg_mgir_fw_info_psid_memcpy_from(payload, fw_info_psid); 8904 *fw_major = mlxsw_reg_mgir_fw_info_extended_major_get(payload); 8905 *fw_minor = mlxsw_reg_mgir_fw_info_extended_minor_get(payload); 8906 *fw_sub_minor = mlxsw_reg_mgir_fw_info_extended_sub_minor_get(payload); 8907 } 8908 8909 /* MRSR - Management Reset and Shutdown Register 8910 * --------------------------------------------- 8911 * MRSR register is used to reset or shutdown the switch or 8912 * the entire system (when applicable). 8913 */ 8914 #define MLXSW_REG_MRSR_ID 0x9023 8915 #define MLXSW_REG_MRSR_LEN 0x08 8916 8917 MLXSW_REG_DEFINE(mrsr, MLXSW_REG_MRSR_ID, MLXSW_REG_MRSR_LEN); 8918 8919 /* reg_mrsr_command 8920 * Reset/shutdown command 8921 * 0 - do nothing 8922 * 1 - software reset 8923 * Access: WO 8924 */ 8925 MLXSW_ITEM32(reg, mrsr, command, 0x00, 0, 4); 8926 8927 static inline void mlxsw_reg_mrsr_pack(char *payload) 8928 { 8929 MLXSW_REG_ZERO(mrsr, payload); 8930 mlxsw_reg_mrsr_command_set(payload, 1); 8931 } 8932 8933 /* MLCR - Management LED Control Register 8934 * -------------------------------------- 8935 * Controls the system LEDs. 8936 */ 8937 #define MLXSW_REG_MLCR_ID 0x902B 8938 #define MLXSW_REG_MLCR_LEN 0x0C 8939 8940 MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN); 8941 8942 /* reg_mlcr_local_port 8943 * Local port number. 8944 * Access: RW 8945 */ 8946 MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8); 8947 8948 #define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF 8949 8950 /* reg_mlcr_beacon_duration 8951 * Duration of the beacon to be active, in seconds. 8952 * 0x0 - Will turn off the beacon. 8953 * 0xFFFF - Will turn on the beacon until explicitly turned off. 8954 * Access: RW 8955 */ 8956 MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16); 8957 8958 /* reg_mlcr_beacon_remain 8959 * Remaining duration of the beacon, in seconds. 8960 * 0xFFFF indicates an infinite amount of time. 8961 * Access: RO 8962 */ 8963 MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16); 8964 8965 static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port, 8966 bool active) 8967 { 8968 MLXSW_REG_ZERO(mlcr, payload); 8969 mlxsw_reg_mlcr_local_port_set(payload, local_port); 8970 mlxsw_reg_mlcr_beacon_duration_set(payload, active ? 8971 MLXSW_REG_MLCR_DURATION_MAX : 0); 8972 } 8973 8974 /* MTPPS - Management Pulse Per Second Register 8975 * -------------------------------------------- 8976 * This register provides the device PPS capabilities, configure the PPS in and 8977 * out modules and holds the PPS in time stamp. 8978 */ 8979 #define MLXSW_REG_MTPPS_ID 0x9053 8980 #define MLXSW_REG_MTPPS_LEN 0x3C 8981 8982 MLXSW_REG_DEFINE(mtpps, MLXSW_REG_MTPPS_ID, MLXSW_REG_MTPPS_LEN); 8983 8984 /* reg_mtpps_enable 8985 * Enables the PPS functionality the specific pin. 8986 * A boolean variable. 8987 * Access: RW 8988 */ 8989 MLXSW_ITEM32(reg, mtpps, enable, 0x20, 31, 1); 8990 8991 enum mlxsw_reg_mtpps_pin_mode { 8992 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN = 0x2, 8993 }; 8994 8995 /* reg_mtpps_pin_mode 8996 * Pin mode to be used. The mode must comply with the supported modes of the 8997 * requested pin. 8998 * Access: RW 8999 */ 9000 MLXSW_ITEM32(reg, mtpps, pin_mode, 0x20, 8, 4); 9001 9002 #define MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN 7 9003 9004 /* reg_mtpps_pin 9005 * Pin to be configured or queried out of the supported pins. 9006 * Access: Index 9007 */ 9008 MLXSW_ITEM32(reg, mtpps, pin, 0x20, 0, 8); 9009 9010 /* reg_mtpps_time_stamp 9011 * When pin_mode = pps_in, the latched device time when it was triggered from 9012 * the external GPIO pin. 9013 * When pin_mode = pps_out or virtual_pin or pps_out_and_virtual_pin, the target 9014 * time to generate next output signal. 9015 * Time is in units of device clock. 9016 * Access: RW 9017 */ 9018 MLXSW_ITEM64(reg, mtpps, time_stamp, 0x28, 0, 64); 9019 9020 static inline void 9021 mlxsw_reg_mtpps_vpin_pack(char *payload, u64 time_stamp) 9022 { 9023 MLXSW_REG_ZERO(mtpps, payload); 9024 mlxsw_reg_mtpps_pin_set(payload, MLXSW_REG_MTPPS_PIN_SP_VIRTUAL_PIN); 9025 mlxsw_reg_mtpps_pin_mode_set(payload, 9026 MLXSW_REG_MTPPS_PIN_MODE_VIRTUAL_PIN); 9027 mlxsw_reg_mtpps_enable_set(payload, true); 9028 mlxsw_reg_mtpps_time_stamp_set(payload, time_stamp); 9029 } 9030 9031 /* MTUTC - Management UTC Register 9032 * ------------------------------- 9033 * Configures the HW UTC counter. 9034 */ 9035 #define MLXSW_REG_MTUTC_ID 0x9055 9036 #define MLXSW_REG_MTUTC_LEN 0x1C 9037 9038 MLXSW_REG_DEFINE(mtutc, MLXSW_REG_MTUTC_ID, MLXSW_REG_MTUTC_LEN); 9039 9040 enum mlxsw_reg_mtutc_operation { 9041 MLXSW_REG_MTUTC_OPERATION_SET_TIME_AT_NEXT_SEC = 0, 9042 MLXSW_REG_MTUTC_OPERATION_ADJUST_FREQ = 3, 9043 }; 9044 9045 /* reg_mtutc_operation 9046 * Operation. 9047 * Access: OP 9048 */ 9049 MLXSW_ITEM32(reg, mtutc, operation, 0x00, 0, 4); 9050 9051 /* reg_mtutc_freq_adjustment 9052 * Frequency adjustment: Every PPS the HW frequency will be 9053 * adjusted by this value. Units of HW clock, where HW counts 9054 * 10^9 HW clocks for 1 HW second. 9055 * Access: RW 9056 */ 9057 MLXSW_ITEM32(reg, mtutc, freq_adjustment, 0x04, 0, 32); 9058 9059 /* reg_mtutc_utc_sec 9060 * UTC seconds. 9061 * Access: WO 9062 */ 9063 MLXSW_ITEM32(reg, mtutc, utc_sec, 0x10, 0, 32); 9064 9065 static inline void 9066 mlxsw_reg_mtutc_pack(char *payload, enum mlxsw_reg_mtutc_operation oper, 9067 u32 freq_adj, u32 utc_sec) 9068 { 9069 MLXSW_REG_ZERO(mtutc, payload); 9070 mlxsw_reg_mtutc_operation_set(payload, oper); 9071 mlxsw_reg_mtutc_freq_adjustment_set(payload, freq_adj); 9072 mlxsw_reg_mtutc_utc_sec_set(payload, utc_sec); 9073 } 9074 9075 /* MCQI - Management Component Query Information 9076 * --------------------------------------------- 9077 * This register allows querying information about firmware components. 9078 */ 9079 #define MLXSW_REG_MCQI_ID 0x9061 9080 #define MLXSW_REG_MCQI_BASE_LEN 0x18 9081 #define MLXSW_REG_MCQI_CAP_LEN 0x14 9082 #define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN) 9083 9084 MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN); 9085 9086 /* reg_mcqi_component_index 9087 * Index of the accessed component. 9088 * Access: Index 9089 */ 9090 MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16); 9091 9092 enum mlxfw_reg_mcqi_info_type { 9093 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES, 9094 }; 9095 9096 /* reg_mcqi_info_type 9097 * Component properties set. 9098 * Access: RW 9099 */ 9100 MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5); 9101 9102 /* reg_mcqi_offset 9103 * The requested/returned data offset from the section start, given in bytes. 9104 * Must be DWORD aligned. 9105 * Access: RW 9106 */ 9107 MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32); 9108 9109 /* reg_mcqi_data_size 9110 * The requested/returned data size, given in bytes. If data_size is not DWORD 9111 * aligned, the last bytes are zero padded. 9112 * Access: RW 9113 */ 9114 MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16); 9115 9116 /* reg_mcqi_cap_max_component_size 9117 * Maximum size for this component, given in bytes. 9118 * Access: RO 9119 */ 9120 MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32); 9121 9122 /* reg_mcqi_cap_log_mcda_word_size 9123 * Log 2 of the access word size in bytes. Read and write access must be aligned 9124 * to the word size. Write access must be done for an integer number of words. 9125 * Access: RO 9126 */ 9127 MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4); 9128 9129 /* reg_mcqi_cap_mcda_max_write_size 9130 * Maximal write size for MCDA register 9131 * Access: RO 9132 */ 9133 MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16); 9134 9135 static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index) 9136 { 9137 MLXSW_REG_ZERO(mcqi, payload); 9138 mlxsw_reg_mcqi_component_index_set(payload, component_index); 9139 mlxsw_reg_mcqi_info_type_set(payload, 9140 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES); 9141 mlxsw_reg_mcqi_offset_set(payload, 0); 9142 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN); 9143 } 9144 9145 static inline void mlxsw_reg_mcqi_unpack(char *payload, 9146 u32 *p_cap_max_component_size, 9147 u8 *p_cap_log_mcda_word_size, 9148 u16 *p_cap_mcda_max_write_size) 9149 { 9150 *p_cap_max_component_size = 9151 mlxsw_reg_mcqi_cap_max_component_size_get(payload); 9152 *p_cap_log_mcda_word_size = 9153 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload); 9154 *p_cap_mcda_max_write_size = 9155 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload); 9156 } 9157 9158 /* MCC - Management Component Control 9159 * ---------------------------------- 9160 * Controls the firmware component and updates the FSM. 9161 */ 9162 #define MLXSW_REG_MCC_ID 0x9062 9163 #define MLXSW_REG_MCC_LEN 0x1C 9164 9165 MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN); 9166 9167 enum mlxsw_reg_mcc_instruction { 9168 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01, 9169 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02, 9170 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03, 9171 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04, 9172 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06, 9173 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08, 9174 }; 9175 9176 /* reg_mcc_instruction 9177 * Command to be executed by the FSM. 9178 * Applicable for write operation only. 9179 * Access: RW 9180 */ 9181 MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8); 9182 9183 /* reg_mcc_component_index 9184 * Index of the accessed component. Applicable only for commands that 9185 * refer to components. Otherwise, this field is reserved. 9186 * Access: Index 9187 */ 9188 MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16); 9189 9190 /* reg_mcc_update_handle 9191 * Token representing the current flow executed by the FSM. 9192 * Access: WO 9193 */ 9194 MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24); 9195 9196 /* reg_mcc_error_code 9197 * Indicates the successful completion of the instruction, or the reason it 9198 * failed 9199 * Access: RO 9200 */ 9201 MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8); 9202 9203 /* reg_mcc_control_state 9204 * Current FSM state 9205 * Access: RO 9206 */ 9207 MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4); 9208 9209 /* reg_mcc_component_size 9210 * Component size in bytes. Valid for UPDATE_COMPONENT instruction. Specifying 9211 * the size may shorten the update time. Value 0x0 means that size is 9212 * unspecified. 9213 * Access: WO 9214 */ 9215 MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32); 9216 9217 static inline void mlxsw_reg_mcc_pack(char *payload, 9218 enum mlxsw_reg_mcc_instruction instr, 9219 u16 component_index, u32 update_handle, 9220 u32 component_size) 9221 { 9222 MLXSW_REG_ZERO(mcc, payload); 9223 mlxsw_reg_mcc_instruction_set(payload, instr); 9224 mlxsw_reg_mcc_component_index_set(payload, component_index); 9225 mlxsw_reg_mcc_update_handle_set(payload, update_handle); 9226 mlxsw_reg_mcc_component_size_set(payload, component_size); 9227 } 9228 9229 static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle, 9230 u8 *p_error_code, u8 *p_control_state) 9231 { 9232 if (p_update_handle) 9233 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload); 9234 if (p_error_code) 9235 *p_error_code = mlxsw_reg_mcc_error_code_get(payload); 9236 if (p_control_state) 9237 *p_control_state = mlxsw_reg_mcc_control_state_get(payload); 9238 } 9239 9240 /* MCDA - Management Component Data Access 9241 * --------------------------------------- 9242 * This register allows reading and writing a firmware component. 9243 */ 9244 #define MLXSW_REG_MCDA_ID 0x9063 9245 #define MLXSW_REG_MCDA_BASE_LEN 0x10 9246 #define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80 9247 #define MLXSW_REG_MCDA_LEN \ 9248 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN) 9249 9250 MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN); 9251 9252 /* reg_mcda_update_handle 9253 * Token representing the current flow executed by the FSM. 9254 * Access: RW 9255 */ 9256 MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24); 9257 9258 /* reg_mcda_offset 9259 * Offset of accessed address relative to component start. Accesses must be in 9260 * accordance to log_mcda_word_size in MCQI reg. 9261 * Access: RW 9262 */ 9263 MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32); 9264 9265 /* reg_mcda_size 9266 * Size of the data accessed, given in bytes. 9267 * Access: RW 9268 */ 9269 MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16); 9270 9271 /* reg_mcda_data 9272 * Data block accessed. 9273 * Access: RW 9274 */ 9275 MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false); 9276 9277 static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle, 9278 u32 offset, u16 size, u8 *data) 9279 { 9280 int i; 9281 9282 MLXSW_REG_ZERO(mcda, payload); 9283 mlxsw_reg_mcda_update_handle_set(payload, update_handle); 9284 mlxsw_reg_mcda_offset_set(payload, offset); 9285 mlxsw_reg_mcda_size_set(payload, size); 9286 9287 for (i = 0; i < size / 4; i++) 9288 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]); 9289 } 9290 9291 /* MPSC - Monitoring Packet Sampling Configuration Register 9292 * -------------------------------------------------------- 9293 * MPSC Register is used to configure the Packet Sampling mechanism. 9294 */ 9295 #define MLXSW_REG_MPSC_ID 0x9080 9296 #define MLXSW_REG_MPSC_LEN 0x1C 9297 9298 MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN); 9299 9300 /* reg_mpsc_local_port 9301 * Local port number 9302 * Not supported for CPU port 9303 * Access: Index 9304 */ 9305 MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8); 9306 9307 /* reg_mpsc_e 9308 * Enable sampling on port local_port 9309 * Access: RW 9310 */ 9311 MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1); 9312 9313 #define MLXSW_REG_MPSC_RATE_MAX 3500000000UL 9314 9315 /* reg_mpsc_rate 9316 * Sampling rate = 1 out of rate packets (with randomization around 9317 * the point). Valid values are: 1 to MLXSW_REG_MPSC_RATE_MAX 9318 * Access: RW 9319 */ 9320 MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32); 9321 9322 static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e, 9323 u32 rate) 9324 { 9325 MLXSW_REG_ZERO(mpsc, payload); 9326 mlxsw_reg_mpsc_local_port_set(payload, local_port); 9327 mlxsw_reg_mpsc_e_set(payload, e); 9328 mlxsw_reg_mpsc_rate_set(payload, rate); 9329 } 9330 9331 /* MGPC - Monitoring General Purpose Counter Set Register 9332 * The MGPC register retrieves and sets the General Purpose Counter Set. 9333 */ 9334 #define MLXSW_REG_MGPC_ID 0x9081 9335 #define MLXSW_REG_MGPC_LEN 0x18 9336 9337 MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN); 9338 9339 /* reg_mgpc_counter_set_type 9340 * Counter set type. 9341 * Access: OP 9342 */ 9343 MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8); 9344 9345 /* reg_mgpc_counter_index 9346 * Counter index. 9347 * Access: Index 9348 */ 9349 MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24); 9350 9351 enum mlxsw_reg_mgpc_opcode { 9352 /* Nop */ 9353 MLXSW_REG_MGPC_OPCODE_NOP = 0x00, 9354 /* Clear counters */ 9355 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08, 9356 }; 9357 9358 /* reg_mgpc_opcode 9359 * Opcode. 9360 * Access: OP 9361 */ 9362 MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4); 9363 9364 /* reg_mgpc_byte_counter 9365 * Byte counter value. 9366 * Access: RW 9367 */ 9368 MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64); 9369 9370 /* reg_mgpc_packet_counter 9371 * Packet counter value. 9372 * Access: RW 9373 */ 9374 MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64); 9375 9376 static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index, 9377 enum mlxsw_reg_mgpc_opcode opcode, 9378 enum mlxsw_reg_flow_counter_set_type set_type) 9379 { 9380 MLXSW_REG_ZERO(mgpc, payload); 9381 mlxsw_reg_mgpc_counter_index_set(payload, counter_index); 9382 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type); 9383 mlxsw_reg_mgpc_opcode_set(payload, opcode); 9384 } 9385 9386 /* MPRS - Monitoring Parsing State Register 9387 * ---------------------------------------- 9388 * The MPRS register is used for setting up the parsing for hash, 9389 * policy-engine and routing. 9390 */ 9391 #define MLXSW_REG_MPRS_ID 0x9083 9392 #define MLXSW_REG_MPRS_LEN 0x14 9393 9394 MLXSW_REG_DEFINE(mprs, MLXSW_REG_MPRS_ID, MLXSW_REG_MPRS_LEN); 9395 9396 /* reg_mprs_parsing_depth 9397 * Minimum parsing depth. 9398 * Need to enlarge parsing depth according to L3, MPLS, tunnels, ACL 9399 * rules, traps, hash, etc. Default is 96 bytes. Reserved when SwitchX-2. 9400 * Access: RW 9401 */ 9402 MLXSW_ITEM32(reg, mprs, parsing_depth, 0x00, 0, 16); 9403 9404 /* reg_mprs_parsing_en 9405 * Parsing enable. 9406 * Bit 0 - Enable parsing of NVE of types VxLAN, VxLAN-GPE, GENEVE and 9407 * NVGRE. Default is enabled. Reserved when SwitchX-2. 9408 * Access: RW 9409 */ 9410 MLXSW_ITEM32(reg, mprs, parsing_en, 0x04, 0, 16); 9411 9412 /* reg_mprs_vxlan_udp_dport 9413 * VxLAN UDP destination port. 9414 * Used for identifying VxLAN packets and for dport field in 9415 * encapsulation. Default is 4789. 9416 * Access: RW 9417 */ 9418 MLXSW_ITEM32(reg, mprs, vxlan_udp_dport, 0x10, 0, 16); 9419 9420 static inline void mlxsw_reg_mprs_pack(char *payload, u16 parsing_depth, 9421 u16 vxlan_udp_dport) 9422 { 9423 MLXSW_REG_ZERO(mprs, payload); 9424 mlxsw_reg_mprs_parsing_depth_set(payload, parsing_depth); 9425 mlxsw_reg_mprs_parsing_en_set(payload, true); 9426 mlxsw_reg_mprs_vxlan_udp_dport_set(payload, vxlan_udp_dport); 9427 } 9428 9429 /* MOGCR - Monitoring Global Configuration Register 9430 * ------------------------------------------------ 9431 */ 9432 #define MLXSW_REG_MOGCR_ID 0x9086 9433 #define MLXSW_REG_MOGCR_LEN 0x20 9434 9435 MLXSW_REG_DEFINE(mogcr, MLXSW_REG_MOGCR_ID, MLXSW_REG_MOGCR_LEN); 9436 9437 /* reg_mogcr_ptp_iftc 9438 * PTP Ingress FIFO Trap Clear 9439 * The PTP_ING_FIFO trap provides MTPPTR with clr according 9440 * to this value. Default 0. 9441 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9442 * Access: RW 9443 */ 9444 MLXSW_ITEM32(reg, mogcr, ptp_iftc, 0x00, 1, 1); 9445 9446 /* reg_mogcr_ptp_eftc 9447 * PTP Egress FIFO Trap Clear 9448 * The PTP_EGR_FIFO trap provides MTPPTR with clr according 9449 * to this value. Default 0. 9450 * Reserved when IB switches and when SwitchX/-2, Spectrum-2 9451 * Access: RW 9452 */ 9453 MLXSW_ITEM32(reg, mogcr, ptp_eftc, 0x00, 0, 1); 9454 9455 /* MTPPPC - Time Precision Packet Port Configuration 9456 * ------------------------------------------------- 9457 * This register serves for configuration of which PTP messages should be 9458 * timestamped. This is a global configuration, despite the register name. 9459 * 9460 * Reserved when Spectrum-2. 9461 */ 9462 #define MLXSW_REG_MTPPPC_ID 0x9090 9463 #define MLXSW_REG_MTPPPC_LEN 0x28 9464 9465 MLXSW_REG_DEFINE(mtpppc, MLXSW_REG_MTPPPC_ID, MLXSW_REG_MTPPPC_LEN); 9466 9467 /* reg_mtpppc_ing_timestamp_message_type 9468 * Bitwise vector of PTP message types to timestamp at ingress. 9469 * MessageType field as defined by IEEE 1588 9470 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9471 * Default all 0 9472 * Access: RW 9473 */ 9474 MLXSW_ITEM32(reg, mtpppc, ing_timestamp_message_type, 0x08, 0, 16); 9475 9476 /* reg_mtpppc_egr_timestamp_message_type 9477 * Bitwise vector of PTP message types to timestamp at egress. 9478 * MessageType field as defined by IEEE 1588 9479 * Each bit corresponds to a value (e.g. Bit0: Sync, Bit1: Delay_Req) 9480 * Default all 0 9481 * Access: RW 9482 */ 9483 MLXSW_ITEM32(reg, mtpppc, egr_timestamp_message_type, 0x0C, 0, 16); 9484 9485 static inline void mlxsw_reg_mtpppc_pack(char *payload, u16 ing, u16 egr) 9486 { 9487 MLXSW_REG_ZERO(mtpppc, payload); 9488 mlxsw_reg_mtpppc_ing_timestamp_message_type_set(payload, ing); 9489 mlxsw_reg_mtpppc_egr_timestamp_message_type_set(payload, egr); 9490 } 9491 9492 /* MTPPTR - Time Precision Packet Timestamping Reading 9493 * --------------------------------------------------- 9494 * The MTPPTR is used for reading the per port PTP timestamp FIFO. 9495 * There is a trap for packets which are latched to the timestamp FIFO, thus the 9496 * SW knows which FIFO to read. Note that packets enter the FIFO before been 9497 * trapped. The sequence number is used to synchronize the timestamp FIFO 9498 * entries and the trapped packets. 9499 * Reserved when Spectrum-2. 9500 */ 9501 9502 #define MLXSW_REG_MTPPTR_ID 0x9091 9503 #define MLXSW_REG_MTPPTR_BASE_LEN 0x10 /* base length, without records */ 9504 #define MLXSW_REG_MTPPTR_REC_LEN 0x10 /* record length */ 9505 #define MLXSW_REG_MTPPTR_REC_MAX_COUNT 4 9506 #define MLXSW_REG_MTPPTR_LEN (MLXSW_REG_MTPPTR_BASE_LEN + \ 9507 MLXSW_REG_MTPPTR_REC_LEN * MLXSW_REG_MTPPTR_REC_MAX_COUNT) 9508 9509 MLXSW_REG_DEFINE(mtpptr, MLXSW_REG_MTPPTR_ID, MLXSW_REG_MTPPTR_LEN); 9510 9511 /* reg_mtpptr_local_port 9512 * Not supported for CPU port. 9513 * Access: Index 9514 */ 9515 MLXSW_ITEM32(reg, mtpptr, local_port, 0x00, 16, 8); 9516 9517 enum mlxsw_reg_mtpptr_dir { 9518 MLXSW_REG_MTPPTR_DIR_INGRESS, 9519 MLXSW_REG_MTPPTR_DIR_EGRESS, 9520 }; 9521 9522 /* reg_mtpptr_dir 9523 * Direction. 9524 * Access: Index 9525 */ 9526 MLXSW_ITEM32(reg, mtpptr, dir, 0x00, 0, 1); 9527 9528 /* reg_mtpptr_clr 9529 * Clear the records. 9530 * Access: OP 9531 */ 9532 MLXSW_ITEM32(reg, mtpptr, clr, 0x04, 31, 1); 9533 9534 /* reg_mtpptr_num_rec 9535 * Number of valid records in the response 9536 * Range 0.. cap_ptp_timestamp_fifo 9537 * Access: RO 9538 */ 9539 MLXSW_ITEM32(reg, mtpptr, num_rec, 0x08, 0, 4); 9540 9541 /* reg_mtpptr_rec_message_type 9542 * MessageType field as defined by IEEE 1588 Each bit corresponds to a value 9543 * (e.g. Bit0: Sync, Bit1: Delay_Req) 9544 * Access: RO 9545 */ 9546 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_message_type, 9547 MLXSW_REG_MTPPTR_BASE_LEN, 8, 4, 9548 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 9549 9550 /* reg_mtpptr_rec_domain_number 9551 * DomainNumber field as defined by IEEE 1588 9552 * Access: RO 9553 */ 9554 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_domain_number, 9555 MLXSW_REG_MTPPTR_BASE_LEN, 0, 8, 9556 MLXSW_REG_MTPPTR_REC_LEN, 0, false); 9557 9558 /* reg_mtpptr_rec_sequence_id 9559 * SequenceId field as defined by IEEE 1588 9560 * Access: RO 9561 */ 9562 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_sequence_id, 9563 MLXSW_REG_MTPPTR_BASE_LEN, 0, 16, 9564 MLXSW_REG_MTPPTR_REC_LEN, 0x4, false); 9565 9566 /* reg_mtpptr_rec_timestamp_high 9567 * Timestamp of when the PTP packet has passed through the port Units of PLL 9568 * clock time. 9569 * For Spectrum-1 the PLL clock is 156.25Mhz and PLL clock time is 6.4nSec. 9570 * Access: RO 9571 */ 9572 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_high, 9573 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 9574 MLXSW_REG_MTPPTR_REC_LEN, 0x8, false); 9575 9576 /* reg_mtpptr_rec_timestamp_low 9577 * See rec_timestamp_high. 9578 * Access: RO 9579 */ 9580 MLXSW_ITEM32_INDEXED(reg, mtpptr, rec_timestamp_low, 9581 MLXSW_REG_MTPPTR_BASE_LEN, 0, 32, 9582 MLXSW_REG_MTPPTR_REC_LEN, 0xC, false); 9583 9584 static inline void mlxsw_reg_mtpptr_unpack(const char *payload, 9585 unsigned int rec, 9586 u8 *p_message_type, 9587 u8 *p_domain_number, 9588 u16 *p_sequence_id, 9589 u64 *p_timestamp) 9590 { 9591 u32 timestamp_high, timestamp_low; 9592 9593 *p_message_type = mlxsw_reg_mtpptr_rec_message_type_get(payload, rec); 9594 *p_domain_number = mlxsw_reg_mtpptr_rec_domain_number_get(payload, rec); 9595 *p_sequence_id = mlxsw_reg_mtpptr_rec_sequence_id_get(payload, rec); 9596 timestamp_high = mlxsw_reg_mtpptr_rec_timestamp_high_get(payload, rec); 9597 timestamp_low = mlxsw_reg_mtpptr_rec_timestamp_low_get(payload, rec); 9598 *p_timestamp = (u64)timestamp_high << 32 | timestamp_low; 9599 } 9600 9601 /* MTPTPT - Monitoring Precision Time Protocol Trap Register 9602 * --------------------------------------------------------- 9603 * This register is used for configuring under which trap to deliver PTP 9604 * packets depending on type of the packet. 9605 */ 9606 #define MLXSW_REG_MTPTPT_ID 0x9092 9607 #define MLXSW_REG_MTPTPT_LEN 0x08 9608 9609 MLXSW_REG_DEFINE(mtptpt, MLXSW_REG_MTPTPT_ID, MLXSW_REG_MTPTPT_LEN); 9610 9611 enum mlxsw_reg_mtptpt_trap_id { 9612 MLXSW_REG_MTPTPT_TRAP_ID_PTP0, 9613 MLXSW_REG_MTPTPT_TRAP_ID_PTP1, 9614 }; 9615 9616 /* reg_mtptpt_trap_id 9617 * Trap id. 9618 * Access: Index 9619 */ 9620 MLXSW_ITEM32(reg, mtptpt, trap_id, 0x00, 0, 4); 9621 9622 /* reg_mtptpt_message_type 9623 * Bitwise vector of PTP message types to trap. This is a necessary but 9624 * non-sufficient condition since need to enable also per port. See MTPPPC. 9625 * Message types are defined by IEEE 1588 Each bit corresponds to a value (e.g. 9626 * Bit0: Sync, Bit1: Delay_Req) 9627 */ 9628 MLXSW_ITEM32(reg, mtptpt, message_type, 0x04, 0, 16); 9629 9630 static inline void mlxsw_reg_mtptptp_pack(char *payload, 9631 enum mlxsw_reg_mtptpt_trap_id trap_id, 9632 u16 message_type) 9633 { 9634 MLXSW_REG_ZERO(mtptpt, payload); 9635 mlxsw_reg_mtptpt_trap_id_set(payload, trap_id); 9636 mlxsw_reg_mtptpt_message_type_set(payload, message_type); 9637 } 9638 9639 /* MGPIR - Management General Peripheral Information Register 9640 * ---------------------------------------------------------- 9641 * MGPIR register allows software to query the hardware and 9642 * firmware general information of peripheral entities. 9643 */ 9644 #define MLXSW_REG_MGPIR_ID 0x9100 9645 #define MLXSW_REG_MGPIR_LEN 0xA0 9646 9647 MLXSW_REG_DEFINE(mgpir, MLXSW_REG_MGPIR_ID, MLXSW_REG_MGPIR_LEN); 9648 9649 enum mlxsw_reg_mgpir_device_type { 9650 MLXSW_REG_MGPIR_DEVICE_TYPE_NONE, 9651 MLXSW_REG_MGPIR_DEVICE_TYPE_GEARBOX_DIE, 9652 }; 9653 9654 /* device_type 9655 * Access: RO 9656 */ 9657 MLXSW_ITEM32(reg, mgpir, device_type, 0x00, 24, 4); 9658 9659 /* devices_per_flash 9660 * Number of devices of device_type per flash (can be shared by few devices). 9661 * Access: RO 9662 */ 9663 MLXSW_ITEM32(reg, mgpir, devices_per_flash, 0x00, 16, 8); 9664 9665 /* num_of_devices 9666 * Number of devices of device_type. 9667 * Access: RO 9668 */ 9669 MLXSW_ITEM32(reg, mgpir, num_of_devices, 0x00, 0, 8); 9670 9671 /* num_of_modules 9672 * Number of modules. 9673 * Access: RO 9674 */ 9675 MLXSW_ITEM32(reg, mgpir, num_of_modules, 0x04, 0, 8); 9676 9677 static inline void mlxsw_reg_mgpir_pack(char *payload) 9678 { 9679 MLXSW_REG_ZERO(mgpir, payload); 9680 } 9681 9682 static inline void 9683 mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices, 9684 enum mlxsw_reg_mgpir_device_type *device_type, 9685 u8 *devices_per_flash, u8 *num_of_modules) 9686 { 9687 if (num_of_devices) 9688 *num_of_devices = mlxsw_reg_mgpir_num_of_devices_get(payload); 9689 if (device_type) 9690 *device_type = mlxsw_reg_mgpir_device_type_get(payload); 9691 if (devices_per_flash) 9692 *devices_per_flash = 9693 mlxsw_reg_mgpir_devices_per_flash_get(payload); 9694 if (num_of_modules) 9695 *num_of_modules = mlxsw_reg_mgpir_num_of_modules_get(payload); 9696 } 9697 9698 /* TNGCR - Tunneling NVE General Configuration Register 9699 * ---------------------------------------------------- 9700 * The TNGCR register is used for setting up the NVE Tunneling configuration. 9701 */ 9702 #define MLXSW_REG_TNGCR_ID 0xA001 9703 #define MLXSW_REG_TNGCR_LEN 0x44 9704 9705 MLXSW_REG_DEFINE(tngcr, MLXSW_REG_TNGCR_ID, MLXSW_REG_TNGCR_LEN); 9706 9707 enum mlxsw_reg_tngcr_type { 9708 MLXSW_REG_TNGCR_TYPE_VXLAN, 9709 MLXSW_REG_TNGCR_TYPE_VXLAN_GPE, 9710 MLXSW_REG_TNGCR_TYPE_GENEVE, 9711 MLXSW_REG_TNGCR_TYPE_NVGRE, 9712 }; 9713 9714 /* reg_tngcr_type 9715 * Tunnel type for encapsulation and decapsulation. The types are mutually 9716 * exclusive. 9717 * Note: For Spectrum the NVE parsing must be enabled in MPRS. 9718 * Access: RW 9719 */ 9720 MLXSW_ITEM32(reg, tngcr, type, 0x00, 0, 4); 9721 9722 /* reg_tngcr_nve_valid 9723 * The VTEP is valid. Allows adding FDB entries for tunnel encapsulation. 9724 * Access: RW 9725 */ 9726 MLXSW_ITEM32(reg, tngcr, nve_valid, 0x04, 31, 1); 9727 9728 /* reg_tngcr_nve_ttl_uc 9729 * The TTL for NVE tunnel encapsulation underlay unicast packets. 9730 * Access: RW 9731 */ 9732 MLXSW_ITEM32(reg, tngcr, nve_ttl_uc, 0x04, 0, 8); 9733 9734 /* reg_tngcr_nve_ttl_mc 9735 * The TTL for NVE tunnel encapsulation underlay multicast packets. 9736 * Access: RW 9737 */ 9738 MLXSW_ITEM32(reg, tngcr, nve_ttl_mc, 0x08, 0, 8); 9739 9740 enum { 9741 /* Do not copy flow label. Calculate flow label using nve_flh. */ 9742 MLXSW_REG_TNGCR_FL_NO_COPY, 9743 /* Copy flow label from inner packet if packet is IPv6 and 9744 * encapsulation is by IPv6. Otherwise, calculate flow label using 9745 * nve_flh. 9746 */ 9747 MLXSW_REG_TNGCR_FL_COPY, 9748 }; 9749 9750 /* reg_tngcr_nve_flc 9751 * For NVE tunnel encapsulation: Flow label copy from inner packet. 9752 * Access: RW 9753 */ 9754 MLXSW_ITEM32(reg, tngcr, nve_flc, 0x0C, 25, 1); 9755 9756 enum { 9757 /* Flow label is static. In Spectrum this means '0'. Spectrum-2 9758 * uses {nve_fl_prefix, nve_fl_suffix}. 9759 */ 9760 MLXSW_REG_TNGCR_FL_NO_HASH, 9761 /* 8 LSBs of the flow label are calculated from ECMP hash of the 9762 * inner packet. 12 MSBs are configured by nve_fl_prefix. 9763 */ 9764 MLXSW_REG_TNGCR_FL_HASH, 9765 }; 9766 9767 /* reg_tngcr_nve_flh 9768 * NVE flow label hash. 9769 * Access: RW 9770 */ 9771 MLXSW_ITEM32(reg, tngcr, nve_flh, 0x0C, 24, 1); 9772 9773 /* reg_tngcr_nve_fl_prefix 9774 * NVE flow label prefix. Constant 12 MSBs of the flow label. 9775 * Access: RW 9776 */ 9777 MLXSW_ITEM32(reg, tngcr, nve_fl_prefix, 0x0C, 8, 12); 9778 9779 /* reg_tngcr_nve_fl_suffix 9780 * NVE flow label suffix. Constant 8 LSBs of the flow label. 9781 * Reserved when nve_flh=1 and for Spectrum. 9782 * Access: RW 9783 */ 9784 MLXSW_ITEM32(reg, tngcr, nve_fl_suffix, 0x0C, 0, 8); 9785 9786 enum { 9787 /* Source UDP port is fixed (default '0') */ 9788 MLXSW_REG_TNGCR_UDP_SPORT_NO_HASH, 9789 /* Source UDP port is calculated based on hash */ 9790 MLXSW_REG_TNGCR_UDP_SPORT_HASH, 9791 }; 9792 9793 /* reg_tngcr_nve_udp_sport_type 9794 * NVE UDP source port type. 9795 * Spectrum uses LAG hash (SLCRv2). Spectrum-2 uses ECMP hash (RECRv2). 9796 * When the source UDP port is calculated based on hash, then the 8 LSBs 9797 * are calculated from hash the 8 MSBs are configured by 9798 * nve_udp_sport_prefix. 9799 * Access: RW 9800 */ 9801 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_type, 0x10, 24, 1); 9802 9803 /* reg_tngcr_nve_udp_sport_prefix 9804 * NVE UDP source port prefix. Constant 8 MSBs of the UDP source port. 9805 * Reserved when NVE type is NVGRE. 9806 * Access: RW 9807 */ 9808 MLXSW_ITEM32(reg, tngcr, nve_udp_sport_prefix, 0x10, 8, 8); 9809 9810 /* reg_tngcr_nve_group_size_mc 9811 * The amount of sequential linked lists of MC entries. The first linked 9812 * list is configured by SFD.underlay_mc_ptr. 9813 * Valid values: 1, 2, 4, 8, 16, 32, 64 9814 * The linked list are configured by TNUMT. 9815 * The hash is set by LAG hash. 9816 * Access: RW 9817 */ 9818 MLXSW_ITEM32(reg, tngcr, nve_group_size_mc, 0x18, 0, 8); 9819 9820 /* reg_tngcr_nve_group_size_flood 9821 * The amount of sequential linked lists of flooding entries. The first 9822 * linked list is configured by SFMR.nve_tunnel_flood_ptr 9823 * Valid values: 1, 2, 4, 8, 16, 32, 64 9824 * The linked list are configured by TNUMT. 9825 * The hash is set by LAG hash. 9826 * Access: RW 9827 */ 9828 MLXSW_ITEM32(reg, tngcr, nve_group_size_flood, 0x1C, 0, 8); 9829 9830 /* reg_tngcr_learn_enable 9831 * During decapsulation, whether to learn from NVE port. 9832 * Reserved when Spectrum-2. See TNPC. 9833 * Access: RW 9834 */ 9835 MLXSW_ITEM32(reg, tngcr, learn_enable, 0x20, 31, 1); 9836 9837 /* reg_tngcr_underlay_virtual_router 9838 * Underlay virtual router. 9839 * Reserved when Spectrum-2. 9840 * Access: RW 9841 */ 9842 MLXSW_ITEM32(reg, tngcr, underlay_virtual_router, 0x20, 0, 16); 9843 9844 /* reg_tngcr_underlay_rif 9845 * Underlay ingress router interface. RIF type should be loopback generic. 9846 * Reserved when Spectrum. 9847 * Access: RW 9848 */ 9849 MLXSW_ITEM32(reg, tngcr, underlay_rif, 0x24, 0, 16); 9850 9851 /* reg_tngcr_usipv4 9852 * Underlay source IPv4 address of the NVE. 9853 * Access: RW 9854 */ 9855 MLXSW_ITEM32(reg, tngcr, usipv4, 0x28, 0, 32); 9856 9857 /* reg_tngcr_usipv6 9858 * Underlay source IPv6 address of the NVE. For Spectrum, must not be 9859 * modified under traffic of NVE tunneling encapsulation. 9860 * Access: RW 9861 */ 9862 MLXSW_ITEM_BUF(reg, tngcr, usipv6, 0x30, 16); 9863 9864 static inline void mlxsw_reg_tngcr_pack(char *payload, 9865 enum mlxsw_reg_tngcr_type type, 9866 bool valid, u8 ttl) 9867 { 9868 MLXSW_REG_ZERO(tngcr, payload); 9869 mlxsw_reg_tngcr_type_set(payload, type); 9870 mlxsw_reg_tngcr_nve_valid_set(payload, valid); 9871 mlxsw_reg_tngcr_nve_ttl_uc_set(payload, ttl); 9872 mlxsw_reg_tngcr_nve_ttl_mc_set(payload, ttl); 9873 mlxsw_reg_tngcr_nve_flc_set(payload, MLXSW_REG_TNGCR_FL_NO_COPY); 9874 mlxsw_reg_tngcr_nve_flh_set(payload, 0); 9875 mlxsw_reg_tngcr_nve_udp_sport_type_set(payload, 9876 MLXSW_REG_TNGCR_UDP_SPORT_HASH); 9877 mlxsw_reg_tngcr_nve_udp_sport_prefix_set(payload, 0); 9878 mlxsw_reg_tngcr_nve_group_size_mc_set(payload, 1); 9879 mlxsw_reg_tngcr_nve_group_size_flood_set(payload, 1); 9880 } 9881 9882 /* TNUMT - Tunneling NVE Underlay Multicast Table Register 9883 * ------------------------------------------------------- 9884 * The TNUMT register is for building the underlay MC table. It is used 9885 * for MC, flooding and BC traffic into the NVE tunnel. 9886 */ 9887 #define MLXSW_REG_TNUMT_ID 0xA003 9888 #define MLXSW_REG_TNUMT_LEN 0x20 9889 9890 MLXSW_REG_DEFINE(tnumt, MLXSW_REG_TNUMT_ID, MLXSW_REG_TNUMT_LEN); 9891 9892 enum mlxsw_reg_tnumt_record_type { 9893 MLXSW_REG_TNUMT_RECORD_TYPE_IPV4, 9894 MLXSW_REG_TNUMT_RECORD_TYPE_IPV6, 9895 MLXSW_REG_TNUMT_RECORD_TYPE_LABEL, 9896 }; 9897 9898 /* reg_tnumt_record_type 9899 * Record type. 9900 * Access: RW 9901 */ 9902 MLXSW_ITEM32(reg, tnumt, record_type, 0x00, 28, 4); 9903 9904 enum mlxsw_reg_tnumt_tunnel_port { 9905 MLXSW_REG_TNUMT_TUNNEL_PORT_NVE, 9906 MLXSW_REG_TNUMT_TUNNEL_PORT_VPLS, 9907 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL0, 9908 MLXSW_REG_TNUMT_TUNNEL_FLEX_TUNNEL1, 9909 }; 9910 9911 /* reg_tnumt_tunnel_port 9912 * Tunnel port. 9913 * Access: RW 9914 */ 9915 MLXSW_ITEM32(reg, tnumt, tunnel_port, 0x00, 24, 4); 9916 9917 /* reg_tnumt_underlay_mc_ptr 9918 * Index to the underlay multicast table. 9919 * For Spectrum the index is to the KVD linear. 9920 * Access: Index 9921 */ 9922 MLXSW_ITEM32(reg, tnumt, underlay_mc_ptr, 0x00, 0, 24); 9923 9924 /* reg_tnumt_vnext 9925 * The next_underlay_mc_ptr is valid. 9926 * Access: RW 9927 */ 9928 MLXSW_ITEM32(reg, tnumt, vnext, 0x04, 31, 1); 9929 9930 /* reg_tnumt_next_underlay_mc_ptr 9931 * The next index to the underlay multicast table. 9932 * Access: RW 9933 */ 9934 MLXSW_ITEM32(reg, tnumt, next_underlay_mc_ptr, 0x04, 0, 24); 9935 9936 /* reg_tnumt_record_size 9937 * Number of IP addresses in the record. 9938 * Range is 1..cap_max_nve_mc_entries_ipv{4,6} 9939 * Access: RW 9940 */ 9941 MLXSW_ITEM32(reg, tnumt, record_size, 0x08, 0, 3); 9942 9943 /* reg_tnumt_udip 9944 * The underlay IPv4 addresses. udip[i] is reserved if i >= size 9945 * Access: RW 9946 */ 9947 MLXSW_ITEM32_INDEXED(reg, tnumt, udip, 0x0C, 0, 32, 0x04, 0x00, false); 9948 9949 /* reg_tnumt_udip_ptr 9950 * The pointer to the underlay IPv6 addresses. udip_ptr[i] is reserved if 9951 * i >= size. The IPv6 addresses are configured by RIPS. 9952 * Access: RW 9953 */ 9954 MLXSW_ITEM32_INDEXED(reg, tnumt, udip_ptr, 0x0C, 0, 24, 0x04, 0x00, false); 9955 9956 static inline void mlxsw_reg_tnumt_pack(char *payload, 9957 enum mlxsw_reg_tnumt_record_type type, 9958 enum mlxsw_reg_tnumt_tunnel_port tport, 9959 u32 underlay_mc_ptr, bool vnext, 9960 u32 next_underlay_mc_ptr, 9961 u8 record_size) 9962 { 9963 MLXSW_REG_ZERO(tnumt, payload); 9964 mlxsw_reg_tnumt_record_type_set(payload, type); 9965 mlxsw_reg_tnumt_tunnel_port_set(payload, tport); 9966 mlxsw_reg_tnumt_underlay_mc_ptr_set(payload, underlay_mc_ptr); 9967 mlxsw_reg_tnumt_vnext_set(payload, vnext); 9968 mlxsw_reg_tnumt_next_underlay_mc_ptr_set(payload, next_underlay_mc_ptr); 9969 mlxsw_reg_tnumt_record_size_set(payload, record_size); 9970 } 9971 9972 /* TNQCR - Tunneling NVE QoS Configuration Register 9973 * ------------------------------------------------ 9974 * The TNQCR register configures how QoS is set in encapsulation into the 9975 * underlay network. 9976 */ 9977 #define MLXSW_REG_TNQCR_ID 0xA010 9978 #define MLXSW_REG_TNQCR_LEN 0x0C 9979 9980 MLXSW_REG_DEFINE(tnqcr, MLXSW_REG_TNQCR_ID, MLXSW_REG_TNQCR_LEN); 9981 9982 /* reg_tnqcr_enc_set_dscp 9983 * For encapsulation: How to set DSCP field: 9984 * 0 - Copy the DSCP from the overlay (inner) IP header to the underlay 9985 * (outer) IP header. If there is no IP header, use TNQDR.dscp 9986 * 1 - Set the DSCP field as TNQDR.dscp 9987 * Access: RW 9988 */ 9989 MLXSW_ITEM32(reg, tnqcr, enc_set_dscp, 0x04, 28, 1); 9990 9991 static inline void mlxsw_reg_tnqcr_pack(char *payload) 9992 { 9993 MLXSW_REG_ZERO(tnqcr, payload); 9994 mlxsw_reg_tnqcr_enc_set_dscp_set(payload, 0); 9995 } 9996 9997 /* TNQDR - Tunneling NVE QoS Default Register 9998 * ------------------------------------------ 9999 * The TNQDR register configures the default QoS settings for NVE 10000 * encapsulation. 10001 */ 10002 #define MLXSW_REG_TNQDR_ID 0xA011 10003 #define MLXSW_REG_TNQDR_LEN 0x08 10004 10005 MLXSW_REG_DEFINE(tnqdr, MLXSW_REG_TNQDR_ID, MLXSW_REG_TNQDR_LEN); 10006 10007 /* reg_tnqdr_local_port 10008 * Local port number (receive port). CPU port is supported. 10009 * Access: Index 10010 */ 10011 MLXSW_ITEM32(reg, tnqdr, local_port, 0x00, 16, 8); 10012 10013 /* reg_tnqdr_dscp 10014 * For encapsulation, the default DSCP. 10015 * Access: RW 10016 */ 10017 MLXSW_ITEM32(reg, tnqdr, dscp, 0x04, 0, 6); 10018 10019 static inline void mlxsw_reg_tnqdr_pack(char *payload, u8 local_port) 10020 { 10021 MLXSW_REG_ZERO(tnqdr, payload); 10022 mlxsw_reg_tnqdr_local_port_set(payload, local_port); 10023 mlxsw_reg_tnqdr_dscp_set(payload, 0); 10024 } 10025 10026 /* TNEEM - Tunneling NVE Encapsulation ECN Mapping Register 10027 * -------------------------------------------------------- 10028 * The TNEEM register maps ECN of the IP header at the ingress to the 10029 * encapsulation to the ECN of the underlay network. 10030 */ 10031 #define MLXSW_REG_TNEEM_ID 0xA012 10032 #define MLXSW_REG_TNEEM_LEN 0x0C 10033 10034 MLXSW_REG_DEFINE(tneem, MLXSW_REG_TNEEM_ID, MLXSW_REG_TNEEM_LEN); 10035 10036 /* reg_tneem_overlay_ecn 10037 * ECN of the IP header in the overlay network. 10038 * Access: Index 10039 */ 10040 MLXSW_ITEM32(reg, tneem, overlay_ecn, 0x04, 24, 2); 10041 10042 /* reg_tneem_underlay_ecn 10043 * ECN of the IP header in the underlay network. 10044 * Access: RW 10045 */ 10046 MLXSW_ITEM32(reg, tneem, underlay_ecn, 0x04, 16, 2); 10047 10048 static inline void mlxsw_reg_tneem_pack(char *payload, u8 overlay_ecn, 10049 u8 underlay_ecn) 10050 { 10051 MLXSW_REG_ZERO(tneem, payload); 10052 mlxsw_reg_tneem_overlay_ecn_set(payload, overlay_ecn); 10053 mlxsw_reg_tneem_underlay_ecn_set(payload, underlay_ecn); 10054 } 10055 10056 /* TNDEM - Tunneling NVE Decapsulation ECN Mapping Register 10057 * -------------------------------------------------------- 10058 * The TNDEM register configures the actions that are done in the 10059 * decapsulation. 10060 */ 10061 #define MLXSW_REG_TNDEM_ID 0xA013 10062 #define MLXSW_REG_TNDEM_LEN 0x0C 10063 10064 MLXSW_REG_DEFINE(tndem, MLXSW_REG_TNDEM_ID, MLXSW_REG_TNDEM_LEN); 10065 10066 /* reg_tndem_underlay_ecn 10067 * ECN field of the IP header in the underlay network. 10068 * Access: Index 10069 */ 10070 MLXSW_ITEM32(reg, tndem, underlay_ecn, 0x04, 24, 2); 10071 10072 /* reg_tndem_overlay_ecn 10073 * ECN field of the IP header in the overlay network. 10074 * Access: Index 10075 */ 10076 MLXSW_ITEM32(reg, tndem, overlay_ecn, 0x04, 16, 2); 10077 10078 /* reg_tndem_eip_ecn 10079 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10080 * from the decapsulation. 10081 * Access: RW 10082 */ 10083 MLXSW_ITEM32(reg, tndem, eip_ecn, 0x04, 8, 2); 10084 10085 /* reg_tndem_trap_en 10086 * Trap enable: 10087 * 0 - No trap due to decap ECN 10088 * 1 - Trap enable with trap_id 10089 * Access: RW 10090 */ 10091 MLXSW_ITEM32(reg, tndem, trap_en, 0x08, 28, 4); 10092 10093 /* reg_tndem_trap_id 10094 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10095 * Reserved when trap_en is '0'. 10096 * Access: RW 10097 */ 10098 MLXSW_ITEM32(reg, tndem, trap_id, 0x08, 0, 9); 10099 10100 static inline void mlxsw_reg_tndem_pack(char *payload, u8 underlay_ecn, 10101 u8 overlay_ecn, u8 ecn, bool trap_en, 10102 u16 trap_id) 10103 { 10104 MLXSW_REG_ZERO(tndem, payload); 10105 mlxsw_reg_tndem_underlay_ecn_set(payload, underlay_ecn); 10106 mlxsw_reg_tndem_overlay_ecn_set(payload, overlay_ecn); 10107 mlxsw_reg_tndem_eip_ecn_set(payload, ecn); 10108 mlxsw_reg_tndem_trap_en_set(payload, trap_en); 10109 mlxsw_reg_tndem_trap_id_set(payload, trap_id); 10110 } 10111 10112 /* TNPC - Tunnel Port Configuration Register 10113 * ----------------------------------------- 10114 * The TNPC register is used for tunnel port configuration. 10115 * Reserved when Spectrum. 10116 */ 10117 #define MLXSW_REG_TNPC_ID 0xA020 10118 #define MLXSW_REG_TNPC_LEN 0x18 10119 10120 MLXSW_REG_DEFINE(tnpc, MLXSW_REG_TNPC_ID, MLXSW_REG_TNPC_LEN); 10121 10122 enum mlxsw_reg_tnpc_tunnel_port { 10123 MLXSW_REG_TNPC_TUNNEL_PORT_NVE, 10124 MLXSW_REG_TNPC_TUNNEL_PORT_VPLS, 10125 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL0, 10126 MLXSW_REG_TNPC_TUNNEL_FLEX_TUNNEL1, 10127 }; 10128 10129 /* reg_tnpc_tunnel_port 10130 * Tunnel port. 10131 * Access: Index 10132 */ 10133 MLXSW_ITEM32(reg, tnpc, tunnel_port, 0x00, 0, 4); 10134 10135 /* reg_tnpc_learn_enable_v6 10136 * During IPv6 underlay decapsulation, whether to learn from tunnel port. 10137 * Access: RW 10138 */ 10139 MLXSW_ITEM32(reg, tnpc, learn_enable_v6, 0x04, 1, 1); 10140 10141 /* reg_tnpc_learn_enable_v4 10142 * During IPv4 underlay decapsulation, whether to learn from tunnel port. 10143 * Access: RW 10144 */ 10145 MLXSW_ITEM32(reg, tnpc, learn_enable_v4, 0x04, 0, 1); 10146 10147 static inline void mlxsw_reg_tnpc_pack(char *payload, 10148 enum mlxsw_reg_tnpc_tunnel_port tport, 10149 bool learn_enable) 10150 { 10151 MLXSW_REG_ZERO(tnpc, payload); 10152 mlxsw_reg_tnpc_tunnel_port_set(payload, tport); 10153 mlxsw_reg_tnpc_learn_enable_v4_set(payload, learn_enable); 10154 mlxsw_reg_tnpc_learn_enable_v6_set(payload, learn_enable); 10155 } 10156 10157 /* TIGCR - Tunneling IPinIP General Configuration Register 10158 * ------------------------------------------------------- 10159 * The TIGCR register is used for setting up the IPinIP Tunnel configuration. 10160 */ 10161 #define MLXSW_REG_TIGCR_ID 0xA801 10162 #define MLXSW_REG_TIGCR_LEN 0x10 10163 10164 MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN); 10165 10166 /* reg_tigcr_ipip_ttlc 10167 * For IPinIP Tunnel encapsulation: whether to copy the ttl from the packet 10168 * header. 10169 * Access: RW 10170 */ 10171 MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1); 10172 10173 /* reg_tigcr_ipip_ttl_uc 10174 * The TTL for IPinIP Tunnel encapsulation of unicast packets if 10175 * reg_tigcr_ipip_ttlc is unset. 10176 * Access: RW 10177 */ 10178 MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8); 10179 10180 static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc) 10181 { 10182 MLXSW_REG_ZERO(tigcr, payload); 10183 mlxsw_reg_tigcr_ttlc_set(payload, ttlc); 10184 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc); 10185 } 10186 10187 /* TIEEM - Tunneling IPinIP Encapsulation ECN Mapping Register 10188 * ----------------------------------------------------------- 10189 * The TIEEM register maps ECN of the IP header at the ingress to the 10190 * encapsulation to the ECN of the underlay network. 10191 */ 10192 #define MLXSW_REG_TIEEM_ID 0xA812 10193 #define MLXSW_REG_TIEEM_LEN 0x0C 10194 10195 MLXSW_REG_DEFINE(tieem, MLXSW_REG_TIEEM_ID, MLXSW_REG_TIEEM_LEN); 10196 10197 /* reg_tieem_overlay_ecn 10198 * ECN of the IP header in the overlay network. 10199 * Access: Index 10200 */ 10201 MLXSW_ITEM32(reg, tieem, overlay_ecn, 0x04, 24, 2); 10202 10203 /* reg_tineem_underlay_ecn 10204 * ECN of the IP header in the underlay network. 10205 * Access: RW 10206 */ 10207 MLXSW_ITEM32(reg, tieem, underlay_ecn, 0x04, 16, 2); 10208 10209 static inline void mlxsw_reg_tieem_pack(char *payload, u8 overlay_ecn, 10210 u8 underlay_ecn) 10211 { 10212 MLXSW_REG_ZERO(tieem, payload); 10213 mlxsw_reg_tieem_overlay_ecn_set(payload, overlay_ecn); 10214 mlxsw_reg_tieem_underlay_ecn_set(payload, underlay_ecn); 10215 } 10216 10217 /* TIDEM - Tunneling IPinIP Decapsulation ECN Mapping Register 10218 * ----------------------------------------------------------- 10219 * The TIDEM register configures the actions that are done in the 10220 * decapsulation. 10221 */ 10222 #define MLXSW_REG_TIDEM_ID 0xA813 10223 #define MLXSW_REG_TIDEM_LEN 0x0C 10224 10225 MLXSW_REG_DEFINE(tidem, MLXSW_REG_TIDEM_ID, MLXSW_REG_TIDEM_LEN); 10226 10227 /* reg_tidem_underlay_ecn 10228 * ECN field of the IP header in the underlay network. 10229 * Access: Index 10230 */ 10231 MLXSW_ITEM32(reg, tidem, underlay_ecn, 0x04, 24, 2); 10232 10233 /* reg_tidem_overlay_ecn 10234 * ECN field of the IP header in the overlay network. 10235 * Access: Index 10236 */ 10237 MLXSW_ITEM32(reg, tidem, overlay_ecn, 0x04, 16, 2); 10238 10239 /* reg_tidem_eip_ecn 10240 * Egress IP ECN. ECN field of the IP header of the packet which goes out 10241 * from the decapsulation. 10242 * Access: RW 10243 */ 10244 MLXSW_ITEM32(reg, tidem, eip_ecn, 0x04, 8, 2); 10245 10246 /* reg_tidem_trap_en 10247 * Trap enable: 10248 * 0 - No trap due to decap ECN 10249 * 1 - Trap enable with trap_id 10250 * Access: RW 10251 */ 10252 MLXSW_ITEM32(reg, tidem, trap_en, 0x08, 28, 4); 10253 10254 /* reg_tidem_trap_id 10255 * Trap ID. Either DECAP_ECN0 or DECAP_ECN1. 10256 * Reserved when trap_en is '0'. 10257 * Access: RW 10258 */ 10259 MLXSW_ITEM32(reg, tidem, trap_id, 0x08, 0, 9); 10260 10261 static inline void mlxsw_reg_tidem_pack(char *payload, u8 underlay_ecn, 10262 u8 overlay_ecn, u8 eip_ecn, 10263 bool trap_en, u16 trap_id) 10264 { 10265 MLXSW_REG_ZERO(tidem, payload); 10266 mlxsw_reg_tidem_underlay_ecn_set(payload, underlay_ecn); 10267 mlxsw_reg_tidem_overlay_ecn_set(payload, overlay_ecn); 10268 mlxsw_reg_tidem_eip_ecn_set(payload, eip_ecn); 10269 mlxsw_reg_tidem_trap_en_set(payload, trap_en); 10270 mlxsw_reg_tidem_trap_id_set(payload, trap_id); 10271 } 10272 10273 /* SBPR - Shared Buffer Pools Register 10274 * ----------------------------------- 10275 * The SBPR configures and retrieves the shared buffer pools and configuration. 10276 */ 10277 #define MLXSW_REG_SBPR_ID 0xB001 10278 #define MLXSW_REG_SBPR_LEN 0x14 10279 10280 MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN); 10281 10282 /* shared direstion enum for SBPR, SBCM, SBPM */ 10283 enum mlxsw_reg_sbxx_dir { 10284 MLXSW_REG_SBXX_DIR_INGRESS, 10285 MLXSW_REG_SBXX_DIR_EGRESS, 10286 }; 10287 10288 /* reg_sbpr_dir 10289 * Direction. 10290 * Access: Index 10291 */ 10292 MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2); 10293 10294 /* reg_sbpr_pool 10295 * Pool index. 10296 * Access: Index 10297 */ 10298 MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4); 10299 10300 /* reg_sbpr_infi_size 10301 * Size is infinite. 10302 * Access: RW 10303 */ 10304 MLXSW_ITEM32(reg, sbpr, infi_size, 0x04, 31, 1); 10305 10306 /* reg_sbpr_size 10307 * Pool size in buffer cells. 10308 * Reserved when infi_size = 1. 10309 * Access: RW 10310 */ 10311 MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24); 10312 10313 enum mlxsw_reg_sbpr_mode { 10314 MLXSW_REG_SBPR_MODE_STATIC, 10315 MLXSW_REG_SBPR_MODE_DYNAMIC, 10316 }; 10317 10318 /* reg_sbpr_mode 10319 * Pool quota calculation mode. 10320 * Access: RW 10321 */ 10322 MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4); 10323 10324 static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool, 10325 enum mlxsw_reg_sbxx_dir dir, 10326 enum mlxsw_reg_sbpr_mode mode, u32 size, 10327 bool infi_size) 10328 { 10329 MLXSW_REG_ZERO(sbpr, payload); 10330 mlxsw_reg_sbpr_pool_set(payload, pool); 10331 mlxsw_reg_sbpr_dir_set(payload, dir); 10332 mlxsw_reg_sbpr_mode_set(payload, mode); 10333 mlxsw_reg_sbpr_size_set(payload, size); 10334 mlxsw_reg_sbpr_infi_size_set(payload, infi_size); 10335 } 10336 10337 /* SBCM - Shared Buffer Class Management Register 10338 * ---------------------------------------------- 10339 * The SBCM register configures and retrieves the shared buffer allocation 10340 * and configuration according to Port-PG, including the binding to pool 10341 * and definition of the associated quota. 10342 */ 10343 #define MLXSW_REG_SBCM_ID 0xB002 10344 #define MLXSW_REG_SBCM_LEN 0x28 10345 10346 MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN); 10347 10348 /* reg_sbcm_local_port 10349 * Local port number. 10350 * For Ingress: excludes CPU port and Router port 10351 * For Egress: excludes IP Router 10352 * Access: Index 10353 */ 10354 MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8); 10355 10356 /* reg_sbcm_pg_buff 10357 * PG buffer - Port PG (dir=ingress) / traffic class (dir=egress) 10358 * For PG buffer: range is 0..cap_max_pg_buffers - 1 10359 * For traffic class: range is 0..cap_max_tclass - 1 10360 * Note that when traffic class is in MC aware mode then the traffic 10361 * classes which are MC aware cannot be configured. 10362 * Access: Index 10363 */ 10364 MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6); 10365 10366 /* reg_sbcm_dir 10367 * Direction. 10368 * Access: Index 10369 */ 10370 MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2); 10371 10372 /* reg_sbcm_min_buff 10373 * Minimum buffer size for the limiter, in cells. 10374 * Access: RW 10375 */ 10376 MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24); 10377 10378 /* shared max_buff limits for dynamic threshold for SBCM, SBPM */ 10379 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1 10380 #define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14 10381 10382 /* reg_sbcm_infi_max 10383 * Max buffer is infinite. 10384 * Access: RW 10385 */ 10386 MLXSW_ITEM32(reg, sbcm, infi_max, 0x1C, 31, 1); 10387 10388 /* reg_sbcm_max_buff 10389 * When the pool associated to the port-pg/tclass is configured to 10390 * static, Maximum buffer size for the limiter configured in cells. 10391 * When the pool associated to the port-pg/tclass is configured to 10392 * dynamic, the max_buff holds the "alpha" parameter, supporting 10393 * the following values: 10394 * 0: 0 10395 * i: (1/128)*2^(i-1), for i=1..14 10396 * 0xFF: Infinity 10397 * Reserved when infi_max = 1. 10398 * Access: RW 10399 */ 10400 MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24); 10401 10402 /* reg_sbcm_pool 10403 * Association of the port-priority to a pool. 10404 * Access: RW 10405 */ 10406 MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4); 10407 10408 static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff, 10409 enum mlxsw_reg_sbxx_dir dir, 10410 u32 min_buff, u32 max_buff, 10411 bool infi_max, u8 pool) 10412 { 10413 MLXSW_REG_ZERO(sbcm, payload); 10414 mlxsw_reg_sbcm_local_port_set(payload, local_port); 10415 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff); 10416 mlxsw_reg_sbcm_dir_set(payload, dir); 10417 mlxsw_reg_sbcm_min_buff_set(payload, min_buff); 10418 mlxsw_reg_sbcm_max_buff_set(payload, max_buff); 10419 mlxsw_reg_sbcm_infi_max_set(payload, infi_max); 10420 mlxsw_reg_sbcm_pool_set(payload, pool); 10421 } 10422 10423 /* SBPM - Shared Buffer Port Management Register 10424 * --------------------------------------------- 10425 * The SBPM register configures and retrieves the shared buffer allocation 10426 * and configuration according to Port-Pool, including the definition 10427 * of the associated quota. 10428 */ 10429 #define MLXSW_REG_SBPM_ID 0xB003 10430 #define MLXSW_REG_SBPM_LEN 0x28 10431 10432 MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN); 10433 10434 /* reg_sbpm_local_port 10435 * Local port number. 10436 * For Ingress: excludes CPU port and Router port 10437 * For Egress: excludes IP Router 10438 * Access: Index 10439 */ 10440 MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8); 10441 10442 /* reg_sbpm_pool 10443 * The pool associated to quota counting on the local_port. 10444 * Access: Index 10445 */ 10446 MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4); 10447 10448 /* reg_sbpm_dir 10449 * Direction. 10450 * Access: Index 10451 */ 10452 MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2); 10453 10454 /* reg_sbpm_buff_occupancy 10455 * Current buffer occupancy in cells. 10456 * Access: RO 10457 */ 10458 MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24); 10459 10460 /* reg_sbpm_clr 10461 * Clear Max Buffer Occupancy 10462 * When this bit is set, max_buff_occupancy field is cleared (and a 10463 * new max value is tracked from the time the clear was performed). 10464 * Access: OP 10465 */ 10466 MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1); 10467 10468 /* reg_sbpm_max_buff_occupancy 10469 * Maximum value of buffer occupancy in cells monitored. Cleared by 10470 * writing to the clr field. 10471 * Access: RO 10472 */ 10473 MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24); 10474 10475 /* reg_sbpm_min_buff 10476 * Minimum buffer size for the limiter, in cells. 10477 * Access: RW 10478 */ 10479 MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24); 10480 10481 /* reg_sbpm_max_buff 10482 * When the pool associated to the port-pg/tclass is configured to 10483 * static, Maximum buffer size for the limiter configured in cells. 10484 * When the pool associated to the port-pg/tclass is configured to 10485 * dynamic, the max_buff holds the "alpha" parameter, supporting 10486 * the following values: 10487 * 0: 0 10488 * i: (1/128)*2^(i-1), for i=1..14 10489 * 0xFF: Infinity 10490 * Access: RW 10491 */ 10492 MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24); 10493 10494 static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool, 10495 enum mlxsw_reg_sbxx_dir dir, bool clr, 10496 u32 min_buff, u32 max_buff) 10497 { 10498 MLXSW_REG_ZERO(sbpm, payload); 10499 mlxsw_reg_sbpm_local_port_set(payload, local_port); 10500 mlxsw_reg_sbpm_pool_set(payload, pool); 10501 mlxsw_reg_sbpm_dir_set(payload, dir); 10502 mlxsw_reg_sbpm_clr_set(payload, clr); 10503 mlxsw_reg_sbpm_min_buff_set(payload, min_buff); 10504 mlxsw_reg_sbpm_max_buff_set(payload, max_buff); 10505 } 10506 10507 static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy, 10508 u32 *p_max_buff_occupancy) 10509 { 10510 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload); 10511 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload); 10512 } 10513 10514 /* SBMM - Shared Buffer Multicast Management Register 10515 * -------------------------------------------------- 10516 * The SBMM register configures and retrieves the shared buffer allocation 10517 * and configuration for MC packets according to Switch-Priority, including 10518 * the binding to pool and definition of the associated quota. 10519 */ 10520 #define MLXSW_REG_SBMM_ID 0xB004 10521 #define MLXSW_REG_SBMM_LEN 0x28 10522 10523 MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN); 10524 10525 /* reg_sbmm_prio 10526 * Switch Priority. 10527 * Access: Index 10528 */ 10529 MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4); 10530 10531 /* reg_sbmm_min_buff 10532 * Minimum buffer size for the limiter, in cells. 10533 * Access: RW 10534 */ 10535 MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24); 10536 10537 /* reg_sbmm_max_buff 10538 * When the pool associated to the port-pg/tclass is configured to 10539 * static, Maximum buffer size for the limiter configured in cells. 10540 * When the pool associated to the port-pg/tclass is configured to 10541 * dynamic, the max_buff holds the "alpha" parameter, supporting 10542 * the following values: 10543 * 0: 0 10544 * i: (1/128)*2^(i-1), for i=1..14 10545 * 0xFF: Infinity 10546 * Access: RW 10547 */ 10548 MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24); 10549 10550 /* reg_sbmm_pool 10551 * Association of the port-priority to a pool. 10552 * Access: RW 10553 */ 10554 MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4); 10555 10556 static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff, 10557 u32 max_buff, u8 pool) 10558 { 10559 MLXSW_REG_ZERO(sbmm, payload); 10560 mlxsw_reg_sbmm_prio_set(payload, prio); 10561 mlxsw_reg_sbmm_min_buff_set(payload, min_buff); 10562 mlxsw_reg_sbmm_max_buff_set(payload, max_buff); 10563 mlxsw_reg_sbmm_pool_set(payload, pool); 10564 } 10565 10566 /* SBSR - Shared Buffer Status Register 10567 * ------------------------------------ 10568 * The SBSR register retrieves the shared buffer occupancy according to 10569 * Port-Pool. Note that this register enables reading a large amount of data. 10570 * It is the user's responsibility to limit the amount of data to ensure the 10571 * response can match the maximum transfer unit. In case the response exceeds 10572 * the maximum transport unit, it will be truncated with no special notice. 10573 */ 10574 #define MLXSW_REG_SBSR_ID 0xB005 10575 #define MLXSW_REG_SBSR_BASE_LEN 0x5C /* base length, without records */ 10576 #define MLXSW_REG_SBSR_REC_LEN 0x8 /* record length */ 10577 #define MLXSW_REG_SBSR_REC_MAX_COUNT 120 10578 #define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \ 10579 MLXSW_REG_SBSR_REC_LEN * \ 10580 MLXSW_REG_SBSR_REC_MAX_COUNT) 10581 10582 MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN); 10583 10584 /* reg_sbsr_clr 10585 * Clear Max Buffer Occupancy. When this bit is set, the max_buff_occupancy 10586 * field is cleared (and a new max value is tracked from the time the clear 10587 * was performed). 10588 * Access: OP 10589 */ 10590 MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1); 10591 10592 /* reg_sbsr_ingress_port_mask 10593 * Bit vector for all ingress network ports. 10594 * Indicates which of the ports (for which the relevant bit is set) 10595 * are affected by the set operation. Configuration of any other port 10596 * does not change. 10597 * Access: Index 10598 */ 10599 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1); 10600 10601 /* reg_sbsr_pg_buff_mask 10602 * Bit vector for all switch priority groups. 10603 * Indicates which of the priorities (for which the relevant bit is set) 10604 * are affected by the set operation. Configuration of any other priority 10605 * does not change. 10606 * Range is 0..cap_max_pg_buffers - 1 10607 * Access: Index 10608 */ 10609 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1); 10610 10611 /* reg_sbsr_egress_port_mask 10612 * Bit vector for all egress network ports. 10613 * Indicates which of the ports (for which the relevant bit is set) 10614 * are affected by the set operation. Configuration of any other port 10615 * does not change. 10616 * Access: Index 10617 */ 10618 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1); 10619 10620 /* reg_sbsr_tclass_mask 10621 * Bit vector for all traffic classes. 10622 * Indicates which of the traffic classes (for which the relevant bit is 10623 * set) are affected by the set operation. Configuration of any other 10624 * traffic class does not change. 10625 * Range is 0..cap_max_tclass - 1 10626 * Access: Index 10627 */ 10628 MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1); 10629 10630 static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr) 10631 { 10632 MLXSW_REG_ZERO(sbsr, payload); 10633 mlxsw_reg_sbsr_clr_set(payload, clr); 10634 } 10635 10636 /* reg_sbsr_rec_buff_occupancy 10637 * Current buffer occupancy in cells. 10638 * Access: RO 10639 */ 10640 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 10641 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false); 10642 10643 /* reg_sbsr_rec_max_buff_occupancy 10644 * Maximum value of buffer occupancy in cells monitored. Cleared by 10645 * writing to the clr field. 10646 * Access: RO 10647 */ 10648 MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN, 10649 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false); 10650 10651 static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index, 10652 u32 *p_buff_occupancy, 10653 u32 *p_max_buff_occupancy) 10654 { 10655 *p_buff_occupancy = 10656 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index); 10657 *p_max_buff_occupancy = 10658 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index); 10659 } 10660 10661 /* SBIB - Shared Buffer Internal Buffer Register 10662 * --------------------------------------------- 10663 * The SBIB register configures per port buffers for internal use. The internal 10664 * buffers consume memory on the port buffers (note that the port buffers are 10665 * used also by PBMC). 10666 * 10667 * For Spectrum this is used for egress mirroring. 10668 */ 10669 #define MLXSW_REG_SBIB_ID 0xB006 10670 #define MLXSW_REG_SBIB_LEN 0x10 10671 10672 MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN); 10673 10674 /* reg_sbib_local_port 10675 * Local port number 10676 * Not supported for CPU port and router port 10677 * Access: Index 10678 */ 10679 MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8); 10680 10681 /* reg_sbib_buff_size 10682 * Units represented in cells 10683 * Allowed range is 0 to (cap_max_headroom_size - 1) 10684 * Default is 0 10685 * Access: RW 10686 */ 10687 MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24); 10688 10689 static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port, 10690 u32 buff_size) 10691 { 10692 MLXSW_REG_ZERO(sbib, payload); 10693 mlxsw_reg_sbib_local_port_set(payload, local_port); 10694 mlxsw_reg_sbib_buff_size_set(payload, buff_size); 10695 } 10696 10697 static const struct mlxsw_reg_info *mlxsw_reg_infos[] = { 10698 MLXSW_REG(sgcr), 10699 MLXSW_REG(spad), 10700 MLXSW_REG(smid), 10701 MLXSW_REG(sspr), 10702 MLXSW_REG(sfdat), 10703 MLXSW_REG(sfd), 10704 MLXSW_REG(sfn), 10705 MLXSW_REG(spms), 10706 MLXSW_REG(spvid), 10707 MLXSW_REG(spvm), 10708 MLXSW_REG(spaft), 10709 MLXSW_REG(sfgc), 10710 MLXSW_REG(sftr), 10711 MLXSW_REG(sfdf), 10712 MLXSW_REG(sldr), 10713 MLXSW_REG(slcr), 10714 MLXSW_REG(slcor), 10715 MLXSW_REG(spmlr), 10716 MLXSW_REG(svfa), 10717 MLXSW_REG(svpe), 10718 MLXSW_REG(sfmr), 10719 MLXSW_REG(spvmlr), 10720 MLXSW_REG(cwtp), 10721 MLXSW_REG(cwtpm), 10722 MLXSW_REG(pgcr), 10723 MLXSW_REG(ppbt), 10724 MLXSW_REG(pacl), 10725 MLXSW_REG(pagt), 10726 MLXSW_REG(ptar), 10727 MLXSW_REG(ppbs), 10728 MLXSW_REG(prcr), 10729 MLXSW_REG(pefa), 10730 MLXSW_REG(pemrbt), 10731 MLXSW_REG(ptce2), 10732 MLXSW_REG(perpt), 10733 MLXSW_REG(peabfe), 10734 MLXSW_REG(perar), 10735 MLXSW_REG(ptce3), 10736 MLXSW_REG(percr), 10737 MLXSW_REG(pererp), 10738 MLXSW_REG(iedr), 10739 MLXSW_REG(qpts), 10740 MLXSW_REG(qpcr), 10741 MLXSW_REG(qtct), 10742 MLXSW_REG(qeec), 10743 MLXSW_REG(qrwe), 10744 MLXSW_REG(qpdsm), 10745 MLXSW_REG(qpdp), 10746 MLXSW_REG(qpdpm), 10747 MLXSW_REG(qtctm), 10748 MLXSW_REG(qpsc), 10749 MLXSW_REG(pmlp), 10750 MLXSW_REG(pmtu), 10751 MLXSW_REG(ptys), 10752 MLXSW_REG(ppad), 10753 MLXSW_REG(paos), 10754 MLXSW_REG(pfcc), 10755 MLXSW_REG(ppcnt), 10756 MLXSW_REG(plib), 10757 MLXSW_REG(pptb), 10758 MLXSW_REG(pbmc), 10759 MLXSW_REG(pspa), 10760 MLXSW_REG(pplr), 10761 MLXSW_REG(pmtm), 10762 MLXSW_REG(htgt), 10763 MLXSW_REG(hpkt), 10764 MLXSW_REG(rgcr), 10765 MLXSW_REG(ritr), 10766 MLXSW_REG(rtar), 10767 MLXSW_REG(ratr), 10768 MLXSW_REG(rtdp), 10769 MLXSW_REG(rdpm), 10770 MLXSW_REG(ricnt), 10771 MLXSW_REG(rrcr), 10772 MLXSW_REG(ralta), 10773 MLXSW_REG(ralst), 10774 MLXSW_REG(raltb), 10775 MLXSW_REG(ralue), 10776 MLXSW_REG(rauht), 10777 MLXSW_REG(raleu), 10778 MLXSW_REG(rauhtd), 10779 MLXSW_REG(rigr2), 10780 MLXSW_REG(recr2), 10781 MLXSW_REG(rmft2), 10782 MLXSW_REG(mfcr), 10783 MLXSW_REG(mfsc), 10784 MLXSW_REG(mfsm), 10785 MLXSW_REG(mfsl), 10786 MLXSW_REG(fore), 10787 MLXSW_REG(mtcap), 10788 MLXSW_REG(mtmp), 10789 MLXSW_REG(mtbr), 10790 MLXSW_REG(mcia), 10791 MLXSW_REG(mpat), 10792 MLXSW_REG(mpar), 10793 MLXSW_REG(mgir), 10794 MLXSW_REG(mrsr), 10795 MLXSW_REG(mlcr), 10796 MLXSW_REG(mtpps), 10797 MLXSW_REG(mtutc), 10798 MLXSW_REG(mpsc), 10799 MLXSW_REG(mcqi), 10800 MLXSW_REG(mcc), 10801 MLXSW_REG(mcda), 10802 MLXSW_REG(mgpc), 10803 MLXSW_REG(mprs), 10804 MLXSW_REG(mogcr), 10805 MLXSW_REG(mtpppc), 10806 MLXSW_REG(mtpptr), 10807 MLXSW_REG(mtptpt), 10808 MLXSW_REG(mgpir), 10809 MLXSW_REG(tngcr), 10810 MLXSW_REG(tnumt), 10811 MLXSW_REG(tnqcr), 10812 MLXSW_REG(tnqdr), 10813 MLXSW_REG(tneem), 10814 MLXSW_REG(tndem), 10815 MLXSW_REG(tnpc), 10816 MLXSW_REG(tigcr), 10817 MLXSW_REG(tieem), 10818 MLXSW_REG(tidem), 10819 MLXSW_REG(sbpr), 10820 MLXSW_REG(sbcm), 10821 MLXSW_REG(sbpm), 10822 MLXSW_REG(sbmm), 10823 MLXSW_REG(sbsr), 10824 MLXSW_REG(sbib), 10825 }; 10826 10827 static inline const char *mlxsw_reg_id_str(u16 reg_id) 10828 { 10829 const struct mlxsw_reg_info *reg_info; 10830 int i; 10831 10832 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) { 10833 reg_info = mlxsw_reg_infos[i]; 10834 if (reg_info->id == reg_id) 10835 return reg_info->name; 10836 } 10837 return "*UNKNOWN*"; 10838 } 10839 10840 /* PUDE - Port Up / Down Event 10841 * --------------------------- 10842 * Reports the operational state change of a port. 10843 */ 10844 #define MLXSW_REG_PUDE_LEN 0x10 10845 10846 /* reg_pude_swid 10847 * Switch partition ID with which to associate the port. 10848 * Access: Index 10849 */ 10850 MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8); 10851 10852 /* reg_pude_local_port 10853 * Local port number. 10854 * Access: Index 10855 */ 10856 MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8); 10857 10858 /* reg_pude_admin_status 10859 * Port administrative state (the desired state). 10860 * 1 - Up. 10861 * 2 - Down. 10862 * 3 - Up once. This means that in case of link failure, the port won't go 10863 * into polling mode, but will wait to be re-enabled by software. 10864 * 4 - Disabled by system. Can only be set by hardware. 10865 * Access: RO 10866 */ 10867 MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4); 10868 10869 /* reg_pude_oper_status 10870 * Port operatioanl state. 10871 * 1 - Up. 10872 * 2 - Down. 10873 * 3 - Down by port failure. This means that the device will not let the 10874 * port up again until explicitly specified by software. 10875 * Access: RO 10876 */ 10877 MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4); 10878 10879 #endif 10880