1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Driver for PowerMac Z85c30 based ESCC cell found in the 4 * "macio" ASICs of various PowerMac models 5 * 6 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org) 7 * 8 * Derived from drivers/macintosh/macserial.c by Paul Mackerras 9 * and drivers/serial/sunzilog.c by David S. Miller 10 * 11 * Hrm... actually, I ripped most of sunzilog (Thanks David !) and 12 * adapted special tweaks needed for us. I don't think it's worth 13 * merging back those though. The DMA code still has to get in 14 * and once done, I expect that driver to remain fairly stable in 15 * the long term, unless we change the driver model again... 16 * 17 * 2004-08-06 Harald Welte <laforge@gnumonks.org> 18 * - Enable BREAK interrupt 19 * - Add support for sysreq 20 * 21 * TODO: - Add DMA support 22 * - Defer port shutdown to a few seconds after close 23 * - maybe put something right into uap->clk_divisor 24 */ 25 26 #undef DEBUG 27 #undef DEBUG_HARD 28 #undef USE_CTRL_O_SYSRQ 29 30 #include <linux/module.h> 31 #include <linux/tty.h> 32 33 #include <linux/tty_flip.h> 34 #include <linux/major.h> 35 #include <linux/string.h> 36 #include <linux/fcntl.h> 37 #include <linux/mm.h> 38 #include <linux/kernel.h> 39 #include <linux/delay.h> 40 #include <linux/init.h> 41 #include <linux/console.h> 42 #include <linux/adb.h> 43 #include <linux/pmu.h> 44 #include <linux/bitops.h> 45 #include <linux/sysrq.h> 46 #include <linux/mutex.h> 47 #include <linux/of_address.h> 48 #include <linux/of_irq.h> 49 #include <asm/sections.h> 50 #include <asm/io.h> 51 #include <asm/irq.h> 52 53 #ifdef CONFIG_PPC_PMAC 54 #include <asm/prom.h> 55 #include <asm/machdep.h> 56 #include <asm/pmac_feature.h> 57 #include <asm/dbdma.h> 58 #include <asm/macio.h> 59 #else 60 #include <linux/platform_device.h> 61 #define of_machine_is_compatible(x) (0) 62 #endif 63 64 #include <linux/serial.h> 65 #include <linux/serial_core.h> 66 67 #include "pmac_zilog.h" 68 69 /* Not yet implemented */ 70 #undef HAS_DBDMA 71 72 static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)"; 73 MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>"); 74 MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports."); 75 MODULE_LICENSE("GPL"); 76 77 #ifdef CONFIG_SERIAL_PMACZILOG_TTYS 78 #define PMACZILOG_MAJOR TTY_MAJOR 79 #define PMACZILOG_MINOR 64 80 #define PMACZILOG_NAME "ttyS" 81 #else 82 #define PMACZILOG_MAJOR 204 83 #define PMACZILOG_MINOR 192 84 #define PMACZILOG_NAME "ttyPZ" 85 #endif 86 87 #define pmz_debug(fmt, arg...) pr_debug("ttyPZ%d: " fmt, uap->port.line, ## arg) 88 #define pmz_error(fmt, arg...) pr_err("ttyPZ%d: " fmt, uap->port.line, ## arg) 89 #define pmz_info(fmt, arg...) pr_info("ttyPZ%d: " fmt, uap->port.line, ## arg) 90 91 /* 92 * For the sake of early serial console, we can do a pre-probe 93 * (optional) of the ports at rather early boot time. 94 */ 95 static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS]; 96 static int pmz_ports_count; 97 98 static struct uart_driver pmz_uart_reg = { 99 .owner = THIS_MODULE, 100 .driver_name = PMACZILOG_NAME, 101 .dev_name = PMACZILOG_NAME, 102 .major = PMACZILOG_MAJOR, 103 .minor = PMACZILOG_MINOR, 104 }; 105 106 107 /* 108 * Load all registers to reprogram the port 109 * This function must only be called when the TX is not busy. The UART 110 * port lock must be held and local interrupts disabled. 111 */ 112 static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) 113 { 114 int i; 115 116 /* Let pending transmits finish. */ 117 for (i = 0; i < 1000; i++) { 118 unsigned char stat = read_zsreg(uap, R1); 119 if (stat & ALL_SNT) 120 break; 121 udelay(100); 122 } 123 124 ZS_CLEARERR(uap); 125 zssync(uap); 126 ZS_CLEARFIFO(uap); 127 zssync(uap); 128 ZS_CLEARERR(uap); 129 130 /* Disable all interrupts. */ 131 write_zsreg(uap, R1, 132 regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); 133 134 /* Set parity, sync config, stop bits, and clock divisor. */ 135 write_zsreg(uap, R4, regs[R4]); 136 137 /* Set misc. TX/RX control bits. */ 138 write_zsreg(uap, R10, regs[R10]); 139 140 /* Set TX/RX controls sans the enable bits. */ 141 write_zsreg(uap, R3, regs[R3] & ~RxENABLE); 142 write_zsreg(uap, R5, regs[R5] & ~TxENABLE); 143 144 /* now set R7 "prime" on ESCC */ 145 write_zsreg(uap, R15, regs[R15] | EN85C30); 146 write_zsreg(uap, R7, regs[R7P]); 147 148 /* make sure we use R7 "non-prime" on ESCC */ 149 write_zsreg(uap, R15, regs[R15] & ~EN85C30); 150 151 /* Synchronous mode config. */ 152 write_zsreg(uap, R6, regs[R6]); 153 write_zsreg(uap, R7, regs[R7]); 154 155 /* Disable baud generator. */ 156 write_zsreg(uap, R14, regs[R14] & ~BRENAB); 157 158 /* Clock mode control. */ 159 write_zsreg(uap, R11, regs[R11]); 160 161 /* Lower and upper byte of baud rate generator divisor. */ 162 write_zsreg(uap, R12, regs[R12]); 163 write_zsreg(uap, R13, regs[R13]); 164 165 /* Now rewrite R14, with BRENAB (if set). */ 166 write_zsreg(uap, R14, regs[R14]); 167 168 /* Reset external status interrupts. */ 169 write_zsreg(uap, R0, RES_EXT_INT); 170 write_zsreg(uap, R0, RES_EXT_INT); 171 172 /* Rewrite R3/R5, this time without enables masked. */ 173 write_zsreg(uap, R3, regs[R3]); 174 write_zsreg(uap, R5, regs[R5]); 175 176 /* Rewrite R1, this time without IRQ enabled masked. */ 177 write_zsreg(uap, R1, regs[R1]); 178 179 /* Enable interrupts */ 180 write_zsreg(uap, R9, regs[R9]); 181 } 182 183 /* 184 * We do like sunzilog to avoid disrupting pending Tx 185 * Reprogram the Zilog channel HW registers with the copies found in the 186 * software state struct. If the transmitter is busy, we defer this update 187 * until the next TX complete interrupt. Else, we do it right now. 188 * 189 * The UART port lock must be held and local interrupts disabled. 190 */ 191 static void pmz_maybe_update_regs(struct uart_pmac_port *uap) 192 { 193 if (!ZS_REGS_HELD(uap)) { 194 if (ZS_TX_ACTIVE(uap)) { 195 uap->flags |= PMACZILOG_FLAG_REGS_HELD; 196 } else { 197 pmz_debug("pmz: maybe_update_regs: updating\n"); 198 pmz_load_zsregs(uap, uap->curregs); 199 } 200 } 201 } 202 203 static void pmz_interrupt_control(struct uart_pmac_port *uap, int enable) 204 { 205 if (enable) { 206 uap->curregs[1] |= INT_ALL_Rx | TxINT_ENAB; 207 if (!ZS_IS_EXTCLK(uap)) 208 uap->curregs[1] |= EXT_INT_ENAB; 209 } else { 210 uap->curregs[1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); 211 } 212 write_zsreg(uap, R1, uap->curregs[1]); 213 } 214 215 static bool pmz_receive_chars(struct uart_pmac_port *uap) 216 { 217 struct tty_port *port; 218 unsigned char ch, r1, drop, flag; 219 int loops = 0; 220 221 /* Sanity check, make sure the old bug is no longer happening */ 222 if (uap->port.state == NULL) { 223 WARN_ON(1); 224 (void)read_zsdata(uap); 225 return false; 226 } 227 port = &uap->port.state->port; 228 229 while (1) { 230 drop = 0; 231 232 r1 = read_zsreg(uap, R1); 233 ch = read_zsdata(uap); 234 235 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { 236 write_zsreg(uap, R0, ERR_RES); 237 zssync(uap); 238 } 239 240 ch &= uap->parity_mask; 241 if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) { 242 uap->flags &= ~PMACZILOG_FLAG_BREAK; 243 } 244 245 #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE) 246 #ifdef USE_CTRL_O_SYSRQ 247 /* Handle the SysRq ^O Hack */ 248 if (ch == '\x0f') { 249 uap->port.sysrq = jiffies + HZ*5; 250 goto next_char; 251 } 252 #endif /* USE_CTRL_O_SYSRQ */ 253 if (uap->port.sysrq) { 254 int swallow; 255 spin_unlock(&uap->port.lock); 256 swallow = uart_handle_sysrq_char(&uap->port, ch); 257 spin_lock(&uap->port.lock); 258 if (swallow) 259 goto next_char; 260 } 261 #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */ 262 263 /* A real serial line, record the character and status. */ 264 if (drop) 265 goto next_char; 266 267 flag = TTY_NORMAL; 268 uap->port.icount.rx++; 269 270 if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) { 271 if (r1 & BRK_ABRT) { 272 pmz_debug("pmz: got break !\n"); 273 r1 &= ~(PAR_ERR | CRC_ERR); 274 uap->port.icount.brk++; 275 if (uart_handle_break(&uap->port)) 276 goto next_char; 277 } 278 else if (r1 & PAR_ERR) 279 uap->port.icount.parity++; 280 else if (r1 & CRC_ERR) 281 uap->port.icount.frame++; 282 if (r1 & Rx_OVR) 283 uap->port.icount.overrun++; 284 r1 &= uap->port.read_status_mask; 285 if (r1 & BRK_ABRT) 286 flag = TTY_BREAK; 287 else if (r1 & PAR_ERR) 288 flag = TTY_PARITY; 289 else if (r1 & CRC_ERR) 290 flag = TTY_FRAME; 291 } 292 293 if (uap->port.ignore_status_mask == 0xff || 294 (r1 & uap->port.ignore_status_mask) == 0) { 295 tty_insert_flip_char(port, ch, flag); 296 } 297 if (r1 & Rx_OVR) 298 tty_insert_flip_char(port, 0, TTY_OVERRUN); 299 next_char: 300 /* We can get stuck in an infinite loop getting char 0 when the 301 * line is in a wrong HW state, we break that here. 302 * When that happens, I disable the receive side of the driver. 303 * Note that what I've been experiencing is a real irq loop where 304 * I'm getting flooded regardless of the actual port speed. 305 * Something strange is going on with the HW 306 */ 307 if ((++loops) > 1000) 308 goto flood; 309 ch = read_zsreg(uap, R0); 310 if (!(ch & Rx_CH_AV)) 311 break; 312 } 313 314 return true; 315 flood: 316 pmz_interrupt_control(uap, 0); 317 pmz_error("pmz: rx irq flood !\n"); 318 return true; 319 } 320 321 static void pmz_status_handle(struct uart_pmac_port *uap) 322 { 323 unsigned char status; 324 325 status = read_zsreg(uap, R0); 326 write_zsreg(uap, R0, RES_EXT_INT); 327 zssync(uap); 328 329 if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) { 330 if (status & SYNC_HUNT) 331 uap->port.icount.dsr++; 332 333 /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. 334 * But it does not tell us which bit has changed, we have to keep 335 * track of this ourselves. 336 * The CTS input is inverted for some reason. -- paulus 337 */ 338 if ((status ^ uap->prev_status) & DCD) 339 uart_handle_dcd_change(&uap->port, 340 (status & DCD)); 341 if ((status ^ uap->prev_status) & CTS) 342 uart_handle_cts_change(&uap->port, 343 !(status & CTS)); 344 345 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 346 } 347 348 if (status & BRK_ABRT) 349 uap->flags |= PMACZILOG_FLAG_BREAK; 350 351 uap->prev_status = status; 352 } 353 354 static void pmz_transmit_chars(struct uart_pmac_port *uap) 355 { 356 struct circ_buf *xmit; 357 358 if (ZS_IS_CONS(uap)) { 359 unsigned char status = read_zsreg(uap, R0); 360 361 /* TX still busy? Just wait for the next TX done interrupt. 362 * 363 * It can occur because of how we do serial console writes. It would 364 * be nice to transmit console writes just like we normally would for 365 * a TTY line. (ie. buffered and TX interrupt driven). That is not 366 * easy because console writes cannot sleep. One solution might be 367 * to poll on enough port->xmit space becoming free. -DaveM 368 */ 369 if (!(status & Tx_BUF_EMP)) 370 return; 371 } 372 373 uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE; 374 375 if (ZS_REGS_HELD(uap)) { 376 pmz_load_zsregs(uap, uap->curregs); 377 uap->flags &= ~PMACZILOG_FLAG_REGS_HELD; 378 } 379 380 if (ZS_TX_STOPPED(uap)) { 381 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 382 goto ack_tx_int; 383 } 384 385 /* Under some circumstances, we see interrupts reported for 386 * a closed channel. The interrupt mask in R1 is clear, but 387 * R3 still signals the interrupts and we see them when taking 388 * an interrupt for the other channel (this could be a qemu 389 * bug but since the ESCC doc doesn't specify precsiely whether 390 * R3 interrup status bits are masked by R1 interrupt enable 391 * bits, better safe than sorry). --BenH. 392 */ 393 if (!ZS_IS_OPEN(uap)) 394 goto ack_tx_int; 395 396 if (uap->port.x_char) { 397 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 398 write_zsdata(uap, uap->port.x_char); 399 zssync(uap); 400 uap->port.icount.tx++; 401 uap->port.x_char = 0; 402 return; 403 } 404 405 if (uap->port.state == NULL) 406 goto ack_tx_int; 407 xmit = &uap->port.state->xmit; 408 if (uart_circ_empty(xmit)) { 409 uart_write_wakeup(&uap->port); 410 goto ack_tx_int; 411 } 412 if (uart_tx_stopped(&uap->port)) 413 goto ack_tx_int; 414 415 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 416 write_zsdata(uap, xmit->buf[xmit->tail]); 417 zssync(uap); 418 419 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 420 uap->port.icount.tx++; 421 422 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 423 uart_write_wakeup(&uap->port); 424 425 return; 426 427 ack_tx_int: 428 write_zsreg(uap, R0, RES_Tx_P); 429 zssync(uap); 430 } 431 432 /* Hrm... we register that twice, fixme later.... */ 433 static irqreturn_t pmz_interrupt(int irq, void *dev_id) 434 { 435 struct uart_pmac_port *uap = dev_id; 436 struct uart_pmac_port *uap_a; 437 struct uart_pmac_port *uap_b; 438 int rc = IRQ_NONE; 439 bool push; 440 u8 r3; 441 442 uap_a = pmz_get_port_A(uap); 443 uap_b = uap_a->mate; 444 445 spin_lock(&uap_a->port.lock); 446 r3 = read_zsreg(uap_a, R3); 447 448 #ifdef DEBUG_HARD 449 pmz_debug("irq, r3: %x\n", r3); 450 #endif 451 /* Channel A */ 452 push = false; 453 if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { 454 if (!ZS_IS_OPEN(uap_a)) { 455 pmz_debug("ChanA interrupt while not open !\n"); 456 goto skip_a; 457 } 458 write_zsreg(uap_a, R0, RES_H_IUS); 459 zssync(uap_a); 460 if (r3 & CHAEXT) 461 pmz_status_handle(uap_a); 462 if (r3 & CHARxIP) 463 push = pmz_receive_chars(uap_a); 464 if (r3 & CHATxIP) 465 pmz_transmit_chars(uap_a); 466 rc = IRQ_HANDLED; 467 } 468 skip_a: 469 spin_unlock(&uap_a->port.lock); 470 if (push) 471 tty_flip_buffer_push(&uap->port.state->port); 472 473 if (!uap_b) 474 goto out; 475 476 spin_lock(&uap_b->port.lock); 477 push = false; 478 if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { 479 if (!ZS_IS_OPEN(uap_b)) { 480 pmz_debug("ChanB interrupt while not open !\n"); 481 goto skip_b; 482 } 483 write_zsreg(uap_b, R0, RES_H_IUS); 484 zssync(uap_b); 485 if (r3 & CHBEXT) 486 pmz_status_handle(uap_b); 487 if (r3 & CHBRxIP) 488 push = pmz_receive_chars(uap_b); 489 if (r3 & CHBTxIP) 490 pmz_transmit_chars(uap_b); 491 rc = IRQ_HANDLED; 492 } 493 skip_b: 494 spin_unlock(&uap_b->port.lock); 495 if (push) 496 tty_flip_buffer_push(&uap->port.state->port); 497 498 out: 499 return rc; 500 } 501 502 /* 503 * Peek the status register, lock not held by caller 504 */ 505 static inline u8 pmz_peek_status(struct uart_pmac_port *uap) 506 { 507 unsigned long flags; 508 u8 status; 509 510 spin_lock_irqsave(&uap->port.lock, flags); 511 status = read_zsreg(uap, R0); 512 spin_unlock_irqrestore(&uap->port.lock, flags); 513 514 return status; 515 } 516 517 /* 518 * Check if transmitter is empty 519 * The port lock is not held. 520 */ 521 static unsigned int pmz_tx_empty(struct uart_port *port) 522 { 523 unsigned char status; 524 525 status = pmz_peek_status(to_pmz(port)); 526 if (status & Tx_BUF_EMP) 527 return TIOCSER_TEMT; 528 return 0; 529 } 530 531 /* 532 * Set Modem Control (RTS & DTR) bits 533 * The port lock is held and interrupts are disabled. 534 * Note: Shall we really filter out RTS on external ports or 535 * should that be dealt at higher level only ? 536 */ 537 static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl) 538 { 539 struct uart_pmac_port *uap = to_pmz(port); 540 unsigned char set_bits, clear_bits; 541 542 /* Do nothing for irda for now... */ 543 if (ZS_IS_IRDA(uap)) 544 return; 545 /* We get called during boot with a port not up yet */ 546 if (!(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap))) 547 return; 548 549 set_bits = clear_bits = 0; 550 551 if (ZS_IS_INTMODEM(uap)) { 552 if (mctrl & TIOCM_RTS) 553 set_bits |= RTS; 554 else 555 clear_bits |= RTS; 556 } 557 if (mctrl & TIOCM_DTR) 558 set_bits |= DTR; 559 else 560 clear_bits |= DTR; 561 562 /* NOTE: Not subject to 'transmitter active' rule. */ 563 uap->curregs[R5] |= set_bits; 564 uap->curregs[R5] &= ~clear_bits; 565 566 write_zsreg(uap, R5, uap->curregs[R5]); 567 pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n", 568 set_bits, clear_bits, uap->curregs[R5]); 569 zssync(uap); 570 } 571 572 /* 573 * Get Modem Control bits (only the input ones, the core will 574 * or that with a cached value of the control ones) 575 * The port lock is held and interrupts are disabled. 576 */ 577 static unsigned int pmz_get_mctrl(struct uart_port *port) 578 { 579 struct uart_pmac_port *uap = to_pmz(port); 580 unsigned char status; 581 unsigned int ret; 582 583 status = read_zsreg(uap, R0); 584 585 ret = 0; 586 if (status & DCD) 587 ret |= TIOCM_CAR; 588 if (status & SYNC_HUNT) 589 ret |= TIOCM_DSR; 590 if (!(status & CTS)) 591 ret |= TIOCM_CTS; 592 593 return ret; 594 } 595 596 /* 597 * Stop TX side. Dealt like sunzilog at next Tx interrupt, 598 * though for DMA, we will have to do a bit more. 599 * The port lock is held and interrupts are disabled. 600 */ 601 static void pmz_stop_tx(struct uart_port *port) 602 { 603 to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED; 604 } 605 606 /* 607 * Kick the Tx side. 608 * The port lock is held and interrupts are disabled. 609 */ 610 static void pmz_start_tx(struct uart_port *port) 611 { 612 struct uart_pmac_port *uap = to_pmz(port); 613 unsigned char status; 614 615 pmz_debug("pmz: start_tx()\n"); 616 617 uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; 618 uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; 619 620 status = read_zsreg(uap, R0); 621 622 /* TX busy? Just wait for the TX done interrupt. */ 623 if (!(status & Tx_BUF_EMP)) 624 return; 625 626 /* Send the first character to jump-start the TX done 627 * IRQ sending engine. 628 */ 629 if (port->x_char) { 630 write_zsdata(uap, port->x_char); 631 zssync(uap); 632 port->icount.tx++; 633 port->x_char = 0; 634 } else { 635 struct circ_buf *xmit = &port->state->xmit; 636 637 if (uart_circ_empty(xmit)) 638 goto out; 639 write_zsdata(uap, xmit->buf[xmit->tail]); 640 zssync(uap); 641 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 642 port->icount.tx++; 643 644 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 645 uart_write_wakeup(&uap->port); 646 } 647 out: 648 pmz_debug("pmz: start_tx() done.\n"); 649 } 650 651 /* 652 * Stop Rx side, basically disable emitting of 653 * Rx interrupts on the port. We don't disable the rx 654 * side of the chip proper though 655 * The port lock is held. 656 */ 657 static void pmz_stop_rx(struct uart_port *port) 658 { 659 struct uart_pmac_port *uap = to_pmz(port); 660 661 pmz_debug("pmz: stop_rx()()\n"); 662 663 /* Disable all RX interrupts. */ 664 uap->curregs[R1] &= ~RxINT_MASK; 665 pmz_maybe_update_regs(uap); 666 667 pmz_debug("pmz: stop_rx() done.\n"); 668 } 669 670 /* 671 * Enable modem status change interrupts 672 * The port lock is held. 673 */ 674 static void pmz_enable_ms(struct uart_port *port) 675 { 676 struct uart_pmac_port *uap = to_pmz(port); 677 unsigned char new_reg; 678 679 if (ZS_IS_IRDA(uap)) 680 return; 681 new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); 682 if (new_reg != uap->curregs[R15]) { 683 uap->curregs[R15] = new_reg; 684 685 /* NOTE: Not subject to 'transmitter active' rule. */ 686 write_zsreg(uap, R15, uap->curregs[R15]); 687 } 688 } 689 690 /* 691 * Control break state emission 692 * The port lock is not held. 693 */ 694 static void pmz_break_ctl(struct uart_port *port, int break_state) 695 { 696 struct uart_pmac_port *uap = to_pmz(port); 697 unsigned char set_bits, clear_bits, new_reg; 698 unsigned long flags; 699 700 set_bits = clear_bits = 0; 701 702 if (break_state) 703 set_bits |= SND_BRK; 704 else 705 clear_bits |= SND_BRK; 706 707 spin_lock_irqsave(&port->lock, flags); 708 709 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; 710 if (new_reg != uap->curregs[R5]) { 711 uap->curregs[R5] = new_reg; 712 write_zsreg(uap, R5, uap->curregs[R5]); 713 } 714 715 spin_unlock_irqrestore(&port->lock, flags); 716 } 717 718 #ifdef CONFIG_PPC_PMAC 719 720 /* 721 * Turn power on or off to the SCC and associated stuff 722 * (port drivers, modem, IR port, etc.) 723 * Returns the number of milliseconds we should wait before 724 * trying to use the port. 725 */ 726 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) 727 { 728 int delay = 0; 729 int rc; 730 731 if (state) { 732 rc = pmac_call_feature( 733 PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1); 734 pmz_debug("port power on result: %d\n", rc); 735 if (ZS_IS_INTMODEM(uap)) { 736 rc = pmac_call_feature( 737 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1); 738 delay = 2500; /* wait for 2.5s before using */ 739 pmz_debug("modem power result: %d\n", rc); 740 } 741 } else { 742 /* TODO: Make that depend on a timer, don't power down 743 * immediately 744 */ 745 if (ZS_IS_INTMODEM(uap)) { 746 rc = pmac_call_feature( 747 PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0); 748 pmz_debug("port power off result: %d\n", rc); 749 } 750 pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0); 751 } 752 return delay; 753 } 754 755 #else 756 757 static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) 758 { 759 return 0; 760 } 761 762 #endif /* !CONFIG_PPC_PMAC */ 763 764 /* 765 * FixZeroBug....Works around a bug in the SCC receiving channel. 766 * Inspired from Darwin code, 15 Sept. 2000 -DanM 767 * 768 * The following sequence prevents a problem that is seen with O'Hare ASICs 769 * (most versions -- also with some Heathrow and Hydra ASICs) where a zero 770 * at the input to the receiver becomes 'stuck' and locks up the receiver. 771 * This problem can occur as a result of a zero bit at the receiver input 772 * coincident with any of the following events: 773 * 774 * The SCC is initialized (hardware or software). 775 * A framing error is detected. 776 * The clocking option changes from synchronous or X1 asynchronous 777 * clocking to X16, X32, or X64 asynchronous clocking. 778 * The decoding mode is changed among NRZ, NRZI, FM0, or FM1. 779 * 780 * This workaround attempts to recover from the lockup condition by placing 781 * the SCC in synchronous loopback mode with a fast clock before programming 782 * any of the asynchronous modes. 783 */ 784 static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap) 785 { 786 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); 787 zssync(uap); 788 udelay(10); 789 write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV); 790 zssync(uap); 791 792 write_zsreg(uap, 4, X1CLK | MONSYNC); 793 write_zsreg(uap, 3, Rx8); 794 write_zsreg(uap, 5, Tx8 | RTS); 795 write_zsreg(uap, 9, NV); /* Didn't we already do this? */ 796 write_zsreg(uap, 11, RCBR | TCBR); 797 write_zsreg(uap, 12, 0); 798 write_zsreg(uap, 13, 0); 799 write_zsreg(uap, 14, (LOOPBAK | BRSRC)); 800 write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB)); 801 write_zsreg(uap, 3, Rx8 | RxENABLE); 802 write_zsreg(uap, 0, RES_EXT_INT); 803 write_zsreg(uap, 0, RES_EXT_INT); 804 write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */ 805 806 /* The channel should be OK now, but it is probably receiving 807 * loopback garbage. 808 * Switch to asynchronous mode, disable the receiver, 809 * and discard everything in the receive buffer. 810 */ 811 write_zsreg(uap, 9, NV); 812 write_zsreg(uap, 4, X16CLK | SB_MASK); 813 write_zsreg(uap, 3, Rx8); 814 815 while (read_zsreg(uap, 0) & Rx_CH_AV) { 816 (void)read_zsreg(uap, 8); 817 write_zsreg(uap, 0, RES_EXT_INT); 818 write_zsreg(uap, 0, ERR_RES); 819 } 820 } 821 822 /* 823 * Real startup routine, powers up the hardware and sets up 824 * the SCC. Returns a delay in ms where you need to wait before 825 * actually using the port, this is typically the internal modem 826 * powerup delay. This routine expect the lock to be taken. 827 */ 828 static int __pmz_startup(struct uart_pmac_port *uap) 829 { 830 int pwr_delay = 0; 831 832 memset(&uap->curregs, 0, sizeof(uap->curregs)); 833 834 /* Power up the SCC & underlying hardware (modem/irda) */ 835 pwr_delay = pmz_set_scc_power(uap, 1); 836 837 /* Nice buggy HW ... */ 838 pmz_fix_zero_bug_scc(uap); 839 840 /* Reset the channel */ 841 uap->curregs[R9] = 0; 842 write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); 843 zssync(uap); 844 udelay(10); 845 write_zsreg(uap, 9, 0); 846 zssync(uap); 847 848 /* Clear the interrupt registers */ 849 write_zsreg(uap, R1, 0); 850 write_zsreg(uap, R0, ERR_RES); 851 write_zsreg(uap, R0, ERR_RES); 852 write_zsreg(uap, R0, RES_H_IUS); 853 write_zsreg(uap, R0, RES_H_IUS); 854 855 /* Setup some valid baud rate */ 856 uap->curregs[R4] = X16CLK | SB1; 857 uap->curregs[R3] = Rx8; 858 uap->curregs[R5] = Tx8 | RTS; 859 if (!ZS_IS_IRDA(uap)) 860 uap->curregs[R5] |= DTR; 861 uap->curregs[R12] = 0; 862 uap->curregs[R13] = 0; 863 uap->curregs[R14] = BRENAB; 864 865 /* Clear handshaking, enable BREAK interrupts */ 866 uap->curregs[R15] = BRKIE; 867 868 /* Master interrupt enable */ 869 uap->curregs[R9] |= NV | MIE; 870 871 pmz_load_zsregs(uap, uap->curregs); 872 873 /* Enable receiver and transmitter. */ 874 write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE); 875 write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); 876 877 /* Remember status for DCD/CTS changes */ 878 uap->prev_status = read_zsreg(uap, R0); 879 880 return pwr_delay; 881 } 882 883 static void pmz_irda_reset(struct uart_pmac_port *uap) 884 { 885 unsigned long flags; 886 887 spin_lock_irqsave(&uap->port.lock, flags); 888 uap->curregs[R5] |= DTR; 889 write_zsreg(uap, R5, uap->curregs[R5]); 890 zssync(uap); 891 spin_unlock_irqrestore(&uap->port.lock, flags); 892 msleep(110); 893 894 spin_lock_irqsave(&uap->port.lock, flags); 895 uap->curregs[R5] &= ~DTR; 896 write_zsreg(uap, R5, uap->curregs[R5]); 897 zssync(uap); 898 spin_unlock_irqrestore(&uap->port.lock, flags); 899 msleep(10); 900 } 901 902 /* 903 * This is the "normal" startup routine, using the above one 904 * wrapped with the lock and doing a schedule delay 905 */ 906 static int pmz_startup(struct uart_port *port) 907 { 908 struct uart_pmac_port *uap = to_pmz(port); 909 unsigned long flags; 910 int pwr_delay = 0; 911 912 pmz_debug("pmz: startup()\n"); 913 914 uap->flags |= PMACZILOG_FLAG_IS_OPEN; 915 916 /* A console is never powered down. Else, power up and 917 * initialize the chip 918 */ 919 if (!ZS_IS_CONS(uap)) { 920 spin_lock_irqsave(&port->lock, flags); 921 pwr_delay = __pmz_startup(uap); 922 spin_unlock_irqrestore(&port->lock, flags); 923 } 924 sprintf(uap->irq_name, PMACZILOG_NAME"%d", uap->port.line); 925 if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, 926 uap->irq_name, uap)) { 927 pmz_error("Unable to register zs interrupt handler.\n"); 928 pmz_set_scc_power(uap, 0); 929 return -ENXIO; 930 } 931 932 /* Right now, we deal with delay by blocking here, I'll be 933 * smarter later on 934 */ 935 if (pwr_delay != 0) { 936 pmz_debug("pmz: delaying %d ms\n", pwr_delay); 937 msleep(pwr_delay); 938 } 939 940 /* IrDA reset is done now */ 941 if (ZS_IS_IRDA(uap)) 942 pmz_irda_reset(uap); 943 944 /* Enable interrupt requests for the channel */ 945 spin_lock_irqsave(&port->lock, flags); 946 pmz_interrupt_control(uap, 1); 947 spin_unlock_irqrestore(&port->lock, flags); 948 949 pmz_debug("pmz: startup() done.\n"); 950 951 return 0; 952 } 953 954 static void pmz_shutdown(struct uart_port *port) 955 { 956 struct uart_pmac_port *uap = to_pmz(port); 957 unsigned long flags; 958 959 pmz_debug("pmz: shutdown()\n"); 960 961 spin_lock_irqsave(&port->lock, flags); 962 963 /* Disable interrupt requests for the channel */ 964 pmz_interrupt_control(uap, 0); 965 966 if (!ZS_IS_CONS(uap)) { 967 /* Disable receiver and transmitter */ 968 uap->curregs[R3] &= ~RxENABLE; 969 uap->curregs[R5] &= ~TxENABLE; 970 971 /* Disable break assertion */ 972 uap->curregs[R5] &= ~SND_BRK; 973 pmz_maybe_update_regs(uap); 974 } 975 976 spin_unlock_irqrestore(&port->lock, flags); 977 978 /* Release interrupt handler */ 979 free_irq(uap->port.irq, uap); 980 981 spin_lock_irqsave(&port->lock, flags); 982 983 uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; 984 985 if (!ZS_IS_CONS(uap)) 986 pmz_set_scc_power(uap, 0); /* Shut the chip down */ 987 988 spin_unlock_irqrestore(&port->lock, flags); 989 990 pmz_debug("pmz: shutdown() done.\n"); 991 } 992 993 /* Shared by TTY driver and serial console setup. The port lock is held 994 * and local interrupts are disabled. 995 */ 996 static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, 997 unsigned int iflag, unsigned long baud) 998 { 999 int brg; 1000 1001 /* Switch to external clocking for IrDA high clock rates. That 1002 * code could be re-used for Midi interfaces with different 1003 * multipliers 1004 */ 1005 if (baud >= 115200 && ZS_IS_IRDA(uap)) { 1006 uap->curregs[R4] = X1CLK; 1007 uap->curregs[R11] = RCTRxCP | TCTRxCP; 1008 uap->curregs[R14] = 0; /* BRG off */ 1009 uap->curregs[R12] = 0; 1010 uap->curregs[R13] = 0; 1011 uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; 1012 } else { 1013 switch (baud) { 1014 case ZS_CLOCK/16: /* 230400 */ 1015 uap->curregs[R4] = X16CLK; 1016 uap->curregs[R11] = 0; 1017 uap->curregs[R14] = 0; 1018 break; 1019 case ZS_CLOCK/32: /* 115200 */ 1020 uap->curregs[R4] = X32CLK; 1021 uap->curregs[R11] = 0; 1022 uap->curregs[R14] = 0; 1023 break; 1024 default: 1025 uap->curregs[R4] = X16CLK; 1026 uap->curregs[R11] = TCBR | RCBR; 1027 brg = BPS_TO_BRG(baud, ZS_CLOCK / 16); 1028 uap->curregs[R12] = (brg & 255); 1029 uap->curregs[R13] = ((brg >> 8) & 255); 1030 uap->curregs[R14] = BRENAB; 1031 } 1032 uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; 1033 } 1034 1035 /* Character size, stop bits, and parity. */ 1036 uap->curregs[3] &= ~RxN_MASK; 1037 uap->curregs[5] &= ~TxN_MASK; 1038 1039 switch (cflag & CSIZE) { 1040 case CS5: 1041 uap->curregs[3] |= Rx5; 1042 uap->curregs[5] |= Tx5; 1043 uap->parity_mask = 0x1f; 1044 break; 1045 case CS6: 1046 uap->curregs[3] |= Rx6; 1047 uap->curregs[5] |= Tx6; 1048 uap->parity_mask = 0x3f; 1049 break; 1050 case CS7: 1051 uap->curregs[3] |= Rx7; 1052 uap->curregs[5] |= Tx7; 1053 uap->parity_mask = 0x7f; 1054 break; 1055 case CS8: 1056 default: 1057 uap->curregs[3] |= Rx8; 1058 uap->curregs[5] |= Tx8; 1059 uap->parity_mask = 0xff; 1060 break; 1061 } 1062 uap->curregs[4] &= ~(SB_MASK); 1063 if (cflag & CSTOPB) 1064 uap->curregs[4] |= SB2; 1065 else 1066 uap->curregs[4] |= SB1; 1067 if (cflag & PARENB) 1068 uap->curregs[4] |= PAR_ENAB; 1069 else 1070 uap->curregs[4] &= ~PAR_ENAB; 1071 if (!(cflag & PARODD)) 1072 uap->curregs[4] |= PAR_EVEN; 1073 else 1074 uap->curregs[4] &= ~PAR_EVEN; 1075 1076 uap->port.read_status_mask = Rx_OVR; 1077 if (iflag & INPCK) 1078 uap->port.read_status_mask |= CRC_ERR | PAR_ERR; 1079 if (iflag & (IGNBRK | BRKINT | PARMRK)) 1080 uap->port.read_status_mask |= BRK_ABRT; 1081 1082 uap->port.ignore_status_mask = 0; 1083 if (iflag & IGNPAR) 1084 uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; 1085 if (iflag & IGNBRK) { 1086 uap->port.ignore_status_mask |= BRK_ABRT; 1087 if (iflag & IGNPAR) 1088 uap->port.ignore_status_mask |= Rx_OVR; 1089 } 1090 1091 if ((cflag & CREAD) == 0) 1092 uap->port.ignore_status_mask = 0xff; 1093 } 1094 1095 1096 /* 1097 * Set the irda codec on the imac to the specified baud rate. 1098 */ 1099 static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) 1100 { 1101 u8 cmdbyte; 1102 int t, version; 1103 1104 switch (*baud) { 1105 /* SIR modes */ 1106 case 2400: 1107 cmdbyte = 0x53; 1108 break; 1109 case 4800: 1110 cmdbyte = 0x52; 1111 break; 1112 case 9600: 1113 cmdbyte = 0x51; 1114 break; 1115 case 19200: 1116 cmdbyte = 0x50; 1117 break; 1118 case 38400: 1119 cmdbyte = 0x4f; 1120 break; 1121 case 57600: 1122 cmdbyte = 0x4e; 1123 break; 1124 case 115200: 1125 cmdbyte = 0x4d; 1126 break; 1127 /* The FIR modes aren't really supported at this point, how 1128 * do we select the speed ? via the FCR on KeyLargo ? 1129 */ 1130 case 1152000: 1131 cmdbyte = 0; 1132 break; 1133 case 4000000: 1134 cmdbyte = 0; 1135 break; 1136 default: /* 9600 */ 1137 cmdbyte = 0x51; 1138 *baud = 9600; 1139 break; 1140 } 1141 1142 /* Wait for transmitter to drain */ 1143 t = 10000; 1144 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0 1145 || (read_zsreg(uap, R1) & ALL_SNT) == 0) { 1146 if (--t <= 0) { 1147 pmz_error("transmitter didn't drain\n"); 1148 return; 1149 } 1150 udelay(10); 1151 } 1152 1153 /* Drain the receiver too */ 1154 t = 100; 1155 (void)read_zsdata(uap); 1156 (void)read_zsdata(uap); 1157 (void)read_zsdata(uap); 1158 mdelay(10); 1159 while (read_zsreg(uap, R0) & Rx_CH_AV) { 1160 read_zsdata(uap); 1161 mdelay(10); 1162 if (--t <= 0) { 1163 pmz_error("receiver didn't drain\n"); 1164 return; 1165 } 1166 } 1167 1168 /* Switch to command mode */ 1169 uap->curregs[R5] |= DTR; 1170 write_zsreg(uap, R5, uap->curregs[R5]); 1171 zssync(uap); 1172 mdelay(1); 1173 1174 /* Switch SCC to 19200 */ 1175 pmz_convert_to_zs(uap, CS8, 0, 19200); 1176 pmz_load_zsregs(uap, uap->curregs); 1177 mdelay(1); 1178 1179 /* Write get_version command byte */ 1180 write_zsdata(uap, 1); 1181 t = 5000; 1182 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { 1183 if (--t <= 0) { 1184 pmz_error("irda_setup timed out on get_version byte\n"); 1185 goto out; 1186 } 1187 udelay(10); 1188 } 1189 version = read_zsdata(uap); 1190 1191 if (version < 4) { 1192 pmz_info("IrDA: dongle version %d not supported\n", version); 1193 goto out; 1194 } 1195 1196 /* Send speed mode */ 1197 write_zsdata(uap, cmdbyte); 1198 t = 5000; 1199 while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { 1200 if (--t <= 0) { 1201 pmz_error("irda_setup timed out on speed mode byte\n"); 1202 goto out; 1203 } 1204 udelay(10); 1205 } 1206 t = read_zsdata(uap); 1207 if (t != cmdbyte) 1208 pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte); 1209 1210 pmz_info("IrDA setup for %ld bps, dongle version: %d\n", 1211 *baud, version); 1212 1213 (void)read_zsdata(uap); 1214 (void)read_zsdata(uap); 1215 (void)read_zsdata(uap); 1216 1217 out: 1218 /* Switch back to data mode */ 1219 uap->curregs[R5] &= ~DTR; 1220 write_zsreg(uap, R5, uap->curregs[R5]); 1221 zssync(uap); 1222 1223 (void)read_zsdata(uap); 1224 (void)read_zsdata(uap); 1225 (void)read_zsdata(uap); 1226 } 1227 1228 1229 static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios, 1230 struct ktermios *old) 1231 { 1232 struct uart_pmac_port *uap = to_pmz(port); 1233 unsigned long baud; 1234 1235 pmz_debug("pmz: set_termios()\n"); 1236 1237 memcpy(&uap->termios_cache, termios, sizeof(struct ktermios)); 1238 1239 /* XXX Check which revs of machines actually allow 1 and 4Mb speeds 1240 * on the IR dongle. Note that the IRTTY driver currently doesn't know 1241 * about the FIR mode and high speed modes. So these are unused. For 1242 * implementing proper support for these, we should probably add some 1243 * DMA as well, at least on the Rx side, which isn't a simple thing 1244 * at this point. 1245 */ 1246 if (ZS_IS_IRDA(uap)) { 1247 /* Calc baud rate */ 1248 baud = uart_get_baud_rate(port, termios, old, 1200, 4000000); 1249 pmz_debug("pmz: switch IRDA to %ld bauds\n", baud); 1250 /* Cet the irda codec to the right rate */ 1251 pmz_irda_setup(uap, &baud); 1252 /* Set final baud rate */ 1253 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); 1254 pmz_load_zsregs(uap, uap->curregs); 1255 zssync(uap); 1256 } else { 1257 baud = uart_get_baud_rate(port, termios, old, 1200, 230400); 1258 pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); 1259 /* Make sure modem status interrupts are correctly configured */ 1260 if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) { 1261 uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE; 1262 uap->flags |= PMACZILOG_FLAG_MODEM_STATUS; 1263 } else { 1264 uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE); 1265 uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS; 1266 } 1267 1268 /* Load registers to the chip */ 1269 pmz_maybe_update_regs(uap); 1270 } 1271 uart_update_timeout(port, termios->c_cflag, baud); 1272 1273 pmz_debug("pmz: set_termios() done.\n"); 1274 } 1275 1276 /* The port lock is not held. */ 1277 static void pmz_set_termios(struct uart_port *port, struct ktermios *termios, 1278 struct ktermios *old) 1279 { 1280 struct uart_pmac_port *uap = to_pmz(port); 1281 unsigned long flags; 1282 1283 spin_lock_irqsave(&port->lock, flags); 1284 1285 /* Disable IRQs on the port */ 1286 pmz_interrupt_control(uap, 0); 1287 1288 /* Setup new port configuration */ 1289 __pmz_set_termios(port, termios, old); 1290 1291 /* Re-enable IRQs on the port */ 1292 if (ZS_IS_OPEN(uap)) 1293 pmz_interrupt_control(uap, 1); 1294 1295 spin_unlock_irqrestore(&port->lock, flags); 1296 } 1297 1298 static const char *pmz_type(struct uart_port *port) 1299 { 1300 struct uart_pmac_port *uap = to_pmz(port); 1301 1302 if (ZS_IS_IRDA(uap)) 1303 return "Z85c30 ESCC - Infrared port"; 1304 else if (ZS_IS_INTMODEM(uap)) 1305 return "Z85c30 ESCC - Internal modem"; 1306 return "Z85c30 ESCC - Serial port"; 1307 } 1308 1309 /* We do not request/release mappings of the registers here, this 1310 * happens at early serial probe time. 1311 */ 1312 static void pmz_release_port(struct uart_port *port) 1313 { 1314 } 1315 1316 static int pmz_request_port(struct uart_port *port) 1317 { 1318 return 0; 1319 } 1320 1321 /* These do not need to do anything interesting either. */ 1322 static void pmz_config_port(struct uart_port *port, int flags) 1323 { 1324 } 1325 1326 /* We do not support letting the user mess with the divisor, IRQ, etc. */ 1327 static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser) 1328 { 1329 return -EINVAL; 1330 } 1331 1332 #ifdef CONFIG_CONSOLE_POLL 1333 1334 static int pmz_poll_get_char(struct uart_port *port) 1335 { 1336 struct uart_pmac_port *uap = 1337 container_of(port, struct uart_pmac_port, port); 1338 int tries = 2; 1339 1340 while (tries) { 1341 if ((read_zsreg(uap, R0) & Rx_CH_AV) != 0) 1342 return read_zsdata(uap); 1343 if (tries--) 1344 udelay(5); 1345 } 1346 1347 return NO_POLL_CHAR; 1348 } 1349 1350 static void pmz_poll_put_char(struct uart_port *port, unsigned char c) 1351 { 1352 struct uart_pmac_port *uap = 1353 container_of(port, struct uart_pmac_port, port); 1354 1355 /* Wait for the transmit buffer to empty. */ 1356 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) 1357 udelay(5); 1358 write_zsdata(uap, c); 1359 } 1360 1361 #endif /* CONFIG_CONSOLE_POLL */ 1362 1363 static const struct uart_ops pmz_pops = { 1364 .tx_empty = pmz_tx_empty, 1365 .set_mctrl = pmz_set_mctrl, 1366 .get_mctrl = pmz_get_mctrl, 1367 .stop_tx = pmz_stop_tx, 1368 .start_tx = pmz_start_tx, 1369 .stop_rx = pmz_stop_rx, 1370 .enable_ms = pmz_enable_ms, 1371 .break_ctl = pmz_break_ctl, 1372 .startup = pmz_startup, 1373 .shutdown = pmz_shutdown, 1374 .set_termios = pmz_set_termios, 1375 .type = pmz_type, 1376 .release_port = pmz_release_port, 1377 .request_port = pmz_request_port, 1378 .config_port = pmz_config_port, 1379 .verify_port = pmz_verify_port, 1380 #ifdef CONFIG_CONSOLE_POLL 1381 .poll_get_char = pmz_poll_get_char, 1382 .poll_put_char = pmz_poll_put_char, 1383 #endif 1384 }; 1385 1386 #ifdef CONFIG_PPC_PMAC 1387 1388 /* 1389 * Setup one port structure after probing, HW is down at this point, 1390 * Unlike sunzilog, we don't need to pre-init the spinlock as we don't 1391 * register our console before uart_add_one_port() is called 1392 */ 1393 static int __init pmz_init_port(struct uart_pmac_port *uap) 1394 { 1395 struct device_node *np = uap->node; 1396 const char *conn; 1397 const struct slot_names_prop { 1398 int count; 1399 char name[1]; 1400 } *slots; 1401 int len; 1402 struct resource r_ports, r_rxdma, r_txdma; 1403 1404 /* 1405 * Request & map chip registers 1406 */ 1407 if (of_address_to_resource(np, 0, &r_ports)) 1408 return -ENODEV; 1409 uap->port.mapbase = r_ports.start; 1410 uap->port.membase = ioremap(uap->port.mapbase, 0x1000); 1411 1412 uap->control_reg = uap->port.membase; 1413 uap->data_reg = uap->control_reg + 0x10; 1414 1415 /* 1416 * Request & map DBDMA registers 1417 */ 1418 #ifdef HAS_DBDMA 1419 if (of_address_to_resource(np, 1, &r_txdma) == 0 && 1420 of_address_to_resource(np, 2, &r_rxdma) == 0) 1421 uap->flags |= PMACZILOG_FLAG_HAS_DMA; 1422 #else 1423 memset(&r_txdma, 0, sizeof(struct resource)); 1424 memset(&r_rxdma, 0, sizeof(struct resource)); 1425 #endif 1426 if (ZS_HAS_DMA(uap)) { 1427 uap->tx_dma_regs = ioremap(r_txdma.start, 0x100); 1428 if (uap->tx_dma_regs == NULL) { 1429 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; 1430 goto no_dma; 1431 } 1432 uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100); 1433 if (uap->rx_dma_regs == NULL) { 1434 iounmap(uap->tx_dma_regs); 1435 uap->tx_dma_regs = NULL; 1436 uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; 1437 goto no_dma; 1438 } 1439 uap->tx_dma_irq = irq_of_parse_and_map(np, 1); 1440 uap->rx_dma_irq = irq_of_parse_and_map(np, 2); 1441 } 1442 no_dma: 1443 1444 /* 1445 * Detect port type 1446 */ 1447 if (of_device_is_compatible(np, "cobalt")) 1448 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; 1449 conn = of_get_property(np, "AAPL,connector", &len); 1450 if (conn && (strcmp(conn, "infrared") == 0)) 1451 uap->flags |= PMACZILOG_FLAG_IS_IRDA; 1452 uap->port_type = PMAC_SCC_ASYNC; 1453 /* 1999 Powerbook G3 has slot-names property instead */ 1454 slots = of_get_property(np, "slot-names", &len); 1455 if (slots && slots->count > 0) { 1456 if (strcmp(slots->name, "IrDA") == 0) 1457 uap->flags |= PMACZILOG_FLAG_IS_IRDA; 1458 else if (strcmp(slots->name, "Modem") == 0) 1459 uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; 1460 } 1461 if (ZS_IS_IRDA(uap)) 1462 uap->port_type = PMAC_SCC_IRDA; 1463 if (ZS_IS_INTMODEM(uap)) { 1464 struct device_node* i2c_modem = 1465 of_find_node_by_name(NULL, "i2c-modem"); 1466 if (i2c_modem) { 1467 const char* mid = 1468 of_get_property(i2c_modem, "modem-id", NULL); 1469 if (mid) switch(*mid) { 1470 case 0x04 : 1471 case 0x05 : 1472 case 0x07 : 1473 case 0x08 : 1474 case 0x0b : 1475 case 0x0c : 1476 uap->port_type = PMAC_SCC_I2S1; 1477 } 1478 printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n", 1479 mid ? (*mid) : 0); 1480 of_node_put(i2c_modem); 1481 } else { 1482 printk(KERN_INFO "pmac_zilog: serial modem detected\n"); 1483 } 1484 } 1485 1486 /* 1487 * Init remaining bits of "port" structure 1488 */ 1489 uap->port.iotype = UPIO_MEM; 1490 uap->port.irq = irq_of_parse_and_map(np, 0); 1491 uap->port.uartclk = ZS_CLOCK; 1492 uap->port.fifosize = 1; 1493 uap->port.ops = &pmz_pops; 1494 uap->port.type = PORT_PMAC_ZILOG; 1495 uap->port.flags = 0; 1496 1497 /* 1498 * Fixup for the port on Gatwick for which the device-tree has 1499 * missing interrupts. Normally, the macio_dev would contain 1500 * fixed up interrupt info, but we use the device-tree directly 1501 * here due to early probing so we need the fixup too. 1502 */ 1503 if (uap->port.irq == 0 && 1504 np->parent && np->parent->parent && 1505 of_device_is_compatible(np->parent->parent, "gatwick")) { 1506 /* IRQs on gatwick are offset by 64 */ 1507 uap->port.irq = irq_create_mapping(NULL, 64 + 15); 1508 uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4); 1509 uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5); 1510 } 1511 1512 /* Setup some valid baud rate information in the register 1513 * shadows so we don't write crap there before baud rate is 1514 * first initialized. 1515 */ 1516 pmz_convert_to_zs(uap, CS8, 0, 9600); 1517 1518 return 0; 1519 } 1520 1521 /* 1522 * Get rid of a port on module removal 1523 */ 1524 static void pmz_dispose_port(struct uart_pmac_port *uap) 1525 { 1526 struct device_node *np; 1527 1528 np = uap->node; 1529 iounmap(uap->rx_dma_regs); 1530 iounmap(uap->tx_dma_regs); 1531 iounmap(uap->control_reg); 1532 uap->node = NULL; 1533 of_node_put(np); 1534 memset(uap, 0, sizeof(struct uart_pmac_port)); 1535 } 1536 1537 /* 1538 * Called upon match with an escc node in the device-tree. 1539 */ 1540 static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match) 1541 { 1542 struct uart_pmac_port *uap; 1543 int i; 1544 1545 /* Iterate the pmz_ports array to find a matching entry 1546 */ 1547 for (i = 0; i < MAX_ZS_PORTS; i++) 1548 if (pmz_ports[i].node == mdev->ofdev.dev.of_node) 1549 break; 1550 if (i >= MAX_ZS_PORTS) 1551 return -ENODEV; 1552 1553 1554 uap = &pmz_ports[i]; 1555 uap->dev = mdev; 1556 uap->port.dev = &mdev->ofdev.dev; 1557 dev_set_drvdata(&mdev->ofdev.dev, uap); 1558 1559 /* We still activate the port even when failing to request resources 1560 * to work around bugs in ancient Apple device-trees 1561 */ 1562 if (macio_request_resources(uap->dev, "pmac_zilog")) 1563 printk(KERN_WARNING "%pOFn: Failed to request resource" 1564 ", port still active\n", 1565 uap->node); 1566 else 1567 uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; 1568 1569 return uart_add_one_port(&pmz_uart_reg, &uap->port); 1570 } 1571 1572 /* 1573 * That one should not be called, macio isn't really a hotswap device, 1574 * we don't expect one of those serial ports to go away... 1575 */ 1576 static int pmz_detach(struct macio_dev *mdev) 1577 { 1578 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1579 1580 if (!uap) 1581 return -ENODEV; 1582 1583 uart_remove_one_port(&pmz_uart_reg, &uap->port); 1584 1585 if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { 1586 macio_release_resources(uap->dev); 1587 uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; 1588 } 1589 dev_set_drvdata(&mdev->ofdev.dev, NULL); 1590 uap->dev = NULL; 1591 uap->port.dev = NULL; 1592 1593 return 0; 1594 } 1595 1596 1597 static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state) 1598 { 1599 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1600 1601 if (uap == NULL) { 1602 printk("HRM... pmz_suspend with NULL uap\n"); 1603 return 0; 1604 } 1605 1606 uart_suspend_port(&pmz_uart_reg, &uap->port); 1607 1608 return 0; 1609 } 1610 1611 1612 static int pmz_resume(struct macio_dev *mdev) 1613 { 1614 struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); 1615 1616 if (uap == NULL) 1617 return 0; 1618 1619 uart_resume_port(&pmz_uart_reg, &uap->port); 1620 1621 return 0; 1622 } 1623 1624 /* 1625 * Probe all ports in the system and build the ports array, we register 1626 * with the serial layer later, so we get a proper struct device which 1627 * allows the tty to attach properly. This is later than it used to be 1628 * but the tty layer really wants it that way. 1629 */ 1630 static int __init pmz_probe(void) 1631 { 1632 struct device_node *node_p, *node_a, *node_b, *np; 1633 int count = 0; 1634 int rc; 1635 1636 /* 1637 * Find all escc chips in the system 1638 */ 1639 for_each_node_by_name(node_p, "escc") { 1640 /* 1641 * First get channel A/B node pointers 1642 * 1643 * TODO: Add routines with proper locking to do that... 1644 */ 1645 node_a = node_b = NULL; 1646 for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) { 1647 if (of_node_name_prefix(np, "ch-a")) 1648 node_a = of_node_get(np); 1649 else if (of_node_name_prefix(np, "ch-b")) 1650 node_b = of_node_get(np); 1651 } 1652 if (!node_a && !node_b) { 1653 of_node_put(node_a); 1654 of_node_put(node_b); 1655 printk(KERN_ERR "pmac_zilog: missing node %c for escc %pOF\n", 1656 (!node_a) ? 'a' : 'b', node_p); 1657 continue; 1658 } 1659 1660 /* 1661 * Fill basic fields in the port structures 1662 */ 1663 if (node_b != NULL) { 1664 pmz_ports[count].mate = &pmz_ports[count+1]; 1665 pmz_ports[count+1].mate = &pmz_ports[count]; 1666 } 1667 pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1668 pmz_ports[count].node = node_a; 1669 pmz_ports[count+1].node = node_b; 1670 pmz_ports[count].port.line = count; 1671 pmz_ports[count+1].port.line = count+1; 1672 1673 /* 1674 * Setup the ports for real 1675 */ 1676 rc = pmz_init_port(&pmz_ports[count]); 1677 if (rc == 0 && node_b != NULL) 1678 rc = pmz_init_port(&pmz_ports[count+1]); 1679 if (rc != 0) { 1680 of_node_put(node_a); 1681 of_node_put(node_b); 1682 memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port)); 1683 memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port)); 1684 continue; 1685 } 1686 count += 2; 1687 } 1688 pmz_ports_count = count; 1689 1690 return 0; 1691 } 1692 1693 #else 1694 1695 extern struct platform_device scc_a_pdev, scc_b_pdev; 1696 1697 static int __init pmz_init_port(struct uart_pmac_port *uap) 1698 { 1699 struct resource *r_ports; 1700 int irq; 1701 1702 r_ports = platform_get_resource(uap->pdev, IORESOURCE_MEM, 0); 1703 irq = platform_get_irq(uap->pdev, 0); 1704 if (!r_ports || irq <= 0) 1705 return -ENODEV; 1706 1707 uap->port.mapbase = r_ports->start; 1708 uap->port.membase = (unsigned char __iomem *) r_ports->start; 1709 uap->port.iotype = UPIO_MEM; 1710 uap->port.irq = irq; 1711 uap->port.uartclk = ZS_CLOCK; 1712 uap->port.fifosize = 1; 1713 uap->port.ops = &pmz_pops; 1714 uap->port.type = PORT_PMAC_ZILOG; 1715 uap->port.flags = 0; 1716 1717 uap->control_reg = uap->port.membase; 1718 uap->data_reg = uap->control_reg + 4; 1719 uap->port_type = 0; 1720 uap->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_PMACZILOG_CONSOLE); 1721 1722 pmz_convert_to_zs(uap, CS8, 0, 9600); 1723 1724 return 0; 1725 } 1726 1727 static int __init pmz_probe(void) 1728 { 1729 int err; 1730 1731 pmz_ports_count = 0; 1732 1733 pmz_ports[0].port.line = 0; 1734 pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A; 1735 pmz_ports[0].pdev = &scc_a_pdev; 1736 err = pmz_init_port(&pmz_ports[0]); 1737 if (err) 1738 return err; 1739 pmz_ports_count++; 1740 1741 pmz_ports[0].mate = &pmz_ports[1]; 1742 pmz_ports[1].mate = &pmz_ports[0]; 1743 pmz_ports[1].port.line = 1; 1744 pmz_ports[1].flags = 0; 1745 pmz_ports[1].pdev = &scc_b_pdev; 1746 err = pmz_init_port(&pmz_ports[1]); 1747 if (err) 1748 return err; 1749 pmz_ports_count++; 1750 1751 return 0; 1752 } 1753 1754 static void pmz_dispose_port(struct uart_pmac_port *uap) 1755 { 1756 memset(uap, 0, sizeof(struct uart_pmac_port)); 1757 } 1758 1759 static int __init pmz_attach(struct platform_device *pdev) 1760 { 1761 struct uart_pmac_port *uap; 1762 int i; 1763 1764 /* Iterate the pmz_ports array to find a matching entry */ 1765 for (i = 0; i < pmz_ports_count; i++) 1766 if (pmz_ports[i].pdev == pdev) 1767 break; 1768 if (i >= pmz_ports_count) 1769 return -ENODEV; 1770 1771 uap = &pmz_ports[i]; 1772 uap->port.dev = &pdev->dev; 1773 platform_set_drvdata(pdev, uap); 1774 1775 return uart_add_one_port(&pmz_uart_reg, &uap->port); 1776 } 1777 1778 static int __exit pmz_detach(struct platform_device *pdev) 1779 { 1780 struct uart_pmac_port *uap = platform_get_drvdata(pdev); 1781 1782 if (!uap) 1783 return -ENODEV; 1784 1785 uart_remove_one_port(&pmz_uart_reg, &uap->port); 1786 1787 uap->port.dev = NULL; 1788 1789 return 0; 1790 } 1791 1792 #endif /* !CONFIG_PPC_PMAC */ 1793 1794 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE 1795 1796 static void pmz_console_write(struct console *con, const char *s, unsigned int count); 1797 static int __init pmz_console_setup(struct console *co, char *options); 1798 1799 static struct console pmz_console = { 1800 .name = PMACZILOG_NAME, 1801 .write = pmz_console_write, 1802 .device = uart_console_device, 1803 .setup = pmz_console_setup, 1804 .flags = CON_PRINTBUFFER, 1805 .index = -1, 1806 .data = &pmz_uart_reg, 1807 }; 1808 1809 #define PMACZILOG_CONSOLE &pmz_console 1810 #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1811 #define PMACZILOG_CONSOLE (NULL) 1812 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 1813 1814 /* 1815 * Register the driver, console driver and ports with the serial 1816 * core 1817 */ 1818 static int __init pmz_register(void) 1819 { 1820 pmz_uart_reg.nr = pmz_ports_count; 1821 pmz_uart_reg.cons = PMACZILOG_CONSOLE; 1822 1823 /* 1824 * Register this driver with the serial core 1825 */ 1826 return uart_register_driver(&pmz_uart_reg); 1827 } 1828 1829 #ifdef CONFIG_PPC_PMAC 1830 1831 static const struct of_device_id pmz_match[] = 1832 { 1833 { 1834 .name = "ch-a", 1835 }, 1836 { 1837 .name = "ch-b", 1838 }, 1839 {}, 1840 }; 1841 MODULE_DEVICE_TABLE (of, pmz_match); 1842 1843 static struct macio_driver pmz_driver = { 1844 .driver = { 1845 .name = "pmac_zilog", 1846 .owner = THIS_MODULE, 1847 .of_match_table = pmz_match, 1848 }, 1849 .probe = pmz_attach, 1850 .remove = pmz_detach, 1851 .suspend = pmz_suspend, 1852 .resume = pmz_resume, 1853 }; 1854 1855 #else 1856 1857 static struct platform_driver pmz_driver = { 1858 .remove = __exit_p(pmz_detach), 1859 .driver = { 1860 .name = "scc", 1861 }, 1862 }; 1863 1864 #endif /* !CONFIG_PPC_PMAC */ 1865 1866 static int __init init_pmz(void) 1867 { 1868 int rc, i; 1869 printk(KERN_INFO "%s\n", version); 1870 1871 /* 1872 * First, we need to do a direct OF-based probe pass. We 1873 * do that because we want serial console up before the 1874 * macio stuffs calls us back, and since that makes it 1875 * easier to pass the proper number of channels to 1876 * uart_register_driver() 1877 */ 1878 if (pmz_ports_count == 0) 1879 pmz_probe(); 1880 1881 /* 1882 * Bail early if no port found 1883 */ 1884 if (pmz_ports_count == 0) 1885 return -ENODEV; 1886 1887 /* 1888 * Now we register with the serial layer 1889 */ 1890 rc = pmz_register(); 1891 if (rc) { 1892 printk(KERN_ERR 1893 "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n" 1894 "pmac_zilog: Did another serial driver already claim the minors?\n"); 1895 /* effectively "pmz_unprobe()" */ 1896 for (i=0; i < pmz_ports_count; i++) 1897 pmz_dispose_port(&pmz_ports[i]); 1898 return rc; 1899 } 1900 1901 /* 1902 * Then we register the macio driver itself 1903 */ 1904 #ifdef CONFIG_PPC_PMAC 1905 return macio_register_driver(&pmz_driver); 1906 #else 1907 return platform_driver_probe(&pmz_driver, pmz_attach); 1908 #endif 1909 } 1910 1911 static void __exit exit_pmz(void) 1912 { 1913 int i; 1914 1915 #ifdef CONFIG_PPC_PMAC 1916 /* Get rid of macio-driver (detach from macio) */ 1917 macio_unregister_driver(&pmz_driver); 1918 #else 1919 platform_driver_unregister(&pmz_driver); 1920 #endif 1921 1922 for (i = 0; i < pmz_ports_count; i++) { 1923 struct uart_pmac_port *uport = &pmz_ports[i]; 1924 #ifdef CONFIG_PPC_PMAC 1925 if (uport->node != NULL) 1926 pmz_dispose_port(uport); 1927 #else 1928 if (uport->pdev != NULL) 1929 pmz_dispose_port(uport); 1930 #endif 1931 } 1932 /* Unregister UART driver */ 1933 uart_unregister_driver(&pmz_uart_reg); 1934 } 1935 1936 #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE 1937 1938 static void pmz_console_putchar(struct uart_port *port, int ch) 1939 { 1940 struct uart_pmac_port *uap = 1941 container_of(port, struct uart_pmac_port, port); 1942 1943 /* Wait for the transmit buffer to empty. */ 1944 while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) 1945 udelay(5); 1946 write_zsdata(uap, ch); 1947 } 1948 1949 /* 1950 * Print a string to the serial port trying not to disturb 1951 * any possible real use of the port... 1952 */ 1953 static void pmz_console_write(struct console *con, const char *s, unsigned int count) 1954 { 1955 struct uart_pmac_port *uap = &pmz_ports[con->index]; 1956 unsigned long flags; 1957 1958 spin_lock_irqsave(&uap->port.lock, flags); 1959 1960 /* Turn of interrupts and enable the transmitter. */ 1961 write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); 1962 write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); 1963 1964 uart_console_write(&uap->port, s, count, pmz_console_putchar); 1965 1966 /* Restore the values in the registers. */ 1967 write_zsreg(uap, R1, uap->curregs[1]); 1968 /* Don't disable the transmitter. */ 1969 1970 spin_unlock_irqrestore(&uap->port.lock, flags); 1971 } 1972 1973 /* 1974 * Setup the serial console 1975 */ 1976 static int __init pmz_console_setup(struct console *co, char *options) 1977 { 1978 struct uart_pmac_port *uap; 1979 struct uart_port *port; 1980 int baud = 38400; 1981 int bits = 8; 1982 int parity = 'n'; 1983 int flow = 'n'; 1984 unsigned long pwr_delay; 1985 1986 /* 1987 * XServe's default to 57600 bps 1988 */ 1989 if (of_machine_is_compatible("RackMac1,1") 1990 || of_machine_is_compatible("RackMac1,2") 1991 || of_machine_is_compatible("MacRISC4")) 1992 baud = 57600; 1993 1994 /* 1995 * Check whether an invalid uart number has been specified, and 1996 * if so, search for the first available port that does have 1997 * console support. 1998 */ 1999 if (co->index >= pmz_ports_count) 2000 co->index = 0; 2001 uap = &pmz_ports[co->index]; 2002 #ifdef CONFIG_PPC_PMAC 2003 if (uap->node == NULL) 2004 return -ENODEV; 2005 #else 2006 if (uap->pdev == NULL) 2007 return -ENODEV; 2008 #endif 2009 port = &uap->port; 2010 2011 /* 2012 * Mark port as beeing a console 2013 */ 2014 uap->flags |= PMACZILOG_FLAG_IS_CONS; 2015 2016 /* 2017 * Temporary fix for uart layer who didn't setup the spinlock yet 2018 */ 2019 spin_lock_init(&port->lock); 2020 2021 /* 2022 * Enable the hardware 2023 */ 2024 pwr_delay = __pmz_startup(uap); 2025 if (pwr_delay) 2026 mdelay(pwr_delay); 2027 2028 if (options) 2029 uart_parse_options(options, &baud, &parity, &bits, &flow); 2030 2031 return uart_set_options(port, co, baud, parity, bits, flow); 2032 } 2033 2034 static int __init pmz_console_init(void) 2035 { 2036 /* Probe ports */ 2037 pmz_probe(); 2038 2039 if (pmz_ports_count == 0) 2040 return -ENODEV; 2041 2042 /* TODO: Autoprobe console based on OF */ 2043 /* pmz_console.index = i; */ 2044 register_console(&pmz_console); 2045 2046 return 0; 2047 2048 } 2049 console_initcall(pmz_console_init); 2050 #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ 2051 2052 module_init(init_pmz); 2053 module_exit(exit_pmz); 2054