1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Freescale lpuart serial port driver 4 * 5 * Copyright 2012-2014 Freescale Semiconductor, Inc. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/console.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dmapool.h> 13 #include <linux/io.h> 14 #include <linux/irq.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_device.h> 18 #include <linux/of_dma.h> 19 #include <linux/serial_core.h> 20 #include <linux/slab.h> 21 #include <linux/tty_flip.h> 22 23 /* All registers are 8-bit width */ 24 #define UARTBDH 0x00 25 #define UARTBDL 0x01 26 #define UARTCR1 0x02 27 #define UARTCR2 0x03 28 #define UARTSR1 0x04 29 #define UARTCR3 0x06 30 #define UARTDR 0x07 31 #define UARTCR4 0x0a 32 #define UARTCR5 0x0b 33 #define UARTMODEM 0x0d 34 #define UARTPFIFO 0x10 35 #define UARTCFIFO 0x11 36 #define UARTSFIFO 0x12 37 #define UARTTWFIFO 0x13 38 #define UARTTCFIFO 0x14 39 #define UARTRWFIFO 0x15 40 41 #define UARTBDH_LBKDIE 0x80 42 #define UARTBDH_RXEDGIE 0x40 43 #define UARTBDH_SBR_MASK 0x1f 44 45 #define UARTCR1_LOOPS 0x80 46 #define UARTCR1_RSRC 0x20 47 #define UARTCR1_M 0x10 48 #define UARTCR1_WAKE 0x08 49 #define UARTCR1_ILT 0x04 50 #define UARTCR1_PE 0x02 51 #define UARTCR1_PT 0x01 52 53 #define UARTCR2_TIE 0x80 54 #define UARTCR2_TCIE 0x40 55 #define UARTCR2_RIE 0x20 56 #define UARTCR2_ILIE 0x10 57 #define UARTCR2_TE 0x08 58 #define UARTCR2_RE 0x04 59 #define UARTCR2_RWU 0x02 60 #define UARTCR2_SBK 0x01 61 62 #define UARTSR1_TDRE 0x80 63 #define UARTSR1_TC 0x40 64 #define UARTSR1_RDRF 0x20 65 #define UARTSR1_IDLE 0x10 66 #define UARTSR1_OR 0x08 67 #define UARTSR1_NF 0x04 68 #define UARTSR1_FE 0x02 69 #define UARTSR1_PE 0x01 70 71 #define UARTCR3_R8 0x80 72 #define UARTCR3_T8 0x40 73 #define UARTCR3_TXDIR 0x20 74 #define UARTCR3_TXINV 0x10 75 #define UARTCR3_ORIE 0x08 76 #define UARTCR3_NEIE 0x04 77 #define UARTCR3_FEIE 0x02 78 #define UARTCR3_PEIE 0x01 79 80 #define UARTCR4_MAEN1 0x80 81 #define UARTCR4_MAEN2 0x40 82 #define UARTCR4_M10 0x20 83 #define UARTCR4_BRFA_MASK 0x1f 84 #define UARTCR4_BRFA_OFF 0 85 86 #define UARTCR5_TDMAS 0x80 87 #define UARTCR5_RDMAS 0x20 88 89 #define UARTMODEM_RXRTSE 0x08 90 #define UARTMODEM_TXRTSPOL 0x04 91 #define UARTMODEM_TXRTSE 0x02 92 #define UARTMODEM_TXCTSE 0x01 93 94 #define UARTPFIFO_TXFE 0x80 95 #define UARTPFIFO_FIFOSIZE_MASK 0x7 96 #define UARTPFIFO_TXSIZE_OFF 4 97 #define UARTPFIFO_RXFE 0x08 98 #define UARTPFIFO_RXSIZE_OFF 0 99 100 #define UARTCFIFO_TXFLUSH 0x80 101 #define UARTCFIFO_RXFLUSH 0x40 102 #define UARTCFIFO_RXOFE 0x04 103 #define UARTCFIFO_TXOFE 0x02 104 #define UARTCFIFO_RXUFE 0x01 105 106 #define UARTSFIFO_TXEMPT 0x80 107 #define UARTSFIFO_RXEMPT 0x40 108 #define UARTSFIFO_RXOF 0x04 109 #define UARTSFIFO_TXOF 0x02 110 #define UARTSFIFO_RXUF 0x01 111 112 /* 32-bit register definition */ 113 #define UARTBAUD 0x00 114 #define UARTSTAT 0x04 115 #define UARTCTRL 0x08 116 #define UARTDATA 0x0C 117 #define UARTMATCH 0x10 118 #define UARTMODIR 0x14 119 #define UARTFIFO 0x18 120 #define UARTWATER 0x1c 121 122 #define UARTBAUD_MAEN1 0x80000000 123 #define UARTBAUD_MAEN2 0x40000000 124 #define UARTBAUD_M10 0x20000000 125 #define UARTBAUD_TDMAE 0x00800000 126 #define UARTBAUD_RDMAE 0x00200000 127 #define UARTBAUD_MATCFG 0x00400000 128 #define UARTBAUD_BOTHEDGE 0x00020000 129 #define UARTBAUD_RESYNCDIS 0x00010000 130 #define UARTBAUD_LBKDIE 0x00008000 131 #define UARTBAUD_RXEDGIE 0x00004000 132 #define UARTBAUD_SBNS 0x00002000 133 #define UARTBAUD_SBR 0x00000000 134 #define UARTBAUD_SBR_MASK 0x1fff 135 #define UARTBAUD_OSR_MASK 0x1f 136 #define UARTBAUD_OSR_SHIFT 24 137 138 #define UARTSTAT_LBKDIF 0x80000000 139 #define UARTSTAT_RXEDGIF 0x40000000 140 #define UARTSTAT_MSBF 0x20000000 141 #define UARTSTAT_RXINV 0x10000000 142 #define UARTSTAT_RWUID 0x08000000 143 #define UARTSTAT_BRK13 0x04000000 144 #define UARTSTAT_LBKDE 0x02000000 145 #define UARTSTAT_RAF 0x01000000 146 #define UARTSTAT_TDRE 0x00800000 147 #define UARTSTAT_TC 0x00400000 148 #define UARTSTAT_RDRF 0x00200000 149 #define UARTSTAT_IDLE 0x00100000 150 #define UARTSTAT_OR 0x00080000 151 #define UARTSTAT_NF 0x00040000 152 #define UARTSTAT_FE 0x00020000 153 #define UARTSTAT_PE 0x00010000 154 #define UARTSTAT_MA1F 0x00008000 155 #define UARTSTAT_M21F 0x00004000 156 157 #define UARTCTRL_R8T9 0x80000000 158 #define UARTCTRL_R9T8 0x40000000 159 #define UARTCTRL_TXDIR 0x20000000 160 #define UARTCTRL_TXINV 0x10000000 161 #define UARTCTRL_ORIE 0x08000000 162 #define UARTCTRL_NEIE 0x04000000 163 #define UARTCTRL_FEIE 0x02000000 164 #define UARTCTRL_PEIE 0x01000000 165 #define UARTCTRL_TIE 0x00800000 166 #define UARTCTRL_TCIE 0x00400000 167 #define UARTCTRL_RIE 0x00200000 168 #define UARTCTRL_ILIE 0x00100000 169 #define UARTCTRL_TE 0x00080000 170 #define UARTCTRL_RE 0x00040000 171 #define UARTCTRL_RWU 0x00020000 172 #define UARTCTRL_SBK 0x00010000 173 #define UARTCTRL_MA1IE 0x00008000 174 #define UARTCTRL_MA2IE 0x00004000 175 #define UARTCTRL_IDLECFG 0x00000100 176 #define UARTCTRL_LOOPS 0x00000080 177 #define UARTCTRL_DOZEEN 0x00000040 178 #define UARTCTRL_RSRC 0x00000020 179 #define UARTCTRL_M 0x00000010 180 #define UARTCTRL_WAKE 0x00000008 181 #define UARTCTRL_ILT 0x00000004 182 #define UARTCTRL_PE 0x00000002 183 #define UARTCTRL_PT 0x00000001 184 185 #define UARTDATA_NOISY 0x00008000 186 #define UARTDATA_PARITYE 0x00004000 187 #define UARTDATA_FRETSC 0x00002000 188 #define UARTDATA_RXEMPT 0x00001000 189 #define UARTDATA_IDLINE 0x00000800 190 #define UARTDATA_MASK 0x3ff 191 192 #define UARTMODIR_IREN 0x00020000 193 #define UARTMODIR_TXCTSSRC 0x00000020 194 #define UARTMODIR_TXCTSC 0x00000010 195 #define UARTMODIR_RXRTSE 0x00000008 196 #define UARTMODIR_TXRTSPOL 0x00000004 197 #define UARTMODIR_TXRTSE 0x00000002 198 #define UARTMODIR_TXCTSE 0x00000001 199 200 #define UARTFIFO_TXEMPT 0x00800000 201 #define UARTFIFO_RXEMPT 0x00400000 202 #define UARTFIFO_TXOF 0x00020000 203 #define UARTFIFO_RXUF 0x00010000 204 #define UARTFIFO_TXFLUSH 0x00008000 205 #define UARTFIFO_RXFLUSH 0x00004000 206 #define UARTFIFO_TXOFE 0x00000200 207 #define UARTFIFO_RXUFE 0x00000100 208 #define UARTFIFO_TXFE 0x00000080 209 #define UARTFIFO_FIFOSIZE_MASK 0x7 210 #define UARTFIFO_TXSIZE_OFF 4 211 #define UARTFIFO_RXFE 0x00000008 212 #define UARTFIFO_RXSIZE_OFF 0 213 #define UARTFIFO_DEPTH(x) (0x1 << ((x) ? ((x) + 1) : 0)) 214 215 #define UARTWATER_COUNT_MASK 0xff 216 #define UARTWATER_TXCNT_OFF 8 217 #define UARTWATER_RXCNT_OFF 24 218 #define UARTWATER_WATER_MASK 0xff 219 #define UARTWATER_TXWATER_OFF 0 220 #define UARTWATER_RXWATER_OFF 16 221 222 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */ 223 #define DMA_RX_TIMEOUT (10) 224 225 #define DRIVER_NAME "fsl-lpuart" 226 #define DEV_NAME "ttyLP" 227 #define UART_NR 6 228 229 /* IMX lpuart has four extra unused regs located at the beginning */ 230 #define IMX_REG_OFF 0x10 231 232 static DEFINE_IDA(fsl_lpuart_ida); 233 234 enum lpuart_type { 235 VF610_LPUART, 236 LS1021A_LPUART, 237 LS1028A_LPUART, 238 IMX7ULP_LPUART, 239 IMX8QXP_LPUART, 240 }; 241 242 struct lpuart_port { 243 struct uart_port port; 244 enum lpuart_type devtype; 245 struct clk *ipg_clk; 246 struct clk *baud_clk; 247 unsigned int txfifo_size; 248 unsigned int rxfifo_size; 249 250 bool lpuart_dma_tx_use; 251 bool lpuart_dma_rx_use; 252 struct dma_chan *dma_tx_chan; 253 struct dma_chan *dma_rx_chan; 254 struct dma_async_tx_descriptor *dma_tx_desc; 255 struct dma_async_tx_descriptor *dma_rx_desc; 256 dma_cookie_t dma_tx_cookie; 257 dma_cookie_t dma_rx_cookie; 258 unsigned int dma_tx_bytes; 259 unsigned int dma_rx_bytes; 260 bool dma_tx_in_progress; 261 unsigned int dma_rx_timeout; 262 struct timer_list lpuart_timer; 263 struct scatterlist rx_sgl, tx_sgl[2]; 264 struct circ_buf rx_ring; 265 int rx_dma_rng_buf_len; 266 unsigned int dma_tx_nents; 267 wait_queue_head_t dma_wait; 268 bool id_allocated; 269 }; 270 271 struct lpuart_soc_data { 272 enum lpuart_type devtype; 273 char iotype; 274 u8 reg_off; 275 }; 276 277 static const struct lpuart_soc_data vf_data = { 278 .devtype = VF610_LPUART, 279 .iotype = UPIO_MEM, 280 }; 281 282 static const struct lpuart_soc_data ls1021a_data = { 283 .devtype = LS1021A_LPUART, 284 .iotype = UPIO_MEM32BE, 285 }; 286 287 static const struct lpuart_soc_data ls1028a_data = { 288 .devtype = LS1028A_LPUART, 289 .iotype = UPIO_MEM32, 290 }; 291 292 static struct lpuart_soc_data imx7ulp_data = { 293 .devtype = IMX7ULP_LPUART, 294 .iotype = UPIO_MEM32, 295 .reg_off = IMX_REG_OFF, 296 }; 297 298 static struct lpuart_soc_data imx8qxp_data = { 299 .devtype = IMX8QXP_LPUART, 300 .iotype = UPIO_MEM32, 301 .reg_off = IMX_REG_OFF, 302 }; 303 304 static const struct of_device_id lpuart_dt_ids[] = { 305 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, }, 306 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, }, 307 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, }, 308 { .compatible = "fsl,imx7ulp-lpuart", .data = &imx7ulp_data, }, 309 { .compatible = "fsl,imx8qxp-lpuart", .data = &imx8qxp_data, }, 310 { /* sentinel */ } 311 }; 312 MODULE_DEVICE_TABLE(of, lpuart_dt_ids); 313 314 /* Forward declare this for the dma callbacks*/ 315 static void lpuart_dma_tx_complete(void *arg); 316 317 static inline bool is_ls1028a_lpuart(struct lpuart_port *sport) 318 { 319 return sport->devtype == LS1028A_LPUART; 320 } 321 322 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport) 323 { 324 return sport->devtype == IMX8QXP_LPUART; 325 } 326 327 static inline u32 lpuart32_read(struct uart_port *port, u32 off) 328 { 329 switch (port->iotype) { 330 case UPIO_MEM32: 331 return readl(port->membase + off); 332 case UPIO_MEM32BE: 333 return ioread32be(port->membase + off); 334 default: 335 return 0; 336 } 337 } 338 339 static inline void lpuart32_write(struct uart_port *port, u32 val, 340 u32 off) 341 { 342 switch (port->iotype) { 343 case UPIO_MEM32: 344 writel(val, port->membase + off); 345 break; 346 case UPIO_MEM32BE: 347 iowrite32be(val, port->membase + off); 348 break; 349 } 350 } 351 352 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en) 353 { 354 int ret = 0; 355 356 if (is_en) { 357 ret = clk_prepare_enable(sport->ipg_clk); 358 if (ret) 359 return ret; 360 361 ret = clk_prepare_enable(sport->baud_clk); 362 if (ret) { 363 clk_disable_unprepare(sport->ipg_clk); 364 return ret; 365 } 366 } else { 367 clk_disable_unprepare(sport->baud_clk); 368 clk_disable_unprepare(sport->ipg_clk); 369 } 370 371 return 0; 372 } 373 374 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport) 375 { 376 if (is_imx8qxp_lpuart(sport)) 377 return clk_get_rate(sport->baud_clk); 378 379 return clk_get_rate(sport->ipg_clk); 380 } 381 382 #define lpuart_enable_clks(x) __lpuart_enable_clks(x, true) 383 #define lpuart_disable_clks(x) __lpuart_enable_clks(x, false) 384 385 static void lpuart_stop_tx(struct uart_port *port) 386 { 387 unsigned char temp; 388 389 temp = readb(port->membase + UARTCR2); 390 temp &= ~(UARTCR2_TIE | UARTCR2_TCIE); 391 writeb(temp, port->membase + UARTCR2); 392 } 393 394 static void lpuart32_stop_tx(struct uart_port *port) 395 { 396 unsigned long temp; 397 398 temp = lpuart32_read(port, UARTCTRL); 399 temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE); 400 lpuart32_write(port, temp, UARTCTRL); 401 } 402 403 static void lpuart_stop_rx(struct uart_port *port) 404 { 405 unsigned char temp; 406 407 temp = readb(port->membase + UARTCR2); 408 writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2); 409 } 410 411 static void lpuart32_stop_rx(struct uart_port *port) 412 { 413 unsigned long temp; 414 415 temp = lpuart32_read(port, UARTCTRL); 416 lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL); 417 } 418 419 static void lpuart_dma_tx(struct lpuart_port *sport) 420 { 421 struct circ_buf *xmit = &sport->port.state->xmit; 422 struct scatterlist *sgl = sport->tx_sgl; 423 struct device *dev = sport->port.dev; 424 struct dma_chan *chan = sport->dma_tx_chan; 425 int ret; 426 427 if (sport->dma_tx_in_progress) 428 return; 429 430 sport->dma_tx_bytes = uart_circ_chars_pending(xmit); 431 432 if (xmit->tail < xmit->head || xmit->head == 0) { 433 sport->dma_tx_nents = 1; 434 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes); 435 } else { 436 sport->dma_tx_nents = 2; 437 sg_init_table(sgl, 2); 438 sg_set_buf(sgl, xmit->buf + xmit->tail, 439 UART_XMIT_SIZE - xmit->tail); 440 sg_set_buf(sgl + 1, xmit->buf, xmit->head); 441 } 442 443 ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents, 444 DMA_TO_DEVICE); 445 if (!ret) { 446 dev_err(dev, "DMA mapping error for TX.\n"); 447 return; 448 } 449 450 sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl, 451 ret, DMA_MEM_TO_DEV, 452 DMA_PREP_INTERRUPT); 453 if (!sport->dma_tx_desc) { 454 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 455 DMA_TO_DEVICE); 456 dev_err(dev, "Cannot prepare TX slave DMA!\n"); 457 return; 458 } 459 460 sport->dma_tx_desc->callback = lpuart_dma_tx_complete; 461 sport->dma_tx_desc->callback_param = sport; 462 sport->dma_tx_in_progress = true; 463 sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc); 464 dma_async_issue_pending(chan); 465 } 466 467 static bool lpuart_stopped_or_empty(struct uart_port *port) 468 { 469 return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port); 470 } 471 472 static void lpuart_dma_tx_complete(void *arg) 473 { 474 struct lpuart_port *sport = arg; 475 struct scatterlist *sgl = &sport->tx_sgl[0]; 476 struct circ_buf *xmit = &sport->port.state->xmit; 477 struct dma_chan *chan = sport->dma_tx_chan; 478 unsigned long flags; 479 480 spin_lock_irqsave(&sport->port.lock, flags); 481 482 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents, 483 DMA_TO_DEVICE); 484 485 xmit->tail = (xmit->tail + sport->dma_tx_bytes) & (UART_XMIT_SIZE - 1); 486 487 sport->port.icount.tx += sport->dma_tx_bytes; 488 sport->dma_tx_in_progress = false; 489 spin_unlock_irqrestore(&sport->port.lock, flags); 490 491 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 492 uart_write_wakeup(&sport->port); 493 494 if (waitqueue_active(&sport->dma_wait)) { 495 wake_up(&sport->dma_wait); 496 return; 497 } 498 499 spin_lock_irqsave(&sport->port.lock, flags); 500 501 if (!lpuart_stopped_or_empty(&sport->port)) 502 lpuart_dma_tx(sport); 503 504 spin_unlock_irqrestore(&sport->port.lock, flags); 505 } 506 507 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport) 508 { 509 switch (sport->port.iotype) { 510 case UPIO_MEM32: 511 return sport->port.mapbase + UARTDATA; 512 case UPIO_MEM32BE: 513 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1; 514 } 515 return sport->port.mapbase + UARTDR; 516 } 517 518 static int lpuart_dma_tx_request(struct uart_port *port) 519 { 520 struct lpuart_port *sport = container_of(port, 521 struct lpuart_port, port); 522 struct dma_slave_config dma_tx_sconfig = {}; 523 int ret; 524 525 dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport); 526 dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 527 dma_tx_sconfig.dst_maxburst = 1; 528 dma_tx_sconfig.direction = DMA_MEM_TO_DEV; 529 ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig); 530 531 if (ret) { 532 dev_err(sport->port.dev, 533 "DMA slave config failed, err = %d\n", ret); 534 return ret; 535 } 536 537 return 0; 538 } 539 540 static bool lpuart_is_32(struct lpuart_port *sport) 541 { 542 return sport->port.iotype == UPIO_MEM32 || 543 sport->port.iotype == UPIO_MEM32BE; 544 } 545 546 static void lpuart_flush_buffer(struct uart_port *port) 547 { 548 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 549 struct dma_chan *chan = sport->dma_tx_chan; 550 u32 val; 551 552 if (sport->lpuart_dma_tx_use) { 553 if (sport->dma_tx_in_progress) { 554 dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0], 555 sport->dma_tx_nents, DMA_TO_DEVICE); 556 sport->dma_tx_in_progress = false; 557 } 558 dmaengine_terminate_all(chan); 559 } 560 561 if (lpuart_is_32(sport)) { 562 val = lpuart32_read(&sport->port, UARTFIFO); 563 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 564 lpuart32_write(&sport->port, val, UARTFIFO); 565 } else { 566 val = readb(sport->port.membase + UARTCFIFO); 567 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH; 568 writeb(val, sport->port.membase + UARTCFIFO); 569 } 570 } 571 572 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset, 573 u8 bit) 574 { 575 while (!(readb(port->membase + offset) & bit)) 576 cpu_relax(); 577 } 578 579 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset, 580 u32 bit) 581 { 582 while (!(lpuart32_read(port, offset) & bit)) 583 cpu_relax(); 584 } 585 586 #if defined(CONFIG_CONSOLE_POLL) 587 588 static int lpuart_poll_init(struct uart_port *port) 589 { 590 struct lpuart_port *sport = container_of(port, 591 struct lpuart_port, port); 592 unsigned long flags; 593 unsigned char temp; 594 595 sport->port.fifosize = 0; 596 597 spin_lock_irqsave(&sport->port.lock, flags); 598 /* Disable Rx & Tx */ 599 writeb(0, sport->port.membase + UARTCR2); 600 601 temp = readb(sport->port.membase + UARTPFIFO); 602 /* Enable Rx and Tx FIFO */ 603 writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE, 604 sport->port.membase + UARTPFIFO); 605 606 /* flush Tx and Rx FIFO */ 607 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 608 sport->port.membase + UARTCFIFO); 609 610 /* explicitly clear RDRF */ 611 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 612 readb(sport->port.membase + UARTDR); 613 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 614 } 615 616 writeb(0, sport->port.membase + UARTTWFIFO); 617 writeb(1, sport->port.membase + UARTRWFIFO); 618 619 /* Enable Rx and Tx */ 620 writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2); 621 spin_unlock_irqrestore(&sport->port.lock, flags); 622 623 return 0; 624 } 625 626 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c) 627 { 628 /* drain */ 629 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 630 writeb(c, port->membase + UARTDR); 631 } 632 633 static int lpuart_poll_get_char(struct uart_port *port) 634 { 635 if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF)) 636 return NO_POLL_CHAR; 637 638 return readb(port->membase + UARTDR); 639 } 640 641 static int lpuart32_poll_init(struct uart_port *port) 642 { 643 unsigned long flags; 644 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 645 u32 temp; 646 647 sport->port.fifosize = 0; 648 649 spin_lock_irqsave(&sport->port.lock, flags); 650 651 /* Disable Rx & Tx */ 652 lpuart32_write(&sport->port, UARTCTRL, 0); 653 654 temp = lpuart32_read(&sport->port, UARTFIFO); 655 656 /* Enable Rx and Tx FIFO */ 657 lpuart32_write(&sport->port, UARTFIFO, 658 temp | UARTFIFO_RXFE | UARTFIFO_TXFE); 659 660 /* flush Tx and Rx FIFO */ 661 lpuart32_write(&sport->port, UARTFIFO, 662 UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH); 663 664 /* explicitly clear RDRF */ 665 if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) { 666 lpuart32_read(&sport->port, UARTDATA); 667 lpuart32_write(&sport->port, UARTFIFO, UARTFIFO_RXUF); 668 } 669 670 /* Enable Rx and Tx */ 671 lpuart32_write(&sport->port, UARTCTRL, UARTCTRL_RE | UARTCTRL_TE); 672 spin_unlock_irqrestore(&sport->port.lock, flags); 673 674 return 0; 675 } 676 677 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c) 678 { 679 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 680 lpuart32_write(port, UARTDATA, c); 681 } 682 683 static int lpuart32_poll_get_char(struct uart_port *port) 684 { 685 if (!(lpuart32_read(port, UARTSTAT) & UARTSTAT_RDRF)) 686 return NO_POLL_CHAR; 687 688 return lpuart32_read(port, UARTDATA); 689 } 690 #endif 691 692 static inline void lpuart_transmit_buffer(struct lpuart_port *sport) 693 { 694 struct circ_buf *xmit = &sport->port.state->xmit; 695 696 if (sport->port.x_char) { 697 writeb(sport->port.x_char, sport->port.membase + UARTDR); 698 sport->port.icount.tx++; 699 sport->port.x_char = 0; 700 return; 701 } 702 703 if (lpuart_stopped_or_empty(&sport->port)) { 704 lpuart_stop_tx(&sport->port); 705 return; 706 } 707 708 while (!uart_circ_empty(xmit) && 709 (readb(sport->port.membase + UARTTCFIFO) < sport->txfifo_size)) { 710 writeb(xmit->buf[xmit->tail], sport->port.membase + UARTDR); 711 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 712 sport->port.icount.tx++; 713 } 714 715 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 716 uart_write_wakeup(&sport->port); 717 718 if (uart_circ_empty(xmit)) 719 lpuart_stop_tx(&sport->port); 720 } 721 722 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport) 723 { 724 struct circ_buf *xmit = &sport->port.state->xmit; 725 unsigned long txcnt; 726 727 if (sport->port.x_char) { 728 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA); 729 sport->port.icount.tx++; 730 sport->port.x_char = 0; 731 return; 732 } 733 734 if (lpuart_stopped_or_empty(&sport->port)) { 735 lpuart32_stop_tx(&sport->port); 736 return; 737 } 738 739 txcnt = lpuart32_read(&sport->port, UARTWATER); 740 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 741 txcnt &= UARTWATER_COUNT_MASK; 742 while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) { 743 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA); 744 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 745 sport->port.icount.tx++; 746 txcnt = lpuart32_read(&sport->port, UARTWATER); 747 txcnt = txcnt >> UARTWATER_TXCNT_OFF; 748 txcnt &= UARTWATER_COUNT_MASK; 749 } 750 751 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 752 uart_write_wakeup(&sport->port); 753 754 if (uart_circ_empty(xmit)) 755 lpuart32_stop_tx(&sport->port); 756 } 757 758 static void lpuart_start_tx(struct uart_port *port) 759 { 760 struct lpuart_port *sport = container_of(port, 761 struct lpuart_port, port); 762 unsigned char temp; 763 764 temp = readb(port->membase + UARTCR2); 765 writeb(temp | UARTCR2_TIE, port->membase + UARTCR2); 766 767 if (sport->lpuart_dma_tx_use) { 768 if (!lpuart_stopped_or_empty(port)) 769 lpuart_dma_tx(sport); 770 } else { 771 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE) 772 lpuart_transmit_buffer(sport); 773 } 774 } 775 776 static void lpuart32_start_tx(struct uart_port *port) 777 { 778 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 779 unsigned long temp; 780 781 if (sport->lpuart_dma_tx_use) { 782 if (!lpuart_stopped_or_empty(port)) 783 lpuart_dma_tx(sport); 784 } else { 785 temp = lpuart32_read(port, UARTCTRL); 786 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL); 787 788 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE) 789 lpuart32_transmit_buffer(sport); 790 } 791 } 792 793 /* return TIOCSER_TEMT when transmitter is not busy */ 794 static unsigned int lpuart_tx_empty(struct uart_port *port) 795 { 796 struct lpuart_port *sport = container_of(port, 797 struct lpuart_port, port); 798 unsigned char sr1 = readb(port->membase + UARTSR1); 799 unsigned char sfifo = readb(port->membase + UARTSFIFO); 800 801 if (sport->dma_tx_in_progress) 802 return 0; 803 804 if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT) 805 return TIOCSER_TEMT; 806 807 return 0; 808 } 809 810 static unsigned int lpuart32_tx_empty(struct uart_port *port) 811 { 812 struct lpuart_port *sport = container_of(port, 813 struct lpuart_port, port); 814 unsigned long stat = lpuart32_read(port, UARTSTAT); 815 unsigned long sfifo = lpuart32_read(port, UARTFIFO); 816 817 if (sport->dma_tx_in_progress) 818 return 0; 819 820 if (stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) 821 return TIOCSER_TEMT; 822 823 return 0; 824 } 825 826 static void lpuart_txint(struct lpuart_port *sport) 827 { 828 unsigned long flags; 829 830 spin_lock_irqsave(&sport->port.lock, flags); 831 lpuart_transmit_buffer(sport); 832 spin_unlock_irqrestore(&sport->port.lock, flags); 833 } 834 835 static void lpuart_rxint(struct lpuart_port *sport) 836 { 837 unsigned int flg, ignored = 0, overrun = 0; 838 struct tty_port *port = &sport->port.state->port; 839 unsigned long flags; 840 unsigned char rx, sr; 841 842 spin_lock_irqsave(&sport->port.lock, flags); 843 844 while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) { 845 flg = TTY_NORMAL; 846 sport->port.icount.rx++; 847 /* 848 * to clear the FE, OR, NF, FE, PE flags, 849 * read SR1 then read DR 850 */ 851 sr = readb(sport->port.membase + UARTSR1); 852 rx = readb(sport->port.membase + UARTDR); 853 854 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 855 continue; 856 857 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) { 858 if (sr & UARTSR1_PE) 859 sport->port.icount.parity++; 860 else if (sr & UARTSR1_FE) 861 sport->port.icount.frame++; 862 863 if (sr & UARTSR1_OR) 864 overrun++; 865 866 if (sr & sport->port.ignore_status_mask) { 867 if (++ignored > 100) 868 goto out; 869 continue; 870 } 871 872 sr &= sport->port.read_status_mask; 873 874 if (sr & UARTSR1_PE) 875 flg = TTY_PARITY; 876 else if (sr & UARTSR1_FE) 877 flg = TTY_FRAME; 878 879 if (sr & UARTSR1_OR) 880 flg = TTY_OVERRUN; 881 882 sport->port.sysrq = 0; 883 } 884 885 tty_insert_flip_char(port, rx, flg); 886 } 887 888 out: 889 if (overrun) { 890 sport->port.icount.overrun += overrun; 891 892 /* 893 * Overruns cause FIFO pointers to become missaligned. 894 * Flushing the receive FIFO reinitializes the pointers. 895 */ 896 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO); 897 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO); 898 } 899 900 spin_unlock_irqrestore(&sport->port.lock, flags); 901 902 tty_flip_buffer_push(port); 903 } 904 905 static void lpuart32_txint(struct lpuart_port *sport) 906 { 907 unsigned long flags; 908 909 spin_lock_irqsave(&sport->port.lock, flags); 910 lpuart32_transmit_buffer(sport); 911 spin_unlock_irqrestore(&sport->port.lock, flags); 912 } 913 914 static void lpuart32_rxint(struct lpuart_port *sport) 915 { 916 unsigned int flg, ignored = 0; 917 struct tty_port *port = &sport->port.state->port; 918 unsigned long flags; 919 unsigned long rx, sr; 920 921 spin_lock_irqsave(&sport->port.lock, flags); 922 923 while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) { 924 flg = TTY_NORMAL; 925 sport->port.icount.rx++; 926 /* 927 * to clear the FE, OR, NF, FE, PE flags, 928 * read STAT then read DATA reg 929 */ 930 sr = lpuart32_read(&sport->port, UARTSTAT); 931 rx = lpuart32_read(&sport->port, UARTDATA); 932 rx &= 0x3ff; 933 934 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) 935 continue; 936 937 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) { 938 if (sr & UARTSTAT_PE) 939 sport->port.icount.parity++; 940 else if (sr & UARTSTAT_FE) 941 sport->port.icount.frame++; 942 943 if (sr & UARTSTAT_OR) 944 sport->port.icount.overrun++; 945 946 if (sr & sport->port.ignore_status_mask) { 947 if (++ignored > 100) 948 goto out; 949 continue; 950 } 951 952 sr &= sport->port.read_status_mask; 953 954 if (sr & UARTSTAT_PE) 955 flg = TTY_PARITY; 956 else if (sr & UARTSTAT_FE) 957 flg = TTY_FRAME; 958 959 if (sr & UARTSTAT_OR) 960 flg = TTY_OVERRUN; 961 962 sport->port.sysrq = 0; 963 } 964 965 tty_insert_flip_char(port, rx, flg); 966 } 967 968 out: 969 spin_unlock_irqrestore(&sport->port.lock, flags); 970 971 tty_flip_buffer_push(port); 972 } 973 974 static irqreturn_t lpuart_int(int irq, void *dev_id) 975 { 976 struct lpuart_port *sport = dev_id; 977 unsigned char sts; 978 979 sts = readb(sport->port.membase + UARTSR1); 980 981 if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use) 982 lpuart_rxint(sport); 983 984 if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use) 985 lpuart_txint(sport); 986 987 return IRQ_HANDLED; 988 } 989 990 static irqreturn_t lpuart32_int(int irq, void *dev_id) 991 { 992 struct lpuart_port *sport = dev_id; 993 unsigned long sts, rxcount; 994 995 sts = lpuart32_read(&sport->port, UARTSTAT); 996 rxcount = lpuart32_read(&sport->port, UARTWATER); 997 rxcount = rxcount >> UARTWATER_RXCNT_OFF; 998 999 if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use) 1000 lpuart32_rxint(sport); 1001 1002 if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use) 1003 lpuart32_txint(sport); 1004 1005 lpuart32_write(&sport->port, sts, UARTSTAT); 1006 return IRQ_HANDLED; 1007 } 1008 1009 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport) 1010 { 1011 struct tty_port *port = &sport->port.state->port; 1012 struct dma_tx_state state; 1013 enum dma_status dmastat; 1014 struct dma_chan *chan = sport->dma_rx_chan; 1015 struct circ_buf *ring = &sport->rx_ring; 1016 unsigned long flags; 1017 int count = 0; 1018 1019 if (lpuart_is_32(sport)) { 1020 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT); 1021 1022 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) { 1023 /* Read DR to clear the error flags */ 1024 lpuart32_read(&sport->port, UARTDATA); 1025 1026 if (sr & UARTSTAT_PE) 1027 sport->port.icount.parity++; 1028 else if (sr & UARTSTAT_FE) 1029 sport->port.icount.frame++; 1030 } 1031 } else { 1032 unsigned char sr = readb(sport->port.membase + UARTSR1); 1033 1034 if (sr & (UARTSR1_PE | UARTSR1_FE)) { 1035 unsigned char cr2; 1036 1037 /* Disable receiver during this operation... */ 1038 cr2 = readb(sport->port.membase + UARTCR2); 1039 cr2 &= ~UARTCR2_RE; 1040 writeb(cr2, sport->port.membase + UARTCR2); 1041 1042 /* Read DR to clear the error flags */ 1043 readb(sport->port.membase + UARTDR); 1044 1045 if (sr & UARTSR1_PE) 1046 sport->port.icount.parity++; 1047 else if (sr & UARTSR1_FE) 1048 sport->port.icount.frame++; 1049 /* 1050 * At this point parity/framing error is 1051 * cleared However, since the DMA already read 1052 * the data register and we had to read it 1053 * again after reading the status register to 1054 * properly clear the flags, the FIFO actually 1055 * underflowed... This requires a clearing of 1056 * the FIFO... 1057 */ 1058 if (readb(sport->port.membase + UARTSFIFO) & 1059 UARTSFIFO_RXUF) { 1060 writeb(UARTSFIFO_RXUF, 1061 sport->port.membase + UARTSFIFO); 1062 writeb(UARTCFIFO_RXFLUSH, 1063 sport->port.membase + UARTCFIFO); 1064 } 1065 1066 cr2 |= UARTCR2_RE; 1067 writeb(cr2, sport->port.membase + UARTCR2); 1068 } 1069 } 1070 1071 async_tx_ack(sport->dma_rx_desc); 1072 1073 spin_lock_irqsave(&sport->port.lock, flags); 1074 1075 dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state); 1076 if (dmastat == DMA_ERROR) { 1077 dev_err(sport->port.dev, "Rx DMA transfer failed!\n"); 1078 spin_unlock_irqrestore(&sport->port.lock, flags); 1079 return; 1080 } 1081 1082 /* CPU claims ownership of RX DMA buffer */ 1083 dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1, 1084 DMA_FROM_DEVICE); 1085 1086 /* 1087 * ring->head points to the end of data already written by the DMA. 1088 * ring->tail points to the beginning of data to be read by the 1089 * framework. 1090 * The current transfer size should not be larger than the dma buffer 1091 * length. 1092 */ 1093 ring->head = sport->rx_sgl.length - state.residue; 1094 BUG_ON(ring->head > sport->rx_sgl.length); 1095 /* 1096 * At this point ring->head may point to the first byte right after the 1097 * last byte of the dma buffer: 1098 * 0 <= ring->head <= sport->rx_sgl.length 1099 * 1100 * However ring->tail must always points inside the dma buffer: 1101 * 0 <= ring->tail <= sport->rx_sgl.length - 1 1102 * 1103 * Since we use a ring buffer, we have to handle the case 1104 * where head is lower than tail. In such a case, we first read from 1105 * tail to the end of the buffer then reset tail. 1106 */ 1107 if (ring->head < ring->tail) { 1108 count = sport->rx_sgl.length - ring->tail; 1109 1110 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1111 ring->tail = 0; 1112 sport->port.icount.rx += count; 1113 } 1114 1115 /* Finally we read data from tail to head */ 1116 if (ring->tail < ring->head) { 1117 count = ring->head - ring->tail; 1118 tty_insert_flip_string(port, ring->buf + ring->tail, count); 1119 /* Wrap ring->head if needed */ 1120 if (ring->head >= sport->rx_sgl.length) 1121 ring->head = 0; 1122 ring->tail = ring->head; 1123 sport->port.icount.rx += count; 1124 } 1125 1126 dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1, 1127 DMA_FROM_DEVICE); 1128 1129 spin_unlock_irqrestore(&sport->port.lock, flags); 1130 1131 tty_flip_buffer_push(port); 1132 mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout); 1133 } 1134 1135 static void lpuart_dma_rx_complete(void *arg) 1136 { 1137 struct lpuart_port *sport = arg; 1138 1139 lpuart_copy_rx_to_tty(sport); 1140 } 1141 1142 static void lpuart_timer_func(struct timer_list *t) 1143 { 1144 struct lpuart_port *sport = from_timer(sport, t, lpuart_timer); 1145 1146 lpuart_copy_rx_to_tty(sport); 1147 } 1148 1149 static inline int lpuart_start_rx_dma(struct lpuart_port *sport) 1150 { 1151 struct dma_slave_config dma_rx_sconfig = {}; 1152 struct circ_buf *ring = &sport->rx_ring; 1153 int ret, nent; 1154 int bits, baud; 1155 struct tty_port *port = &sport->port.state->port; 1156 struct tty_struct *tty = port->tty; 1157 struct ktermios *termios = &tty->termios; 1158 struct dma_chan *chan = sport->dma_rx_chan; 1159 1160 baud = tty_get_baud_rate(tty); 1161 1162 bits = (termios->c_cflag & CSIZE) == CS7 ? 9 : 10; 1163 if (termios->c_cflag & PARENB) 1164 bits++; 1165 1166 /* 1167 * Calculate length of one DMA buffer size to keep latency below 1168 * 10ms at any baud rate. 1169 */ 1170 sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud / bits / 1000) * 2; 1171 sport->rx_dma_rng_buf_len = (1 << (fls(sport->rx_dma_rng_buf_len) - 1)); 1172 if (sport->rx_dma_rng_buf_len < 16) 1173 sport->rx_dma_rng_buf_len = 16; 1174 1175 ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC); 1176 if (!ring->buf) 1177 return -ENOMEM; 1178 1179 sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len); 1180 nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1, 1181 DMA_FROM_DEVICE); 1182 1183 if (!nent) { 1184 dev_err(sport->port.dev, "DMA Rx mapping error\n"); 1185 return -EINVAL; 1186 } 1187 1188 dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport); 1189 dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 1190 dma_rx_sconfig.src_maxburst = 1; 1191 dma_rx_sconfig.direction = DMA_DEV_TO_MEM; 1192 ret = dmaengine_slave_config(chan, &dma_rx_sconfig); 1193 1194 if (ret < 0) { 1195 dev_err(sport->port.dev, 1196 "DMA Rx slave config failed, err = %d\n", ret); 1197 return ret; 1198 } 1199 1200 sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan, 1201 sg_dma_address(&sport->rx_sgl), 1202 sport->rx_sgl.length, 1203 sport->rx_sgl.length / 2, 1204 DMA_DEV_TO_MEM, 1205 DMA_PREP_INTERRUPT); 1206 if (!sport->dma_rx_desc) { 1207 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n"); 1208 return -EFAULT; 1209 } 1210 1211 sport->dma_rx_desc->callback = lpuart_dma_rx_complete; 1212 sport->dma_rx_desc->callback_param = sport; 1213 sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc); 1214 dma_async_issue_pending(chan); 1215 1216 if (lpuart_is_32(sport)) { 1217 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD); 1218 1219 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD); 1220 } else { 1221 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS, 1222 sport->port.membase + UARTCR5); 1223 } 1224 1225 return 0; 1226 } 1227 1228 static void lpuart_dma_rx_free(struct uart_port *port) 1229 { 1230 struct lpuart_port *sport = container_of(port, 1231 struct lpuart_port, port); 1232 struct dma_chan *chan = sport->dma_rx_chan; 1233 1234 dmaengine_terminate_all(chan); 1235 dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE); 1236 kfree(sport->rx_ring.buf); 1237 sport->rx_ring.tail = 0; 1238 sport->rx_ring.head = 0; 1239 sport->dma_rx_desc = NULL; 1240 sport->dma_rx_cookie = -EINVAL; 1241 } 1242 1243 static int lpuart_config_rs485(struct uart_port *port, 1244 struct serial_rs485 *rs485) 1245 { 1246 struct lpuart_port *sport = container_of(port, 1247 struct lpuart_port, port); 1248 1249 u8 modem = readb(sport->port.membase + UARTMODEM) & 1250 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1251 writeb(modem, sport->port.membase + UARTMODEM); 1252 1253 /* clear unsupported configurations */ 1254 rs485->delay_rts_before_send = 0; 1255 rs485->delay_rts_after_send = 0; 1256 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1257 1258 if (rs485->flags & SER_RS485_ENABLED) { 1259 /* Enable auto RS-485 RTS mode */ 1260 modem |= UARTMODEM_TXRTSE; 1261 1262 /* 1263 * RTS needs to be logic HIGH either during transer _or_ after 1264 * transfer, other variants are not supported by the hardware. 1265 */ 1266 1267 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1268 SER_RS485_RTS_AFTER_SEND))) 1269 rs485->flags |= SER_RS485_RTS_ON_SEND; 1270 1271 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1272 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1273 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1274 1275 /* 1276 * The hardware defaults to RTS logic HIGH while transfer. 1277 * Switch polarity in case RTS shall be logic HIGH 1278 * after transfer. 1279 * Note: UART is assumed to be active high. 1280 */ 1281 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1282 modem &= ~UARTMODEM_TXRTSPOL; 1283 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1284 modem |= UARTMODEM_TXRTSPOL; 1285 } 1286 1287 /* Store the new configuration */ 1288 sport->port.rs485 = *rs485; 1289 1290 writeb(modem, sport->port.membase + UARTMODEM); 1291 return 0; 1292 } 1293 1294 static int lpuart32_config_rs485(struct uart_port *port, 1295 struct serial_rs485 *rs485) 1296 { 1297 struct lpuart_port *sport = container_of(port, 1298 struct lpuart_port, port); 1299 1300 unsigned long modem = lpuart32_read(&sport->port, UARTMODIR) 1301 & ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE); 1302 lpuart32_write(&sport->port, modem, UARTMODIR); 1303 1304 /* clear unsupported configurations */ 1305 rs485->delay_rts_before_send = 0; 1306 rs485->delay_rts_after_send = 0; 1307 rs485->flags &= ~SER_RS485_RX_DURING_TX; 1308 1309 if (rs485->flags & SER_RS485_ENABLED) { 1310 /* Enable auto RS-485 RTS mode */ 1311 modem |= UARTMODEM_TXRTSE; 1312 1313 /* 1314 * RTS needs to be logic HIGH either during transer _or_ after 1315 * transfer, other variants are not supported by the hardware. 1316 */ 1317 1318 if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | 1319 SER_RS485_RTS_AFTER_SEND))) 1320 rs485->flags |= SER_RS485_RTS_ON_SEND; 1321 1322 if (rs485->flags & SER_RS485_RTS_ON_SEND && 1323 rs485->flags & SER_RS485_RTS_AFTER_SEND) 1324 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; 1325 1326 /* 1327 * The hardware defaults to RTS logic HIGH while transfer. 1328 * Switch polarity in case RTS shall be logic HIGH 1329 * after transfer. 1330 * Note: UART is assumed to be active high. 1331 */ 1332 if (rs485->flags & SER_RS485_RTS_ON_SEND) 1333 modem &= ~UARTMODEM_TXRTSPOL; 1334 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) 1335 modem |= UARTMODEM_TXRTSPOL; 1336 } 1337 1338 /* Store the new configuration */ 1339 sport->port.rs485 = *rs485; 1340 1341 lpuart32_write(&sport->port, modem, UARTMODIR); 1342 return 0; 1343 } 1344 1345 static unsigned int lpuart_get_mctrl(struct uart_port *port) 1346 { 1347 unsigned int temp = 0; 1348 unsigned char reg; 1349 1350 reg = readb(port->membase + UARTMODEM); 1351 if (reg & UARTMODEM_TXCTSE) 1352 temp |= TIOCM_CTS; 1353 1354 if (reg & UARTMODEM_RXRTSE) 1355 temp |= TIOCM_RTS; 1356 1357 return temp; 1358 } 1359 1360 static unsigned int lpuart32_get_mctrl(struct uart_port *port) 1361 { 1362 unsigned int temp = 0; 1363 unsigned long reg; 1364 1365 reg = lpuart32_read(port, UARTMODIR); 1366 if (reg & UARTMODIR_TXCTSE) 1367 temp |= TIOCM_CTS; 1368 1369 if (reg & UARTMODIR_RXRTSE) 1370 temp |= TIOCM_RTS; 1371 1372 return temp; 1373 } 1374 1375 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl) 1376 { 1377 unsigned char temp; 1378 struct lpuart_port *sport = container_of(port, 1379 struct lpuart_port, port); 1380 1381 /* Make sure RXRTSE bit is not set when RS485 is enabled */ 1382 if (!(sport->port.rs485.flags & SER_RS485_ENABLED)) { 1383 temp = readb(sport->port.membase + UARTMODEM) & 1384 ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1385 1386 if (mctrl & TIOCM_RTS) 1387 temp |= UARTMODEM_RXRTSE; 1388 1389 if (mctrl & TIOCM_CTS) 1390 temp |= UARTMODEM_TXCTSE; 1391 1392 writeb(temp, port->membase + UARTMODEM); 1393 } 1394 } 1395 1396 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl) 1397 { 1398 1399 } 1400 1401 static void lpuart_break_ctl(struct uart_port *port, int break_state) 1402 { 1403 unsigned char temp; 1404 1405 temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK; 1406 1407 if (break_state != 0) 1408 temp |= UARTCR2_SBK; 1409 1410 writeb(temp, port->membase + UARTCR2); 1411 } 1412 1413 static void lpuart32_break_ctl(struct uart_port *port, int break_state) 1414 { 1415 unsigned long temp; 1416 1417 temp = lpuart32_read(port, UARTCTRL) & ~UARTCTRL_SBK; 1418 1419 if (break_state != 0) 1420 temp |= UARTCTRL_SBK; 1421 1422 lpuart32_write(port, temp, UARTCTRL); 1423 } 1424 1425 static void lpuart_setup_watermark(struct lpuart_port *sport) 1426 { 1427 unsigned char val, cr2; 1428 unsigned char cr2_saved; 1429 1430 cr2 = readb(sport->port.membase + UARTCR2); 1431 cr2_saved = cr2; 1432 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE | 1433 UARTCR2_RIE | UARTCR2_RE); 1434 writeb(cr2, sport->port.membase + UARTCR2); 1435 1436 val = readb(sport->port.membase + UARTPFIFO); 1437 writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE, 1438 sport->port.membase + UARTPFIFO); 1439 1440 /* flush Tx and Rx FIFO */ 1441 writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH, 1442 sport->port.membase + UARTCFIFO); 1443 1444 /* explicitly clear RDRF */ 1445 if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) { 1446 readb(sport->port.membase + UARTDR); 1447 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO); 1448 } 1449 1450 writeb(0, sport->port.membase + UARTTWFIFO); 1451 writeb(1, sport->port.membase + UARTRWFIFO); 1452 1453 /* Restore cr2 */ 1454 writeb(cr2_saved, sport->port.membase + UARTCR2); 1455 } 1456 1457 static void lpuart_setup_watermark_enable(struct lpuart_port *sport) 1458 { 1459 unsigned char cr2; 1460 1461 lpuart_setup_watermark(sport); 1462 1463 cr2 = readb(sport->port.membase + UARTCR2); 1464 cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE; 1465 writeb(cr2, sport->port.membase + UARTCR2); 1466 } 1467 1468 static void lpuart32_setup_watermark(struct lpuart_port *sport) 1469 { 1470 unsigned long val, ctrl; 1471 unsigned long ctrl_saved; 1472 1473 ctrl = lpuart32_read(&sport->port, UARTCTRL); 1474 ctrl_saved = ctrl; 1475 ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | 1476 UARTCTRL_RIE | UARTCTRL_RE); 1477 lpuart32_write(&sport->port, ctrl, UARTCTRL); 1478 1479 /* enable FIFO mode */ 1480 val = lpuart32_read(&sport->port, UARTFIFO); 1481 val |= UARTFIFO_TXFE | UARTFIFO_RXFE; 1482 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH; 1483 lpuart32_write(&sport->port, val, UARTFIFO); 1484 1485 /* set the watermark */ 1486 val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); 1487 lpuart32_write(&sport->port, val, UARTWATER); 1488 1489 /* Restore cr2 */ 1490 lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); 1491 } 1492 1493 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport) 1494 { 1495 u32 temp; 1496 1497 lpuart32_setup_watermark(sport); 1498 1499 temp = lpuart32_read(&sport->port, UARTCTRL); 1500 temp |= UARTCTRL_RE | UARTCTRL_TE | UARTCTRL_ILIE; 1501 lpuart32_write(&sport->port, temp, UARTCTRL); 1502 } 1503 1504 static void rx_dma_timer_init(struct lpuart_port *sport) 1505 { 1506 timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0); 1507 sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout; 1508 add_timer(&sport->lpuart_timer); 1509 } 1510 1511 static void lpuart_request_dma(struct lpuart_port *sport) 1512 { 1513 sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx"); 1514 if (IS_ERR(sport->dma_tx_chan)) { 1515 dev_dbg_once(sport->port.dev, 1516 "DMA tx channel request failed, operating without tx DMA (%ld)\n", 1517 PTR_ERR(sport->dma_tx_chan)); 1518 sport->dma_tx_chan = NULL; 1519 } 1520 1521 sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx"); 1522 if (IS_ERR(sport->dma_rx_chan)) { 1523 dev_dbg_once(sport->port.dev, 1524 "DMA rx channel request failed, operating without rx DMA (%ld)\n", 1525 PTR_ERR(sport->dma_rx_chan)); 1526 sport->dma_rx_chan = NULL; 1527 } 1528 } 1529 1530 static void lpuart_tx_dma_startup(struct lpuart_port *sport) 1531 { 1532 u32 uartbaud; 1533 int ret; 1534 1535 if (!sport->dma_tx_chan) 1536 goto err; 1537 1538 ret = lpuart_dma_tx_request(&sport->port); 1539 if (ret) 1540 goto err; 1541 1542 init_waitqueue_head(&sport->dma_wait); 1543 sport->lpuart_dma_tx_use = true; 1544 if (lpuart_is_32(sport)) { 1545 uartbaud = lpuart32_read(&sport->port, UARTBAUD); 1546 lpuart32_write(&sport->port, 1547 uartbaud | UARTBAUD_TDMAE, UARTBAUD); 1548 } else { 1549 writeb(readb(sport->port.membase + UARTCR5) | 1550 UARTCR5_TDMAS, sport->port.membase + UARTCR5); 1551 } 1552 1553 return; 1554 1555 err: 1556 sport->lpuart_dma_tx_use = false; 1557 } 1558 1559 static void lpuart_rx_dma_startup(struct lpuart_port *sport) 1560 { 1561 int ret; 1562 1563 if (!sport->dma_rx_chan) 1564 goto err; 1565 1566 ret = lpuart_start_rx_dma(sport); 1567 if (ret) 1568 goto err; 1569 1570 /* set Rx DMA timeout */ 1571 sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT); 1572 if (!sport->dma_rx_timeout) 1573 sport->dma_rx_timeout = 1; 1574 1575 sport->lpuart_dma_rx_use = true; 1576 rx_dma_timer_init(sport); 1577 1578 return; 1579 1580 err: 1581 sport->lpuart_dma_rx_use = false; 1582 } 1583 1584 static int lpuart_startup(struct uart_port *port) 1585 { 1586 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1587 unsigned long flags; 1588 unsigned char temp; 1589 1590 /* determine FIFO size and enable FIFO mode */ 1591 temp = readb(sport->port.membase + UARTPFIFO); 1592 1593 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) & 1594 UARTPFIFO_FIFOSIZE_MASK); 1595 sport->port.fifosize = sport->txfifo_size; 1596 1597 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) & 1598 UARTPFIFO_FIFOSIZE_MASK); 1599 1600 lpuart_request_dma(sport); 1601 1602 spin_lock_irqsave(&sport->port.lock, flags); 1603 1604 lpuart_setup_watermark_enable(sport); 1605 1606 lpuart_rx_dma_startup(sport); 1607 lpuart_tx_dma_startup(sport); 1608 1609 spin_unlock_irqrestore(&sport->port.lock, flags); 1610 1611 return 0; 1612 } 1613 1614 static void lpuart32_configure(struct lpuart_port *sport) 1615 { 1616 unsigned long temp; 1617 1618 if (sport->lpuart_dma_rx_use) { 1619 /* RXWATER must be 0 */ 1620 temp = lpuart32_read(&sport->port, UARTWATER); 1621 temp &= ~(UARTWATER_WATER_MASK << UARTWATER_RXWATER_OFF); 1622 lpuart32_write(&sport->port, temp, UARTWATER); 1623 } 1624 temp = lpuart32_read(&sport->port, UARTCTRL); 1625 if (!sport->lpuart_dma_rx_use) 1626 temp |= UARTCTRL_RIE; 1627 if (!sport->lpuart_dma_tx_use) 1628 temp |= UARTCTRL_TIE; 1629 lpuart32_write(&sport->port, temp, UARTCTRL); 1630 } 1631 1632 static int lpuart32_startup(struct uart_port *port) 1633 { 1634 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1635 unsigned long flags; 1636 unsigned long temp; 1637 1638 /* determine FIFO size */ 1639 temp = lpuart32_read(&sport->port, UARTFIFO); 1640 1641 sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) & 1642 UARTFIFO_FIFOSIZE_MASK); 1643 sport->port.fifosize = sport->txfifo_size; 1644 1645 sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) & 1646 UARTFIFO_FIFOSIZE_MASK); 1647 1648 /* 1649 * The LS1028A has a fixed length of 16 words. Although it supports the 1650 * RX/TXSIZE fields their encoding is different. Eg the reference manual 1651 * states 0b101 is 16 words. 1652 */ 1653 if (is_ls1028a_lpuart(sport)) { 1654 sport->rxfifo_size = 16; 1655 sport->txfifo_size = 16; 1656 sport->port.fifosize = sport->txfifo_size; 1657 } 1658 1659 lpuart_request_dma(sport); 1660 1661 spin_lock_irqsave(&sport->port.lock, flags); 1662 1663 lpuart32_setup_watermark_enable(sport); 1664 1665 lpuart_rx_dma_startup(sport); 1666 lpuart_tx_dma_startup(sport); 1667 1668 lpuart32_configure(sport); 1669 1670 spin_unlock_irqrestore(&sport->port.lock, flags); 1671 return 0; 1672 } 1673 1674 static void lpuart_dma_shutdown(struct lpuart_port *sport) 1675 { 1676 if (sport->lpuart_dma_rx_use) { 1677 del_timer_sync(&sport->lpuart_timer); 1678 lpuart_dma_rx_free(&sport->port); 1679 } 1680 1681 if (sport->lpuart_dma_tx_use) { 1682 if (wait_event_interruptible(sport->dma_wait, 1683 !sport->dma_tx_in_progress) != false) { 1684 sport->dma_tx_in_progress = false; 1685 dmaengine_terminate_all(sport->dma_tx_chan); 1686 } 1687 } 1688 1689 if (sport->dma_tx_chan) 1690 dma_release_channel(sport->dma_tx_chan); 1691 if (sport->dma_rx_chan) 1692 dma_release_channel(sport->dma_rx_chan); 1693 } 1694 1695 static void lpuart_shutdown(struct uart_port *port) 1696 { 1697 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1698 unsigned char temp; 1699 unsigned long flags; 1700 1701 spin_lock_irqsave(&port->lock, flags); 1702 1703 /* disable Rx/Tx and interrupts */ 1704 temp = readb(port->membase + UARTCR2); 1705 temp &= ~(UARTCR2_TE | UARTCR2_RE | 1706 UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 1707 writeb(temp, port->membase + UARTCR2); 1708 1709 spin_unlock_irqrestore(&port->lock, flags); 1710 1711 lpuart_dma_shutdown(sport); 1712 } 1713 1714 static void lpuart32_shutdown(struct uart_port *port) 1715 { 1716 struct lpuart_port *sport = 1717 container_of(port, struct lpuart_port, port); 1718 unsigned long temp; 1719 unsigned long flags; 1720 1721 spin_lock_irqsave(&port->lock, flags); 1722 1723 /* disable Rx/Tx and interrupts */ 1724 temp = lpuart32_read(port, UARTCTRL); 1725 temp &= ~(UARTCTRL_TE | UARTCTRL_RE | 1726 UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 1727 lpuart32_write(port, temp, UARTCTRL); 1728 1729 spin_unlock_irqrestore(&port->lock, flags); 1730 1731 lpuart_dma_shutdown(sport); 1732 } 1733 1734 static void 1735 lpuart_set_termios(struct uart_port *port, struct ktermios *termios, 1736 struct ktermios *old) 1737 { 1738 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1739 unsigned long flags; 1740 unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem; 1741 unsigned int baud; 1742 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1743 unsigned int sbr, brfa; 1744 1745 cr1 = old_cr1 = readb(sport->port.membase + UARTCR1); 1746 old_cr2 = readb(sport->port.membase + UARTCR2); 1747 cr3 = readb(sport->port.membase + UARTCR3); 1748 cr4 = readb(sport->port.membase + UARTCR4); 1749 bdh = readb(sport->port.membase + UARTBDH); 1750 modem = readb(sport->port.membase + UARTMODEM); 1751 /* 1752 * only support CS8 and CS7, and for CS7 must enable PE. 1753 * supported mode: 1754 * - (7,e/o,1) 1755 * - (8,n,1) 1756 * - (8,m/s,1) 1757 * - (8,e/o,1) 1758 */ 1759 while ((termios->c_cflag & CSIZE) != CS8 && 1760 (termios->c_cflag & CSIZE) != CS7) { 1761 termios->c_cflag &= ~CSIZE; 1762 termios->c_cflag |= old_csize; 1763 old_csize = CS8; 1764 } 1765 1766 if ((termios->c_cflag & CSIZE) == CS8 || 1767 (termios->c_cflag & CSIZE) == CS7) 1768 cr1 = old_cr1 & ~UARTCR1_M; 1769 1770 if (termios->c_cflag & CMSPAR) { 1771 if ((termios->c_cflag & CSIZE) != CS8) { 1772 termios->c_cflag &= ~CSIZE; 1773 termios->c_cflag |= CS8; 1774 } 1775 cr1 |= UARTCR1_M; 1776 } 1777 1778 /* 1779 * When auto RS-485 RTS mode is enabled, 1780 * hardware flow control need to be disabled. 1781 */ 1782 if (sport->port.rs485.flags & SER_RS485_ENABLED) 1783 termios->c_cflag &= ~CRTSCTS; 1784 1785 if (termios->c_cflag & CRTSCTS) 1786 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE; 1787 else 1788 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); 1789 1790 termios->c_cflag &= ~CSTOPB; 1791 1792 /* parity must be enabled when CS7 to match 8-bits format */ 1793 if ((termios->c_cflag & CSIZE) == CS7) 1794 termios->c_cflag |= PARENB; 1795 1796 if (termios->c_cflag & PARENB) { 1797 if (termios->c_cflag & CMSPAR) { 1798 cr1 &= ~UARTCR1_PE; 1799 if (termios->c_cflag & PARODD) 1800 cr3 |= UARTCR3_T8; 1801 else 1802 cr3 &= ~UARTCR3_T8; 1803 } else { 1804 cr1 |= UARTCR1_PE; 1805 if ((termios->c_cflag & CSIZE) == CS8) 1806 cr1 |= UARTCR1_M; 1807 if (termios->c_cflag & PARODD) 1808 cr1 |= UARTCR1_PT; 1809 else 1810 cr1 &= ~UARTCR1_PT; 1811 } 1812 } else { 1813 cr1 &= ~UARTCR1_PE; 1814 } 1815 1816 /* ask the core to calculate the divisor */ 1817 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16); 1818 1819 /* 1820 * Need to update the Ring buffer length according to the selected 1821 * baud rate and restart Rx DMA path. 1822 * 1823 * Since timer function acqures sport->port.lock, need to stop before 1824 * acquring same lock because otherwise del_timer_sync() can deadlock. 1825 */ 1826 if (old && sport->lpuart_dma_rx_use) { 1827 del_timer_sync(&sport->lpuart_timer); 1828 lpuart_dma_rx_free(&sport->port); 1829 } 1830 1831 spin_lock_irqsave(&sport->port.lock, flags); 1832 1833 sport->port.read_status_mask = 0; 1834 if (termios->c_iflag & INPCK) 1835 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE; 1836 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 1837 sport->port.read_status_mask |= UARTSR1_FE; 1838 1839 /* characters to ignore */ 1840 sport->port.ignore_status_mask = 0; 1841 if (termios->c_iflag & IGNPAR) 1842 sport->port.ignore_status_mask |= UARTSR1_PE; 1843 if (termios->c_iflag & IGNBRK) { 1844 sport->port.ignore_status_mask |= UARTSR1_FE; 1845 /* 1846 * if we're ignoring parity and break indicators, 1847 * ignore overruns too (for real raw support). 1848 */ 1849 if (termios->c_iflag & IGNPAR) 1850 sport->port.ignore_status_mask |= UARTSR1_OR; 1851 } 1852 1853 /* update the per-port timeout */ 1854 uart_update_timeout(port, termios->c_cflag, baud); 1855 1856 /* wait transmit engin complete */ 1857 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 1858 1859 /* disable transmit and receive */ 1860 writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE), 1861 sport->port.membase + UARTCR2); 1862 1863 sbr = sport->port.uartclk / (16 * baud); 1864 brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud; 1865 bdh &= ~UARTBDH_SBR_MASK; 1866 bdh |= (sbr >> 8) & 0x1F; 1867 cr4 &= ~UARTCR4_BRFA_MASK; 1868 brfa &= UARTCR4_BRFA_MASK; 1869 writeb(cr4 | brfa, sport->port.membase + UARTCR4); 1870 writeb(bdh, sport->port.membase + UARTBDH); 1871 writeb(sbr & 0xFF, sport->port.membase + UARTBDL); 1872 writeb(cr3, sport->port.membase + UARTCR3); 1873 writeb(cr1, sport->port.membase + UARTCR1); 1874 writeb(modem, sport->port.membase + UARTMODEM); 1875 1876 /* restore control register */ 1877 writeb(old_cr2, sport->port.membase + UARTCR2); 1878 1879 if (old && sport->lpuart_dma_rx_use) { 1880 if (!lpuart_start_rx_dma(sport)) 1881 rx_dma_timer_init(sport); 1882 else 1883 sport->lpuart_dma_rx_use = false; 1884 } 1885 1886 spin_unlock_irqrestore(&sport->port.lock, flags); 1887 } 1888 1889 static void __lpuart32_serial_setbrg(struct uart_port *port, 1890 unsigned int baudrate, bool use_rx_dma, 1891 bool use_tx_dma) 1892 { 1893 u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp; 1894 u32 clk = port->uartclk; 1895 1896 /* 1897 * The idea is to use the best OSR (over-sampling rate) possible. 1898 * Note, OSR is typically hard-set to 16 in other LPUART instantiations. 1899 * Loop to find the best OSR value possible, one that generates minimum 1900 * baud_diff iterate through the rest of the supported values of OSR. 1901 * 1902 * Calculation Formula: 1903 * Baud Rate = baud clock / ((OSR+1) × SBR) 1904 */ 1905 baud_diff = baudrate; 1906 osr = 0; 1907 sbr = 0; 1908 1909 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 1910 /* calculate the temporary sbr value */ 1911 tmp_sbr = (clk / (baudrate * tmp_osr)); 1912 if (tmp_sbr == 0) 1913 tmp_sbr = 1; 1914 1915 /* 1916 * calculate the baud rate difference based on the temporary 1917 * osr and sbr values 1918 */ 1919 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate; 1920 1921 /* select best values between sbr and sbr+1 */ 1922 tmp = clk / (tmp_osr * (tmp_sbr + 1)); 1923 if (tmp_diff > (baudrate - tmp)) { 1924 tmp_diff = baudrate - tmp; 1925 tmp_sbr++; 1926 } 1927 1928 if (tmp_diff <= baud_diff) { 1929 baud_diff = tmp_diff; 1930 osr = tmp_osr; 1931 sbr = tmp_sbr; 1932 1933 if (!baud_diff) 1934 break; 1935 } 1936 } 1937 1938 /* handle buadrate outside acceptable rate */ 1939 if (baud_diff > ((baudrate / 100) * 3)) 1940 dev_warn(port->dev, 1941 "unacceptable baud rate difference of more than 3%%\n"); 1942 1943 tmp = lpuart32_read(port, UARTBAUD); 1944 1945 if ((osr > 3) && (osr < 8)) 1946 tmp |= UARTBAUD_BOTHEDGE; 1947 1948 tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT); 1949 tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT; 1950 1951 tmp &= ~UARTBAUD_SBR_MASK; 1952 tmp |= sbr & UARTBAUD_SBR_MASK; 1953 1954 if (!use_rx_dma) 1955 tmp &= ~UARTBAUD_RDMAE; 1956 if (!use_tx_dma) 1957 tmp &= ~UARTBAUD_TDMAE; 1958 1959 lpuart32_write(port, tmp, UARTBAUD); 1960 } 1961 1962 static void lpuart32_serial_setbrg(struct lpuart_port *sport, 1963 unsigned int baudrate) 1964 { 1965 __lpuart32_serial_setbrg(&sport->port, baudrate, 1966 sport->lpuart_dma_rx_use, 1967 sport->lpuart_dma_tx_use); 1968 } 1969 1970 1971 static void 1972 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, 1973 struct ktermios *old) 1974 { 1975 struct lpuart_port *sport = container_of(port, struct lpuart_port, port); 1976 unsigned long flags; 1977 unsigned long ctrl, old_ctrl, modem; 1978 unsigned int baud; 1979 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8; 1980 1981 ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL); 1982 modem = lpuart32_read(&sport->port, UARTMODIR); 1983 /* 1984 * only support CS8 and CS7, and for CS7 must enable PE. 1985 * supported mode: 1986 * - (7,e/o,1) 1987 * - (8,n,1) 1988 * - (8,m/s,1) 1989 * - (8,e/o,1) 1990 */ 1991 while ((termios->c_cflag & CSIZE) != CS8 && 1992 (termios->c_cflag & CSIZE) != CS7) { 1993 termios->c_cflag &= ~CSIZE; 1994 termios->c_cflag |= old_csize; 1995 old_csize = CS8; 1996 } 1997 1998 if ((termios->c_cflag & CSIZE) == CS8 || 1999 (termios->c_cflag & CSIZE) == CS7) 2000 ctrl = old_ctrl & ~UARTCTRL_M; 2001 2002 if (termios->c_cflag & CMSPAR) { 2003 if ((termios->c_cflag & CSIZE) != CS8) { 2004 termios->c_cflag &= ~CSIZE; 2005 termios->c_cflag |= CS8; 2006 } 2007 ctrl |= UARTCTRL_M; 2008 } 2009 2010 /* 2011 * When auto RS-485 RTS mode is enabled, 2012 * hardware flow control need to be disabled. 2013 */ 2014 if (sport->port.rs485.flags & SER_RS485_ENABLED) 2015 termios->c_cflag &= ~CRTSCTS; 2016 2017 if (termios->c_cflag & CRTSCTS) { 2018 modem |= (UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2019 } else { 2020 termios->c_cflag &= ~CRTSCTS; 2021 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE); 2022 } 2023 2024 if (termios->c_cflag & CSTOPB) 2025 termios->c_cflag &= ~CSTOPB; 2026 2027 /* parity must be enabled when CS7 to match 8-bits format */ 2028 if ((termios->c_cflag & CSIZE) == CS7) 2029 termios->c_cflag |= PARENB; 2030 2031 if ((termios->c_cflag & PARENB)) { 2032 if (termios->c_cflag & CMSPAR) { 2033 ctrl &= ~UARTCTRL_PE; 2034 ctrl |= UARTCTRL_M; 2035 } else { 2036 ctrl |= UARTCTRL_PE; 2037 if ((termios->c_cflag & CSIZE) == CS8) 2038 ctrl |= UARTCTRL_M; 2039 if (termios->c_cflag & PARODD) 2040 ctrl |= UARTCTRL_PT; 2041 else 2042 ctrl &= ~UARTCTRL_PT; 2043 } 2044 } else { 2045 ctrl &= ~UARTCTRL_PE; 2046 } 2047 2048 /* ask the core to calculate the divisor */ 2049 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4); 2050 2051 /* 2052 * Need to update the Ring buffer length according to the selected 2053 * baud rate and restart Rx DMA path. 2054 * 2055 * Since timer function acqures sport->port.lock, need to stop before 2056 * acquring same lock because otherwise del_timer_sync() can deadlock. 2057 */ 2058 if (old && sport->lpuart_dma_rx_use) { 2059 del_timer_sync(&sport->lpuart_timer); 2060 lpuart_dma_rx_free(&sport->port); 2061 } 2062 2063 spin_lock_irqsave(&sport->port.lock, flags); 2064 2065 sport->port.read_status_mask = 0; 2066 if (termios->c_iflag & INPCK) 2067 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE; 2068 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2069 sport->port.read_status_mask |= UARTSTAT_FE; 2070 2071 /* characters to ignore */ 2072 sport->port.ignore_status_mask = 0; 2073 if (termios->c_iflag & IGNPAR) 2074 sport->port.ignore_status_mask |= UARTSTAT_PE; 2075 if (termios->c_iflag & IGNBRK) { 2076 sport->port.ignore_status_mask |= UARTSTAT_FE; 2077 /* 2078 * if we're ignoring parity and break indicators, 2079 * ignore overruns too (for real raw support). 2080 */ 2081 if (termios->c_iflag & IGNPAR) 2082 sport->port.ignore_status_mask |= UARTSTAT_OR; 2083 } 2084 2085 /* update the per-port timeout */ 2086 uart_update_timeout(port, termios->c_cflag, baud); 2087 2088 /* wait transmit engin complete */ 2089 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2090 2091 /* disable transmit and receive */ 2092 lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE), 2093 UARTCTRL); 2094 2095 lpuart32_serial_setbrg(sport, baud); 2096 lpuart32_write(&sport->port, modem, UARTMODIR); 2097 lpuart32_write(&sport->port, ctrl, UARTCTRL); 2098 /* restore control register */ 2099 2100 if (old && sport->lpuart_dma_rx_use) { 2101 if (!lpuart_start_rx_dma(sport)) 2102 rx_dma_timer_init(sport); 2103 else 2104 sport->lpuart_dma_rx_use = false; 2105 } 2106 2107 spin_unlock_irqrestore(&sport->port.lock, flags); 2108 } 2109 2110 static const char *lpuart_type(struct uart_port *port) 2111 { 2112 return "FSL_LPUART"; 2113 } 2114 2115 static void lpuart_release_port(struct uart_port *port) 2116 { 2117 /* nothing to do */ 2118 } 2119 2120 static int lpuart_request_port(struct uart_port *port) 2121 { 2122 return 0; 2123 } 2124 2125 /* configure/autoconfigure the port */ 2126 static void lpuart_config_port(struct uart_port *port, int flags) 2127 { 2128 if (flags & UART_CONFIG_TYPE) 2129 port->type = PORT_LPUART; 2130 } 2131 2132 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser) 2133 { 2134 int ret = 0; 2135 2136 if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART) 2137 ret = -EINVAL; 2138 if (port->irq != ser->irq) 2139 ret = -EINVAL; 2140 if (ser->io_type != UPIO_MEM) 2141 ret = -EINVAL; 2142 if (port->uartclk / 16 != ser->baud_base) 2143 ret = -EINVAL; 2144 if (port->iobase != ser->port) 2145 ret = -EINVAL; 2146 if (ser->hub6 != 0) 2147 ret = -EINVAL; 2148 return ret; 2149 } 2150 2151 static const struct uart_ops lpuart_pops = { 2152 .tx_empty = lpuart_tx_empty, 2153 .set_mctrl = lpuart_set_mctrl, 2154 .get_mctrl = lpuart_get_mctrl, 2155 .stop_tx = lpuart_stop_tx, 2156 .start_tx = lpuart_start_tx, 2157 .stop_rx = lpuart_stop_rx, 2158 .break_ctl = lpuart_break_ctl, 2159 .startup = lpuart_startup, 2160 .shutdown = lpuart_shutdown, 2161 .set_termios = lpuart_set_termios, 2162 .type = lpuart_type, 2163 .request_port = lpuart_request_port, 2164 .release_port = lpuart_release_port, 2165 .config_port = lpuart_config_port, 2166 .verify_port = lpuart_verify_port, 2167 .flush_buffer = lpuart_flush_buffer, 2168 #if defined(CONFIG_CONSOLE_POLL) 2169 .poll_init = lpuart_poll_init, 2170 .poll_get_char = lpuart_poll_get_char, 2171 .poll_put_char = lpuart_poll_put_char, 2172 #endif 2173 }; 2174 2175 static const struct uart_ops lpuart32_pops = { 2176 .tx_empty = lpuart32_tx_empty, 2177 .set_mctrl = lpuart32_set_mctrl, 2178 .get_mctrl = lpuart32_get_mctrl, 2179 .stop_tx = lpuart32_stop_tx, 2180 .start_tx = lpuart32_start_tx, 2181 .stop_rx = lpuart32_stop_rx, 2182 .break_ctl = lpuart32_break_ctl, 2183 .startup = lpuart32_startup, 2184 .shutdown = lpuart32_shutdown, 2185 .set_termios = lpuart32_set_termios, 2186 .type = lpuart_type, 2187 .request_port = lpuart_request_port, 2188 .release_port = lpuart_release_port, 2189 .config_port = lpuart_config_port, 2190 .verify_port = lpuart_verify_port, 2191 .flush_buffer = lpuart_flush_buffer, 2192 #if defined(CONFIG_CONSOLE_POLL) 2193 .poll_init = lpuart32_poll_init, 2194 .poll_get_char = lpuart32_poll_get_char, 2195 .poll_put_char = lpuart32_poll_put_char, 2196 #endif 2197 }; 2198 2199 static struct lpuart_port *lpuart_ports[UART_NR]; 2200 2201 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE 2202 static void lpuart_console_putchar(struct uart_port *port, int ch) 2203 { 2204 lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE); 2205 writeb(ch, port->membase + UARTDR); 2206 } 2207 2208 static void lpuart32_console_putchar(struct uart_port *port, int ch) 2209 { 2210 lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE); 2211 lpuart32_write(port, ch, UARTDATA); 2212 } 2213 2214 static void 2215 lpuart_console_write(struct console *co, const char *s, unsigned int count) 2216 { 2217 struct lpuart_port *sport = lpuart_ports[co->index]; 2218 unsigned char old_cr2, cr2; 2219 unsigned long flags; 2220 int locked = 1; 2221 2222 if (sport->port.sysrq || oops_in_progress) 2223 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2224 else 2225 spin_lock_irqsave(&sport->port.lock, flags); 2226 2227 /* first save CR2 and then disable interrupts */ 2228 cr2 = old_cr2 = readb(sport->port.membase + UARTCR2); 2229 cr2 |= UARTCR2_TE | UARTCR2_RE; 2230 cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE); 2231 writeb(cr2, sport->port.membase + UARTCR2); 2232 2233 uart_console_write(&sport->port, s, count, lpuart_console_putchar); 2234 2235 /* wait for transmitter finish complete and restore CR2 */ 2236 lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC); 2237 2238 writeb(old_cr2, sport->port.membase + UARTCR2); 2239 2240 if (locked) 2241 spin_unlock_irqrestore(&sport->port.lock, flags); 2242 } 2243 2244 static void 2245 lpuart32_console_write(struct console *co, const char *s, unsigned int count) 2246 { 2247 struct lpuart_port *sport = lpuart_ports[co->index]; 2248 unsigned long old_cr, cr; 2249 unsigned long flags; 2250 int locked = 1; 2251 2252 if (sport->port.sysrq || oops_in_progress) 2253 locked = spin_trylock_irqsave(&sport->port.lock, flags); 2254 else 2255 spin_lock_irqsave(&sport->port.lock, flags); 2256 2257 /* first save CR2 and then disable interrupts */ 2258 cr = old_cr = lpuart32_read(&sport->port, UARTCTRL); 2259 cr |= UARTCTRL_TE | UARTCTRL_RE; 2260 cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE); 2261 lpuart32_write(&sport->port, cr, UARTCTRL); 2262 2263 uart_console_write(&sport->port, s, count, lpuart32_console_putchar); 2264 2265 /* wait for transmitter finish complete and restore CR2 */ 2266 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC); 2267 2268 lpuart32_write(&sport->port, old_cr, UARTCTRL); 2269 2270 if (locked) 2271 spin_unlock_irqrestore(&sport->port.lock, flags); 2272 } 2273 2274 /* 2275 * if the port was already initialised (eg, by a boot loader), 2276 * try to determine the current setup. 2277 */ 2278 static void __init 2279 lpuart_console_get_options(struct lpuart_port *sport, int *baud, 2280 int *parity, int *bits) 2281 { 2282 unsigned char cr, bdh, bdl, brfa; 2283 unsigned int sbr, uartclk, baud_raw; 2284 2285 cr = readb(sport->port.membase + UARTCR2); 2286 cr &= UARTCR2_TE | UARTCR2_RE; 2287 if (!cr) 2288 return; 2289 2290 /* ok, the port was enabled */ 2291 2292 cr = readb(sport->port.membase + UARTCR1); 2293 2294 *parity = 'n'; 2295 if (cr & UARTCR1_PE) { 2296 if (cr & UARTCR1_PT) 2297 *parity = 'o'; 2298 else 2299 *parity = 'e'; 2300 } 2301 2302 if (cr & UARTCR1_M) 2303 *bits = 9; 2304 else 2305 *bits = 8; 2306 2307 bdh = readb(sport->port.membase + UARTBDH); 2308 bdh &= UARTBDH_SBR_MASK; 2309 bdl = readb(sport->port.membase + UARTBDL); 2310 sbr = bdh; 2311 sbr <<= 8; 2312 sbr |= bdl; 2313 brfa = readb(sport->port.membase + UARTCR4); 2314 brfa &= UARTCR4_BRFA_MASK; 2315 2316 uartclk = lpuart_get_baud_clk_rate(sport); 2317 /* 2318 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2319 */ 2320 baud_raw = uartclk / (16 * (sbr + brfa / 32)); 2321 2322 if (*baud != baud_raw) 2323 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2324 "from %d to %d\n", baud_raw, *baud); 2325 } 2326 2327 static void __init 2328 lpuart32_console_get_options(struct lpuart_port *sport, int *baud, 2329 int *parity, int *bits) 2330 { 2331 unsigned long cr, bd; 2332 unsigned int sbr, uartclk, baud_raw; 2333 2334 cr = lpuart32_read(&sport->port, UARTCTRL); 2335 cr &= UARTCTRL_TE | UARTCTRL_RE; 2336 if (!cr) 2337 return; 2338 2339 /* ok, the port was enabled */ 2340 2341 cr = lpuart32_read(&sport->port, UARTCTRL); 2342 2343 *parity = 'n'; 2344 if (cr & UARTCTRL_PE) { 2345 if (cr & UARTCTRL_PT) 2346 *parity = 'o'; 2347 else 2348 *parity = 'e'; 2349 } 2350 2351 if (cr & UARTCTRL_M) 2352 *bits = 9; 2353 else 2354 *bits = 8; 2355 2356 bd = lpuart32_read(&sport->port, UARTBAUD); 2357 bd &= UARTBAUD_SBR_MASK; 2358 sbr = bd; 2359 uartclk = lpuart_get_baud_clk_rate(sport); 2360 /* 2361 * baud = mod_clk/(16*(sbr[13]+(brfa)/32) 2362 */ 2363 baud_raw = uartclk / (16 * sbr); 2364 2365 if (*baud != baud_raw) 2366 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate" 2367 "from %d to %d\n", baud_raw, *baud); 2368 } 2369 2370 static int __init lpuart_console_setup(struct console *co, char *options) 2371 { 2372 struct lpuart_port *sport; 2373 int baud = 115200; 2374 int bits = 8; 2375 int parity = 'n'; 2376 int flow = 'n'; 2377 2378 /* 2379 * check whether an invalid uart number has been specified, and 2380 * if so, search for the first available port that does have 2381 * console support. 2382 */ 2383 if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports)) 2384 co->index = 0; 2385 2386 sport = lpuart_ports[co->index]; 2387 if (sport == NULL) 2388 return -ENODEV; 2389 2390 if (options) 2391 uart_parse_options(options, &baud, &parity, &bits, &flow); 2392 else 2393 if (lpuart_is_32(sport)) 2394 lpuart32_console_get_options(sport, &baud, &parity, &bits); 2395 else 2396 lpuart_console_get_options(sport, &baud, &parity, &bits); 2397 2398 if (lpuart_is_32(sport)) 2399 lpuart32_setup_watermark(sport); 2400 else 2401 lpuart_setup_watermark(sport); 2402 2403 return uart_set_options(&sport->port, co, baud, parity, bits, flow); 2404 } 2405 2406 static struct uart_driver lpuart_reg; 2407 static struct console lpuart_console = { 2408 .name = DEV_NAME, 2409 .write = lpuart_console_write, 2410 .device = uart_console_device, 2411 .setup = lpuart_console_setup, 2412 .flags = CON_PRINTBUFFER, 2413 .index = -1, 2414 .data = &lpuart_reg, 2415 }; 2416 2417 static struct console lpuart32_console = { 2418 .name = DEV_NAME, 2419 .write = lpuart32_console_write, 2420 .device = uart_console_device, 2421 .setup = lpuart_console_setup, 2422 .flags = CON_PRINTBUFFER, 2423 .index = -1, 2424 .data = &lpuart_reg, 2425 }; 2426 2427 static void lpuart_early_write(struct console *con, const char *s, unsigned n) 2428 { 2429 struct earlycon_device *dev = con->data; 2430 2431 uart_console_write(&dev->port, s, n, lpuart_console_putchar); 2432 } 2433 2434 static void lpuart32_early_write(struct console *con, const char *s, unsigned n) 2435 { 2436 struct earlycon_device *dev = con->data; 2437 2438 uart_console_write(&dev->port, s, n, lpuart32_console_putchar); 2439 } 2440 2441 static int __init lpuart_early_console_setup(struct earlycon_device *device, 2442 const char *opt) 2443 { 2444 if (!device->port.membase) 2445 return -ENODEV; 2446 2447 device->con->write = lpuart_early_write; 2448 return 0; 2449 } 2450 2451 static int __init lpuart32_early_console_setup(struct earlycon_device *device, 2452 const char *opt) 2453 { 2454 if (!device->port.membase) 2455 return -ENODEV; 2456 2457 if (device->port.iotype != UPIO_MEM32) 2458 device->port.iotype = UPIO_MEM32BE; 2459 2460 device->con->write = lpuart32_early_write; 2461 return 0; 2462 } 2463 2464 static int __init ls1028a_early_console_setup(struct earlycon_device *device, 2465 const char *opt) 2466 { 2467 u32 cr; 2468 2469 if (!device->port.membase) 2470 return -ENODEV; 2471 2472 device->port.iotype = UPIO_MEM32; 2473 device->con->write = lpuart32_early_write; 2474 2475 /* set the baudrate */ 2476 if (device->port.uartclk && device->baud) 2477 __lpuart32_serial_setbrg(&device->port, device->baud, 2478 false, false); 2479 2480 /* enable transmitter */ 2481 cr = lpuart32_read(&device->port, UARTCTRL); 2482 cr |= UARTCTRL_TE; 2483 lpuart32_write(&device->port, cr, UARTCTRL); 2484 2485 return 0; 2486 } 2487 2488 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device, 2489 const char *opt) 2490 { 2491 if (!device->port.membase) 2492 return -ENODEV; 2493 2494 device->port.iotype = UPIO_MEM32; 2495 device->port.membase += IMX_REG_OFF; 2496 device->con->write = lpuart32_early_write; 2497 2498 return 0; 2499 } 2500 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup); 2501 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup); 2502 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup); 2503 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup); 2504 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup); 2505 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup); 2506 2507 #define LPUART_CONSOLE (&lpuart_console) 2508 #define LPUART32_CONSOLE (&lpuart32_console) 2509 #else 2510 #define LPUART_CONSOLE NULL 2511 #define LPUART32_CONSOLE NULL 2512 #endif 2513 2514 static struct uart_driver lpuart_reg = { 2515 .owner = THIS_MODULE, 2516 .driver_name = DRIVER_NAME, 2517 .dev_name = DEV_NAME, 2518 .nr = ARRAY_SIZE(lpuart_ports), 2519 .cons = LPUART_CONSOLE, 2520 }; 2521 2522 static int lpuart_probe(struct platform_device *pdev) 2523 { 2524 const struct of_device_id *of_id = of_match_device(lpuart_dt_ids, 2525 &pdev->dev); 2526 const struct lpuart_soc_data *sdata = of_id->data; 2527 struct device_node *np = pdev->dev.of_node; 2528 struct lpuart_port *sport; 2529 struct resource *res; 2530 int ret; 2531 2532 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL); 2533 if (!sport) 2534 return -ENOMEM; 2535 2536 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2537 sport->port.membase = devm_ioremap_resource(&pdev->dev, res); 2538 if (IS_ERR(sport->port.membase)) 2539 return PTR_ERR(sport->port.membase); 2540 2541 sport->port.membase += sdata->reg_off; 2542 sport->port.mapbase = res->start; 2543 sport->port.dev = &pdev->dev; 2544 sport->port.type = PORT_LPUART; 2545 sport->devtype = sdata->devtype; 2546 ret = platform_get_irq(pdev, 0); 2547 if (ret < 0) 2548 return ret; 2549 sport->port.irq = ret; 2550 sport->port.iotype = sdata->iotype; 2551 if (lpuart_is_32(sport)) 2552 sport->port.ops = &lpuart32_pops; 2553 else 2554 sport->port.ops = &lpuart_pops; 2555 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE); 2556 sport->port.flags = UPF_BOOT_AUTOCONF; 2557 2558 if (lpuart_is_32(sport)) 2559 sport->port.rs485_config = lpuart32_config_rs485; 2560 else 2561 sport->port.rs485_config = lpuart_config_rs485; 2562 2563 sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); 2564 if (IS_ERR(sport->ipg_clk)) { 2565 ret = PTR_ERR(sport->ipg_clk); 2566 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret); 2567 return ret; 2568 } 2569 2570 sport->baud_clk = NULL; 2571 if (is_imx8qxp_lpuart(sport)) { 2572 sport->baud_clk = devm_clk_get(&pdev->dev, "baud"); 2573 if (IS_ERR(sport->baud_clk)) { 2574 ret = PTR_ERR(sport->baud_clk); 2575 dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret); 2576 return ret; 2577 } 2578 } 2579 2580 ret = of_alias_get_id(np, "serial"); 2581 if (ret < 0) { 2582 ret = ida_simple_get(&fsl_lpuart_ida, 0, UART_NR, GFP_KERNEL); 2583 if (ret < 0) { 2584 dev_err(&pdev->dev, "port line is full, add device failed\n"); 2585 return ret; 2586 } 2587 sport->id_allocated = true; 2588 } 2589 if (ret >= ARRAY_SIZE(lpuart_ports)) { 2590 dev_err(&pdev->dev, "serial%d out of range\n", ret); 2591 ret = -EINVAL; 2592 goto failed_out_of_range; 2593 } 2594 sport->port.line = ret; 2595 2596 ret = lpuart_enable_clks(sport); 2597 if (ret) 2598 goto failed_clock_enable; 2599 sport->port.uartclk = lpuart_get_baud_clk_rate(sport); 2600 2601 lpuart_ports[sport->port.line] = sport; 2602 2603 platform_set_drvdata(pdev, &sport->port); 2604 2605 if (lpuart_is_32(sport)) { 2606 lpuart_reg.cons = LPUART32_CONSOLE; 2607 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart32_int, 0, 2608 DRIVER_NAME, sport); 2609 } else { 2610 lpuart_reg.cons = LPUART_CONSOLE; 2611 ret = devm_request_irq(&pdev->dev, sport->port.irq, lpuart_int, 0, 2612 DRIVER_NAME, sport); 2613 } 2614 2615 if (ret) 2616 goto failed_irq_request; 2617 2618 ret = uart_add_one_port(&lpuart_reg, &sport->port); 2619 if (ret) 2620 goto failed_attach_port; 2621 2622 ret = uart_get_rs485_mode(&sport->port); 2623 if (ret) 2624 goto failed_get_rs485; 2625 2626 if (sport->port.rs485.flags & SER_RS485_RX_DURING_TX) 2627 dev_err(&pdev->dev, "driver doesn't support RX during TX\n"); 2628 2629 if (sport->port.rs485.delay_rts_before_send || 2630 sport->port.rs485.delay_rts_after_send) 2631 dev_err(&pdev->dev, "driver doesn't support RTS delays\n"); 2632 2633 sport->port.rs485_config(&sport->port, &sport->port.rs485); 2634 2635 return 0; 2636 2637 failed_get_rs485: 2638 failed_attach_port: 2639 failed_irq_request: 2640 lpuart_disable_clks(sport); 2641 failed_clock_enable: 2642 failed_out_of_range: 2643 if (sport->id_allocated) 2644 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2645 return ret; 2646 } 2647 2648 static int lpuart_remove(struct platform_device *pdev) 2649 { 2650 struct lpuart_port *sport = platform_get_drvdata(pdev); 2651 2652 uart_remove_one_port(&lpuart_reg, &sport->port); 2653 2654 if (sport->id_allocated) 2655 ida_simple_remove(&fsl_lpuart_ida, sport->port.line); 2656 2657 lpuart_disable_clks(sport); 2658 2659 if (sport->dma_tx_chan) 2660 dma_release_channel(sport->dma_tx_chan); 2661 2662 if (sport->dma_rx_chan) 2663 dma_release_channel(sport->dma_rx_chan); 2664 2665 return 0; 2666 } 2667 2668 static int __maybe_unused lpuart_suspend(struct device *dev) 2669 { 2670 struct lpuart_port *sport = dev_get_drvdata(dev); 2671 unsigned long temp; 2672 bool irq_wake; 2673 2674 if (lpuart_is_32(sport)) { 2675 /* disable Rx/Tx and interrupts */ 2676 temp = lpuart32_read(&sport->port, UARTCTRL); 2677 temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE); 2678 lpuart32_write(&sport->port, temp, UARTCTRL); 2679 } else { 2680 /* disable Rx/Tx and interrupts */ 2681 temp = readb(sport->port.membase + UARTCR2); 2682 temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE); 2683 writeb(temp, sport->port.membase + UARTCR2); 2684 } 2685 2686 uart_suspend_port(&lpuart_reg, &sport->port); 2687 2688 /* uart_suspend_port() might set wakeup flag */ 2689 irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2690 2691 if (sport->lpuart_dma_rx_use) { 2692 /* 2693 * EDMA driver during suspend will forcefully release any 2694 * non-idle DMA channels. If port wakeup is enabled or if port 2695 * is console port or 'no_console_suspend' is set the Rx DMA 2696 * cannot resume as as expected, hence gracefully release the 2697 * Rx DMA path before suspend and start Rx DMA path on resume. 2698 */ 2699 if (irq_wake) { 2700 del_timer_sync(&sport->lpuart_timer); 2701 lpuart_dma_rx_free(&sport->port); 2702 } 2703 2704 /* Disable Rx DMA to use UART port as wakeup source */ 2705 if (lpuart_is_32(sport)) { 2706 temp = lpuart32_read(&sport->port, UARTBAUD); 2707 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE, 2708 UARTBAUD); 2709 } else { 2710 writeb(readb(sport->port.membase + UARTCR5) & 2711 ~UARTCR5_RDMAS, sport->port.membase + UARTCR5); 2712 } 2713 } 2714 2715 if (sport->lpuart_dma_tx_use) { 2716 sport->dma_tx_in_progress = false; 2717 dmaengine_terminate_all(sport->dma_tx_chan); 2718 } 2719 2720 if (sport->port.suspended && !irq_wake) 2721 lpuart_disable_clks(sport); 2722 2723 return 0; 2724 } 2725 2726 static int __maybe_unused lpuart_resume(struct device *dev) 2727 { 2728 struct lpuart_port *sport = dev_get_drvdata(dev); 2729 bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq)); 2730 2731 if (sport->port.suspended && !irq_wake) 2732 lpuart_enable_clks(sport); 2733 2734 if (lpuart_is_32(sport)) 2735 lpuart32_setup_watermark_enable(sport); 2736 else 2737 lpuart_setup_watermark_enable(sport); 2738 2739 if (sport->lpuart_dma_rx_use) { 2740 if (irq_wake) { 2741 if (!lpuart_start_rx_dma(sport)) 2742 rx_dma_timer_init(sport); 2743 else 2744 sport->lpuart_dma_rx_use = false; 2745 } 2746 } 2747 2748 lpuart_tx_dma_startup(sport); 2749 2750 if (lpuart_is_32(sport)) 2751 lpuart32_configure(sport); 2752 2753 uart_resume_port(&lpuart_reg, &sport->port); 2754 2755 return 0; 2756 } 2757 2758 static SIMPLE_DEV_PM_OPS(lpuart_pm_ops, lpuart_suspend, lpuart_resume); 2759 2760 static struct platform_driver lpuart_driver = { 2761 .probe = lpuart_probe, 2762 .remove = lpuart_remove, 2763 .driver = { 2764 .name = "fsl-lpuart", 2765 .of_match_table = lpuart_dt_ids, 2766 .pm = &lpuart_pm_ops, 2767 }, 2768 }; 2769 2770 static int __init lpuart_serial_init(void) 2771 { 2772 int ret = uart_register_driver(&lpuart_reg); 2773 2774 if (ret) 2775 return ret; 2776 2777 ret = platform_driver_register(&lpuart_driver); 2778 if (ret) 2779 uart_unregister_driver(&lpuart_reg); 2780 2781 return ret; 2782 } 2783 2784 static void __exit lpuart_serial_exit(void) 2785 { 2786 ida_destroy(&fsl_lpuart_ida); 2787 platform_driver_unregister(&lpuart_driver); 2788 uart_unregister_driver(&lpuart_reg); 2789 } 2790 2791 module_init(lpuart_serial_init); 2792 module_exit(lpuart_serial_exit); 2793 2794 MODULE_DESCRIPTION("Freescale lpuart serial port driver"); 2795 MODULE_LICENSE("GPL v2"); 2796