1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * 5 * This module enables machines with Intel VT-x extensions to run virtual 6 * machines without emulation or binary translation. 7 * 8 * Copyright (C) 2006 Qumranet, Inc. 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates. 10 * 11 * Authors: 12 * Avi Kivity <avi@qumranet.com> 13 * Yaniv Kamay <yaniv@qumranet.com> 14 */ 15 16 #include <linux/frame.h> 17 #include <linux/highmem.h> 18 #include <linux/hrtimer.h> 19 #include <linux/kernel.h> 20 #include <linux/kvm_host.h> 21 #include <linux/module.h> 22 #include <linux/moduleparam.h> 23 #include <linux/mod_devicetable.h> 24 #include <linux/mm.h> 25 #include <linux/sched.h> 26 #include <linux/sched/smt.h> 27 #include <linux/slab.h> 28 #include <linux/tboot.h> 29 #include <linux/trace_events.h> 30 31 #include <asm/apic.h> 32 #include <asm/asm.h> 33 #include <asm/cpu.h> 34 #include <asm/debugreg.h> 35 #include <asm/desc.h> 36 #include <asm/fpu/internal.h> 37 #include <asm/io.h> 38 #include <asm/irq_remapping.h> 39 #include <asm/kexec.h> 40 #include <asm/perf_event.h> 41 #include <asm/mce.h> 42 #include <asm/mmu_context.h> 43 #include <asm/mshyperv.h> 44 #include <asm/spec-ctrl.h> 45 #include <asm/virtext.h> 46 #include <asm/vmx.h> 47 48 #include "capabilities.h" 49 #include "cpuid.h" 50 #include "evmcs.h" 51 #include "irq.h" 52 #include "kvm_cache_regs.h" 53 #include "lapic.h" 54 #include "mmu.h" 55 #include "nested.h" 56 #include "ops.h" 57 #include "pmu.h" 58 #include "trace.h" 59 #include "vmcs.h" 60 #include "vmcs12.h" 61 #include "vmx.h" 62 #include "x86.h" 63 64 MODULE_AUTHOR("Qumranet"); 65 MODULE_LICENSE("GPL"); 66 67 static const struct x86_cpu_id vmx_cpu_id[] = { 68 X86_FEATURE_MATCH(X86_FEATURE_VMX), 69 {} 70 }; 71 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id); 72 73 bool __read_mostly enable_vpid = 1; 74 module_param_named(vpid, enable_vpid, bool, 0444); 75 76 static bool __read_mostly enable_vnmi = 1; 77 module_param_named(vnmi, enable_vnmi, bool, S_IRUGO); 78 79 bool __read_mostly flexpriority_enabled = 1; 80 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO); 81 82 bool __read_mostly enable_ept = 1; 83 module_param_named(ept, enable_ept, bool, S_IRUGO); 84 85 bool __read_mostly enable_unrestricted_guest = 1; 86 module_param_named(unrestricted_guest, 87 enable_unrestricted_guest, bool, S_IRUGO); 88 89 bool __read_mostly enable_ept_ad_bits = 1; 90 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO); 91 92 static bool __read_mostly emulate_invalid_guest_state = true; 93 module_param(emulate_invalid_guest_state, bool, S_IRUGO); 94 95 static bool __read_mostly fasteoi = 1; 96 module_param(fasteoi, bool, S_IRUGO); 97 98 static bool __read_mostly enable_apicv = 1; 99 module_param(enable_apicv, bool, S_IRUGO); 100 101 /* 102 * If nested=1, nested virtualization is supported, i.e., guests may use 103 * VMX and be a hypervisor for its own guests. If nested=0, guests may not 104 * use VMX instructions. 105 */ 106 static bool __read_mostly nested = 1; 107 module_param(nested, bool, S_IRUGO); 108 109 bool __read_mostly enable_pml = 1; 110 module_param_named(pml, enable_pml, bool, S_IRUGO); 111 112 static bool __read_mostly dump_invalid_vmcs = 0; 113 module_param(dump_invalid_vmcs, bool, 0644); 114 115 #define MSR_BITMAP_MODE_X2APIC 1 116 #define MSR_BITMAP_MODE_X2APIC_APICV 2 117 118 #define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL 119 120 /* Guest_tsc -> host_tsc conversion requires 64-bit division. */ 121 static int __read_mostly cpu_preemption_timer_multi; 122 static bool __read_mostly enable_preemption_timer = 1; 123 #ifdef CONFIG_X86_64 124 module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO); 125 #endif 126 127 #define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD) 128 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE 129 #define KVM_VM_CR0_ALWAYS_ON \ 130 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \ 131 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE) 132 #define KVM_CR4_GUEST_OWNED_BITS \ 133 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \ 134 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD) 135 136 #define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE 137 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE) 138 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE) 139 140 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM)) 141 142 #define MSR_IA32_RTIT_STATUS_MASK (~(RTIT_STATUS_FILTEREN | \ 143 RTIT_STATUS_CONTEXTEN | RTIT_STATUS_TRIGGEREN | \ 144 RTIT_STATUS_ERROR | RTIT_STATUS_STOPPED | \ 145 RTIT_STATUS_BYTECNT)) 146 147 #define MSR_IA32_RTIT_OUTPUT_BASE_MASK \ 148 (~((1UL << cpuid_query_maxphyaddr(vcpu)) - 1) | 0x7f) 149 150 /* 151 * These 2 parameters are used to config the controls for Pause-Loop Exiting: 152 * ple_gap: upper bound on the amount of time between two successive 153 * executions of PAUSE in a loop. Also indicate if ple enabled. 154 * According to test, this time is usually smaller than 128 cycles. 155 * ple_window: upper bound on the amount of time a guest is allowed to execute 156 * in a PAUSE loop. Tests indicate that most spinlocks are held for 157 * less than 2^12 cycles 158 * Time is measured based on a counter that runs at the same rate as the TSC, 159 * refer SDM volume 3b section 21.6.13 & 22.1.3. 160 */ 161 static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP; 162 module_param(ple_gap, uint, 0444); 163 164 static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW; 165 module_param(ple_window, uint, 0444); 166 167 /* Default doubles per-vcpu window every exit. */ 168 static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW; 169 module_param(ple_window_grow, uint, 0444); 170 171 /* Default resets per-vcpu window every exit to ple_window. */ 172 static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK; 173 module_param(ple_window_shrink, uint, 0444); 174 175 /* Default is to compute the maximum so we can never overflow. */ 176 static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX; 177 module_param(ple_window_max, uint, 0444); 178 179 /* Default is SYSTEM mode, 1 for host-guest mode */ 180 int __read_mostly pt_mode = PT_MODE_SYSTEM; 181 module_param(pt_mode, int, S_IRUGO); 182 183 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush); 184 static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond); 185 static DEFINE_MUTEX(vmx_l1d_flush_mutex); 186 187 /* Storage for pre module init parameter parsing */ 188 static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO; 189 190 static const struct { 191 const char *option; 192 bool for_parse; 193 } vmentry_l1d_param[] = { 194 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true}, 195 [VMENTER_L1D_FLUSH_NEVER] = {"never", true}, 196 [VMENTER_L1D_FLUSH_COND] = {"cond", true}, 197 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true}, 198 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false}, 199 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false}, 200 }; 201 202 #define L1D_CACHE_ORDER 4 203 static void *vmx_l1d_flush_pages; 204 205 static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf) 206 { 207 struct page *page; 208 unsigned int i; 209 210 if (!boot_cpu_has_bug(X86_BUG_L1TF)) { 211 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 212 return 0; 213 } 214 215 if (!enable_ept) { 216 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED; 217 return 0; 218 } 219 220 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) { 221 u64 msr; 222 223 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr); 224 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) { 225 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED; 226 return 0; 227 } 228 } 229 230 /* If set to auto use the default l1tf mitigation method */ 231 if (l1tf == VMENTER_L1D_FLUSH_AUTO) { 232 switch (l1tf_mitigation) { 233 case L1TF_MITIGATION_OFF: 234 l1tf = VMENTER_L1D_FLUSH_NEVER; 235 break; 236 case L1TF_MITIGATION_FLUSH_NOWARN: 237 case L1TF_MITIGATION_FLUSH: 238 case L1TF_MITIGATION_FLUSH_NOSMT: 239 l1tf = VMENTER_L1D_FLUSH_COND; 240 break; 241 case L1TF_MITIGATION_FULL: 242 case L1TF_MITIGATION_FULL_FORCE: 243 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 244 break; 245 } 246 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) { 247 l1tf = VMENTER_L1D_FLUSH_ALWAYS; 248 } 249 250 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages && 251 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) { 252 /* 253 * This allocation for vmx_l1d_flush_pages is not tied to a VM 254 * lifetime and so should not be charged to a memcg. 255 */ 256 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER); 257 if (!page) 258 return -ENOMEM; 259 vmx_l1d_flush_pages = page_address(page); 260 261 /* 262 * Initialize each page with a different pattern in 263 * order to protect against KSM in the nested 264 * virtualization case. 265 */ 266 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) { 267 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1, 268 PAGE_SIZE); 269 } 270 } 271 272 l1tf_vmx_mitigation = l1tf; 273 274 if (l1tf != VMENTER_L1D_FLUSH_NEVER) 275 static_branch_enable(&vmx_l1d_should_flush); 276 else 277 static_branch_disable(&vmx_l1d_should_flush); 278 279 if (l1tf == VMENTER_L1D_FLUSH_COND) 280 static_branch_enable(&vmx_l1d_flush_cond); 281 else 282 static_branch_disable(&vmx_l1d_flush_cond); 283 return 0; 284 } 285 286 static int vmentry_l1d_flush_parse(const char *s) 287 { 288 unsigned int i; 289 290 if (s) { 291 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) { 292 if (vmentry_l1d_param[i].for_parse && 293 sysfs_streq(s, vmentry_l1d_param[i].option)) 294 return i; 295 } 296 } 297 return -EINVAL; 298 } 299 300 static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp) 301 { 302 int l1tf, ret; 303 304 l1tf = vmentry_l1d_flush_parse(s); 305 if (l1tf < 0) 306 return l1tf; 307 308 if (!boot_cpu_has(X86_BUG_L1TF)) 309 return 0; 310 311 /* 312 * Has vmx_init() run already? If not then this is the pre init 313 * parameter parsing. In that case just store the value and let 314 * vmx_init() do the proper setup after enable_ept has been 315 * established. 316 */ 317 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) { 318 vmentry_l1d_flush_param = l1tf; 319 return 0; 320 } 321 322 mutex_lock(&vmx_l1d_flush_mutex); 323 ret = vmx_setup_l1d_flush(l1tf); 324 mutex_unlock(&vmx_l1d_flush_mutex); 325 return ret; 326 } 327 328 static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp) 329 { 330 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param))) 331 return sprintf(s, "???\n"); 332 333 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option); 334 } 335 336 static const struct kernel_param_ops vmentry_l1d_flush_ops = { 337 .set = vmentry_l1d_flush_set, 338 .get = vmentry_l1d_flush_get, 339 }; 340 module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644); 341 342 static bool guest_state_valid(struct kvm_vcpu *vcpu); 343 static u32 vmx_segment_access_rights(struct kvm_segment *var); 344 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 345 u32 msr, int type); 346 347 void vmx_vmexit(void); 348 349 #define vmx_insn_failed(fmt...) \ 350 do { \ 351 WARN_ONCE(1, fmt); \ 352 pr_warn_ratelimited(fmt); \ 353 } while (0) 354 355 asmlinkage void vmread_error(unsigned long field, bool fault) 356 { 357 if (fault) 358 kvm_spurious_fault(); 359 else 360 vmx_insn_failed("kvm: vmread failed: field=%lx\n", field); 361 } 362 363 noinline void vmwrite_error(unsigned long field, unsigned long value) 364 { 365 vmx_insn_failed("kvm: vmwrite failed: field=%lx val=%lx err=%d\n", 366 field, value, vmcs_read32(VM_INSTRUCTION_ERROR)); 367 } 368 369 noinline void vmclear_error(struct vmcs *vmcs, u64 phys_addr) 370 { 371 vmx_insn_failed("kvm: vmclear failed: %p/%llx\n", vmcs, phys_addr); 372 } 373 374 noinline void vmptrld_error(struct vmcs *vmcs, u64 phys_addr) 375 { 376 vmx_insn_failed("kvm: vmptrld failed: %p/%llx\n", vmcs, phys_addr); 377 } 378 379 noinline void invvpid_error(unsigned long ext, u16 vpid, gva_t gva) 380 { 381 vmx_insn_failed("kvm: invvpid failed: ext=0x%lx vpid=%u gva=0x%lx\n", 382 ext, vpid, gva); 383 } 384 385 noinline void invept_error(unsigned long ext, u64 eptp, gpa_t gpa) 386 { 387 vmx_insn_failed("kvm: invept failed: ext=0x%lx eptp=%llx gpa=0x%llx\n", 388 ext, eptp, gpa); 389 } 390 391 static DEFINE_PER_CPU(struct vmcs *, vmxarea); 392 DEFINE_PER_CPU(struct vmcs *, current_vmcs); 393 /* 394 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed 395 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it. 396 */ 397 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu); 398 399 /* 400 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we 401 * can find which vCPU should be waken up. 402 */ 403 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu); 404 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock); 405 406 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS); 407 static DEFINE_SPINLOCK(vmx_vpid_lock); 408 409 struct vmcs_config vmcs_config; 410 struct vmx_capability vmx_capability; 411 412 #define VMX_SEGMENT_FIELD(seg) \ 413 [VCPU_SREG_##seg] = { \ 414 .selector = GUEST_##seg##_SELECTOR, \ 415 .base = GUEST_##seg##_BASE, \ 416 .limit = GUEST_##seg##_LIMIT, \ 417 .ar_bytes = GUEST_##seg##_AR_BYTES, \ 418 } 419 420 static const struct kvm_vmx_segment_field { 421 unsigned selector; 422 unsigned base; 423 unsigned limit; 424 unsigned ar_bytes; 425 } kvm_vmx_segment_fields[] = { 426 VMX_SEGMENT_FIELD(CS), 427 VMX_SEGMENT_FIELD(DS), 428 VMX_SEGMENT_FIELD(ES), 429 VMX_SEGMENT_FIELD(FS), 430 VMX_SEGMENT_FIELD(GS), 431 VMX_SEGMENT_FIELD(SS), 432 VMX_SEGMENT_FIELD(TR), 433 VMX_SEGMENT_FIELD(LDTR), 434 }; 435 436 u64 host_efer; 437 static unsigned long host_idt_base; 438 439 /* 440 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm 441 * will emulate SYSCALL in legacy mode if the vendor string in guest 442 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To 443 * support this emulation, IA32_STAR must always be included in 444 * vmx_msr_index[], even in i386 builds. 445 */ 446 const u32 vmx_msr_index[] = { 447 #ifdef CONFIG_X86_64 448 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, 449 #endif 450 MSR_EFER, MSR_TSC_AUX, MSR_STAR, 451 MSR_IA32_TSX_CTRL, 452 }; 453 454 #if IS_ENABLED(CONFIG_HYPERV) 455 static bool __read_mostly enlightened_vmcs = true; 456 module_param(enlightened_vmcs, bool, 0444); 457 458 /* check_ept_pointer() should be under protection of ept_pointer_lock. */ 459 static void check_ept_pointer_match(struct kvm *kvm) 460 { 461 struct kvm_vcpu *vcpu; 462 u64 tmp_eptp = INVALID_PAGE; 463 int i; 464 465 kvm_for_each_vcpu(i, vcpu, kvm) { 466 if (!VALID_PAGE(tmp_eptp)) { 467 tmp_eptp = to_vmx(vcpu)->ept_pointer; 468 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) { 469 to_kvm_vmx(kvm)->ept_pointers_match 470 = EPT_POINTERS_MISMATCH; 471 return; 472 } 473 } 474 475 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH; 476 } 477 478 static int kvm_fill_hv_flush_list_func(struct hv_guest_mapping_flush_list *flush, 479 void *data) 480 { 481 struct kvm_tlb_range *range = data; 482 483 return hyperv_fill_flush_guest_mapping_list(flush, range->start_gfn, 484 range->pages); 485 } 486 487 static inline int __hv_remote_flush_tlb_with_range(struct kvm *kvm, 488 struct kvm_vcpu *vcpu, struct kvm_tlb_range *range) 489 { 490 u64 ept_pointer = to_vmx(vcpu)->ept_pointer; 491 492 /* 493 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs address 494 * of the base of EPT PML4 table, strip off EPT configuration 495 * information. 496 */ 497 if (range) 498 return hyperv_flush_guest_mapping_range(ept_pointer & PAGE_MASK, 499 kvm_fill_hv_flush_list_func, (void *)range); 500 else 501 return hyperv_flush_guest_mapping(ept_pointer & PAGE_MASK); 502 } 503 504 static int hv_remote_flush_tlb_with_range(struct kvm *kvm, 505 struct kvm_tlb_range *range) 506 { 507 struct kvm_vcpu *vcpu; 508 int ret = 0, i; 509 510 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 511 512 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK) 513 check_ept_pointer_match(kvm); 514 515 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) { 516 kvm_for_each_vcpu(i, vcpu, kvm) { 517 /* If ept_pointer is invalid pointer, bypass flush request. */ 518 if (VALID_PAGE(to_vmx(vcpu)->ept_pointer)) 519 ret |= __hv_remote_flush_tlb_with_range( 520 kvm, vcpu, range); 521 } 522 } else { 523 ret = __hv_remote_flush_tlb_with_range(kvm, 524 kvm_get_vcpu(kvm, 0), range); 525 } 526 527 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 528 return ret; 529 } 530 static int hv_remote_flush_tlb(struct kvm *kvm) 531 { 532 return hv_remote_flush_tlb_with_range(kvm, NULL); 533 } 534 535 static int hv_enable_direct_tlbflush(struct kvm_vcpu *vcpu) 536 { 537 struct hv_enlightened_vmcs *evmcs; 538 struct hv_partition_assist_pg **p_hv_pa_pg = 539 &vcpu->kvm->arch.hyperv.hv_pa_pg; 540 /* 541 * Synthetic VM-Exit is not enabled in current code and so All 542 * evmcs in singe VM shares same assist page. 543 */ 544 if (!*p_hv_pa_pg) 545 *p_hv_pa_pg = kzalloc(PAGE_SIZE, GFP_KERNEL); 546 547 if (!*p_hv_pa_pg) 548 return -ENOMEM; 549 550 evmcs = (struct hv_enlightened_vmcs *)to_vmx(vcpu)->loaded_vmcs->vmcs; 551 552 evmcs->partition_assist_page = 553 __pa(*p_hv_pa_pg); 554 evmcs->hv_vm_id = (unsigned long)vcpu->kvm; 555 evmcs->hv_enlightenments_control.nested_flush_hypercall = 1; 556 557 return 0; 558 } 559 560 #endif /* IS_ENABLED(CONFIG_HYPERV) */ 561 562 /* 563 * Comment's format: document - errata name - stepping - processor name. 564 * Refer from 565 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp 566 */ 567 static u32 vmx_preemption_cpu_tfms[] = { 568 /* 323344.pdf - BA86 - D0 - Xeon 7500 Series */ 569 0x000206E6, 570 /* 323056.pdf - AAX65 - C2 - Xeon L3406 */ 571 /* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */ 572 /* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */ 573 0x00020652, 574 /* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */ 575 0x00020655, 576 /* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */ 577 /* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */ 578 /* 579 * 320767.pdf - AAP86 - B1 - 580 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile 581 */ 582 0x000106E5, 583 /* 321333.pdf - AAM126 - C0 - Xeon 3500 */ 584 0x000106A0, 585 /* 321333.pdf - AAM126 - C1 - Xeon 3500 */ 586 0x000106A1, 587 /* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */ 588 0x000106A4, 589 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */ 590 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */ 591 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */ 592 0x000106A5, 593 /* Xeon E3-1220 V2 */ 594 0x000306A8, 595 }; 596 597 static inline bool cpu_has_broken_vmx_preemption_timer(void) 598 { 599 u32 eax = cpuid_eax(0x00000001), i; 600 601 /* Clear the reserved bits */ 602 eax &= ~(0x3U << 14 | 0xfU << 28); 603 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++) 604 if (eax == vmx_preemption_cpu_tfms[i]) 605 return true; 606 607 return false; 608 } 609 610 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu) 611 { 612 return flexpriority_enabled && lapic_in_kernel(vcpu); 613 } 614 615 static inline bool report_flexpriority(void) 616 { 617 return flexpriority_enabled; 618 } 619 620 static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr) 621 { 622 int i; 623 624 for (i = 0; i < vmx->nmsrs; ++i) 625 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr) 626 return i; 627 return -1; 628 } 629 630 struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr) 631 { 632 int i; 633 634 i = __find_msr_index(vmx, msr); 635 if (i >= 0) 636 return &vmx->guest_msrs[i]; 637 return NULL; 638 } 639 640 static int vmx_set_guest_msr(struct vcpu_vmx *vmx, struct shared_msr_entry *msr, u64 data) 641 { 642 int ret = 0; 643 644 u64 old_msr_data = msr->data; 645 msr->data = data; 646 if (msr - vmx->guest_msrs < vmx->save_nmsrs) { 647 preempt_disable(); 648 ret = kvm_set_shared_msr(msr->index, msr->data, 649 msr->mask); 650 preempt_enable(); 651 if (ret) 652 msr->data = old_msr_data; 653 } 654 return ret; 655 } 656 657 void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs) 658 { 659 vmcs_clear(loaded_vmcs->vmcs); 660 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched) 661 vmcs_clear(loaded_vmcs->shadow_vmcs); 662 loaded_vmcs->cpu = -1; 663 loaded_vmcs->launched = 0; 664 } 665 666 #ifdef CONFIG_KEXEC_CORE 667 /* 668 * This bitmap is used to indicate whether the vmclear 669 * operation is enabled on all cpus. All disabled by 670 * default. 671 */ 672 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE; 673 674 static inline void crash_enable_local_vmclear(int cpu) 675 { 676 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap); 677 } 678 679 static inline void crash_disable_local_vmclear(int cpu) 680 { 681 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap); 682 } 683 684 static inline int crash_local_vmclear_enabled(int cpu) 685 { 686 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap); 687 } 688 689 static void crash_vmclear_local_loaded_vmcss(void) 690 { 691 int cpu = raw_smp_processor_id(); 692 struct loaded_vmcs *v; 693 694 if (!crash_local_vmclear_enabled(cpu)) 695 return; 696 697 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu), 698 loaded_vmcss_on_cpu_link) 699 vmcs_clear(v->vmcs); 700 } 701 #else 702 static inline void crash_enable_local_vmclear(int cpu) { } 703 static inline void crash_disable_local_vmclear(int cpu) { } 704 #endif /* CONFIG_KEXEC_CORE */ 705 706 static void __loaded_vmcs_clear(void *arg) 707 { 708 struct loaded_vmcs *loaded_vmcs = arg; 709 int cpu = raw_smp_processor_id(); 710 711 if (loaded_vmcs->cpu != cpu) 712 return; /* vcpu migration can race with cpu offline */ 713 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs) 714 per_cpu(current_vmcs, cpu) = NULL; 715 crash_disable_local_vmclear(cpu); 716 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link); 717 718 /* 719 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link 720 * is before setting loaded_vmcs->vcpu to -1 which is done in 721 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist 722 * then adds the vmcs into percpu list before it is deleted. 723 */ 724 smp_wmb(); 725 726 loaded_vmcs_init(loaded_vmcs); 727 crash_enable_local_vmclear(cpu); 728 } 729 730 void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs) 731 { 732 int cpu = loaded_vmcs->cpu; 733 734 if (cpu != -1) 735 smp_call_function_single(cpu, 736 __loaded_vmcs_clear, loaded_vmcs, 1); 737 } 738 739 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg, 740 unsigned field) 741 { 742 bool ret; 743 u32 mask = 1 << (seg * SEG_FIELD_NR + field); 744 745 if (!kvm_register_is_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS)) { 746 kvm_register_mark_available(&vmx->vcpu, VCPU_EXREG_SEGMENTS); 747 vmx->segment_cache.bitmask = 0; 748 } 749 ret = vmx->segment_cache.bitmask & mask; 750 vmx->segment_cache.bitmask |= mask; 751 return ret; 752 } 753 754 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg) 755 { 756 u16 *p = &vmx->segment_cache.seg[seg].selector; 757 758 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL)) 759 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector); 760 return *p; 761 } 762 763 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg) 764 { 765 ulong *p = &vmx->segment_cache.seg[seg].base; 766 767 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE)) 768 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base); 769 return *p; 770 } 771 772 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg) 773 { 774 u32 *p = &vmx->segment_cache.seg[seg].limit; 775 776 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT)) 777 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit); 778 return *p; 779 } 780 781 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg) 782 { 783 u32 *p = &vmx->segment_cache.seg[seg].ar; 784 785 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR)) 786 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes); 787 return *p; 788 } 789 790 void update_exception_bitmap(struct kvm_vcpu *vcpu) 791 { 792 u32 eb; 793 794 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) | 795 (1u << DB_VECTOR) | (1u << AC_VECTOR); 796 /* 797 * Guest access to VMware backdoor ports could legitimately 798 * trigger #GP because of TSS I/O permission bitmap. 799 * We intercept those #GP and allow access to them anyway 800 * as VMware does. 801 */ 802 if (enable_vmware_backdoor) 803 eb |= (1u << GP_VECTOR); 804 if ((vcpu->guest_debug & 805 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) == 806 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) 807 eb |= 1u << BP_VECTOR; 808 if (to_vmx(vcpu)->rmode.vm86_active) 809 eb = ~0; 810 if (enable_ept) 811 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */ 812 813 /* When we are running a nested L2 guest and L1 specified for it a 814 * certain exception bitmap, we must trap the same exceptions and pass 815 * them to L1. When running L2, we will only handle the exceptions 816 * specified above if L1 did not want them. 817 */ 818 if (is_guest_mode(vcpu)) 819 eb |= get_vmcs12(vcpu)->exception_bitmap; 820 821 vmcs_write32(EXCEPTION_BITMAP, eb); 822 } 823 824 /* 825 * Check if MSR is intercepted for currently loaded MSR bitmap. 826 */ 827 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr) 828 { 829 unsigned long *msr_bitmap; 830 int f = sizeof(unsigned long); 831 832 if (!cpu_has_vmx_msr_bitmap()) 833 return true; 834 835 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap; 836 837 if (msr <= 0x1fff) { 838 return !!test_bit(msr, msr_bitmap + 0x800 / f); 839 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 840 msr &= 0x1fff; 841 return !!test_bit(msr, msr_bitmap + 0xc00 / f); 842 } 843 844 return true; 845 } 846 847 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx, 848 unsigned long entry, unsigned long exit) 849 { 850 vm_entry_controls_clearbit(vmx, entry); 851 vm_exit_controls_clearbit(vmx, exit); 852 } 853 854 int vmx_find_msr_index(struct vmx_msrs *m, u32 msr) 855 { 856 unsigned int i; 857 858 for (i = 0; i < m->nr; ++i) { 859 if (m->val[i].index == msr) 860 return i; 861 } 862 return -ENOENT; 863 } 864 865 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr) 866 { 867 int i; 868 struct msr_autoload *m = &vmx->msr_autoload; 869 870 switch (msr) { 871 case MSR_EFER: 872 if (cpu_has_load_ia32_efer()) { 873 clear_atomic_switch_msr_special(vmx, 874 VM_ENTRY_LOAD_IA32_EFER, 875 VM_EXIT_LOAD_IA32_EFER); 876 return; 877 } 878 break; 879 case MSR_CORE_PERF_GLOBAL_CTRL: 880 if (cpu_has_load_perf_global_ctrl()) { 881 clear_atomic_switch_msr_special(vmx, 882 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 883 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL); 884 return; 885 } 886 break; 887 } 888 i = vmx_find_msr_index(&m->guest, msr); 889 if (i < 0) 890 goto skip_guest; 891 --m->guest.nr; 892 m->guest.val[i] = m->guest.val[m->guest.nr]; 893 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 894 895 skip_guest: 896 i = vmx_find_msr_index(&m->host, msr); 897 if (i < 0) 898 return; 899 900 --m->host.nr; 901 m->host.val[i] = m->host.val[m->host.nr]; 902 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 903 } 904 905 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx, 906 unsigned long entry, unsigned long exit, 907 unsigned long guest_val_vmcs, unsigned long host_val_vmcs, 908 u64 guest_val, u64 host_val) 909 { 910 vmcs_write64(guest_val_vmcs, guest_val); 911 if (host_val_vmcs != HOST_IA32_EFER) 912 vmcs_write64(host_val_vmcs, host_val); 913 vm_entry_controls_setbit(vmx, entry); 914 vm_exit_controls_setbit(vmx, exit); 915 } 916 917 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr, 918 u64 guest_val, u64 host_val, bool entry_only) 919 { 920 int i, j = 0; 921 struct msr_autoload *m = &vmx->msr_autoload; 922 923 switch (msr) { 924 case MSR_EFER: 925 if (cpu_has_load_ia32_efer()) { 926 add_atomic_switch_msr_special(vmx, 927 VM_ENTRY_LOAD_IA32_EFER, 928 VM_EXIT_LOAD_IA32_EFER, 929 GUEST_IA32_EFER, 930 HOST_IA32_EFER, 931 guest_val, host_val); 932 return; 933 } 934 break; 935 case MSR_CORE_PERF_GLOBAL_CTRL: 936 if (cpu_has_load_perf_global_ctrl()) { 937 add_atomic_switch_msr_special(vmx, 938 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL, 939 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL, 940 GUEST_IA32_PERF_GLOBAL_CTRL, 941 HOST_IA32_PERF_GLOBAL_CTRL, 942 guest_val, host_val); 943 return; 944 } 945 break; 946 case MSR_IA32_PEBS_ENABLE: 947 /* PEBS needs a quiescent period after being disabled (to write 948 * a record). Disabling PEBS through VMX MSR swapping doesn't 949 * provide that period, so a CPU could write host's record into 950 * guest's memory. 951 */ 952 wrmsrl(MSR_IA32_PEBS_ENABLE, 0); 953 } 954 955 i = vmx_find_msr_index(&m->guest, msr); 956 if (!entry_only) 957 j = vmx_find_msr_index(&m->host, msr); 958 959 if ((i < 0 && m->guest.nr == NR_LOADSTORE_MSRS) || 960 (j < 0 && m->host.nr == NR_LOADSTORE_MSRS)) { 961 printk_once(KERN_WARNING "Not enough msr switch entries. " 962 "Can't add msr %x\n", msr); 963 return; 964 } 965 if (i < 0) { 966 i = m->guest.nr++; 967 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr); 968 } 969 m->guest.val[i].index = msr; 970 m->guest.val[i].value = guest_val; 971 972 if (entry_only) 973 return; 974 975 if (j < 0) { 976 j = m->host.nr++; 977 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr); 978 } 979 m->host.val[j].index = msr; 980 m->host.val[j].value = host_val; 981 } 982 983 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset) 984 { 985 u64 guest_efer = vmx->vcpu.arch.efer; 986 u64 ignore_bits = 0; 987 988 /* Shadow paging assumes NX to be available. */ 989 if (!enable_ept) 990 guest_efer |= EFER_NX; 991 992 /* 993 * LMA and LME handled by hardware; SCE meaningless outside long mode. 994 */ 995 ignore_bits |= EFER_SCE; 996 #ifdef CONFIG_X86_64 997 ignore_bits |= EFER_LMA | EFER_LME; 998 /* SCE is meaningful only in long mode on Intel */ 999 if (guest_efer & EFER_LMA) 1000 ignore_bits &= ~(u64)EFER_SCE; 1001 #endif 1002 1003 /* 1004 * On EPT, we can't emulate NX, so we must switch EFER atomically. 1005 * On CPUs that support "load IA32_EFER", always switch EFER 1006 * atomically, since it's faster than switching it manually. 1007 */ 1008 if (cpu_has_load_ia32_efer() || 1009 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) { 1010 if (!(guest_efer & EFER_LMA)) 1011 guest_efer &= ~EFER_LME; 1012 if (guest_efer != host_efer) 1013 add_atomic_switch_msr(vmx, MSR_EFER, 1014 guest_efer, host_efer, false); 1015 else 1016 clear_atomic_switch_msr(vmx, MSR_EFER); 1017 return false; 1018 } else { 1019 clear_atomic_switch_msr(vmx, MSR_EFER); 1020 1021 guest_efer &= ~ignore_bits; 1022 guest_efer |= host_efer & ignore_bits; 1023 1024 vmx->guest_msrs[efer_offset].data = guest_efer; 1025 vmx->guest_msrs[efer_offset].mask = ~ignore_bits; 1026 1027 return true; 1028 } 1029 } 1030 1031 #ifdef CONFIG_X86_32 1032 /* 1033 * On 32-bit kernels, VM exits still load the FS and GS bases from the 1034 * VMCS rather than the segment table. KVM uses this helper to figure 1035 * out the current bases to poke them into the VMCS before entry. 1036 */ 1037 static unsigned long segment_base(u16 selector) 1038 { 1039 struct desc_struct *table; 1040 unsigned long v; 1041 1042 if (!(selector & ~SEGMENT_RPL_MASK)) 1043 return 0; 1044 1045 table = get_current_gdt_ro(); 1046 1047 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) { 1048 u16 ldt_selector = kvm_read_ldt(); 1049 1050 if (!(ldt_selector & ~SEGMENT_RPL_MASK)) 1051 return 0; 1052 1053 table = (struct desc_struct *)segment_base(ldt_selector); 1054 } 1055 v = get_desc_base(&table[selector >> 3]); 1056 return v; 1057 } 1058 #endif 1059 1060 static inline bool pt_can_write_msr(struct vcpu_vmx *vmx) 1061 { 1062 return (pt_mode == PT_MODE_HOST_GUEST) && 1063 !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 1064 } 1065 1066 static inline void pt_load_msr(struct pt_ctx *ctx, u32 addr_range) 1067 { 1068 u32 i; 1069 1070 wrmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1071 wrmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1072 wrmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1073 wrmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1074 for (i = 0; i < addr_range; i++) { 1075 wrmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1076 wrmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1077 } 1078 } 1079 1080 static inline void pt_save_msr(struct pt_ctx *ctx, u32 addr_range) 1081 { 1082 u32 i; 1083 1084 rdmsrl(MSR_IA32_RTIT_STATUS, ctx->status); 1085 rdmsrl(MSR_IA32_RTIT_OUTPUT_BASE, ctx->output_base); 1086 rdmsrl(MSR_IA32_RTIT_OUTPUT_MASK, ctx->output_mask); 1087 rdmsrl(MSR_IA32_RTIT_CR3_MATCH, ctx->cr3_match); 1088 for (i = 0; i < addr_range; i++) { 1089 rdmsrl(MSR_IA32_RTIT_ADDR0_A + i * 2, ctx->addr_a[i]); 1090 rdmsrl(MSR_IA32_RTIT_ADDR0_B + i * 2, ctx->addr_b[i]); 1091 } 1092 } 1093 1094 static void pt_guest_enter(struct vcpu_vmx *vmx) 1095 { 1096 if (pt_mode == PT_MODE_SYSTEM) 1097 return; 1098 1099 /* 1100 * GUEST_IA32_RTIT_CTL is already set in the VMCS. 1101 * Save host state before VM entry. 1102 */ 1103 rdmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1104 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1105 wrmsrl(MSR_IA32_RTIT_CTL, 0); 1106 pt_save_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1107 pt_load_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1108 } 1109 } 1110 1111 static void pt_guest_exit(struct vcpu_vmx *vmx) 1112 { 1113 if (pt_mode == PT_MODE_SYSTEM) 1114 return; 1115 1116 if (vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) { 1117 pt_save_msr(&vmx->pt_desc.guest, vmx->pt_desc.addr_range); 1118 pt_load_msr(&vmx->pt_desc.host, vmx->pt_desc.addr_range); 1119 } 1120 1121 /* Reload host state (IA32_RTIT_CTL will be cleared on VM exit). */ 1122 wrmsrl(MSR_IA32_RTIT_CTL, vmx->pt_desc.host.ctl); 1123 } 1124 1125 void vmx_set_host_fs_gs(struct vmcs_host_state *host, u16 fs_sel, u16 gs_sel, 1126 unsigned long fs_base, unsigned long gs_base) 1127 { 1128 if (unlikely(fs_sel != host->fs_sel)) { 1129 if (!(fs_sel & 7)) 1130 vmcs_write16(HOST_FS_SELECTOR, fs_sel); 1131 else 1132 vmcs_write16(HOST_FS_SELECTOR, 0); 1133 host->fs_sel = fs_sel; 1134 } 1135 if (unlikely(gs_sel != host->gs_sel)) { 1136 if (!(gs_sel & 7)) 1137 vmcs_write16(HOST_GS_SELECTOR, gs_sel); 1138 else 1139 vmcs_write16(HOST_GS_SELECTOR, 0); 1140 host->gs_sel = gs_sel; 1141 } 1142 if (unlikely(fs_base != host->fs_base)) { 1143 vmcs_writel(HOST_FS_BASE, fs_base); 1144 host->fs_base = fs_base; 1145 } 1146 if (unlikely(gs_base != host->gs_base)) { 1147 vmcs_writel(HOST_GS_BASE, gs_base); 1148 host->gs_base = gs_base; 1149 } 1150 } 1151 1152 void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu) 1153 { 1154 struct vcpu_vmx *vmx = to_vmx(vcpu); 1155 struct vmcs_host_state *host_state; 1156 #ifdef CONFIG_X86_64 1157 int cpu = raw_smp_processor_id(); 1158 #endif 1159 unsigned long fs_base, gs_base; 1160 u16 fs_sel, gs_sel; 1161 int i; 1162 1163 vmx->req_immediate_exit = false; 1164 1165 /* 1166 * Note that guest MSRs to be saved/restored can also be changed 1167 * when guest state is loaded. This happens when guest transitions 1168 * to/from long-mode by setting MSR_EFER.LMA. 1169 */ 1170 if (!vmx->guest_msrs_ready) { 1171 vmx->guest_msrs_ready = true; 1172 for (i = 0; i < vmx->save_nmsrs; ++i) 1173 kvm_set_shared_msr(vmx->guest_msrs[i].index, 1174 vmx->guest_msrs[i].data, 1175 vmx->guest_msrs[i].mask); 1176 1177 } 1178 if (vmx->guest_state_loaded) 1179 return; 1180 1181 host_state = &vmx->loaded_vmcs->host_state; 1182 1183 /* 1184 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not 1185 * allow segment selectors with cpl > 0 or ti == 1. 1186 */ 1187 host_state->ldt_sel = kvm_read_ldt(); 1188 1189 #ifdef CONFIG_X86_64 1190 savesegment(ds, host_state->ds_sel); 1191 savesegment(es, host_state->es_sel); 1192 1193 gs_base = cpu_kernelmode_gs_base(cpu); 1194 if (likely(is_64bit_mm(current->mm))) { 1195 save_fsgs_for_kvm(); 1196 fs_sel = current->thread.fsindex; 1197 gs_sel = current->thread.gsindex; 1198 fs_base = current->thread.fsbase; 1199 vmx->msr_host_kernel_gs_base = current->thread.gsbase; 1200 } else { 1201 savesegment(fs, fs_sel); 1202 savesegment(gs, gs_sel); 1203 fs_base = read_msr(MSR_FS_BASE); 1204 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE); 1205 } 1206 1207 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1208 #else 1209 savesegment(fs, fs_sel); 1210 savesegment(gs, gs_sel); 1211 fs_base = segment_base(fs_sel); 1212 gs_base = segment_base(gs_sel); 1213 #endif 1214 1215 vmx_set_host_fs_gs(host_state, fs_sel, gs_sel, fs_base, gs_base); 1216 vmx->guest_state_loaded = true; 1217 } 1218 1219 static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx) 1220 { 1221 struct vmcs_host_state *host_state; 1222 1223 if (!vmx->guest_state_loaded) 1224 return; 1225 1226 host_state = &vmx->loaded_vmcs->host_state; 1227 1228 ++vmx->vcpu.stat.host_state_reload; 1229 1230 #ifdef CONFIG_X86_64 1231 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1232 #endif 1233 if (host_state->ldt_sel || (host_state->gs_sel & 7)) { 1234 kvm_load_ldt(host_state->ldt_sel); 1235 #ifdef CONFIG_X86_64 1236 load_gs_index(host_state->gs_sel); 1237 #else 1238 loadsegment(gs, host_state->gs_sel); 1239 #endif 1240 } 1241 if (host_state->fs_sel & 7) 1242 loadsegment(fs, host_state->fs_sel); 1243 #ifdef CONFIG_X86_64 1244 if (unlikely(host_state->ds_sel | host_state->es_sel)) { 1245 loadsegment(ds, host_state->ds_sel); 1246 loadsegment(es, host_state->es_sel); 1247 } 1248 #endif 1249 invalidate_tss_limit(); 1250 #ifdef CONFIG_X86_64 1251 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base); 1252 #endif 1253 load_fixmap_gdt(raw_smp_processor_id()); 1254 vmx->guest_state_loaded = false; 1255 vmx->guest_msrs_ready = false; 1256 } 1257 1258 #ifdef CONFIG_X86_64 1259 static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx) 1260 { 1261 preempt_disable(); 1262 if (vmx->guest_state_loaded) 1263 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base); 1264 preempt_enable(); 1265 return vmx->msr_guest_kernel_gs_base; 1266 } 1267 1268 static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data) 1269 { 1270 preempt_disable(); 1271 if (vmx->guest_state_loaded) 1272 wrmsrl(MSR_KERNEL_GS_BASE, data); 1273 preempt_enable(); 1274 vmx->msr_guest_kernel_gs_base = data; 1275 } 1276 #endif 1277 1278 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu) 1279 { 1280 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1281 struct pi_desc old, new; 1282 unsigned int dest; 1283 1284 /* 1285 * In case of hot-plug or hot-unplug, we may have to undo 1286 * vmx_vcpu_pi_put even if there is no assigned device. And we 1287 * always keep PI.NDST up to date for simplicity: it makes the 1288 * code easier, and CPU migration is not a fast path. 1289 */ 1290 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu) 1291 return; 1292 1293 /* 1294 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change 1295 * PI.NDST: pi_post_block is the one expected to change PID.NDST and the 1296 * wakeup handler expects the vCPU to be on the blocked_vcpu_list that 1297 * matches PI.NDST. Otherwise, a vcpu may not be able to be woken up 1298 * correctly. 1299 */ 1300 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR || vcpu->cpu == cpu) { 1301 pi_clear_sn(pi_desc); 1302 goto after_clear_sn; 1303 } 1304 1305 /* The full case. */ 1306 do { 1307 old.control = new.control = pi_desc->control; 1308 1309 dest = cpu_physical_id(cpu); 1310 1311 if (x2apic_enabled()) 1312 new.ndst = dest; 1313 else 1314 new.ndst = (dest << 8) & 0xFF00; 1315 1316 new.sn = 0; 1317 } while (cmpxchg64(&pi_desc->control, old.control, 1318 new.control) != old.control); 1319 1320 after_clear_sn: 1321 1322 /* 1323 * Clear SN before reading the bitmap. The VT-d firmware 1324 * writes the bitmap and reads SN atomically (5.2.3 in the 1325 * spec), so it doesn't really have a memory barrier that 1326 * pairs with this, but we cannot do that and we need one. 1327 */ 1328 smp_mb__after_atomic(); 1329 1330 if (!pi_is_pir_empty(pi_desc)) 1331 pi_set_on(pi_desc); 1332 } 1333 1334 void vmx_vcpu_load_vmcs(struct kvm_vcpu *vcpu, int cpu) 1335 { 1336 struct vcpu_vmx *vmx = to_vmx(vcpu); 1337 bool already_loaded = vmx->loaded_vmcs->cpu == cpu; 1338 1339 if (!already_loaded) { 1340 loaded_vmcs_clear(vmx->loaded_vmcs); 1341 local_irq_disable(); 1342 crash_disable_local_vmclear(cpu); 1343 1344 /* 1345 * Read loaded_vmcs->cpu should be before fetching 1346 * loaded_vmcs->loaded_vmcss_on_cpu_link. 1347 * See the comments in __loaded_vmcs_clear(). 1348 */ 1349 smp_rmb(); 1350 1351 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link, 1352 &per_cpu(loaded_vmcss_on_cpu, cpu)); 1353 crash_enable_local_vmclear(cpu); 1354 local_irq_enable(); 1355 } 1356 1357 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) { 1358 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs; 1359 vmcs_load(vmx->loaded_vmcs->vmcs); 1360 indirect_branch_prediction_barrier(); 1361 } 1362 1363 if (!already_loaded) { 1364 void *gdt = get_current_gdt_ro(); 1365 unsigned long sysenter_esp; 1366 1367 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 1368 1369 /* 1370 * Linux uses per-cpu TSS and GDT, so set these when switching 1371 * processors. See 22.2.4. 1372 */ 1373 vmcs_writel(HOST_TR_BASE, 1374 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss); 1375 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */ 1376 1377 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); 1378 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */ 1379 1380 vmx->loaded_vmcs->cpu = cpu; 1381 } 1382 1383 /* Setup TSC multiplier */ 1384 if (kvm_has_tsc_control && 1385 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) 1386 decache_tsc_multiplier(vmx); 1387 } 1388 1389 /* 1390 * Switches to specified vcpu, until a matching vcpu_put(), but assumes 1391 * vcpu mutex is already taken. 1392 */ 1393 void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu) 1394 { 1395 struct vcpu_vmx *vmx = to_vmx(vcpu); 1396 1397 vmx_vcpu_load_vmcs(vcpu, cpu); 1398 1399 vmx_vcpu_pi_load(vcpu, cpu); 1400 1401 vmx->host_pkru = read_pkru(); 1402 vmx->host_debugctlmsr = get_debugctlmsr(); 1403 } 1404 1405 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu) 1406 { 1407 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 1408 1409 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 1410 !irq_remapping_cap(IRQ_POSTING_CAP) || 1411 !kvm_vcpu_apicv_active(vcpu)) 1412 return; 1413 1414 /* Set SN when the vCPU is preempted */ 1415 if (vcpu->preempted) 1416 pi_set_sn(pi_desc); 1417 } 1418 1419 static void vmx_vcpu_put(struct kvm_vcpu *vcpu) 1420 { 1421 vmx_vcpu_pi_put(vcpu); 1422 1423 vmx_prepare_switch_to_host(to_vmx(vcpu)); 1424 } 1425 1426 static bool emulation_required(struct kvm_vcpu *vcpu) 1427 { 1428 return emulate_invalid_guest_state && !guest_state_valid(vcpu); 1429 } 1430 1431 unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu) 1432 { 1433 struct vcpu_vmx *vmx = to_vmx(vcpu); 1434 unsigned long rflags, save_rflags; 1435 1436 if (!kvm_register_is_available(vcpu, VCPU_EXREG_RFLAGS)) { 1437 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1438 rflags = vmcs_readl(GUEST_RFLAGS); 1439 if (vmx->rmode.vm86_active) { 1440 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 1441 save_rflags = vmx->rmode.save_rflags; 1442 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 1443 } 1444 vmx->rflags = rflags; 1445 } 1446 return vmx->rflags; 1447 } 1448 1449 void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags) 1450 { 1451 struct vcpu_vmx *vmx = to_vmx(vcpu); 1452 unsigned long old_rflags; 1453 1454 if (enable_unrestricted_guest) { 1455 kvm_register_mark_available(vcpu, VCPU_EXREG_RFLAGS); 1456 vmx->rflags = rflags; 1457 vmcs_writel(GUEST_RFLAGS, rflags); 1458 return; 1459 } 1460 1461 old_rflags = vmx_get_rflags(vcpu); 1462 vmx->rflags = rflags; 1463 if (vmx->rmode.vm86_active) { 1464 vmx->rmode.save_rflags = rflags; 1465 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 1466 } 1467 vmcs_writel(GUEST_RFLAGS, rflags); 1468 1469 if ((old_rflags ^ vmx->rflags) & X86_EFLAGS_VM) 1470 vmx->emulation_required = emulation_required(vcpu); 1471 } 1472 1473 u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu) 1474 { 1475 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1476 int ret = 0; 1477 1478 if (interruptibility & GUEST_INTR_STATE_STI) 1479 ret |= KVM_X86_SHADOW_INT_STI; 1480 if (interruptibility & GUEST_INTR_STATE_MOV_SS) 1481 ret |= KVM_X86_SHADOW_INT_MOV_SS; 1482 1483 return ret; 1484 } 1485 1486 void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask) 1487 { 1488 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO); 1489 u32 interruptibility = interruptibility_old; 1490 1491 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS); 1492 1493 if (mask & KVM_X86_SHADOW_INT_MOV_SS) 1494 interruptibility |= GUEST_INTR_STATE_MOV_SS; 1495 else if (mask & KVM_X86_SHADOW_INT_STI) 1496 interruptibility |= GUEST_INTR_STATE_STI; 1497 1498 if ((interruptibility != interruptibility_old)) 1499 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility); 1500 } 1501 1502 static int vmx_rtit_ctl_check(struct kvm_vcpu *vcpu, u64 data) 1503 { 1504 struct vcpu_vmx *vmx = to_vmx(vcpu); 1505 unsigned long value; 1506 1507 /* 1508 * Any MSR write that attempts to change bits marked reserved will 1509 * case a #GP fault. 1510 */ 1511 if (data & vmx->pt_desc.ctl_bitmask) 1512 return 1; 1513 1514 /* 1515 * Any attempt to modify IA32_RTIT_CTL while TraceEn is set will 1516 * result in a #GP unless the same write also clears TraceEn. 1517 */ 1518 if ((vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN) && 1519 ((vmx->pt_desc.guest.ctl ^ data) & ~RTIT_CTL_TRACEEN)) 1520 return 1; 1521 1522 /* 1523 * WRMSR to IA32_RTIT_CTL that sets TraceEn but clears this bit 1524 * and FabricEn would cause #GP, if 1525 * CPUID.(EAX=14H, ECX=0):ECX.SNGLRGNOUT[bit 2] = 0 1526 */ 1527 if ((data & RTIT_CTL_TRACEEN) && !(data & RTIT_CTL_TOPA) && 1528 !(data & RTIT_CTL_FABRIC_EN) && 1529 !intel_pt_validate_cap(vmx->pt_desc.caps, 1530 PT_CAP_single_range_output)) 1531 return 1; 1532 1533 /* 1534 * MTCFreq, CycThresh and PSBFreq encodings check, any MSR write that 1535 * utilize encodings marked reserved will casue a #GP fault. 1536 */ 1537 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc_periods); 1538 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc) && 1539 !test_bit((data & RTIT_CTL_MTC_RANGE) >> 1540 RTIT_CTL_MTC_RANGE_OFFSET, &value)) 1541 return 1; 1542 value = intel_pt_validate_cap(vmx->pt_desc.caps, 1543 PT_CAP_cycle_thresholds); 1544 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1545 !test_bit((data & RTIT_CTL_CYC_THRESH) >> 1546 RTIT_CTL_CYC_THRESH_OFFSET, &value)) 1547 return 1; 1548 value = intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_periods); 1549 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc) && 1550 !test_bit((data & RTIT_CTL_PSB_FREQ) >> 1551 RTIT_CTL_PSB_FREQ_OFFSET, &value)) 1552 return 1; 1553 1554 /* 1555 * If ADDRx_CFG is reserved or the encodings is >2 will 1556 * cause a #GP fault. 1557 */ 1558 value = (data & RTIT_CTL_ADDR0) >> RTIT_CTL_ADDR0_OFFSET; 1559 if ((value && (vmx->pt_desc.addr_range < 1)) || (value > 2)) 1560 return 1; 1561 value = (data & RTIT_CTL_ADDR1) >> RTIT_CTL_ADDR1_OFFSET; 1562 if ((value && (vmx->pt_desc.addr_range < 2)) || (value > 2)) 1563 return 1; 1564 value = (data & RTIT_CTL_ADDR2) >> RTIT_CTL_ADDR2_OFFSET; 1565 if ((value && (vmx->pt_desc.addr_range < 3)) || (value > 2)) 1566 return 1; 1567 value = (data & RTIT_CTL_ADDR3) >> RTIT_CTL_ADDR3_OFFSET; 1568 if ((value && (vmx->pt_desc.addr_range < 4)) || (value > 2)) 1569 return 1; 1570 1571 return 0; 1572 } 1573 1574 static int skip_emulated_instruction(struct kvm_vcpu *vcpu) 1575 { 1576 unsigned long rip; 1577 1578 /* 1579 * Using VMCS.VM_EXIT_INSTRUCTION_LEN on EPT misconfig depends on 1580 * undefined behavior: Intel's SDM doesn't mandate the VMCS field be 1581 * set when EPT misconfig occurs. In practice, real hardware updates 1582 * VM_EXIT_INSTRUCTION_LEN on EPT misconfig, but other hypervisors 1583 * (namely Hyper-V) don't set it due to it being undefined behavior, 1584 * i.e. we end up advancing IP with some random value. 1585 */ 1586 if (!static_cpu_has(X86_FEATURE_HYPERVISOR) || 1587 to_vmx(vcpu)->exit_reason != EXIT_REASON_EPT_MISCONFIG) { 1588 rip = kvm_rip_read(vcpu); 1589 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 1590 kvm_rip_write(vcpu, rip); 1591 } else { 1592 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP)) 1593 return 0; 1594 } 1595 1596 /* skipping an emulated instruction also counts */ 1597 vmx_set_interrupt_shadow(vcpu, 0); 1598 1599 return 1; 1600 } 1601 1602 static void vmx_clear_hlt(struct kvm_vcpu *vcpu) 1603 { 1604 /* 1605 * Ensure that we clear the HLT state in the VMCS. We don't need to 1606 * explicitly skip the instruction because if the HLT state is set, 1607 * then the instruction is already executing and RIP has already been 1608 * advanced. 1609 */ 1610 if (kvm_hlt_in_guest(vcpu->kvm) && 1611 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT) 1612 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 1613 } 1614 1615 static void vmx_queue_exception(struct kvm_vcpu *vcpu) 1616 { 1617 struct vcpu_vmx *vmx = to_vmx(vcpu); 1618 unsigned nr = vcpu->arch.exception.nr; 1619 bool has_error_code = vcpu->arch.exception.has_error_code; 1620 u32 error_code = vcpu->arch.exception.error_code; 1621 u32 intr_info = nr | INTR_INFO_VALID_MASK; 1622 1623 kvm_deliver_exception_payload(vcpu); 1624 1625 if (has_error_code) { 1626 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code); 1627 intr_info |= INTR_INFO_DELIVER_CODE_MASK; 1628 } 1629 1630 if (vmx->rmode.vm86_active) { 1631 int inc_eip = 0; 1632 if (kvm_exception_is_soft(nr)) 1633 inc_eip = vcpu->arch.event_exit_inst_len; 1634 kvm_inject_realmode_interrupt(vcpu, nr, inc_eip); 1635 return; 1636 } 1637 1638 WARN_ON_ONCE(vmx->emulation_required); 1639 1640 if (kvm_exception_is_soft(nr)) { 1641 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1642 vmx->vcpu.arch.event_exit_inst_len); 1643 intr_info |= INTR_TYPE_SOFT_EXCEPTION; 1644 } else 1645 intr_info |= INTR_TYPE_HARD_EXCEPTION; 1646 1647 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info); 1648 1649 vmx_clear_hlt(vcpu); 1650 } 1651 1652 static bool vmx_rdtscp_supported(void) 1653 { 1654 return cpu_has_vmx_rdtscp(); 1655 } 1656 1657 static bool vmx_invpcid_supported(void) 1658 { 1659 return cpu_has_vmx_invpcid(); 1660 } 1661 1662 /* 1663 * Swap MSR entry in host/guest MSR entry array. 1664 */ 1665 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to) 1666 { 1667 struct shared_msr_entry tmp; 1668 1669 tmp = vmx->guest_msrs[to]; 1670 vmx->guest_msrs[to] = vmx->guest_msrs[from]; 1671 vmx->guest_msrs[from] = tmp; 1672 } 1673 1674 /* 1675 * Set up the vmcs to automatically save and restore system 1676 * msrs. Don't touch the 64-bit msrs if the guest is in legacy 1677 * mode, as fiddling with msrs is very expensive. 1678 */ 1679 static void setup_msrs(struct vcpu_vmx *vmx) 1680 { 1681 int save_nmsrs, index; 1682 1683 save_nmsrs = 0; 1684 #ifdef CONFIG_X86_64 1685 /* 1686 * The SYSCALL MSRs are only needed on long mode guests, and only 1687 * when EFER.SCE is set. 1688 */ 1689 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) { 1690 index = __find_msr_index(vmx, MSR_STAR); 1691 if (index >= 0) 1692 move_msr_up(vmx, index, save_nmsrs++); 1693 index = __find_msr_index(vmx, MSR_LSTAR); 1694 if (index >= 0) 1695 move_msr_up(vmx, index, save_nmsrs++); 1696 index = __find_msr_index(vmx, MSR_SYSCALL_MASK); 1697 if (index >= 0) 1698 move_msr_up(vmx, index, save_nmsrs++); 1699 } 1700 #endif 1701 index = __find_msr_index(vmx, MSR_EFER); 1702 if (index >= 0 && update_transition_efer(vmx, index)) 1703 move_msr_up(vmx, index, save_nmsrs++); 1704 index = __find_msr_index(vmx, MSR_TSC_AUX); 1705 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP)) 1706 move_msr_up(vmx, index, save_nmsrs++); 1707 index = __find_msr_index(vmx, MSR_IA32_TSX_CTRL); 1708 if (index >= 0) 1709 move_msr_up(vmx, index, save_nmsrs++); 1710 1711 vmx->save_nmsrs = save_nmsrs; 1712 vmx->guest_msrs_ready = false; 1713 1714 if (cpu_has_vmx_msr_bitmap()) 1715 vmx_update_msr_bitmap(&vmx->vcpu); 1716 } 1717 1718 static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu) 1719 { 1720 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1721 1722 if (is_guest_mode(vcpu) && 1723 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1724 return vcpu->arch.tsc_offset - vmcs12->tsc_offset; 1725 1726 return vcpu->arch.tsc_offset; 1727 } 1728 1729 static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset) 1730 { 1731 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 1732 u64 g_tsc_offset = 0; 1733 1734 /* 1735 * We're here if L1 chose not to trap WRMSR to TSC. According 1736 * to the spec, this should set L1's TSC; The offset that L1 1737 * set for L2 remains unchanged, and still needs to be added 1738 * to the newly set TSC to get L2's TSC. 1739 */ 1740 if (is_guest_mode(vcpu) && 1741 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETTING)) 1742 g_tsc_offset = vmcs12->tsc_offset; 1743 1744 trace_kvm_write_tsc_offset(vcpu->vcpu_id, 1745 vcpu->arch.tsc_offset - g_tsc_offset, 1746 offset); 1747 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset); 1748 return offset + g_tsc_offset; 1749 } 1750 1751 /* 1752 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX 1753 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for 1754 * all guests if the "nested" module option is off, and can also be disabled 1755 * for a single guest by disabling its VMX cpuid bit. 1756 */ 1757 bool nested_vmx_allowed(struct kvm_vcpu *vcpu) 1758 { 1759 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX); 1760 } 1761 1762 static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu, 1763 uint64_t val) 1764 { 1765 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits; 1766 1767 return !(val & ~valid_bits); 1768 } 1769 1770 static int vmx_get_msr_feature(struct kvm_msr_entry *msr) 1771 { 1772 switch (msr->index) { 1773 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1774 if (!nested) 1775 return 1; 1776 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data); 1777 default: 1778 return 1; 1779 } 1780 } 1781 1782 /* 1783 * Reads an msr value (of 'msr_index') into 'pdata'. 1784 * Returns 0 on success, non-0 otherwise. 1785 * Assumes vcpu_load() was already called. 1786 */ 1787 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1788 { 1789 struct vcpu_vmx *vmx = to_vmx(vcpu); 1790 struct shared_msr_entry *msr; 1791 u32 index; 1792 1793 switch (msr_info->index) { 1794 #ifdef CONFIG_X86_64 1795 case MSR_FS_BASE: 1796 msr_info->data = vmcs_readl(GUEST_FS_BASE); 1797 break; 1798 case MSR_GS_BASE: 1799 msr_info->data = vmcs_readl(GUEST_GS_BASE); 1800 break; 1801 case MSR_KERNEL_GS_BASE: 1802 msr_info->data = vmx_read_guest_kernel_gs_base(vmx); 1803 break; 1804 #endif 1805 case MSR_EFER: 1806 return kvm_get_msr_common(vcpu, msr_info); 1807 case MSR_IA32_TSX_CTRL: 1808 if (!msr_info->host_initiated && 1809 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 1810 return 1; 1811 goto find_shared_msr; 1812 case MSR_IA32_UMWAIT_CONTROL: 1813 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1814 return 1; 1815 1816 msr_info->data = vmx->msr_ia32_umwait_control; 1817 break; 1818 case MSR_IA32_SPEC_CTRL: 1819 if (!msr_info->host_initiated && 1820 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 1821 return 1; 1822 1823 msr_info->data = to_vmx(vcpu)->spec_ctrl; 1824 break; 1825 case MSR_IA32_SYSENTER_CS: 1826 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS); 1827 break; 1828 case MSR_IA32_SYSENTER_EIP: 1829 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP); 1830 break; 1831 case MSR_IA32_SYSENTER_ESP: 1832 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP); 1833 break; 1834 case MSR_IA32_BNDCFGS: 1835 if (!kvm_mpx_supported() || 1836 (!msr_info->host_initiated && 1837 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1838 return 1; 1839 msr_info->data = vmcs_read64(GUEST_BNDCFGS); 1840 break; 1841 case MSR_IA32_MCG_EXT_CTL: 1842 if (!msr_info->host_initiated && 1843 !(vmx->msr_ia32_feature_control & 1844 FEAT_CTL_LMCE_ENABLED)) 1845 return 1; 1846 msr_info->data = vcpu->arch.mcg_ext_ctl; 1847 break; 1848 case MSR_IA32_FEAT_CTL: 1849 msr_info->data = vmx->msr_ia32_feature_control; 1850 break; 1851 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 1852 if (!nested_vmx_allowed(vcpu)) 1853 return 1; 1854 if (vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index, 1855 &msr_info->data)) 1856 return 1; 1857 /* 1858 * Enlightened VMCS v1 doesn't have certain fields, but buggy 1859 * Hyper-V versions are still trying to use corresponding 1860 * features when they are exposed. Filter out the essential 1861 * minimum. 1862 */ 1863 if (!msr_info->host_initiated && 1864 vmx->nested.enlightened_vmcs_enabled) 1865 nested_evmcs_filter_control_msr(msr_info->index, 1866 &msr_info->data); 1867 break; 1868 case MSR_IA32_RTIT_CTL: 1869 if (pt_mode != PT_MODE_HOST_GUEST) 1870 return 1; 1871 msr_info->data = vmx->pt_desc.guest.ctl; 1872 break; 1873 case MSR_IA32_RTIT_STATUS: 1874 if (pt_mode != PT_MODE_HOST_GUEST) 1875 return 1; 1876 msr_info->data = vmx->pt_desc.guest.status; 1877 break; 1878 case MSR_IA32_RTIT_CR3_MATCH: 1879 if ((pt_mode != PT_MODE_HOST_GUEST) || 1880 !intel_pt_validate_cap(vmx->pt_desc.caps, 1881 PT_CAP_cr3_filtering)) 1882 return 1; 1883 msr_info->data = vmx->pt_desc.guest.cr3_match; 1884 break; 1885 case MSR_IA32_RTIT_OUTPUT_BASE: 1886 if ((pt_mode != PT_MODE_HOST_GUEST) || 1887 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1888 PT_CAP_topa_output) && 1889 !intel_pt_validate_cap(vmx->pt_desc.caps, 1890 PT_CAP_single_range_output))) 1891 return 1; 1892 msr_info->data = vmx->pt_desc.guest.output_base; 1893 break; 1894 case MSR_IA32_RTIT_OUTPUT_MASK: 1895 if ((pt_mode != PT_MODE_HOST_GUEST) || 1896 (!intel_pt_validate_cap(vmx->pt_desc.caps, 1897 PT_CAP_topa_output) && 1898 !intel_pt_validate_cap(vmx->pt_desc.caps, 1899 PT_CAP_single_range_output))) 1900 return 1; 1901 msr_info->data = vmx->pt_desc.guest.output_mask; 1902 break; 1903 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 1904 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 1905 if ((pt_mode != PT_MODE_HOST_GUEST) || 1906 (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 1907 PT_CAP_num_address_ranges))) 1908 return 1; 1909 if (index % 2) 1910 msr_info->data = vmx->pt_desc.guest.addr_b[index / 2]; 1911 else 1912 msr_info->data = vmx->pt_desc.guest.addr_a[index / 2]; 1913 break; 1914 case MSR_TSC_AUX: 1915 if (!msr_info->host_initiated && 1916 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 1917 return 1; 1918 goto find_shared_msr; 1919 default: 1920 find_shared_msr: 1921 msr = find_msr_entry(vmx, msr_info->index); 1922 if (msr) { 1923 msr_info->data = msr->data; 1924 break; 1925 } 1926 return kvm_get_msr_common(vcpu, msr_info); 1927 } 1928 1929 return 0; 1930 } 1931 1932 /* 1933 * Writes msr value into the appropriate "register". 1934 * Returns 0 on success, non-0 otherwise. 1935 * Assumes vcpu_load() was already called. 1936 */ 1937 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 1938 { 1939 struct vcpu_vmx *vmx = to_vmx(vcpu); 1940 struct shared_msr_entry *msr; 1941 int ret = 0; 1942 u32 msr_index = msr_info->index; 1943 u64 data = msr_info->data; 1944 u32 index; 1945 1946 switch (msr_index) { 1947 case MSR_EFER: 1948 ret = kvm_set_msr_common(vcpu, msr_info); 1949 break; 1950 #ifdef CONFIG_X86_64 1951 case MSR_FS_BASE: 1952 vmx_segment_cache_clear(vmx); 1953 vmcs_writel(GUEST_FS_BASE, data); 1954 break; 1955 case MSR_GS_BASE: 1956 vmx_segment_cache_clear(vmx); 1957 vmcs_writel(GUEST_GS_BASE, data); 1958 break; 1959 case MSR_KERNEL_GS_BASE: 1960 vmx_write_guest_kernel_gs_base(vmx, data); 1961 break; 1962 #endif 1963 case MSR_IA32_SYSENTER_CS: 1964 if (is_guest_mode(vcpu)) 1965 get_vmcs12(vcpu)->guest_sysenter_cs = data; 1966 vmcs_write32(GUEST_SYSENTER_CS, data); 1967 break; 1968 case MSR_IA32_SYSENTER_EIP: 1969 if (is_guest_mode(vcpu)) 1970 get_vmcs12(vcpu)->guest_sysenter_eip = data; 1971 vmcs_writel(GUEST_SYSENTER_EIP, data); 1972 break; 1973 case MSR_IA32_SYSENTER_ESP: 1974 if (is_guest_mode(vcpu)) 1975 get_vmcs12(vcpu)->guest_sysenter_esp = data; 1976 vmcs_writel(GUEST_SYSENTER_ESP, data); 1977 break; 1978 case MSR_IA32_DEBUGCTLMSR: 1979 if (is_guest_mode(vcpu) && get_vmcs12(vcpu)->vm_exit_controls & 1980 VM_EXIT_SAVE_DEBUG_CONTROLS) 1981 get_vmcs12(vcpu)->guest_ia32_debugctl = data; 1982 1983 ret = kvm_set_msr_common(vcpu, msr_info); 1984 break; 1985 1986 case MSR_IA32_BNDCFGS: 1987 if (!kvm_mpx_supported() || 1988 (!msr_info->host_initiated && 1989 !guest_cpuid_has(vcpu, X86_FEATURE_MPX))) 1990 return 1; 1991 if (is_noncanonical_address(data & PAGE_MASK, vcpu) || 1992 (data & MSR_IA32_BNDCFGS_RSVD)) 1993 return 1; 1994 vmcs_write64(GUEST_BNDCFGS, data); 1995 break; 1996 case MSR_IA32_UMWAIT_CONTROL: 1997 if (!msr_info->host_initiated && !vmx_has_waitpkg(vmx)) 1998 return 1; 1999 2000 /* The reserved bit 1 and non-32 bit [63:32] should be zero */ 2001 if (data & (BIT_ULL(1) | GENMASK_ULL(63, 32))) 2002 return 1; 2003 2004 vmx->msr_ia32_umwait_control = data; 2005 break; 2006 case MSR_IA32_SPEC_CTRL: 2007 if (!msr_info->host_initiated && 2008 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2009 return 1; 2010 2011 if (data & ~kvm_spec_ctrl_valid_bits(vcpu)) 2012 return 1; 2013 2014 vmx->spec_ctrl = data; 2015 if (!data) 2016 break; 2017 2018 /* 2019 * For non-nested: 2020 * When it's written (to non-zero) for the first time, pass 2021 * it through. 2022 * 2023 * For nested: 2024 * The handling of the MSR bitmap for L2 guests is done in 2025 * nested_vmx_prepare_msr_bitmap. We should not touch the 2026 * vmcs02.msr_bitmap here since it gets completely overwritten 2027 * in the merging. We update the vmcs01 here for L1 as well 2028 * since it will end up touching the MSR anyway now. 2029 */ 2030 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, 2031 MSR_IA32_SPEC_CTRL, 2032 MSR_TYPE_RW); 2033 break; 2034 case MSR_IA32_TSX_CTRL: 2035 if (!msr_info->host_initiated && 2036 !(vcpu->arch.arch_capabilities & ARCH_CAP_TSX_CTRL_MSR)) 2037 return 1; 2038 if (data & ~(TSX_CTRL_RTM_DISABLE | TSX_CTRL_CPUID_CLEAR)) 2039 return 1; 2040 goto find_shared_msr; 2041 case MSR_IA32_PRED_CMD: 2042 if (!msr_info->host_initiated && 2043 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL)) 2044 return 1; 2045 2046 if (data & ~PRED_CMD_IBPB) 2047 return 1; 2048 if (!boot_cpu_has(X86_FEATURE_SPEC_CTRL)) 2049 return 1; 2050 if (!data) 2051 break; 2052 2053 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); 2054 2055 /* 2056 * For non-nested: 2057 * When it's written (to non-zero) for the first time, pass 2058 * it through. 2059 * 2060 * For nested: 2061 * The handling of the MSR bitmap for L2 guests is done in 2062 * nested_vmx_prepare_msr_bitmap. We should not touch the 2063 * vmcs02.msr_bitmap here since it gets completely overwritten 2064 * in the merging. 2065 */ 2066 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD, 2067 MSR_TYPE_W); 2068 break; 2069 case MSR_IA32_CR_PAT: 2070 if (!kvm_pat_valid(data)) 2071 return 1; 2072 2073 if (is_guest_mode(vcpu) && 2074 get_vmcs12(vcpu)->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT) 2075 get_vmcs12(vcpu)->guest_ia32_pat = data; 2076 2077 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) { 2078 vmcs_write64(GUEST_IA32_PAT, data); 2079 vcpu->arch.pat = data; 2080 break; 2081 } 2082 ret = kvm_set_msr_common(vcpu, msr_info); 2083 break; 2084 case MSR_IA32_TSC_ADJUST: 2085 ret = kvm_set_msr_common(vcpu, msr_info); 2086 break; 2087 case MSR_IA32_MCG_EXT_CTL: 2088 if ((!msr_info->host_initiated && 2089 !(to_vmx(vcpu)->msr_ia32_feature_control & 2090 FEAT_CTL_LMCE_ENABLED)) || 2091 (data & ~MCG_EXT_CTL_LMCE_EN)) 2092 return 1; 2093 vcpu->arch.mcg_ext_ctl = data; 2094 break; 2095 case MSR_IA32_FEAT_CTL: 2096 if (!vmx_feature_control_msr_valid(vcpu, data) || 2097 (to_vmx(vcpu)->msr_ia32_feature_control & 2098 FEAT_CTL_LOCKED && !msr_info->host_initiated)) 2099 return 1; 2100 vmx->msr_ia32_feature_control = data; 2101 if (msr_info->host_initiated && data == 0) 2102 vmx_leave_nested(vcpu); 2103 break; 2104 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 2105 if (!msr_info->host_initiated) 2106 return 1; /* they are read-only */ 2107 if (!nested_vmx_allowed(vcpu)) 2108 return 1; 2109 return vmx_set_vmx_msr(vcpu, msr_index, data); 2110 case MSR_IA32_RTIT_CTL: 2111 if ((pt_mode != PT_MODE_HOST_GUEST) || 2112 vmx_rtit_ctl_check(vcpu, data) || 2113 vmx->nested.vmxon) 2114 return 1; 2115 vmcs_write64(GUEST_IA32_RTIT_CTL, data); 2116 vmx->pt_desc.guest.ctl = data; 2117 pt_update_intercept_for_msr(vmx); 2118 break; 2119 case MSR_IA32_RTIT_STATUS: 2120 if (!pt_can_write_msr(vmx)) 2121 return 1; 2122 if (data & MSR_IA32_RTIT_STATUS_MASK) 2123 return 1; 2124 vmx->pt_desc.guest.status = data; 2125 break; 2126 case MSR_IA32_RTIT_CR3_MATCH: 2127 if (!pt_can_write_msr(vmx)) 2128 return 1; 2129 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2130 PT_CAP_cr3_filtering)) 2131 return 1; 2132 vmx->pt_desc.guest.cr3_match = data; 2133 break; 2134 case MSR_IA32_RTIT_OUTPUT_BASE: 2135 if (!pt_can_write_msr(vmx)) 2136 return 1; 2137 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2138 PT_CAP_topa_output) && 2139 !intel_pt_validate_cap(vmx->pt_desc.caps, 2140 PT_CAP_single_range_output)) 2141 return 1; 2142 if (data & MSR_IA32_RTIT_OUTPUT_BASE_MASK) 2143 return 1; 2144 vmx->pt_desc.guest.output_base = data; 2145 break; 2146 case MSR_IA32_RTIT_OUTPUT_MASK: 2147 if (!pt_can_write_msr(vmx)) 2148 return 1; 2149 if (!intel_pt_validate_cap(vmx->pt_desc.caps, 2150 PT_CAP_topa_output) && 2151 !intel_pt_validate_cap(vmx->pt_desc.caps, 2152 PT_CAP_single_range_output)) 2153 return 1; 2154 vmx->pt_desc.guest.output_mask = data; 2155 break; 2156 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B: 2157 if (!pt_can_write_msr(vmx)) 2158 return 1; 2159 index = msr_info->index - MSR_IA32_RTIT_ADDR0_A; 2160 if (index >= 2 * intel_pt_validate_cap(vmx->pt_desc.caps, 2161 PT_CAP_num_address_ranges)) 2162 return 1; 2163 if (is_noncanonical_address(data, vcpu)) 2164 return 1; 2165 if (index % 2) 2166 vmx->pt_desc.guest.addr_b[index / 2] = data; 2167 else 2168 vmx->pt_desc.guest.addr_a[index / 2] = data; 2169 break; 2170 case MSR_TSC_AUX: 2171 if (!msr_info->host_initiated && 2172 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP)) 2173 return 1; 2174 /* Check reserved bit, higher 32 bits should be zero */ 2175 if ((data >> 32) != 0) 2176 return 1; 2177 goto find_shared_msr; 2178 2179 default: 2180 find_shared_msr: 2181 msr = find_msr_entry(vmx, msr_index); 2182 if (msr) 2183 ret = vmx_set_guest_msr(vmx, msr, data); 2184 else 2185 ret = kvm_set_msr_common(vcpu, msr_info); 2186 } 2187 2188 return ret; 2189 } 2190 2191 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg) 2192 { 2193 kvm_register_mark_available(vcpu, reg); 2194 2195 switch (reg) { 2196 case VCPU_REGS_RSP: 2197 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP); 2198 break; 2199 case VCPU_REGS_RIP: 2200 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP); 2201 break; 2202 case VCPU_EXREG_PDPTR: 2203 if (enable_ept) 2204 ept_save_pdptrs(vcpu); 2205 break; 2206 case VCPU_EXREG_CR3: 2207 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu))) 2208 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3); 2209 break; 2210 default: 2211 WARN_ON_ONCE(1); 2212 break; 2213 } 2214 } 2215 2216 static __init int cpu_has_kvm_support(void) 2217 { 2218 return cpu_has_vmx(); 2219 } 2220 2221 static __init int vmx_disabled_by_bios(void) 2222 { 2223 return !boot_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 2224 !boot_cpu_has(X86_FEATURE_VMX); 2225 } 2226 2227 static void kvm_cpu_vmxon(u64 addr) 2228 { 2229 cr4_set_bits(X86_CR4_VMXE); 2230 intel_pt_handle_vmx(1); 2231 2232 asm volatile ("vmxon %0" : : "m"(addr)); 2233 } 2234 2235 static int hardware_enable(void) 2236 { 2237 int cpu = raw_smp_processor_id(); 2238 u64 phys_addr = __pa(per_cpu(vmxarea, cpu)); 2239 2240 if (cr4_read_shadow() & X86_CR4_VMXE) 2241 return -EBUSY; 2242 2243 /* 2244 * This can happen if we hot-added a CPU but failed to allocate 2245 * VP assist page for it. 2246 */ 2247 if (static_branch_unlikely(&enable_evmcs) && 2248 !hv_get_vp_assist_page(cpu)) 2249 return -EFAULT; 2250 2251 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu)); 2252 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu)); 2253 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 2254 2255 /* 2256 * Now we can enable the vmclear operation in kdump 2257 * since the loaded_vmcss_on_cpu list on this cpu 2258 * has been initialized. 2259 * 2260 * Though the cpu is not in VMX operation now, there 2261 * is no problem to enable the vmclear operation 2262 * for the loaded_vmcss_on_cpu list is empty! 2263 */ 2264 crash_enable_local_vmclear(cpu); 2265 2266 kvm_cpu_vmxon(phys_addr); 2267 if (enable_ept) 2268 ept_sync_global(); 2269 2270 return 0; 2271 } 2272 2273 static void vmclear_local_loaded_vmcss(void) 2274 { 2275 int cpu = raw_smp_processor_id(); 2276 struct loaded_vmcs *v, *n; 2277 2278 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu), 2279 loaded_vmcss_on_cpu_link) 2280 __loaded_vmcs_clear(v); 2281 } 2282 2283 2284 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot() 2285 * tricks. 2286 */ 2287 static void kvm_cpu_vmxoff(void) 2288 { 2289 asm volatile (__ex("vmxoff")); 2290 2291 intel_pt_handle_vmx(0); 2292 cr4_clear_bits(X86_CR4_VMXE); 2293 } 2294 2295 static void hardware_disable(void) 2296 { 2297 vmclear_local_loaded_vmcss(); 2298 kvm_cpu_vmxoff(); 2299 } 2300 2301 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt, 2302 u32 msr, u32 *result) 2303 { 2304 u32 vmx_msr_low, vmx_msr_high; 2305 u32 ctl = ctl_min | ctl_opt; 2306 2307 rdmsr(msr, vmx_msr_low, vmx_msr_high); 2308 2309 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */ 2310 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */ 2311 2312 /* Ensure minimum (required) set of control bits are supported. */ 2313 if (ctl_min & ~ctl) 2314 return -EIO; 2315 2316 *result = ctl; 2317 return 0; 2318 } 2319 2320 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf, 2321 struct vmx_capability *vmx_cap) 2322 { 2323 u32 vmx_msr_low, vmx_msr_high; 2324 u32 min, opt, min2, opt2; 2325 u32 _pin_based_exec_control = 0; 2326 u32 _cpu_based_exec_control = 0; 2327 u32 _cpu_based_2nd_exec_control = 0; 2328 u32 _vmexit_control = 0; 2329 u32 _vmentry_control = 0; 2330 2331 memset(vmcs_conf, 0, sizeof(*vmcs_conf)); 2332 min = CPU_BASED_HLT_EXITING | 2333 #ifdef CONFIG_X86_64 2334 CPU_BASED_CR8_LOAD_EXITING | 2335 CPU_BASED_CR8_STORE_EXITING | 2336 #endif 2337 CPU_BASED_CR3_LOAD_EXITING | 2338 CPU_BASED_CR3_STORE_EXITING | 2339 CPU_BASED_UNCOND_IO_EXITING | 2340 CPU_BASED_MOV_DR_EXITING | 2341 CPU_BASED_USE_TSC_OFFSETTING | 2342 CPU_BASED_MWAIT_EXITING | 2343 CPU_BASED_MONITOR_EXITING | 2344 CPU_BASED_INVLPG_EXITING | 2345 CPU_BASED_RDPMC_EXITING; 2346 2347 opt = CPU_BASED_TPR_SHADOW | 2348 CPU_BASED_USE_MSR_BITMAPS | 2349 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS; 2350 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS, 2351 &_cpu_based_exec_control) < 0) 2352 return -EIO; 2353 #ifdef CONFIG_X86_64 2354 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2355 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING & 2356 ~CPU_BASED_CR8_STORE_EXITING; 2357 #endif 2358 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) { 2359 min2 = 0; 2360 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 2361 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2362 SECONDARY_EXEC_WBINVD_EXITING | 2363 SECONDARY_EXEC_ENABLE_VPID | 2364 SECONDARY_EXEC_ENABLE_EPT | 2365 SECONDARY_EXEC_UNRESTRICTED_GUEST | 2366 SECONDARY_EXEC_PAUSE_LOOP_EXITING | 2367 SECONDARY_EXEC_DESC | 2368 SECONDARY_EXEC_RDTSCP | 2369 SECONDARY_EXEC_ENABLE_INVPCID | 2370 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2371 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | 2372 SECONDARY_EXEC_SHADOW_VMCS | 2373 SECONDARY_EXEC_XSAVES | 2374 SECONDARY_EXEC_RDSEED_EXITING | 2375 SECONDARY_EXEC_RDRAND_EXITING | 2376 SECONDARY_EXEC_ENABLE_PML | 2377 SECONDARY_EXEC_TSC_SCALING | 2378 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE | 2379 SECONDARY_EXEC_PT_USE_GPA | 2380 SECONDARY_EXEC_PT_CONCEAL_VMX | 2381 SECONDARY_EXEC_ENABLE_VMFUNC | 2382 SECONDARY_EXEC_ENCLS_EXITING; 2383 if (adjust_vmx_controls(min2, opt2, 2384 MSR_IA32_VMX_PROCBASED_CTLS2, 2385 &_cpu_based_2nd_exec_control) < 0) 2386 return -EIO; 2387 } 2388 #ifndef CONFIG_X86_64 2389 if (!(_cpu_based_2nd_exec_control & 2390 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) 2391 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW; 2392 #endif 2393 2394 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)) 2395 _cpu_based_2nd_exec_control &= ~( 2396 SECONDARY_EXEC_APIC_REGISTER_VIRT | 2397 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 2398 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 2399 2400 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP, 2401 &vmx_cap->ept, &vmx_cap->vpid); 2402 2403 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) { 2404 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT 2405 enabled */ 2406 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING | 2407 CPU_BASED_CR3_STORE_EXITING | 2408 CPU_BASED_INVLPG_EXITING); 2409 } else if (vmx_cap->ept) { 2410 vmx_cap->ept = 0; 2411 pr_warn_once("EPT CAP should not exist if not support " 2412 "1-setting enable EPT VM-execution control\n"); 2413 } 2414 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) && 2415 vmx_cap->vpid) { 2416 vmx_cap->vpid = 0; 2417 pr_warn_once("VPID CAP should not exist if not support " 2418 "1-setting enable VPID VM-execution control\n"); 2419 } 2420 2421 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT; 2422 #ifdef CONFIG_X86_64 2423 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE; 2424 #endif 2425 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | 2426 VM_EXIT_LOAD_IA32_PAT | 2427 VM_EXIT_LOAD_IA32_EFER | 2428 VM_EXIT_CLEAR_BNDCFGS | 2429 VM_EXIT_PT_CONCEAL_PIP | 2430 VM_EXIT_CLEAR_IA32_RTIT_CTL; 2431 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS, 2432 &_vmexit_control) < 0) 2433 return -EIO; 2434 2435 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING; 2436 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR | 2437 PIN_BASED_VMX_PREEMPTION_TIMER; 2438 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS, 2439 &_pin_based_exec_control) < 0) 2440 return -EIO; 2441 2442 if (cpu_has_broken_vmx_preemption_timer()) 2443 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 2444 if (!(_cpu_based_2nd_exec_control & 2445 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)) 2446 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR; 2447 2448 min = VM_ENTRY_LOAD_DEBUG_CONTROLS; 2449 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | 2450 VM_ENTRY_LOAD_IA32_PAT | 2451 VM_ENTRY_LOAD_IA32_EFER | 2452 VM_ENTRY_LOAD_BNDCFGS | 2453 VM_ENTRY_PT_CONCEAL_PIP | 2454 VM_ENTRY_LOAD_IA32_RTIT_CTL; 2455 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS, 2456 &_vmentry_control) < 0) 2457 return -EIO; 2458 2459 /* 2460 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they 2461 * can't be used due to an errata where VM Exit may incorrectly clear 2462 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the 2463 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL. 2464 */ 2465 if (boot_cpu_data.x86 == 0x6) { 2466 switch (boot_cpu_data.x86_model) { 2467 case 26: /* AAK155 */ 2468 case 30: /* AAP115 */ 2469 case 37: /* AAT100 */ 2470 case 44: /* BC86,AAY89,BD102 */ 2471 case 46: /* BA97 */ 2472 _vmentry_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL; 2473 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL; 2474 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL " 2475 "does not work properly. Using workaround\n"); 2476 break; 2477 default: 2478 break; 2479 } 2480 } 2481 2482 2483 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high); 2484 2485 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */ 2486 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE) 2487 return -EIO; 2488 2489 #ifdef CONFIG_X86_64 2490 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */ 2491 if (vmx_msr_high & (1u<<16)) 2492 return -EIO; 2493 #endif 2494 2495 /* Require Write-Back (WB) memory type for VMCS accesses. */ 2496 if (((vmx_msr_high >> 18) & 15) != 6) 2497 return -EIO; 2498 2499 vmcs_conf->size = vmx_msr_high & 0x1fff; 2500 vmcs_conf->order = get_order(vmcs_conf->size); 2501 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff; 2502 2503 vmcs_conf->revision_id = vmx_msr_low; 2504 2505 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control; 2506 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control; 2507 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control; 2508 vmcs_conf->vmexit_ctrl = _vmexit_control; 2509 vmcs_conf->vmentry_ctrl = _vmentry_control; 2510 2511 if (static_branch_unlikely(&enable_evmcs)) 2512 evmcs_sanitize_exec_ctrls(vmcs_conf); 2513 2514 return 0; 2515 } 2516 2517 struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu, gfp_t flags) 2518 { 2519 int node = cpu_to_node(cpu); 2520 struct page *pages; 2521 struct vmcs *vmcs; 2522 2523 pages = __alloc_pages_node(node, flags, vmcs_config.order); 2524 if (!pages) 2525 return NULL; 2526 vmcs = page_address(pages); 2527 memset(vmcs, 0, vmcs_config.size); 2528 2529 /* KVM supports Enlightened VMCS v1 only */ 2530 if (static_branch_unlikely(&enable_evmcs)) 2531 vmcs->hdr.revision_id = KVM_EVMCS_VERSION; 2532 else 2533 vmcs->hdr.revision_id = vmcs_config.revision_id; 2534 2535 if (shadow) 2536 vmcs->hdr.shadow_vmcs = 1; 2537 return vmcs; 2538 } 2539 2540 void free_vmcs(struct vmcs *vmcs) 2541 { 2542 free_pages((unsigned long)vmcs, vmcs_config.order); 2543 } 2544 2545 /* 2546 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded 2547 */ 2548 void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2549 { 2550 if (!loaded_vmcs->vmcs) 2551 return; 2552 loaded_vmcs_clear(loaded_vmcs); 2553 free_vmcs(loaded_vmcs->vmcs); 2554 loaded_vmcs->vmcs = NULL; 2555 if (loaded_vmcs->msr_bitmap) 2556 free_page((unsigned long)loaded_vmcs->msr_bitmap); 2557 WARN_ON(loaded_vmcs->shadow_vmcs != NULL); 2558 } 2559 2560 int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs) 2561 { 2562 loaded_vmcs->vmcs = alloc_vmcs(false); 2563 if (!loaded_vmcs->vmcs) 2564 return -ENOMEM; 2565 2566 loaded_vmcs->shadow_vmcs = NULL; 2567 loaded_vmcs->hv_timer_soft_disabled = false; 2568 loaded_vmcs_init(loaded_vmcs); 2569 2570 if (cpu_has_vmx_msr_bitmap()) { 2571 loaded_vmcs->msr_bitmap = (unsigned long *) 2572 __get_free_page(GFP_KERNEL_ACCOUNT); 2573 if (!loaded_vmcs->msr_bitmap) 2574 goto out_vmcs; 2575 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE); 2576 2577 if (IS_ENABLED(CONFIG_HYPERV) && 2578 static_branch_unlikely(&enable_evmcs) && 2579 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) { 2580 struct hv_enlightened_vmcs *evmcs = 2581 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs; 2582 2583 evmcs->hv_enlightenments_control.msr_bitmap = 1; 2584 } 2585 } 2586 2587 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state)); 2588 memset(&loaded_vmcs->controls_shadow, 0, 2589 sizeof(struct vmcs_controls_shadow)); 2590 2591 return 0; 2592 2593 out_vmcs: 2594 free_loaded_vmcs(loaded_vmcs); 2595 return -ENOMEM; 2596 } 2597 2598 static void free_kvm_area(void) 2599 { 2600 int cpu; 2601 2602 for_each_possible_cpu(cpu) { 2603 free_vmcs(per_cpu(vmxarea, cpu)); 2604 per_cpu(vmxarea, cpu) = NULL; 2605 } 2606 } 2607 2608 static __init int alloc_kvm_area(void) 2609 { 2610 int cpu; 2611 2612 for_each_possible_cpu(cpu) { 2613 struct vmcs *vmcs; 2614 2615 vmcs = alloc_vmcs_cpu(false, cpu, GFP_KERNEL); 2616 if (!vmcs) { 2617 free_kvm_area(); 2618 return -ENOMEM; 2619 } 2620 2621 /* 2622 * When eVMCS is enabled, alloc_vmcs_cpu() sets 2623 * vmcs->revision_id to KVM_EVMCS_VERSION instead of 2624 * revision_id reported by MSR_IA32_VMX_BASIC. 2625 * 2626 * However, even though not explicitly documented by 2627 * TLFS, VMXArea passed as VMXON argument should 2628 * still be marked with revision_id reported by 2629 * physical CPU. 2630 */ 2631 if (static_branch_unlikely(&enable_evmcs)) 2632 vmcs->hdr.revision_id = vmcs_config.revision_id; 2633 2634 per_cpu(vmxarea, cpu) = vmcs; 2635 } 2636 return 0; 2637 } 2638 2639 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg, 2640 struct kvm_segment *save) 2641 { 2642 if (!emulate_invalid_guest_state) { 2643 /* 2644 * CS and SS RPL should be equal during guest entry according 2645 * to VMX spec, but in reality it is not always so. Since vcpu 2646 * is in the middle of the transition from real mode to 2647 * protected mode it is safe to assume that RPL 0 is a good 2648 * default value. 2649 */ 2650 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS) 2651 save->selector &= ~SEGMENT_RPL_MASK; 2652 save->dpl = save->selector & SEGMENT_RPL_MASK; 2653 save->s = 1; 2654 } 2655 vmx_set_segment(vcpu, save, seg); 2656 } 2657 2658 static void enter_pmode(struct kvm_vcpu *vcpu) 2659 { 2660 unsigned long flags; 2661 struct vcpu_vmx *vmx = to_vmx(vcpu); 2662 2663 /* 2664 * Update real mode segment cache. It may be not up-to-date if sement 2665 * register was written while vcpu was in a guest mode. 2666 */ 2667 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2668 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2669 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2670 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2671 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2672 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2673 2674 vmx->rmode.vm86_active = 0; 2675 2676 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2677 2678 flags = vmcs_readl(GUEST_RFLAGS); 2679 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS; 2680 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS; 2681 vmcs_writel(GUEST_RFLAGS, flags); 2682 2683 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) | 2684 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME)); 2685 2686 update_exception_bitmap(vcpu); 2687 2688 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2689 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2690 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2691 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2692 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2693 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2694 } 2695 2696 static void fix_rmode_seg(int seg, struct kvm_segment *save) 2697 { 2698 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 2699 struct kvm_segment var = *save; 2700 2701 var.dpl = 0x3; 2702 if (seg == VCPU_SREG_CS) 2703 var.type = 0x3; 2704 2705 if (!emulate_invalid_guest_state) { 2706 var.selector = var.base >> 4; 2707 var.base = var.base & 0xffff0; 2708 var.limit = 0xffff; 2709 var.g = 0; 2710 var.db = 0; 2711 var.present = 1; 2712 var.s = 1; 2713 var.l = 0; 2714 var.unusable = 0; 2715 var.type = 0x3; 2716 var.avl = 0; 2717 if (save->base & 0xf) 2718 printk_once(KERN_WARNING "kvm: segment base is not " 2719 "paragraph aligned when entering " 2720 "protected mode (seg=%d)", seg); 2721 } 2722 2723 vmcs_write16(sf->selector, var.selector); 2724 vmcs_writel(sf->base, var.base); 2725 vmcs_write32(sf->limit, var.limit); 2726 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var)); 2727 } 2728 2729 static void enter_rmode(struct kvm_vcpu *vcpu) 2730 { 2731 unsigned long flags; 2732 struct vcpu_vmx *vmx = to_vmx(vcpu); 2733 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm); 2734 2735 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR); 2736 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES); 2737 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS); 2738 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS); 2739 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS); 2740 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS); 2741 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS); 2742 2743 vmx->rmode.vm86_active = 1; 2744 2745 /* 2746 * Very old userspace does not call KVM_SET_TSS_ADDR before entering 2747 * vcpu. Warn the user that an update is overdue. 2748 */ 2749 if (!kvm_vmx->tss_addr) 2750 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be " 2751 "called before entering vcpu\n"); 2752 2753 vmx_segment_cache_clear(vmx); 2754 2755 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr); 2756 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1); 2757 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 2758 2759 flags = vmcs_readl(GUEST_RFLAGS); 2760 vmx->rmode.save_rflags = flags; 2761 2762 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM; 2763 2764 vmcs_writel(GUEST_RFLAGS, flags); 2765 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME); 2766 update_exception_bitmap(vcpu); 2767 2768 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]); 2769 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]); 2770 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]); 2771 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]); 2772 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]); 2773 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]); 2774 2775 kvm_mmu_reset_context(vcpu); 2776 } 2777 2778 void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer) 2779 { 2780 struct vcpu_vmx *vmx = to_vmx(vcpu); 2781 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER); 2782 2783 if (!msr) 2784 return; 2785 2786 vcpu->arch.efer = efer; 2787 if (efer & EFER_LMA) { 2788 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2789 msr->data = efer; 2790 } else { 2791 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2792 2793 msr->data = efer & ~EFER_LME; 2794 } 2795 setup_msrs(vmx); 2796 } 2797 2798 #ifdef CONFIG_X86_64 2799 2800 static void enter_lmode(struct kvm_vcpu *vcpu) 2801 { 2802 u32 guest_tr_ar; 2803 2804 vmx_segment_cache_clear(to_vmx(vcpu)); 2805 2806 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES); 2807 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) { 2808 pr_debug_ratelimited("%s: tss fixup for long mode. \n", 2809 __func__); 2810 vmcs_write32(GUEST_TR_AR_BYTES, 2811 (guest_tr_ar & ~VMX_AR_TYPE_MASK) 2812 | VMX_AR_TYPE_BUSY_64_TSS); 2813 } 2814 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA); 2815 } 2816 2817 static void exit_lmode(struct kvm_vcpu *vcpu) 2818 { 2819 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE); 2820 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA); 2821 } 2822 2823 #endif 2824 2825 static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr) 2826 { 2827 int vpid = to_vmx(vcpu)->vpid; 2828 2829 if (!vpid_sync_vcpu_addr(vpid, addr)) 2830 vpid_sync_context(vpid); 2831 2832 /* 2833 * If VPIDs are not supported or enabled, then the above is a no-op. 2834 * But we don't really need a TLB flush in that case anyway, because 2835 * each VM entry/exit includes an implicit flush when VPID is 0. 2836 */ 2837 } 2838 2839 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu) 2840 { 2841 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits; 2842 2843 vcpu->arch.cr0 &= ~cr0_guest_owned_bits; 2844 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits; 2845 } 2846 2847 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu) 2848 { 2849 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits; 2850 2851 vcpu->arch.cr4 &= ~cr4_guest_owned_bits; 2852 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits; 2853 } 2854 2855 static void ept_load_pdptrs(struct kvm_vcpu *vcpu) 2856 { 2857 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2858 2859 if (!kvm_register_is_dirty(vcpu, VCPU_EXREG_PDPTR)) 2860 return; 2861 2862 if (is_pae_paging(vcpu)) { 2863 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]); 2864 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]); 2865 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]); 2866 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]); 2867 } 2868 } 2869 2870 void ept_save_pdptrs(struct kvm_vcpu *vcpu) 2871 { 2872 struct kvm_mmu *mmu = vcpu->arch.walk_mmu; 2873 2874 if (is_pae_paging(vcpu)) { 2875 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0); 2876 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1); 2877 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2); 2878 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3); 2879 } 2880 2881 kvm_register_mark_dirty(vcpu, VCPU_EXREG_PDPTR); 2882 } 2883 2884 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0, 2885 unsigned long cr0, 2886 struct kvm_vcpu *vcpu) 2887 { 2888 struct vcpu_vmx *vmx = to_vmx(vcpu); 2889 2890 if (!kvm_register_is_available(vcpu, VCPU_EXREG_CR3)) 2891 vmx_cache_reg(vcpu, VCPU_EXREG_CR3); 2892 if (!(cr0 & X86_CR0_PG)) { 2893 /* From paging/starting to nonpaging */ 2894 exec_controls_setbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2895 CPU_BASED_CR3_STORE_EXITING); 2896 vcpu->arch.cr0 = cr0; 2897 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2898 } else if (!is_paging(vcpu)) { 2899 /* From nonpaging to paging */ 2900 exec_controls_clearbit(vmx, CPU_BASED_CR3_LOAD_EXITING | 2901 CPU_BASED_CR3_STORE_EXITING); 2902 vcpu->arch.cr0 = cr0; 2903 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu)); 2904 } 2905 2906 if (!(cr0 & X86_CR0_WP)) 2907 *hw_cr0 &= ~X86_CR0_WP; 2908 } 2909 2910 void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0) 2911 { 2912 struct vcpu_vmx *vmx = to_vmx(vcpu); 2913 unsigned long hw_cr0; 2914 2915 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF); 2916 if (enable_unrestricted_guest) 2917 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST; 2918 else { 2919 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON; 2920 2921 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE)) 2922 enter_pmode(vcpu); 2923 2924 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE)) 2925 enter_rmode(vcpu); 2926 } 2927 2928 #ifdef CONFIG_X86_64 2929 if (vcpu->arch.efer & EFER_LME) { 2930 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) 2931 enter_lmode(vcpu); 2932 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) 2933 exit_lmode(vcpu); 2934 } 2935 #endif 2936 2937 if (enable_ept && !enable_unrestricted_guest) 2938 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu); 2939 2940 vmcs_writel(CR0_READ_SHADOW, cr0); 2941 vmcs_writel(GUEST_CR0, hw_cr0); 2942 vcpu->arch.cr0 = cr0; 2943 2944 /* depends on vcpu->arch.cr0 to be set to a new value */ 2945 vmx->emulation_required = emulation_required(vcpu); 2946 } 2947 2948 static int get_ept_level(struct kvm_vcpu *vcpu) 2949 { 2950 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48)) 2951 return 5; 2952 return 4; 2953 } 2954 2955 u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa) 2956 { 2957 u64 eptp = VMX_EPTP_MT_WB; 2958 2959 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4; 2960 2961 if (enable_ept_ad_bits && 2962 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu))) 2963 eptp |= VMX_EPTP_AD_ENABLE_BIT; 2964 eptp |= (root_hpa & PAGE_MASK); 2965 2966 return eptp; 2967 } 2968 2969 void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) 2970 { 2971 struct kvm *kvm = vcpu->kvm; 2972 bool update_guest_cr3 = true; 2973 unsigned long guest_cr3; 2974 u64 eptp; 2975 2976 guest_cr3 = cr3; 2977 if (enable_ept) { 2978 eptp = construct_eptp(vcpu, cr3); 2979 vmcs_write64(EPT_POINTER, eptp); 2980 2981 if (kvm_x86_ops->tlb_remote_flush) { 2982 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock); 2983 to_vmx(vcpu)->ept_pointer = eptp; 2984 to_kvm_vmx(kvm)->ept_pointers_match 2985 = EPT_POINTERS_CHECK; 2986 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock); 2987 } 2988 2989 /* Loading vmcs02.GUEST_CR3 is handled by nested VM-Enter. */ 2990 if (is_guest_mode(vcpu)) 2991 update_guest_cr3 = false; 2992 else if (!enable_unrestricted_guest && !is_paging(vcpu)) 2993 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr; 2994 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail)) 2995 guest_cr3 = vcpu->arch.cr3; 2996 else /* vmcs01.GUEST_CR3 is already up-to-date. */ 2997 update_guest_cr3 = false; 2998 ept_load_pdptrs(vcpu); 2999 } 3000 3001 if (update_guest_cr3) 3002 vmcs_writel(GUEST_CR3, guest_cr3); 3003 } 3004 3005 int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) 3006 { 3007 struct vcpu_vmx *vmx = to_vmx(vcpu); 3008 /* 3009 * Pass through host's Machine Check Enable value to hw_cr4, which 3010 * is in force while we are in guest mode. Do not let guests control 3011 * this bit, even if host CR4.MCE == 0. 3012 */ 3013 unsigned long hw_cr4; 3014 3015 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE); 3016 if (enable_unrestricted_guest) 3017 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST; 3018 else if (vmx->rmode.vm86_active) 3019 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON; 3020 else 3021 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON; 3022 3023 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) { 3024 if (cr4 & X86_CR4_UMIP) { 3025 secondary_exec_controls_setbit(vmx, SECONDARY_EXEC_DESC); 3026 hw_cr4 &= ~X86_CR4_UMIP; 3027 } else if (!is_guest_mode(vcpu) || 3028 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC)) { 3029 secondary_exec_controls_clearbit(vmx, SECONDARY_EXEC_DESC); 3030 } 3031 } 3032 3033 if (cr4 & X86_CR4_VMXE) { 3034 /* 3035 * To use VMXON (and later other VMX instructions), a guest 3036 * must first be able to turn on cr4.VMXE (see handle_vmon()). 3037 * So basically the check on whether to allow nested VMX 3038 * is here. We operate under the default treatment of SMM, 3039 * so VMX cannot be enabled under SMM. 3040 */ 3041 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu)) 3042 return 1; 3043 } 3044 3045 if (vmx->nested.vmxon && !nested_cr4_valid(vcpu, cr4)) 3046 return 1; 3047 3048 vcpu->arch.cr4 = cr4; 3049 3050 if (!enable_unrestricted_guest) { 3051 if (enable_ept) { 3052 if (!is_paging(vcpu)) { 3053 hw_cr4 &= ~X86_CR4_PAE; 3054 hw_cr4 |= X86_CR4_PSE; 3055 } else if (!(cr4 & X86_CR4_PAE)) { 3056 hw_cr4 &= ~X86_CR4_PAE; 3057 } 3058 } 3059 3060 /* 3061 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in 3062 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs 3063 * to be manually disabled when guest switches to non-paging 3064 * mode. 3065 * 3066 * If !enable_unrestricted_guest, the CPU is always running 3067 * with CR0.PG=1 and CR4 needs to be modified. 3068 * If enable_unrestricted_guest, the CPU automatically 3069 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0. 3070 */ 3071 if (!is_paging(vcpu)) 3072 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE); 3073 } 3074 3075 vmcs_writel(CR4_READ_SHADOW, cr4); 3076 vmcs_writel(GUEST_CR4, hw_cr4); 3077 return 0; 3078 } 3079 3080 void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3081 { 3082 struct vcpu_vmx *vmx = to_vmx(vcpu); 3083 u32 ar; 3084 3085 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3086 *var = vmx->rmode.segs[seg]; 3087 if (seg == VCPU_SREG_TR 3088 || var->selector == vmx_read_guest_seg_selector(vmx, seg)) 3089 return; 3090 var->base = vmx_read_guest_seg_base(vmx, seg); 3091 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3092 return; 3093 } 3094 var->base = vmx_read_guest_seg_base(vmx, seg); 3095 var->limit = vmx_read_guest_seg_limit(vmx, seg); 3096 var->selector = vmx_read_guest_seg_selector(vmx, seg); 3097 ar = vmx_read_guest_seg_ar(vmx, seg); 3098 var->unusable = (ar >> 16) & 1; 3099 var->type = ar & 15; 3100 var->s = (ar >> 4) & 1; 3101 var->dpl = (ar >> 5) & 3; 3102 /* 3103 * Some userspaces do not preserve unusable property. Since usable 3104 * segment has to be present according to VMX spec we can use present 3105 * property to amend userspace bug by making unusable segment always 3106 * nonpresent. vmx_segment_access_rights() already marks nonpresent 3107 * segment as unusable. 3108 */ 3109 var->present = !var->unusable; 3110 var->avl = (ar >> 12) & 1; 3111 var->l = (ar >> 13) & 1; 3112 var->db = (ar >> 14) & 1; 3113 var->g = (ar >> 15) & 1; 3114 } 3115 3116 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg) 3117 { 3118 struct kvm_segment s; 3119 3120 if (to_vmx(vcpu)->rmode.vm86_active) { 3121 vmx_get_segment(vcpu, &s, seg); 3122 return s.base; 3123 } 3124 return vmx_read_guest_seg_base(to_vmx(vcpu), seg); 3125 } 3126 3127 int vmx_get_cpl(struct kvm_vcpu *vcpu) 3128 { 3129 struct vcpu_vmx *vmx = to_vmx(vcpu); 3130 3131 if (unlikely(vmx->rmode.vm86_active)) 3132 return 0; 3133 else { 3134 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS); 3135 return VMX_AR_DPL(ar); 3136 } 3137 } 3138 3139 static u32 vmx_segment_access_rights(struct kvm_segment *var) 3140 { 3141 u32 ar; 3142 3143 if (var->unusable || !var->present) 3144 ar = 1 << 16; 3145 else { 3146 ar = var->type & 15; 3147 ar |= (var->s & 1) << 4; 3148 ar |= (var->dpl & 3) << 5; 3149 ar |= (var->present & 1) << 7; 3150 ar |= (var->avl & 1) << 12; 3151 ar |= (var->l & 1) << 13; 3152 ar |= (var->db & 1) << 14; 3153 ar |= (var->g & 1) << 15; 3154 } 3155 3156 return ar; 3157 } 3158 3159 void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg) 3160 { 3161 struct vcpu_vmx *vmx = to_vmx(vcpu); 3162 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3163 3164 vmx_segment_cache_clear(vmx); 3165 3166 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) { 3167 vmx->rmode.segs[seg] = *var; 3168 if (seg == VCPU_SREG_TR) 3169 vmcs_write16(sf->selector, var->selector); 3170 else if (var->s) 3171 fix_rmode_seg(seg, &vmx->rmode.segs[seg]); 3172 goto out; 3173 } 3174 3175 vmcs_writel(sf->base, var->base); 3176 vmcs_write32(sf->limit, var->limit); 3177 vmcs_write16(sf->selector, var->selector); 3178 3179 /* 3180 * Fix the "Accessed" bit in AR field of segment registers for older 3181 * qemu binaries. 3182 * IA32 arch specifies that at the time of processor reset the 3183 * "Accessed" bit in the AR field of segment registers is 1. And qemu 3184 * is setting it to 0 in the userland code. This causes invalid guest 3185 * state vmexit when "unrestricted guest" mode is turned on. 3186 * Fix for this setup issue in cpu_reset is being pushed in the qemu 3187 * tree. Newer qemu binaries with that qemu fix would not need this 3188 * kvm hack. 3189 */ 3190 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR)) 3191 var->type |= 0x1; /* Accessed */ 3192 3193 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var)); 3194 3195 out: 3196 vmx->emulation_required = emulation_required(vcpu); 3197 } 3198 3199 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l) 3200 { 3201 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS); 3202 3203 *db = (ar >> 14) & 1; 3204 *l = (ar >> 13) & 1; 3205 } 3206 3207 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3208 { 3209 dt->size = vmcs_read32(GUEST_IDTR_LIMIT); 3210 dt->address = vmcs_readl(GUEST_IDTR_BASE); 3211 } 3212 3213 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3214 { 3215 vmcs_write32(GUEST_IDTR_LIMIT, dt->size); 3216 vmcs_writel(GUEST_IDTR_BASE, dt->address); 3217 } 3218 3219 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3220 { 3221 dt->size = vmcs_read32(GUEST_GDTR_LIMIT); 3222 dt->address = vmcs_readl(GUEST_GDTR_BASE); 3223 } 3224 3225 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt) 3226 { 3227 vmcs_write32(GUEST_GDTR_LIMIT, dt->size); 3228 vmcs_writel(GUEST_GDTR_BASE, dt->address); 3229 } 3230 3231 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg) 3232 { 3233 struct kvm_segment var; 3234 u32 ar; 3235 3236 vmx_get_segment(vcpu, &var, seg); 3237 var.dpl = 0x3; 3238 if (seg == VCPU_SREG_CS) 3239 var.type = 0x3; 3240 ar = vmx_segment_access_rights(&var); 3241 3242 if (var.base != (var.selector << 4)) 3243 return false; 3244 if (var.limit != 0xffff) 3245 return false; 3246 if (ar != 0xf3) 3247 return false; 3248 3249 return true; 3250 } 3251 3252 static bool code_segment_valid(struct kvm_vcpu *vcpu) 3253 { 3254 struct kvm_segment cs; 3255 unsigned int cs_rpl; 3256 3257 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3258 cs_rpl = cs.selector & SEGMENT_RPL_MASK; 3259 3260 if (cs.unusable) 3261 return false; 3262 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK)) 3263 return false; 3264 if (!cs.s) 3265 return false; 3266 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) { 3267 if (cs.dpl > cs_rpl) 3268 return false; 3269 } else { 3270 if (cs.dpl != cs_rpl) 3271 return false; 3272 } 3273 if (!cs.present) 3274 return false; 3275 3276 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */ 3277 return true; 3278 } 3279 3280 static bool stack_segment_valid(struct kvm_vcpu *vcpu) 3281 { 3282 struct kvm_segment ss; 3283 unsigned int ss_rpl; 3284 3285 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3286 ss_rpl = ss.selector & SEGMENT_RPL_MASK; 3287 3288 if (ss.unusable) 3289 return true; 3290 if (ss.type != 3 && ss.type != 7) 3291 return false; 3292 if (!ss.s) 3293 return false; 3294 if (ss.dpl != ss_rpl) /* DPL != RPL */ 3295 return false; 3296 if (!ss.present) 3297 return false; 3298 3299 return true; 3300 } 3301 3302 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg) 3303 { 3304 struct kvm_segment var; 3305 unsigned int rpl; 3306 3307 vmx_get_segment(vcpu, &var, seg); 3308 rpl = var.selector & SEGMENT_RPL_MASK; 3309 3310 if (var.unusable) 3311 return true; 3312 if (!var.s) 3313 return false; 3314 if (!var.present) 3315 return false; 3316 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) { 3317 if (var.dpl < rpl) /* DPL < RPL */ 3318 return false; 3319 } 3320 3321 /* TODO: Add other members to kvm_segment_field to allow checking for other access 3322 * rights flags 3323 */ 3324 return true; 3325 } 3326 3327 static bool tr_valid(struct kvm_vcpu *vcpu) 3328 { 3329 struct kvm_segment tr; 3330 3331 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR); 3332 3333 if (tr.unusable) 3334 return false; 3335 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3336 return false; 3337 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */ 3338 return false; 3339 if (!tr.present) 3340 return false; 3341 3342 return true; 3343 } 3344 3345 static bool ldtr_valid(struct kvm_vcpu *vcpu) 3346 { 3347 struct kvm_segment ldtr; 3348 3349 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR); 3350 3351 if (ldtr.unusable) 3352 return true; 3353 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */ 3354 return false; 3355 if (ldtr.type != 2) 3356 return false; 3357 if (!ldtr.present) 3358 return false; 3359 3360 return true; 3361 } 3362 3363 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu) 3364 { 3365 struct kvm_segment cs, ss; 3366 3367 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS); 3368 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS); 3369 3370 return ((cs.selector & SEGMENT_RPL_MASK) == 3371 (ss.selector & SEGMENT_RPL_MASK)); 3372 } 3373 3374 /* 3375 * Check if guest state is valid. Returns true if valid, false if 3376 * not. 3377 * We assume that registers are always usable 3378 */ 3379 static bool guest_state_valid(struct kvm_vcpu *vcpu) 3380 { 3381 if (enable_unrestricted_guest) 3382 return true; 3383 3384 /* real mode guest state checks */ 3385 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) { 3386 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS)) 3387 return false; 3388 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS)) 3389 return false; 3390 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS)) 3391 return false; 3392 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES)) 3393 return false; 3394 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS)) 3395 return false; 3396 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS)) 3397 return false; 3398 } else { 3399 /* protected mode guest state checks */ 3400 if (!cs_ss_rpl_check(vcpu)) 3401 return false; 3402 if (!code_segment_valid(vcpu)) 3403 return false; 3404 if (!stack_segment_valid(vcpu)) 3405 return false; 3406 if (!data_segment_valid(vcpu, VCPU_SREG_DS)) 3407 return false; 3408 if (!data_segment_valid(vcpu, VCPU_SREG_ES)) 3409 return false; 3410 if (!data_segment_valid(vcpu, VCPU_SREG_FS)) 3411 return false; 3412 if (!data_segment_valid(vcpu, VCPU_SREG_GS)) 3413 return false; 3414 if (!tr_valid(vcpu)) 3415 return false; 3416 if (!ldtr_valid(vcpu)) 3417 return false; 3418 } 3419 /* TODO: 3420 * - Add checks on RIP 3421 * - Add checks on RFLAGS 3422 */ 3423 3424 return true; 3425 } 3426 3427 static int init_rmode_tss(struct kvm *kvm) 3428 { 3429 gfn_t fn; 3430 u16 data = 0; 3431 int idx, r; 3432 3433 idx = srcu_read_lock(&kvm->srcu); 3434 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT; 3435 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3436 if (r < 0) 3437 goto out; 3438 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE; 3439 r = kvm_write_guest_page(kvm, fn++, &data, 3440 TSS_IOPB_BASE_OFFSET, sizeof(u16)); 3441 if (r < 0) 3442 goto out; 3443 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE); 3444 if (r < 0) 3445 goto out; 3446 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE); 3447 if (r < 0) 3448 goto out; 3449 data = ~0; 3450 r = kvm_write_guest_page(kvm, fn, &data, 3451 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1, 3452 sizeof(u8)); 3453 out: 3454 srcu_read_unlock(&kvm->srcu, idx); 3455 return r; 3456 } 3457 3458 static int init_rmode_identity_map(struct kvm *kvm) 3459 { 3460 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm); 3461 int i, r = 0; 3462 kvm_pfn_t identity_map_pfn; 3463 u32 tmp; 3464 3465 /* Protect kvm_vmx->ept_identity_pagetable_done. */ 3466 mutex_lock(&kvm->slots_lock); 3467 3468 if (likely(kvm_vmx->ept_identity_pagetable_done)) 3469 goto out; 3470 3471 if (!kvm_vmx->ept_identity_map_addr) 3472 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR; 3473 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT; 3474 3475 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT, 3476 kvm_vmx->ept_identity_map_addr, PAGE_SIZE); 3477 if (r < 0) 3478 goto out; 3479 3480 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE); 3481 if (r < 0) 3482 goto out; 3483 /* Set up identity-mapping pagetable for EPT in real mode */ 3484 for (i = 0; i < PT32_ENT_PER_PAGE; i++) { 3485 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | 3486 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE); 3487 r = kvm_write_guest_page(kvm, identity_map_pfn, 3488 &tmp, i * sizeof(tmp), sizeof(tmp)); 3489 if (r < 0) 3490 goto out; 3491 } 3492 kvm_vmx->ept_identity_pagetable_done = true; 3493 3494 out: 3495 mutex_unlock(&kvm->slots_lock); 3496 return r; 3497 } 3498 3499 static void seg_setup(int seg) 3500 { 3501 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg]; 3502 unsigned int ar; 3503 3504 vmcs_write16(sf->selector, 0); 3505 vmcs_writel(sf->base, 0); 3506 vmcs_write32(sf->limit, 0xffff); 3507 ar = 0x93; 3508 if (seg == VCPU_SREG_CS) 3509 ar |= 0x08; /* code segment */ 3510 3511 vmcs_write32(sf->ar_bytes, ar); 3512 } 3513 3514 static int alloc_apic_access_page(struct kvm *kvm) 3515 { 3516 struct page *page; 3517 int r = 0; 3518 3519 mutex_lock(&kvm->slots_lock); 3520 if (kvm->arch.apic_access_page_done) 3521 goto out; 3522 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 3523 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE); 3524 if (r) 3525 goto out; 3526 3527 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT); 3528 if (is_error_page(page)) { 3529 r = -EFAULT; 3530 goto out; 3531 } 3532 3533 /* 3534 * Do not pin the page in memory, so that memory hot-unplug 3535 * is able to migrate it. 3536 */ 3537 put_page(page); 3538 kvm->arch.apic_access_page_done = true; 3539 out: 3540 mutex_unlock(&kvm->slots_lock); 3541 return r; 3542 } 3543 3544 int allocate_vpid(void) 3545 { 3546 int vpid; 3547 3548 if (!enable_vpid) 3549 return 0; 3550 spin_lock(&vmx_vpid_lock); 3551 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS); 3552 if (vpid < VMX_NR_VPIDS) 3553 __set_bit(vpid, vmx_vpid_bitmap); 3554 else 3555 vpid = 0; 3556 spin_unlock(&vmx_vpid_lock); 3557 return vpid; 3558 } 3559 3560 void free_vpid(int vpid) 3561 { 3562 if (!enable_vpid || vpid == 0) 3563 return; 3564 spin_lock(&vmx_vpid_lock); 3565 __clear_bit(vpid, vmx_vpid_bitmap); 3566 spin_unlock(&vmx_vpid_lock); 3567 } 3568 3569 static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, 3570 u32 msr, int type) 3571 { 3572 int f = sizeof(unsigned long); 3573 3574 if (!cpu_has_vmx_msr_bitmap()) 3575 return; 3576 3577 if (static_branch_unlikely(&enable_evmcs)) 3578 evmcs_touch_msr_bitmap(); 3579 3580 /* 3581 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3582 * have the write-low and read-high bitmap offsets the wrong way round. 3583 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3584 */ 3585 if (msr <= 0x1fff) { 3586 if (type & MSR_TYPE_R) 3587 /* read-low */ 3588 __clear_bit(msr, msr_bitmap + 0x000 / f); 3589 3590 if (type & MSR_TYPE_W) 3591 /* write-low */ 3592 __clear_bit(msr, msr_bitmap + 0x800 / f); 3593 3594 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3595 msr &= 0x1fff; 3596 if (type & MSR_TYPE_R) 3597 /* read-high */ 3598 __clear_bit(msr, msr_bitmap + 0x400 / f); 3599 3600 if (type & MSR_TYPE_W) 3601 /* write-high */ 3602 __clear_bit(msr, msr_bitmap + 0xc00 / f); 3603 3604 } 3605 } 3606 3607 static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap, 3608 u32 msr, int type) 3609 { 3610 int f = sizeof(unsigned long); 3611 3612 if (!cpu_has_vmx_msr_bitmap()) 3613 return; 3614 3615 if (static_branch_unlikely(&enable_evmcs)) 3616 evmcs_touch_msr_bitmap(); 3617 3618 /* 3619 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals 3620 * have the write-low and read-high bitmap offsets the wrong way round. 3621 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff. 3622 */ 3623 if (msr <= 0x1fff) { 3624 if (type & MSR_TYPE_R) 3625 /* read-low */ 3626 __set_bit(msr, msr_bitmap + 0x000 / f); 3627 3628 if (type & MSR_TYPE_W) 3629 /* write-low */ 3630 __set_bit(msr, msr_bitmap + 0x800 / f); 3631 3632 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) { 3633 msr &= 0x1fff; 3634 if (type & MSR_TYPE_R) 3635 /* read-high */ 3636 __set_bit(msr, msr_bitmap + 0x400 / f); 3637 3638 if (type & MSR_TYPE_W) 3639 /* write-high */ 3640 __set_bit(msr, msr_bitmap + 0xc00 / f); 3641 3642 } 3643 } 3644 3645 static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap, 3646 u32 msr, int type, bool value) 3647 { 3648 if (value) 3649 vmx_enable_intercept_for_msr(msr_bitmap, msr, type); 3650 else 3651 vmx_disable_intercept_for_msr(msr_bitmap, msr, type); 3652 } 3653 3654 static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu) 3655 { 3656 u8 mode = 0; 3657 3658 if (cpu_has_secondary_exec_ctrls() && 3659 (secondary_exec_controls_get(to_vmx(vcpu)) & 3660 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) { 3661 mode |= MSR_BITMAP_MODE_X2APIC; 3662 if (enable_apicv && kvm_vcpu_apicv_active(vcpu)) 3663 mode |= MSR_BITMAP_MODE_X2APIC_APICV; 3664 } 3665 3666 return mode; 3667 } 3668 3669 static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap, 3670 u8 mode) 3671 { 3672 int msr; 3673 3674 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) { 3675 unsigned word = msr / BITS_PER_LONG; 3676 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0; 3677 msr_bitmap[word + (0x800 / sizeof(long))] = ~0; 3678 } 3679 3680 if (mode & MSR_BITMAP_MODE_X2APIC) { 3681 /* 3682 * TPR reads and writes can be virtualized even if virtual interrupt 3683 * delivery is not in use. 3684 */ 3685 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW); 3686 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) { 3687 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R); 3688 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W); 3689 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W); 3690 } 3691 } 3692 } 3693 3694 void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu) 3695 { 3696 struct vcpu_vmx *vmx = to_vmx(vcpu); 3697 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3698 u8 mode = vmx_msr_bitmap_mode(vcpu); 3699 u8 changed = mode ^ vmx->msr_bitmap_mode; 3700 3701 if (!changed) 3702 return; 3703 3704 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV)) 3705 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode); 3706 3707 vmx->msr_bitmap_mode = mode; 3708 } 3709 3710 void pt_update_intercept_for_msr(struct vcpu_vmx *vmx) 3711 { 3712 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap; 3713 bool flag = !(vmx->pt_desc.guest.ctl & RTIT_CTL_TRACEEN); 3714 u32 i; 3715 3716 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_STATUS, 3717 MSR_TYPE_RW, flag); 3718 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_BASE, 3719 MSR_TYPE_RW, flag); 3720 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_OUTPUT_MASK, 3721 MSR_TYPE_RW, flag); 3722 vmx_set_intercept_for_msr(msr_bitmap, MSR_IA32_RTIT_CR3_MATCH, 3723 MSR_TYPE_RW, flag); 3724 for (i = 0; i < vmx->pt_desc.addr_range; i++) { 3725 vmx_set_intercept_for_msr(msr_bitmap, 3726 MSR_IA32_RTIT_ADDR0_A + i * 2, MSR_TYPE_RW, flag); 3727 vmx_set_intercept_for_msr(msr_bitmap, 3728 MSR_IA32_RTIT_ADDR0_B + i * 2, MSR_TYPE_RW, flag); 3729 } 3730 } 3731 3732 static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu) 3733 { 3734 struct vcpu_vmx *vmx = to_vmx(vcpu); 3735 void *vapic_page; 3736 u32 vppr; 3737 int rvi; 3738 3739 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) || 3740 !nested_cpu_has_vid(get_vmcs12(vcpu)) || 3741 WARN_ON_ONCE(!vmx->nested.virtual_apic_map.gfn)) 3742 return false; 3743 3744 rvi = vmx_get_rvi(); 3745 3746 vapic_page = vmx->nested.virtual_apic_map.hva; 3747 vppr = *((u32 *)(vapic_page + APIC_PROCPRI)); 3748 3749 return ((rvi & 0xf0) > (vppr & 0xf0)); 3750 } 3751 3752 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu, 3753 bool nested) 3754 { 3755 #ifdef CONFIG_SMP 3756 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR; 3757 3758 if (vcpu->mode == IN_GUEST_MODE) { 3759 /* 3760 * The vector of interrupt to be delivered to vcpu had 3761 * been set in PIR before this function. 3762 * 3763 * Following cases will be reached in this block, and 3764 * we always send a notification event in all cases as 3765 * explained below. 3766 * 3767 * Case 1: vcpu keeps in non-root mode. Sending a 3768 * notification event posts the interrupt to vcpu. 3769 * 3770 * Case 2: vcpu exits to root mode and is still 3771 * runnable. PIR will be synced to vIRR before the 3772 * next vcpu entry. Sending a notification event in 3773 * this case has no effect, as vcpu is not in root 3774 * mode. 3775 * 3776 * Case 3: vcpu exits to root mode and is blocked. 3777 * vcpu_block() has already synced PIR to vIRR and 3778 * never blocks vcpu if vIRR is not cleared. Therefore, 3779 * a blocked vcpu here does not wait for any requested 3780 * interrupts in PIR, and sending a notification event 3781 * which has no effect is safe here. 3782 */ 3783 3784 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec); 3785 return true; 3786 } 3787 #endif 3788 return false; 3789 } 3790 3791 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu, 3792 int vector) 3793 { 3794 struct vcpu_vmx *vmx = to_vmx(vcpu); 3795 3796 if (is_guest_mode(vcpu) && 3797 vector == vmx->nested.posted_intr_nv) { 3798 /* 3799 * If a posted intr is not recognized by hardware, 3800 * we will accomplish it in the next vmentry. 3801 */ 3802 vmx->nested.pi_pending = true; 3803 kvm_make_request(KVM_REQ_EVENT, vcpu); 3804 /* the PIR and ON have been set by L1. */ 3805 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true)) 3806 kvm_vcpu_kick(vcpu); 3807 return 0; 3808 } 3809 return -1; 3810 } 3811 /* 3812 * Send interrupt to vcpu via posted interrupt way. 3813 * 1. If target vcpu is running(non-root mode), send posted interrupt 3814 * notification to vcpu and hardware will sync PIR to vIRR atomically. 3815 * 2. If target vcpu isn't running(root mode), kick it to pick up the 3816 * interrupt from PIR in next vmentry. 3817 */ 3818 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector) 3819 { 3820 struct vcpu_vmx *vmx = to_vmx(vcpu); 3821 int r; 3822 3823 r = vmx_deliver_nested_posted_interrupt(vcpu, vector); 3824 if (!r) 3825 return; 3826 3827 if (pi_test_and_set_pir(vector, &vmx->pi_desc)) 3828 return; 3829 3830 /* If a previous notification has sent the IPI, nothing to do. */ 3831 if (pi_test_and_set_on(&vmx->pi_desc)) 3832 return; 3833 3834 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false)) 3835 kvm_vcpu_kick(vcpu); 3836 } 3837 3838 /* 3839 * Set up the vmcs's constant host-state fields, i.e., host-state fields that 3840 * will not change in the lifetime of the guest. 3841 * Note that host-state that does change is set elsewhere. E.g., host-state 3842 * that is set differently for each CPU is set in vmx_vcpu_load(), not here. 3843 */ 3844 void vmx_set_constant_host_state(struct vcpu_vmx *vmx) 3845 { 3846 u32 low32, high32; 3847 unsigned long tmpl; 3848 unsigned long cr0, cr3, cr4; 3849 3850 cr0 = read_cr0(); 3851 WARN_ON(cr0 & X86_CR0_TS); 3852 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */ 3853 3854 /* 3855 * Save the most likely value for this task's CR3 in the VMCS. 3856 * We can't use __get_current_cr3_fast() because we're not atomic. 3857 */ 3858 cr3 = __read_cr3(); 3859 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */ 3860 vmx->loaded_vmcs->host_state.cr3 = cr3; 3861 3862 /* Save the most likely value for this task's CR4 in the VMCS. */ 3863 cr4 = cr4_read_shadow(); 3864 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */ 3865 vmx->loaded_vmcs->host_state.cr4 = cr4; 3866 3867 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */ 3868 #ifdef CONFIG_X86_64 3869 /* 3870 * Load null selectors, so we can avoid reloading them in 3871 * vmx_prepare_switch_to_host(), in case userspace uses 3872 * the null selectors too (the expected case). 3873 */ 3874 vmcs_write16(HOST_DS_SELECTOR, 0); 3875 vmcs_write16(HOST_ES_SELECTOR, 0); 3876 #else 3877 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3878 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3879 #endif 3880 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */ 3881 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */ 3882 3883 vmcs_writel(HOST_IDTR_BASE, host_idt_base); /* 22.2.4 */ 3884 3885 vmcs_writel(HOST_RIP, (unsigned long)vmx_vmexit); /* 22.2.5 */ 3886 3887 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32); 3888 vmcs_write32(HOST_IA32_SYSENTER_CS, low32); 3889 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl); 3890 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */ 3891 3892 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) { 3893 rdmsr(MSR_IA32_CR_PAT, low32, high32); 3894 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32)); 3895 } 3896 3897 if (cpu_has_load_ia32_efer()) 3898 vmcs_write64(HOST_IA32_EFER, host_efer); 3899 } 3900 3901 void set_cr4_guest_host_mask(struct vcpu_vmx *vmx) 3902 { 3903 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS; 3904 if (enable_ept) 3905 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE; 3906 if (is_guest_mode(&vmx->vcpu)) 3907 vmx->vcpu.arch.cr4_guest_owned_bits &= 3908 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask; 3909 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits); 3910 } 3911 3912 u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx) 3913 { 3914 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl; 3915 3916 if (!kvm_vcpu_apicv_active(&vmx->vcpu)) 3917 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR; 3918 3919 if (!enable_vnmi) 3920 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS; 3921 3922 if (!enable_preemption_timer) 3923 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER; 3924 3925 return pin_based_exec_ctrl; 3926 } 3927 3928 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) 3929 { 3930 struct vcpu_vmx *vmx = to_vmx(vcpu); 3931 3932 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 3933 if (cpu_has_secondary_exec_ctrls()) { 3934 if (kvm_vcpu_apicv_active(vcpu)) 3935 secondary_exec_controls_setbit(vmx, 3936 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3937 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3938 else 3939 secondary_exec_controls_clearbit(vmx, 3940 SECONDARY_EXEC_APIC_REGISTER_VIRT | 3941 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3942 } 3943 3944 if (cpu_has_vmx_msr_bitmap()) 3945 vmx_update_msr_bitmap(vcpu); 3946 } 3947 3948 u32 vmx_exec_control(struct vcpu_vmx *vmx) 3949 { 3950 u32 exec_control = vmcs_config.cpu_based_exec_ctrl; 3951 3952 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT) 3953 exec_control &= ~CPU_BASED_MOV_DR_EXITING; 3954 3955 if (!cpu_need_tpr_shadow(&vmx->vcpu)) { 3956 exec_control &= ~CPU_BASED_TPR_SHADOW; 3957 #ifdef CONFIG_X86_64 3958 exec_control |= CPU_BASED_CR8_STORE_EXITING | 3959 CPU_BASED_CR8_LOAD_EXITING; 3960 #endif 3961 } 3962 if (!enable_ept) 3963 exec_control |= CPU_BASED_CR3_STORE_EXITING | 3964 CPU_BASED_CR3_LOAD_EXITING | 3965 CPU_BASED_INVLPG_EXITING; 3966 if (kvm_mwait_in_guest(vmx->vcpu.kvm)) 3967 exec_control &= ~(CPU_BASED_MWAIT_EXITING | 3968 CPU_BASED_MONITOR_EXITING); 3969 if (kvm_hlt_in_guest(vmx->vcpu.kvm)) 3970 exec_control &= ~CPU_BASED_HLT_EXITING; 3971 return exec_control; 3972 } 3973 3974 3975 static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx) 3976 { 3977 struct kvm_vcpu *vcpu = &vmx->vcpu; 3978 3979 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl; 3980 3981 if (pt_mode == PT_MODE_SYSTEM) 3982 exec_control &= ~(SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX); 3983 if (!cpu_need_virtualize_apic_accesses(vcpu)) 3984 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 3985 if (vmx->vpid == 0) 3986 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID; 3987 if (!enable_ept) { 3988 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT; 3989 enable_unrestricted_guest = 0; 3990 } 3991 if (!enable_unrestricted_guest) 3992 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST; 3993 if (kvm_pause_in_guest(vmx->vcpu.kvm)) 3994 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING; 3995 if (!kvm_vcpu_apicv_active(vcpu)) 3996 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT | 3997 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY); 3998 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 3999 4000 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP, 4001 * in vmx_set_cr4. */ 4002 exec_control &= ~SECONDARY_EXEC_DESC; 4003 4004 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD 4005 (handle_vmptrld). 4006 We can NOT enable shadow_vmcs here because we don't have yet 4007 a current VMCS12 4008 */ 4009 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS; 4010 4011 if (!enable_pml) 4012 exec_control &= ~SECONDARY_EXEC_ENABLE_PML; 4013 4014 if (vmx_xsaves_supported()) { 4015 /* Exposing XSAVES only when XSAVE is exposed */ 4016 bool xsaves_enabled = 4017 boot_cpu_has(X86_FEATURE_XSAVE) && 4018 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) && 4019 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES); 4020 4021 vcpu->arch.xsaves_enabled = xsaves_enabled; 4022 4023 if (!xsaves_enabled) 4024 exec_control &= ~SECONDARY_EXEC_XSAVES; 4025 4026 if (nested) { 4027 if (xsaves_enabled) 4028 vmx->nested.msrs.secondary_ctls_high |= 4029 SECONDARY_EXEC_XSAVES; 4030 else 4031 vmx->nested.msrs.secondary_ctls_high &= 4032 ~SECONDARY_EXEC_XSAVES; 4033 } 4034 } 4035 4036 if (vmx_rdtscp_supported()) { 4037 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP); 4038 if (!rdtscp_enabled) 4039 exec_control &= ~SECONDARY_EXEC_RDTSCP; 4040 4041 if (nested) { 4042 if (rdtscp_enabled) 4043 vmx->nested.msrs.secondary_ctls_high |= 4044 SECONDARY_EXEC_RDTSCP; 4045 else 4046 vmx->nested.msrs.secondary_ctls_high &= 4047 ~SECONDARY_EXEC_RDTSCP; 4048 } 4049 } 4050 4051 if (vmx_invpcid_supported()) { 4052 /* Exposing INVPCID only when PCID is exposed */ 4053 bool invpcid_enabled = 4054 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) && 4055 guest_cpuid_has(vcpu, X86_FEATURE_PCID); 4056 4057 if (!invpcid_enabled) { 4058 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID; 4059 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID); 4060 } 4061 4062 if (nested) { 4063 if (invpcid_enabled) 4064 vmx->nested.msrs.secondary_ctls_high |= 4065 SECONDARY_EXEC_ENABLE_INVPCID; 4066 else 4067 vmx->nested.msrs.secondary_ctls_high &= 4068 ~SECONDARY_EXEC_ENABLE_INVPCID; 4069 } 4070 } 4071 4072 if (vmx_rdrand_supported()) { 4073 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND); 4074 if (rdrand_enabled) 4075 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING; 4076 4077 if (nested) { 4078 if (rdrand_enabled) 4079 vmx->nested.msrs.secondary_ctls_high |= 4080 SECONDARY_EXEC_RDRAND_EXITING; 4081 else 4082 vmx->nested.msrs.secondary_ctls_high &= 4083 ~SECONDARY_EXEC_RDRAND_EXITING; 4084 } 4085 } 4086 4087 if (vmx_rdseed_supported()) { 4088 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED); 4089 if (rdseed_enabled) 4090 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING; 4091 4092 if (nested) { 4093 if (rdseed_enabled) 4094 vmx->nested.msrs.secondary_ctls_high |= 4095 SECONDARY_EXEC_RDSEED_EXITING; 4096 else 4097 vmx->nested.msrs.secondary_ctls_high &= 4098 ~SECONDARY_EXEC_RDSEED_EXITING; 4099 } 4100 } 4101 4102 if (vmx_waitpkg_supported()) { 4103 bool waitpkg_enabled = 4104 guest_cpuid_has(vcpu, X86_FEATURE_WAITPKG); 4105 4106 if (!waitpkg_enabled) 4107 exec_control &= ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4108 4109 if (nested) { 4110 if (waitpkg_enabled) 4111 vmx->nested.msrs.secondary_ctls_high |= 4112 SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4113 else 4114 vmx->nested.msrs.secondary_ctls_high &= 4115 ~SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE; 4116 } 4117 } 4118 4119 vmx->secondary_exec_control = exec_control; 4120 } 4121 4122 static void ept_set_mmio_spte_mask(void) 4123 { 4124 /* 4125 * EPT Misconfigurations can be generated if the value of bits 2:0 4126 * of an EPT paging-structure entry is 110b (write/execute). 4127 */ 4128 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK, 4129 VMX_EPT_MISCONFIG_WX_VALUE, 0); 4130 } 4131 4132 #define VMX_XSS_EXIT_BITMAP 0 4133 4134 /* 4135 * Noting that the initialization of Guest-state Area of VMCS is in 4136 * vmx_vcpu_reset(). 4137 */ 4138 static void init_vmcs(struct vcpu_vmx *vmx) 4139 { 4140 if (nested) 4141 nested_vmx_set_vmcs_shadowing_bitmap(); 4142 4143 if (cpu_has_vmx_msr_bitmap()) 4144 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap)); 4145 4146 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */ 4147 4148 /* Control */ 4149 pin_controls_set(vmx, vmx_pin_based_exec_ctrl(vmx)); 4150 4151 exec_controls_set(vmx, vmx_exec_control(vmx)); 4152 4153 if (cpu_has_secondary_exec_ctrls()) { 4154 vmx_compute_secondary_exec_control(vmx); 4155 secondary_exec_controls_set(vmx, vmx->secondary_exec_control); 4156 } 4157 4158 if (kvm_vcpu_apicv_active(&vmx->vcpu)) { 4159 vmcs_write64(EOI_EXIT_BITMAP0, 0); 4160 vmcs_write64(EOI_EXIT_BITMAP1, 0); 4161 vmcs_write64(EOI_EXIT_BITMAP2, 0); 4162 vmcs_write64(EOI_EXIT_BITMAP3, 0); 4163 4164 vmcs_write16(GUEST_INTR_STATUS, 0); 4165 4166 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR); 4167 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc))); 4168 } 4169 4170 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) { 4171 vmcs_write32(PLE_GAP, ple_gap); 4172 vmx->ple_window = ple_window; 4173 vmx->ple_window_dirty = true; 4174 } 4175 4176 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0); 4177 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0); 4178 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */ 4179 4180 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */ 4181 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */ 4182 vmx_set_constant_host_state(vmx); 4183 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */ 4184 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */ 4185 4186 if (cpu_has_vmx_vmfunc()) 4187 vmcs_write64(VM_FUNCTION_CONTROL, 0); 4188 4189 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0); 4190 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0); 4191 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val)); 4192 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0); 4193 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val)); 4194 4195 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) 4196 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat); 4197 4198 vm_exit_controls_set(vmx, vmx_vmexit_ctrl()); 4199 4200 /* 22.2.1, 20.8.1 */ 4201 vm_entry_controls_set(vmx, vmx_vmentry_ctrl()); 4202 4203 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS; 4204 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS); 4205 4206 set_cr4_guest_host_mask(vmx); 4207 4208 if (vmx->vpid != 0) 4209 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid); 4210 4211 if (vmx_xsaves_supported()) 4212 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP); 4213 4214 if (enable_pml) { 4215 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg)); 4216 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 4217 } 4218 4219 if (cpu_has_vmx_encls_vmexit()) 4220 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull); 4221 4222 if (pt_mode == PT_MODE_HOST_GUEST) { 4223 memset(&vmx->pt_desc, 0, sizeof(vmx->pt_desc)); 4224 /* Bit[6~0] are forced to 1, writes are ignored. */ 4225 vmx->pt_desc.guest.output_mask = 0x7F; 4226 vmcs_write64(GUEST_IA32_RTIT_CTL, 0); 4227 } 4228 } 4229 4230 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) 4231 { 4232 struct vcpu_vmx *vmx = to_vmx(vcpu); 4233 struct msr_data apic_base_msr; 4234 u64 cr0; 4235 4236 vmx->rmode.vm86_active = 0; 4237 vmx->spec_ctrl = 0; 4238 4239 vmx->msr_ia32_umwait_control = 0; 4240 4241 vcpu->arch.microcode_version = 0x100000000ULL; 4242 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val(); 4243 vmx->hv_deadline_tsc = -1; 4244 kvm_set_cr8(vcpu, 0); 4245 4246 if (!init_event) { 4247 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE | 4248 MSR_IA32_APICBASE_ENABLE; 4249 if (kvm_vcpu_is_reset_bsp(vcpu)) 4250 apic_base_msr.data |= MSR_IA32_APICBASE_BSP; 4251 apic_base_msr.host_initiated = true; 4252 kvm_set_apic_base(vcpu, &apic_base_msr); 4253 } 4254 4255 vmx_segment_cache_clear(vmx); 4256 4257 seg_setup(VCPU_SREG_CS); 4258 vmcs_write16(GUEST_CS_SELECTOR, 0xf000); 4259 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul); 4260 4261 seg_setup(VCPU_SREG_DS); 4262 seg_setup(VCPU_SREG_ES); 4263 seg_setup(VCPU_SREG_FS); 4264 seg_setup(VCPU_SREG_GS); 4265 seg_setup(VCPU_SREG_SS); 4266 4267 vmcs_write16(GUEST_TR_SELECTOR, 0); 4268 vmcs_writel(GUEST_TR_BASE, 0); 4269 vmcs_write32(GUEST_TR_LIMIT, 0xffff); 4270 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b); 4271 4272 vmcs_write16(GUEST_LDTR_SELECTOR, 0); 4273 vmcs_writel(GUEST_LDTR_BASE, 0); 4274 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff); 4275 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082); 4276 4277 if (!init_event) { 4278 vmcs_write32(GUEST_SYSENTER_CS, 0); 4279 vmcs_writel(GUEST_SYSENTER_ESP, 0); 4280 vmcs_writel(GUEST_SYSENTER_EIP, 0); 4281 vmcs_write64(GUEST_IA32_DEBUGCTL, 0); 4282 } 4283 4284 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED); 4285 kvm_rip_write(vcpu, 0xfff0); 4286 4287 vmcs_writel(GUEST_GDTR_BASE, 0); 4288 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff); 4289 4290 vmcs_writel(GUEST_IDTR_BASE, 0); 4291 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff); 4292 4293 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE); 4294 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0); 4295 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0); 4296 if (kvm_mpx_supported()) 4297 vmcs_write64(GUEST_BNDCFGS, 0); 4298 4299 setup_msrs(vmx); 4300 4301 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */ 4302 4303 if (cpu_has_vmx_tpr_shadow() && !init_event) { 4304 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0); 4305 if (cpu_need_tpr_shadow(vcpu)) 4306 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 4307 __pa(vcpu->arch.apic->regs)); 4308 vmcs_write32(TPR_THRESHOLD, 0); 4309 } 4310 4311 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu); 4312 4313 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET; 4314 vmx->vcpu.arch.cr0 = cr0; 4315 vmx_set_cr0(vcpu, cr0); /* enter rmode */ 4316 vmx_set_cr4(vcpu, 0); 4317 vmx_set_efer(vcpu, 0); 4318 4319 update_exception_bitmap(vcpu); 4320 4321 vpid_sync_context(vmx->vpid); 4322 if (init_event) 4323 vmx_clear_hlt(vcpu); 4324 } 4325 4326 static void enable_irq_window(struct kvm_vcpu *vcpu) 4327 { 4328 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4329 } 4330 4331 static void enable_nmi_window(struct kvm_vcpu *vcpu) 4332 { 4333 if (!enable_vnmi || 4334 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) { 4335 enable_irq_window(vcpu); 4336 return; 4337 } 4338 4339 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 4340 } 4341 4342 static void vmx_inject_irq(struct kvm_vcpu *vcpu) 4343 { 4344 struct vcpu_vmx *vmx = to_vmx(vcpu); 4345 uint32_t intr; 4346 int irq = vcpu->arch.interrupt.nr; 4347 4348 trace_kvm_inj_virq(irq); 4349 4350 ++vcpu->stat.irq_injections; 4351 if (vmx->rmode.vm86_active) { 4352 int inc_eip = 0; 4353 if (vcpu->arch.interrupt.soft) 4354 inc_eip = vcpu->arch.event_exit_inst_len; 4355 kvm_inject_realmode_interrupt(vcpu, irq, inc_eip); 4356 return; 4357 } 4358 intr = irq | INTR_INFO_VALID_MASK; 4359 if (vcpu->arch.interrupt.soft) { 4360 intr |= INTR_TYPE_SOFT_INTR; 4361 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 4362 vmx->vcpu.arch.event_exit_inst_len); 4363 } else 4364 intr |= INTR_TYPE_EXT_INTR; 4365 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr); 4366 4367 vmx_clear_hlt(vcpu); 4368 } 4369 4370 static void vmx_inject_nmi(struct kvm_vcpu *vcpu) 4371 { 4372 struct vcpu_vmx *vmx = to_vmx(vcpu); 4373 4374 if (!enable_vnmi) { 4375 /* 4376 * Tracking the NMI-blocked state in software is built upon 4377 * finding the next open IRQ window. This, in turn, depends on 4378 * well-behaving guests: They have to keep IRQs disabled at 4379 * least as long as the NMI handler runs. Otherwise we may 4380 * cause NMI nesting, maybe breaking the guest. But as this is 4381 * highly unlikely, we can live with the residual risk. 4382 */ 4383 vmx->loaded_vmcs->soft_vnmi_blocked = 1; 4384 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4385 } 4386 4387 ++vcpu->stat.nmi_injections; 4388 vmx->loaded_vmcs->nmi_known_unmasked = false; 4389 4390 if (vmx->rmode.vm86_active) { 4391 kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0); 4392 return; 4393 } 4394 4395 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 4396 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR); 4397 4398 vmx_clear_hlt(vcpu); 4399 } 4400 4401 bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu) 4402 { 4403 struct vcpu_vmx *vmx = to_vmx(vcpu); 4404 bool masked; 4405 4406 if (!enable_vnmi) 4407 return vmx->loaded_vmcs->soft_vnmi_blocked; 4408 if (vmx->loaded_vmcs->nmi_known_unmasked) 4409 return false; 4410 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI; 4411 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4412 return masked; 4413 } 4414 4415 void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked) 4416 { 4417 struct vcpu_vmx *vmx = to_vmx(vcpu); 4418 4419 if (!enable_vnmi) { 4420 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) { 4421 vmx->loaded_vmcs->soft_vnmi_blocked = masked; 4422 vmx->loaded_vmcs->vnmi_blocked_time = 0; 4423 } 4424 } else { 4425 vmx->loaded_vmcs->nmi_known_unmasked = !masked; 4426 if (masked) 4427 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 4428 GUEST_INTR_STATE_NMI); 4429 else 4430 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO, 4431 GUEST_INTR_STATE_NMI); 4432 } 4433 } 4434 4435 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu) 4436 { 4437 if (to_vmx(vcpu)->nested.nested_run_pending) 4438 return 0; 4439 4440 if (!enable_vnmi && 4441 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked) 4442 return 0; 4443 4444 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4445 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI 4446 | GUEST_INTR_STATE_NMI)); 4447 } 4448 4449 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu) 4450 { 4451 return (!to_vmx(vcpu)->nested.nested_run_pending && 4452 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) && 4453 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 4454 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS)); 4455 } 4456 4457 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr) 4458 { 4459 int ret; 4460 4461 if (enable_unrestricted_guest) 4462 return 0; 4463 4464 mutex_lock(&kvm->slots_lock); 4465 ret = __x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr, 4466 PAGE_SIZE * 3); 4467 mutex_unlock(&kvm->slots_lock); 4468 4469 if (ret) 4470 return ret; 4471 to_kvm_vmx(kvm)->tss_addr = addr; 4472 return init_rmode_tss(kvm); 4473 } 4474 4475 static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr) 4476 { 4477 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr; 4478 return 0; 4479 } 4480 4481 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec) 4482 { 4483 switch (vec) { 4484 case BP_VECTOR: 4485 /* 4486 * Update instruction length as we may reinject the exception 4487 * from user space while in guest debugging mode. 4488 */ 4489 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len = 4490 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4491 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) 4492 return false; 4493 /* fall through */ 4494 case DB_VECTOR: 4495 if (vcpu->guest_debug & 4496 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) 4497 return false; 4498 /* fall through */ 4499 case DE_VECTOR: 4500 case OF_VECTOR: 4501 case BR_VECTOR: 4502 case UD_VECTOR: 4503 case DF_VECTOR: 4504 case SS_VECTOR: 4505 case GP_VECTOR: 4506 case MF_VECTOR: 4507 return true; 4508 break; 4509 } 4510 return false; 4511 } 4512 4513 static int handle_rmode_exception(struct kvm_vcpu *vcpu, 4514 int vec, u32 err_code) 4515 { 4516 /* 4517 * Instruction with address size override prefix opcode 0x67 4518 * Cause the #SS fault with 0 error code in VM86 mode. 4519 */ 4520 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) { 4521 if (kvm_emulate_instruction(vcpu, 0)) { 4522 if (vcpu->arch.halt_request) { 4523 vcpu->arch.halt_request = 0; 4524 return kvm_vcpu_halt(vcpu); 4525 } 4526 return 1; 4527 } 4528 return 0; 4529 } 4530 4531 /* 4532 * Forward all other exceptions that are valid in real mode. 4533 * FIXME: Breaks guest debugging in real mode, needs to be fixed with 4534 * the required debugging infrastructure rework. 4535 */ 4536 kvm_queue_exception(vcpu, vec); 4537 return 1; 4538 } 4539 4540 /* 4541 * Trigger machine check on the host. We assume all the MSRs are already set up 4542 * by the CPU and that we still run on the same CPU as the MCE occurred on. 4543 * We pass a fake environment to the machine check handler because we want 4544 * the guest to be always treated like user space, no matter what context 4545 * it used internally. 4546 */ 4547 static void kvm_machine_check(void) 4548 { 4549 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64) 4550 struct pt_regs regs = { 4551 .cs = 3, /* Fake ring 3 no matter what the guest ran on */ 4552 .flags = X86_EFLAGS_IF, 4553 }; 4554 4555 do_machine_check(®s, 0); 4556 #endif 4557 } 4558 4559 static int handle_machine_check(struct kvm_vcpu *vcpu) 4560 { 4561 /* handled by vmx_vcpu_run() */ 4562 return 1; 4563 } 4564 4565 static int handle_exception_nmi(struct kvm_vcpu *vcpu) 4566 { 4567 struct vcpu_vmx *vmx = to_vmx(vcpu); 4568 struct kvm_run *kvm_run = vcpu->run; 4569 u32 intr_info, ex_no, error_code; 4570 unsigned long cr2, rip, dr6; 4571 u32 vect_info; 4572 4573 vect_info = vmx->idt_vectoring_info; 4574 intr_info = vmx->exit_intr_info; 4575 4576 if (is_machine_check(intr_info) || is_nmi(intr_info)) 4577 return 1; /* handled by handle_exception_nmi_irqoff() */ 4578 4579 if (is_invalid_opcode(intr_info)) 4580 return handle_ud(vcpu); 4581 4582 error_code = 0; 4583 if (intr_info & INTR_INFO_DELIVER_CODE_MASK) 4584 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE); 4585 4586 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) { 4587 WARN_ON_ONCE(!enable_vmware_backdoor); 4588 4589 /* 4590 * VMware backdoor emulation on #GP interception only handles 4591 * IN{S}, OUT{S}, and RDPMC, none of which generate a non-zero 4592 * error code on #GP. 4593 */ 4594 if (error_code) { 4595 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code); 4596 return 1; 4597 } 4598 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP); 4599 } 4600 4601 /* 4602 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing 4603 * MMIO, it is better to report an internal error. 4604 * See the comments in vmx_handle_exit. 4605 */ 4606 if ((vect_info & VECTORING_INFO_VALID_MASK) && 4607 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) { 4608 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 4609 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX; 4610 vcpu->run->internal.ndata = 3; 4611 vcpu->run->internal.data[0] = vect_info; 4612 vcpu->run->internal.data[1] = intr_info; 4613 vcpu->run->internal.data[2] = error_code; 4614 return 0; 4615 } 4616 4617 if (is_page_fault(intr_info)) { 4618 cr2 = vmcs_readl(EXIT_QUALIFICATION); 4619 /* EPT won't cause page fault directly */ 4620 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept); 4621 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0); 4622 } 4623 4624 ex_no = intr_info & INTR_INFO_VECTOR_MASK; 4625 4626 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no)) 4627 return handle_rmode_exception(vcpu, ex_no, error_code); 4628 4629 switch (ex_no) { 4630 case AC_VECTOR: 4631 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code); 4632 return 1; 4633 case DB_VECTOR: 4634 dr6 = vmcs_readl(EXIT_QUALIFICATION); 4635 if (!(vcpu->guest_debug & 4636 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) { 4637 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4638 vcpu->arch.dr6 |= dr6 | DR6_RTM; 4639 if (is_icebp(intr_info)) 4640 WARN_ON(!skip_emulated_instruction(vcpu)); 4641 4642 kvm_queue_exception(vcpu, DB_VECTOR); 4643 return 1; 4644 } 4645 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1; 4646 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7); 4647 /* fall through */ 4648 case BP_VECTOR: 4649 /* 4650 * Update instruction length as we may reinject #BP from 4651 * user space while in guest debugging mode. Reading it for 4652 * #DB as well causes no harm, it is not used in that case. 4653 */ 4654 vmx->vcpu.arch.event_exit_inst_len = 4655 vmcs_read32(VM_EXIT_INSTRUCTION_LEN); 4656 kvm_run->exit_reason = KVM_EXIT_DEBUG; 4657 rip = kvm_rip_read(vcpu); 4658 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip; 4659 kvm_run->debug.arch.exception = ex_no; 4660 break; 4661 default: 4662 kvm_run->exit_reason = KVM_EXIT_EXCEPTION; 4663 kvm_run->ex.exception = ex_no; 4664 kvm_run->ex.error_code = error_code; 4665 break; 4666 } 4667 return 0; 4668 } 4669 4670 static __always_inline int handle_external_interrupt(struct kvm_vcpu *vcpu) 4671 { 4672 ++vcpu->stat.irq_exits; 4673 return 1; 4674 } 4675 4676 static int handle_triple_fault(struct kvm_vcpu *vcpu) 4677 { 4678 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN; 4679 vcpu->mmio_needed = 0; 4680 return 0; 4681 } 4682 4683 static int handle_io(struct kvm_vcpu *vcpu) 4684 { 4685 unsigned long exit_qualification; 4686 int size, in, string; 4687 unsigned port; 4688 4689 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4690 string = (exit_qualification & 16) != 0; 4691 4692 ++vcpu->stat.io_exits; 4693 4694 if (string) 4695 return kvm_emulate_instruction(vcpu, 0); 4696 4697 port = exit_qualification >> 16; 4698 size = (exit_qualification & 7) + 1; 4699 in = (exit_qualification & 8) != 0; 4700 4701 return kvm_fast_pio(vcpu, size, port, in); 4702 } 4703 4704 static void 4705 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall) 4706 { 4707 /* 4708 * Patch in the VMCALL instruction: 4709 */ 4710 hypercall[0] = 0x0f; 4711 hypercall[1] = 0x01; 4712 hypercall[2] = 0xc1; 4713 } 4714 4715 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */ 4716 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val) 4717 { 4718 if (is_guest_mode(vcpu)) { 4719 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4720 unsigned long orig_val = val; 4721 4722 /* 4723 * We get here when L2 changed cr0 in a way that did not change 4724 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr), 4725 * but did change L0 shadowed bits. So we first calculate the 4726 * effective cr0 value that L1 would like to write into the 4727 * hardware. It consists of the L2-owned bits from the new 4728 * value combined with the L1-owned bits from L1's guest_cr0. 4729 */ 4730 val = (val & ~vmcs12->cr0_guest_host_mask) | 4731 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask); 4732 4733 if (!nested_guest_cr0_valid(vcpu, val)) 4734 return 1; 4735 4736 if (kvm_set_cr0(vcpu, val)) 4737 return 1; 4738 vmcs_writel(CR0_READ_SHADOW, orig_val); 4739 return 0; 4740 } else { 4741 if (to_vmx(vcpu)->nested.vmxon && 4742 !nested_host_cr0_valid(vcpu, val)) 4743 return 1; 4744 4745 return kvm_set_cr0(vcpu, val); 4746 } 4747 } 4748 4749 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val) 4750 { 4751 if (is_guest_mode(vcpu)) { 4752 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 4753 unsigned long orig_val = val; 4754 4755 /* analogously to handle_set_cr0 */ 4756 val = (val & ~vmcs12->cr4_guest_host_mask) | 4757 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask); 4758 if (kvm_set_cr4(vcpu, val)) 4759 return 1; 4760 vmcs_writel(CR4_READ_SHADOW, orig_val); 4761 return 0; 4762 } else 4763 return kvm_set_cr4(vcpu, val); 4764 } 4765 4766 static int handle_desc(struct kvm_vcpu *vcpu) 4767 { 4768 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP)); 4769 return kvm_emulate_instruction(vcpu, 0); 4770 } 4771 4772 static int handle_cr(struct kvm_vcpu *vcpu) 4773 { 4774 unsigned long exit_qualification, val; 4775 int cr; 4776 int reg; 4777 int err; 4778 int ret; 4779 4780 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4781 cr = exit_qualification & 15; 4782 reg = (exit_qualification >> 8) & 15; 4783 switch ((exit_qualification >> 4) & 3) { 4784 case 0: /* mov to cr */ 4785 val = kvm_register_readl(vcpu, reg); 4786 trace_kvm_cr_write(cr, val); 4787 switch (cr) { 4788 case 0: 4789 err = handle_set_cr0(vcpu, val); 4790 return kvm_complete_insn_gp(vcpu, err); 4791 case 3: 4792 WARN_ON_ONCE(enable_unrestricted_guest); 4793 err = kvm_set_cr3(vcpu, val); 4794 return kvm_complete_insn_gp(vcpu, err); 4795 case 4: 4796 err = handle_set_cr4(vcpu, val); 4797 return kvm_complete_insn_gp(vcpu, err); 4798 case 8: { 4799 u8 cr8_prev = kvm_get_cr8(vcpu); 4800 u8 cr8 = (u8)val; 4801 err = kvm_set_cr8(vcpu, cr8); 4802 ret = kvm_complete_insn_gp(vcpu, err); 4803 if (lapic_in_kernel(vcpu)) 4804 return ret; 4805 if (cr8_prev <= cr8) 4806 return ret; 4807 /* 4808 * TODO: we might be squashing a 4809 * KVM_GUESTDBG_SINGLESTEP-triggered 4810 * KVM_EXIT_DEBUG here. 4811 */ 4812 vcpu->run->exit_reason = KVM_EXIT_SET_TPR; 4813 return 0; 4814 } 4815 } 4816 break; 4817 case 2: /* clts */ 4818 WARN_ONCE(1, "Guest should always own CR0.TS"); 4819 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS)); 4820 trace_kvm_cr_write(0, kvm_read_cr0(vcpu)); 4821 return kvm_skip_emulated_instruction(vcpu); 4822 case 1: /*mov from cr*/ 4823 switch (cr) { 4824 case 3: 4825 WARN_ON_ONCE(enable_unrestricted_guest); 4826 val = kvm_read_cr3(vcpu); 4827 kvm_register_write(vcpu, reg, val); 4828 trace_kvm_cr_read(cr, val); 4829 return kvm_skip_emulated_instruction(vcpu); 4830 case 8: 4831 val = kvm_get_cr8(vcpu); 4832 kvm_register_write(vcpu, reg, val); 4833 trace_kvm_cr_read(cr, val); 4834 return kvm_skip_emulated_instruction(vcpu); 4835 } 4836 break; 4837 case 3: /* lmsw */ 4838 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f; 4839 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val); 4840 kvm_lmsw(vcpu, val); 4841 4842 return kvm_skip_emulated_instruction(vcpu); 4843 default: 4844 break; 4845 } 4846 vcpu->run->exit_reason = 0; 4847 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n", 4848 (int)(exit_qualification >> 4) & 3, cr); 4849 return 0; 4850 } 4851 4852 static int handle_dr(struct kvm_vcpu *vcpu) 4853 { 4854 unsigned long exit_qualification; 4855 int dr, dr7, reg; 4856 4857 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4858 dr = exit_qualification & DEBUG_REG_ACCESS_NUM; 4859 4860 /* First, if DR does not exist, trigger UD */ 4861 if (!kvm_require_dr(vcpu, dr)) 4862 return 1; 4863 4864 /* Do not handle if the CPL > 0, will trigger GP on re-entry */ 4865 if (!kvm_require_cpl(vcpu, 0)) 4866 return 1; 4867 dr7 = vmcs_readl(GUEST_DR7); 4868 if (dr7 & DR7_GD) { 4869 /* 4870 * As the vm-exit takes precedence over the debug trap, we 4871 * need to emulate the latter, either for the host or the 4872 * guest debugging itself. 4873 */ 4874 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) { 4875 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6; 4876 vcpu->run->debug.arch.dr7 = dr7; 4877 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu); 4878 vcpu->run->debug.arch.exception = DB_VECTOR; 4879 vcpu->run->exit_reason = KVM_EXIT_DEBUG; 4880 return 0; 4881 } else { 4882 vcpu->arch.dr6 &= ~DR_TRAP_BITS; 4883 vcpu->arch.dr6 |= DR6_BD | DR6_RTM; 4884 kvm_queue_exception(vcpu, DB_VECTOR); 4885 return 1; 4886 } 4887 } 4888 4889 if (vcpu->guest_debug == 0) { 4890 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4891 4892 /* 4893 * No more DR vmexits; force a reload of the debug registers 4894 * and reenter on this instruction. The next vmexit will 4895 * retrieve the full state of the debug registers. 4896 */ 4897 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT; 4898 return 1; 4899 } 4900 4901 reg = DEBUG_REG_ACCESS_REG(exit_qualification); 4902 if (exit_qualification & TYPE_MOV_FROM_DR) { 4903 unsigned long val; 4904 4905 if (kvm_get_dr(vcpu, dr, &val)) 4906 return 1; 4907 kvm_register_write(vcpu, reg, val); 4908 } else 4909 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg))) 4910 return 1; 4911 4912 return kvm_skip_emulated_instruction(vcpu); 4913 } 4914 4915 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu) 4916 { 4917 return vcpu->arch.dr6; 4918 } 4919 4920 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val) 4921 { 4922 } 4923 4924 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu) 4925 { 4926 get_debugreg(vcpu->arch.db[0], 0); 4927 get_debugreg(vcpu->arch.db[1], 1); 4928 get_debugreg(vcpu->arch.db[2], 2); 4929 get_debugreg(vcpu->arch.db[3], 3); 4930 get_debugreg(vcpu->arch.dr6, 6); 4931 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7); 4932 4933 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT; 4934 exec_controls_setbit(to_vmx(vcpu), CPU_BASED_MOV_DR_EXITING); 4935 } 4936 4937 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val) 4938 { 4939 vmcs_writel(GUEST_DR7, val); 4940 } 4941 4942 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu) 4943 { 4944 kvm_apic_update_ppr(vcpu); 4945 return 1; 4946 } 4947 4948 static int handle_interrupt_window(struct kvm_vcpu *vcpu) 4949 { 4950 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_INTR_WINDOW_EXITING); 4951 4952 kvm_make_request(KVM_REQ_EVENT, vcpu); 4953 4954 ++vcpu->stat.irq_window_exits; 4955 return 1; 4956 } 4957 4958 static int handle_vmcall(struct kvm_vcpu *vcpu) 4959 { 4960 return kvm_emulate_hypercall(vcpu); 4961 } 4962 4963 static int handle_invd(struct kvm_vcpu *vcpu) 4964 { 4965 return kvm_emulate_instruction(vcpu, 0); 4966 } 4967 4968 static int handle_invlpg(struct kvm_vcpu *vcpu) 4969 { 4970 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 4971 4972 kvm_mmu_invlpg(vcpu, exit_qualification); 4973 return kvm_skip_emulated_instruction(vcpu); 4974 } 4975 4976 static int handle_rdpmc(struct kvm_vcpu *vcpu) 4977 { 4978 int err; 4979 4980 err = kvm_rdpmc(vcpu); 4981 return kvm_complete_insn_gp(vcpu, err); 4982 } 4983 4984 static int handle_wbinvd(struct kvm_vcpu *vcpu) 4985 { 4986 return kvm_emulate_wbinvd(vcpu); 4987 } 4988 4989 static int handle_xsetbv(struct kvm_vcpu *vcpu) 4990 { 4991 u64 new_bv = kvm_read_edx_eax(vcpu); 4992 u32 index = kvm_rcx_read(vcpu); 4993 4994 if (kvm_set_xcr(vcpu, index, new_bv) == 0) 4995 return kvm_skip_emulated_instruction(vcpu); 4996 return 1; 4997 } 4998 4999 static int handle_apic_access(struct kvm_vcpu *vcpu) 5000 { 5001 if (likely(fasteoi)) { 5002 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5003 int access_type, offset; 5004 5005 access_type = exit_qualification & APIC_ACCESS_TYPE; 5006 offset = exit_qualification & APIC_ACCESS_OFFSET; 5007 /* 5008 * Sane guest uses MOV to write EOI, with written value 5009 * not cared. So make a short-circuit here by avoiding 5010 * heavy instruction emulation. 5011 */ 5012 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) && 5013 (offset == APIC_EOI)) { 5014 kvm_lapic_set_eoi(vcpu); 5015 return kvm_skip_emulated_instruction(vcpu); 5016 } 5017 } 5018 return kvm_emulate_instruction(vcpu, 0); 5019 } 5020 5021 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu) 5022 { 5023 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5024 int vector = exit_qualification & 0xff; 5025 5026 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */ 5027 kvm_apic_set_eoi_accelerated(vcpu, vector); 5028 return 1; 5029 } 5030 5031 static int handle_apic_write(struct kvm_vcpu *vcpu) 5032 { 5033 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5034 u32 offset = exit_qualification & 0xfff; 5035 5036 /* APIC-write VM exit is trap-like and thus no need to adjust IP */ 5037 kvm_apic_write_nodecode(vcpu, offset); 5038 return 1; 5039 } 5040 5041 static int handle_task_switch(struct kvm_vcpu *vcpu) 5042 { 5043 struct vcpu_vmx *vmx = to_vmx(vcpu); 5044 unsigned long exit_qualification; 5045 bool has_error_code = false; 5046 u32 error_code = 0; 5047 u16 tss_selector; 5048 int reason, type, idt_v, idt_index; 5049 5050 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK); 5051 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK); 5052 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK); 5053 5054 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5055 5056 reason = (u32)exit_qualification >> 30; 5057 if (reason == TASK_SWITCH_GATE && idt_v) { 5058 switch (type) { 5059 case INTR_TYPE_NMI_INTR: 5060 vcpu->arch.nmi_injected = false; 5061 vmx_set_nmi_mask(vcpu, true); 5062 break; 5063 case INTR_TYPE_EXT_INTR: 5064 case INTR_TYPE_SOFT_INTR: 5065 kvm_clear_interrupt_queue(vcpu); 5066 break; 5067 case INTR_TYPE_HARD_EXCEPTION: 5068 if (vmx->idt_vectoring_info & 5069 VECTORING_INFO_DELIVER_CODE_MASK) { 5070 has_error_code = true; 5071 error_code = 5072 vmcs_read32(IDT_VECTORING_ERROR_CODE); 5073 } 5074 /* fall through */ 5075 case INTR_TYPE_SOFT_EXCEPTION: 5076 kvm_clear_exception_queue(vcpu); 5077 break; 5078 default: 5079 break; 5080 } 5081 } 5082 tss_selector = exit_qualification; 5083 5084 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION && 5085 type != INTR_TYPE_EXT_INTR && 5086 type != INTR_TYPE_NMI_INTR)) 5087 WARN_ON(!skip_emulated_instruction(vcpu)); 5088 5089 /* 5090 * TODO: What about debug traps on tss switch? 5091 * Are we supposed to inject them and update dr6? 5092 */ 5093 return kvm_task_switch(vcpu, tss_selector, 5094 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, 5095 reason, has_error_code, error_code); 5096 } 5097 5098 static int handle_ept_violation(struct kvm_vcpu *vcpu) 5099 { 5100 unsigned long exit_qualification; 5101 gpa_t gpa; 5102 u64 error_code; 5103 5104 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5105 5106 /* 5107 * EPT violation happened while executing iret from NMI, 5108 * "blocked by NMI" bit has to be set before next VM entry. 5109 * There are errata that may cause this bit to not be set: 5110 * AAK134, BY25. 5111 */ 5112 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5113 enable_vnmi && 5114 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5115 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI); 5116 5117 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5118 trace_kvm_page_fault(gpa, exit_qualification); 5119 5120 /* Is it a read fault? */ 5121 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ) 5122 ? PFERR_USER_MASK : 0; 5123 /* Is it a write fault? */ 5124 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE) 5125 ? PFERR_WRITE_MASK : 0; 5126 /* Is it a fetch fault? */ 5127 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR) 5128 ? PFERR_FETCH_MASK : 0; 5129 /* ept page table entry is present? */ 5130 error_code |= (exit_qualification & 5131 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE | 5132 EPT_VIOLATION_EXECUTABLE)) 5133 ? PFERR_PRESENT_MASK : 0; 5134 5135 error_code |= (exit_qualification & 0x100) != 0 ? 5136 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK; 5137 5138 vcpu->arch.exit_qualification = exit_qualification; 5139 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0); 5140 } 5141 5142 static int handle_ept_misconfig(struct kvm_vcpu *vcpu) 5143 { 5144 gpa_t gpa; 5145 5146 /* 5147 * A nested guest cannot optimize MMIO vmexits, because we have an 5148 * nGPA here instead of the required GPA. 5149 */ 5150 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5151 if (!is_guest_mode(vcpu) && 5152 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) { 5153 trace_kvm_fast_mmio(gpa); 5154 return kvm_skip_emulated_instruction(vcpu); 5155 } 5156 5157 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0); 5158 } 5159 5160 static int handle_nmi_window(struct kvm_vcpu *vcpu) 5161 { 5162 WARN_ON_ONCE(!enable_vnmi); 5163 exec_controls_clearbit(to_vmx(vcpu), CPU_BASED_NMI_WINDOW_EXITING); 5164 ++vcpu->stat.nmi_window_exits; 5165 kvm_make_request(KVM_REQ_EVENT, vcpu); 5166 5167 return 1; 5168 } 5169 5170 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu) 5171 { 5172 struct vcpu_vmx *vmx = to_vmx(vcpu); 5173 bool intr_window_requested; 5174 unsigned count = 130; 5175 5176 /* 5177 * We should never reach the point where we are emulating L2 5178 * due to invalid guest state as that means we incorrectly 5179 * allowed a nested VMEntry with an invalid vmcs12. 5180 */ 5181 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending); 5182 5183 intr_window_requested = exec_controls_get(vmx) & 5184 CPU_BASED_INTR_WINDOW_EXITING; 5185 5186 while (vmx->emulation_required && count-- != 0) { 5187 if (intr_window_requested && vmx_interrupt_allowed(vcpu)) 5188 return handle_interrupt_window(&vmx->vcpu); 5189 5190 if (kvm_test_request(KVM_REQ_EVENT, vcpu)) 5191 return 1; 5192 5193 if (!kvm_emulate_instruction(vcpu, 0)) 5194 return 0; 5195 5196 if (vmx->emulation_required && !vmx->rmode.vm86_active && 5197 vcpu->arch.exception.pending) { 5198 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5199 vcpu->run->internal.suberror = 5200 KVM_INTERNAL_ERROR_EMULATION; 5201 vcpu->run->internal.ndata = 0; 5202 return 0; 5203 } 5204 5205 if (vcpu->arch.halt_request) { 5206 vcpu->arch.halt_request = 0; 5207 return kvm_vcpu_halt(vcpu); 5208 } 5209 5210 /* 5211 * Note, return 1 and not 0, vcpu_run() is responsible for 5212 * morphing the pending signal into the proper return code. 5213 */ 5214 if (signal_pending(current)) 5215 return 1; 5216 5217 if (need_resched()) 5218 schedule(); 5219 } 5220 5221 return 1; 5222 } 5223 5224 static void grow_ple_window(struct kvm_vcpu *vcpu) 5225 { 5226 struct vcpu_vmx *vmx = to_vmx(vcpu); 5227 unsigned int old = vmx->ple_window; 5228 5229 vmx->ple_window = __grow_ple_window(old, ple_window, 5230 ple_window_grow, 5231 ple_window_max); 5232 5233 if (vmx->ple_window != old) { 5234 vmx->ple_window_dirty = true; 5235 trace_kvm_ple_window_update(vcpu->vcpu_id, 5236 vmx->ple_window, old); 5237 } 5238 } 5239 5240 static void shrink_ple_window(struct kvm_vcpu *vcpu) 5241 { 5242 struct vcpu_vmx *vmx = to_vmx(vcpu); 5243 unsigned int old = vmx->ple_window; 5244 5245 vmx->ple_window = __shrink_ple_window(old, ple_window, 5246 ple_window_shrink, 5247 ple_window); 5248 5249 if (vmx->ple_window != old) { 5250 vmx->ple_window_dirty = true; 5251 trace_kvm_ple_window_update(vcpu->vcpu_id, 5252 vmx->ple_window, old); 5253 } 5254 } 5255 5256 /* 5257 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR. 5258 */ 5259 static void wakeup_handler(void) 5260 { 5261 struct kvm_vcpu *vcpu; 5262 int cpu = smp_processor_id(); 5263 5264 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5265 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu), 5266 blocked_vcpu_list) { 5267 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 5268 5269 if (pi_test_on(pi_desc) == 1) 5270 kvm_vcpu_kick(vcpu); 5271 } 5272 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu)); 5273 } 5274 5275 static void vmx_enable_tdp(void) 5276 { 5277 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK, 5278 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull, 5279 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull, 5280 0ull, VMX_EPT_EXECUTABLE_MASK, 5281 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK, 5282 VMX_EPT_RWX_MASK, 0ull); 5283 5284 ept_set_mmio_spte_mask(); 5285 kvm_enable_tdp(); 5286 } 5287 5288 /* 5289 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE 5290 * exiting, so only get here on cpu with PAUSE-Loop-Exiting. 5291 */ 5292 static int handle_pause(struct kvm_vcpu *vcpu) 5293 { 5294 if (!kvm_pause_in_guest(vcpu->kvm)) 5295 grow_ple_window(vcpu); 5296 5297 /* 5298 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting" 5299 * VM-execution control is ignored if CPL > 0. OTOH, KVM 5300 * never set PAUSE_EXITING and just set PLE if supported, 5301 * so the vcpu must be CPL=0 if it gets a PAUSE exit. 5302 */ 5303 kvm_vcpu_on_spin(vcpu, true); 5304 return kvm_skip_emulated_instruction(vcpu); 5305 } 5306 5307 static int handle_nop(struct kvm_vcpu *vcpu) 5308 { 5309 return kvm_skip_emulated_instruction(vcpu); 5310 } 5311 5312 static int handle_mwait(struct kvm_vcpu *vcpu) 5313 { 5314 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n"); 5315 return handle_nop(vcpu); 5316 } 5317 5318 static int handle_invalid_op(struct kvm_vcpu *vcpu) 5319 { 5320 kvm_queue_exception(vcpu, UD_VECTOR); 5321 return 1; 5322 } 5323 5324 static int handle_monitor_trap(struct kvm_vcpu *vcpu) 5325 { 5326 return 1; 5327 } 5328 5329 static int handle_monitor(struct kvm_vcpu *vcpu) 5330 { 5331 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n"); 5332 return handle_nop(vcpu); 5333 } 5334 5335 static int handle_invpcid(struct kvm_vcpu *vcpu) 5336 { 5337 u32 vmx_instruction_info; 5338 unsigned long type; 5339 bool pcid_enabled; 5340 gva_t gva; 5341 struct x86_exception e; 5342 unsigned i; 5343 unsigned long roots_to_free = 0; 5344 struct { 5345 u64 pcid; 5346 u64 gla; 5347 } operand; 5348 5349 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) { 5350 kvm_queue_exception(vcpu, UD_VECTOR); 5351 return 1; 5352 } 5353 5354 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO); 5355 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf); 5356 5357 if (type > 3) { 5358 kvm_inject_gp(vcpu, 0); 5359 return 1; 5360 } 5361 5362 /* According to the Intel instruction reference, the memory operand 5363 * is read even if it isn't needed (e.g., for type==all) 5364 */ 5365 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION), 5366 vmx_instruction_info, false, 5367 sizeof(operand), &gva)) 5368 return 1; 5369 5370 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) { 5371 kvm_inject_page_fault(vcpu, &e); 5372 return 1; 5373 } 5374 5375 if (operand.pcid >> 12 != 0) { 5376 kvm_inject_gp(vcpu, 0); 5377 return 1; 5378 } 5379 5380 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE); 5381 5382 switch (type) { 5383 case INVPCID_TYPE_INDIV_ADDR: 5384 if ((!pcid_enabled && (operand.pcid != 0)) || 5385 is_noncanonical_address(operand.gla, vcpu)) { 5386 kvm_inject_gp(vcpu, 0); 5387 return 1; 5388 } 5389 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid); 5390 return kvm_skip_emulated_instruction(vcpu); 5391 5392 case INVPCID_TYPE_SINGLE_CTXT: 5393 if (!pcid_enabled && (operand.pcid != 0)) { 5394 kvm_inject_gp(vcpu, 0); 5395 return 1; 5396 } 5397 5398 if (kvm_get_active_pcid(vcpu) == operand.pcid) { 5399 kvm_mmu_sync_roots(vcpu); 5400 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); 5401 } 5402 5403 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) 5404 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3) 5405 == operand.pcid) 5406 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i); 5407 5408 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free); 5409 /* 5410 * If neither the current cr3 nor any of the prev_roots use the 5411 * given PCID, then nothing needs to be done here because a 5412 * resync will happen anyway before switching to any other CR3. 5413 */ 5414 5415 return kvm_skip_emulated_instruction(vcpu); 5416 5417 case INVPCID_TYPE_ALL_NON_GLOBAL: 5418 /* 5419 * Currently, KVM doesn't mark global entries in the shadow 5420 * page tables, so a non-global flush just degenerates to a 5421 * global flush. If needed, we could optimize this later by 5422 * keeping track of global entries in shadow page tables. 5423 */ 5424 5425 /* fall-through */ 5426 case INVPCID_TYPE_ALL_INCL_GLOBAL: 5427 kvm_mmu_unload(vcpu); 5428 return kvm_skip_emulated_instruction(vcpu); 5429 5430 default: 5431 BUG(); /* We have already checked above that type <= 3 */ 5432 } 5433 } 5434 5435 static int handle_pml_full(struct kvm_vcpu *vcpu) 5436 { 5437 unsigned long exit_qualification; 5438 5439 trace_kvm_pml_full(vcpu->vcpu_id); 5440 5441 exit_qualification = vmcs_readl(EXIT_QUALIFICATION); 5442 5443 /* 5444 * PML buffer FULL happened while executing iret from NMI, 5445 * "blocked by NMI" bit has to be set before next VM entry. 5446 */ 5447 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) && 5448 enable_vnmi && 5449 (exit_qualification & INTR_INFO_UNBLOCK_NMI)) 5450 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 5451 GUEST_INTR_STATE_NMI); 5452 5453 /* 5454 * PML buffer already flushed at beginning of VMEXIT. Nothing to do 5455 * here.., and there's no userspace involvement needed for PML. 5456 */ 5457 return 1; 5458 } 5459 5460 static int handle_preemption_timer(struct kvm_vcpu *vcpu) 5461 { 5462 struct vcpu_vmx *vmx = to_vmx(vcpu); 5463 5464 if (!vmx->req_immediate_exit && 5465 !unlikely(vmx->loaded_vmcs->hv_timer_soft_disabled)) 5466 kvm_lapic_expired_hv_timer(vcpu); 5467 5468 return 1; 5469 } 5470 5471 /* 5472 * When nested=0, all VMX instruction VM Exits filter here. The handlers 5473 * are overwritten by nested_vmx_setup() when nested=1. 5474 */ 5475 static int handle_vmx_instruction(struct kvm_vcpu *vcpu) 5476 { 5477 kvm_queue_exception(vcpu, UD_VECTOR); 5478 return 1; 5479 } 5480 5481 static int handle_encls(struct kvm_vcpu *vcpu) 5482 { 5483 /* 5484 * SGX virtualization is not yet supported. There is no software 5485 * enable bit for SGX, so we have to trap ENCLS and inject a #UD 5486 * to prevent the guest from executing ENCLS. 5487 */ 5488 kvm_queue_exception(vcpu, UD_VECTOR); 5489 return 1; 5490 } 5491 5492 /* 5493 * The exit handlers return 1 if the exit was handled fully and guest execution 5494 * may resume. Otherwise they set the kvm_run parameter to indicate what needs 5495 * to be done to userspace and return 0. 5496 */ 5497 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { 5498 [EXIT_REASON_EXCEPTION_NMI] = handle_exception_nmi, 5499 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt, 5500 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault, 5501 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window, 5502 [EXIT_REASON_IO_INSTRUCTION] = handle_io, 5503 [EXIT_REASON_CR_ACCESS] = handle_cr, 5504 [EXIT_REASON_DR_ACCESS] = handle_dr, 5505 [EXIT_REASON_CPUID] = kvm_emulate_cpuid, 5506 [EXIT_REASON_MSR_READ] = kvm_emulate_rdmsr, 5507 [EXIT_REASON_MSR_WRITE] = kvm_emulate_wrmsr, 5508 [EXIT_REASON_INTERRUPT_WINDOW] = handle_interrupt_window, 5509 [EXIT_REASON_HLT] = kvm_emulate_halt, 5510 [EXIT_REASON_INVD] = handle_invd, 5511 [EXIT_REASON_INVLPG] = handle_invlpg, 5512 [EXIT_REASON_RDPMC] = handle_rdpmc, 5513 [EXIT_REASON_VMCALL] = handle_vmcall, 5514 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction, 5515 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction, 5516 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction, 5517 [EXIT_REASON_VMPTRST] = handle_vmx_instruction, 5518 [EXIT_REASON_VMREAD] = handle_vmx_instruction, 5519 [EXIT_REASON_VMRESUME] = handle_vmx_instruction, 5520 [EXIT_REASON_VMWRITE] = handle_vmx_instruction, 5521 [EXIT_REASON_VMOFF] = handle_vmx_instruction, 5522 [EXIT_REASON_VMON] = handle_vmx_instruction, 5523 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold, 5524 [EXIT_REASON_APIC_ACCESS] = handle_apic_access, 5525 [EXIT_REASON_APIC_WRITE] = handle_apic_write, 5526 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced, 5527 [EXIT_REASON_WBINVD] = handle_wbinvd, 5528 [EXIT_REASON_XSETBV] = handle_xsetbv, 5529 [EXIT_REASON_TASK_SWITCH] = handle_task_switch, 5530 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check, 5531 [EXIT_REASON_GDTR_IDTR] = handle_desc, 5532 [EXIT_REASON_LDTR_TR] = handle_desc, 5533 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation, 5534 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig, 5535 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause, 5536 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait, 5537 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap, 5538 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor, 5539 [EXIT_REASON_INVEPT] = handle_vmx_instruction, 5540 [EXIT_REASON_INVVPID] = handle_vmx_instruction, 5541 [EXIT_REASON_RDRAND] = handle_invalid_op, 5542 [EXIT_REASON_RDSEED] = handle_invalid_op, 5543 [EXIT_REASON_PML_FULL] = handle_pml_full, 5544 [EXIT_REASON_INVPCID] = handle_invpcid, 5545 [EXIT_REASON_VMFUNC] = handle_vmx_instruction, 5546 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer, 5547 [EXIT_REASON_ENCLS] = handle_encls, 5548 }; 5549 5550 static const int kvm_vmx_max_exit_handlers = 5551 ARRAY_SIZE(kvm_vmx_exit_handlers); 5552 5553 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2) 5554 { 5555 *info1 = vmcs_readl(EXIT_QUALIFICATION); 5556 *info2 = vmcs_read32(VM_EXIT_INTR_INFO); 5557 } 5558 5559 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx) 5560 { 5561 if (vmx->pml_pg) { 5562 __free_page(vmx->pml_pg); 5563 vmx->pml_pg = NULL; 5564 } 5565 } 5566 5567 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu) 5568 { 5569 struct vcpu_vmx *vmx = to_vmx(vcpu); 5570 u64 *pml_buf; 5571 u16 pml_idx; 5572 5573 pml_idx = vmcs_read16(GUEST_PML_INDEX); 5574 5575 /* Do nothing if PML buffer is empty */ 5576 if (pml_idx == (PML_ENTITY_NUM - 1)) 5577 return; 5578 5579 /* PML index always points to next available PML buffer entity */ 5580 if (pml_idx >= PML_ENTITY_NUM) 5581 pml_idx = 0; 5582 else 5583 pml_idx++; 5584 5585 pml_buf = page_address(vmx->pml_pg); 5586 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) { 5587 u64 gpa; 5588 5589 gpa = pml_buf[pml_idx]; 5590 WARN_ON(gpa & (PAGE_SIZE - 1)); 5591 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT); 5592 } 5593 5594 /* reset PML index */ 5595 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1); 5596 } 5597 5598 /* 5599 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap. 5600 * Called before reporting dirty_bitmap to userspace. 5601 */ 5602 static void kvm_flush_pml_buffers(struct kvm *kvm) 5603 { 5604 int i; 5605 struct kvm_vcpu *vcpu; 5606 /* 5607 * We only need to kick vcpu out of guest mode here, as PML buffer 5608 * is flushed at beginning of all VMEXITs, and it's obvious that only 5609 * vcpus running in guest are possible to have unflushed GPAs in PML 5610 * buffer. 5611 */ 5612 kvm_for_each_vcpu(i, vcpu, kvm) 5613 kvm_vcpu_kick(vcpu); 5614 } 5615 5616 static void vmx_dump_sel(char *name, uint32_t sel) 5617 { 5618 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n", 5619 name, vmcs_read16(sel), 5620 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR), 5621 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR), 5622 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR)); 5623 } 5624 5625 static void vmx_dump_dtsel(char *name, uint32_t limit) 5626 { 5627 pr_err("%s limit=0x%08x, base=0x%016lx\n", 5628 name, vmcs_read32(limit), 5629 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT)); 5630 } 5631 5632 void dump_vmcs(void) 5633 { 5634 u32 vmentry_ctl, vmexit_ctl; 5635 u32 cpu_based_exec_ctrl, pin_based_exec_ctrl, secondary_exec_control; 5636 unsigned long cr4; 5637 u64 efer; 5638 int i, n; 5639 5640 if (!dump_invalid_vmcs) { 5641 pr_warn_ratelimited("set kvm_intel.dump_invalid_vmcs=1 to dump internal KVM state.\n"); 5642 return; 5643 } 5644 5645 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS); 5646 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS); 5647 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL); 5648 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL); 5649 cr4 = vmcs_readl(GUEST_CR4); 5650 efer = vmcs_read64(GUEST_IA32_EFER); 5651 secondary_exec_control = 0; 5652 if (cpu_has_secondary_exec_ctrls()) 5653 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL); 5654 5655 pr_err("*** Guest State ***\n"); 5656 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5657 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW), 5658 vmcs_readl(CR0_GUEST_HOST_MASK)); 5659 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n", 5660 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK)); 5661 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3)); 5662 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) && 5663 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA)) 5664 { 5665 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n", 5666 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1)); 5667 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n", 5668 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3)); 5669 } 5670 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n", 5671 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP)); 5672 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n", 5673 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7)); 5674 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5675 vmcs_readl(GUEST_SYSENTER_ESP), 5676 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP)); 5677 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR); 5678 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR); 5679 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR); 5680 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR); 5681 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR); 5682 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR); 5683 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT); 5684 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR); 5685 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT); 5686 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR); 5687 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) || 5688 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER))) 5689 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5690 efer, vmcs_read64(GUEST_IA32_PAT)); 5691 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n", 5692 vmcs_read64(GUEST_IA32_DEBUGCTL), 5693 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS)); 5694 if (cpu_has_load_perf_global_ctrl() && 5695 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL) 5696 pr_err("PerfGlobCtl = 0x%016llx\n", 5697 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL)); 5698 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS) 5699 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS)); 5700 pr_err("Interruptibility = %08x ActivityState = %08x\n", 5701 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO), 5702 vmcs_read32(GUEST_ACTIVITY_STATE)); 5703 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) 5704 pr_err("InterruptStatus = %04x\n", 5705 vmcs_read16(GUEST_INTR_STATUS)); 5706 5707 pr_err("*** Host State ***\n"); 5708 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n", 5709 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP)); 5710 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n", 5711 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR), 5712 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR), 5713 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR), 5714 vmcs_read16(HOST_TR_SELECTOR)); 5715 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n", 5716 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE), 5717 vmcs_readl(HOST_TR_BASE)); 5718 pr_err("GDTBase=%016lx IDTBase=%016lx\n", 5719 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE)); 5720 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n", 5721 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3), 5722 vmcs_readl(HOST_CR4)); 5723 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n", 5724 vmcs_readl(HOST_IA32_SYSENTER_ESP), 5725 vmcs_read32(HOST_IA32_SYSENTER_CS), 5726 vmcs_readl(HOST_IA32_SYSENTER_EIP)); 5727 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER)) 5728 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n", 5729 vmcs_read64(HOST_IA32_EFER), 5730 vmcs_read64(HOST_IA32_PAT)); 5731 if (cpu_has_load_perf_global_ctrl() && 5732 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL) 5733 pr_err("PerfGlobCtl = 0x%016llx\n", 5734 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL)); 5735 5736 pr_err("*** Control State ***\n"); 5737 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n", 5738 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control); 5739 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl); 5740 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n", 5741 vmcs_read32(EXCEPTION_BITMAP), 5742 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK), 5743 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH)); 5744 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n", 5745 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 5746 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE), 5747 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN)); 5748 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n", 5749 vmcs_read32(VM_EXIT_INTR_INFO), 5750 vmcs_read32(VM_EXIT_INTR_ERROR_CODE), 5751 vmcs_read32(VM_EXIT_INSTRUCTION_LEN)); 5752 pr_err(" reason=%08x qualification=%016lx\n", 5753 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION)); 5754 pr_err("IDTVectoring: info=%08x errcode=%08x\n", 5755 vmcs_read32(IDT_VECTORING_INFO_FIELD), 5756 vmcs_read32(IDT_VECTORING_ERROR_CODE)); 5757 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET)); 5758 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING) 5759 pr_err("TSC Multiplier = 0x%016llx\n", 5760 vmcs_read64(TSC_MULTIPLIER)); 5761 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW) { 5762 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) { 5763 u16 status = vmcs_read16(GUEST_INTR_STATUS); 5764 pr_err("SVI|RVI = %02x|%02x ", status >> 8, status & 0xff); 5765 } 5766 pr_cont("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD)); 5767 if (secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) 5768 pr_err("APIC-access addr = 0x%016llx ", vmcs_read64(APIC_ACCESS_ADDR)); 5769 pr_cont("virt-APIC addr = 0x%016llx\n", vmcs_read64(VIRTUAL_APIC_PAGE_ADDR)); 5770 } 5771 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR) 5772 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV)); 5773 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT)) 5774 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER)); 5775 n = vmcs_read32(CR3_TARGET_COUNT); 5776 for (i = 0; i + 1 < n; i += 4) 5777 pr_err("CR3 target%u=%016lx target%u=%016lx\n", 5778 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2), 5779 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2)); 5780 if (i < n) 5781 pr_err("CR3 target%u=%016lx\n", 5782 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2)); 5783 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING) 5784 pr_err("PLE Gap=%08x Window=%08x\n", 5785 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW)); 5786 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID) 5787 pr_err("Virtual processor ID = 0x%04x\n", 5788 vmcs_read16(VIRTUAL_PROCESSOR_ID)); 5789 } 5790 5791 /* 5792 * The guest has exited. See if we can fix it or if we need userspace 5793 * assistance. 5794 */ 5795 static int vmx_handle_exit(struct kvm_vcpu *vcpu, 5796 enum exit_fastpath_completion exit_fastpath) 5797 { 5798 struct vcpu_vmx *vmx = to_vmx(vcpu); 5799 u32 exit_reason = vmx->exit_reason; 5800 u32 vectoring_info = vmx->idt_vectoring_info; 5801 5802 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX); 5803 5804 /* 5805 * Flush logged GPAs PML buffer, this will make dirty_bitmap more 5806 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before 5807 * querying dirty_bitmap, we only need to kick all vcpus out of guest 5808 * mode as if vcpus is in root mode, the PML buffer must has been 5809 * flushed already. 5810 */ 5811 if (enable_pml) 5812 vmx_flush_pml_buffer(vcpu); 5813 5814 /* If guest state is invalid, start emulating */ 5815 if (vmx->emulation_required) 5816 return handle_invalid_guest_state(vcpu); 5817 5818 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason)) 5819 return nested_vmx_reflect_vmexit(vcpu, exit_reason); 5820 5821 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) { 5822 dump_vmcs(); 5823 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5824 vcpu->run->fail_entry.hardware_entry_failure_reason 5825 = exit_reason; 5826 return 0; 5827 } 5828 5829 if (unlikely(vmx->fail)) { 5830 dump_vmcs(); 5831 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY; 5832 vcpu->run->fail_entry.hardware_entry_failure_reason 5833 = vmcs_read32(VM_INSTRUCTION_ERROR); 5834 return 0; 5835 } 5836 5837 /* 5838 * Note: 5839 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by 5840 * delivery event since it indicates guest is accessing MMIO. 5841 * The vm-exit can be triggered again after return to guest that 5842 * will cause infinite loop. 5843 */ 5844 if ((vectoring_info & VECTORING_INFO_VALID_MASK) && 5845 (exit_reason != EXIT_REASON_EXCEPTION_NMI && 5846 exit_reason != EXIT_REASON_EPT_VIOLATION && 5847 exit_reason != EXIT_REASON_PML_FULL && 5848 exit_reason != EXIT_REASON_TASK_SWITCH)) { 5849 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5850 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV; 5851 vcpu->run->internal.ndata = 3; 5852 vcpu->run->internal.data[0] = vectoring_info; 5853 vcpu->run->internal.data[1] = exit_reason; 5854 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification; 5855 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) { 5856 vcpu->run->internal.ndata++; 5857 vcpu->run->internal.data[3] = 5858 vmcs_read64(GUEST_PHYSICAL_ADDRESS); 5859 } 5860 return 0; 5861 } 5862 5863 if (unlikely(!enable_vnmi && 5864 vmx->loaded_vmcs->soft_vnmi_blocked)) { 5865 if (vmx_interrupt_allowed(vcpu)) { 5866 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5867 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL && 5868 vcpu->arch.nmi_pending) { 5869 /* 5870 * This CPU don't support us in finding the end of an 5871 * NMI-blocked window if the guest runs with IRQs 5872 * disabled. So we pull the trigger after 1 s of 5873 * futile waiting, but inform the user about this. 5874 */ 5875 printk(KERN_WARNING "%s: Breaking out of NMI-blocked " 5876 "state on VCPU %d after 1 s timeout\n", 5877 __func__, vcpu->vcpu_id); 5878 vmx->loaded_vmcs->soft_vnmi_blocked = 0; 5879 } 5880 } 5881 5882 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) { 5883 kvm_skip_emulated_instruction(vcpu); 5884 return 1; 5885 } 5886 5887 if (exit_reason >= kvm_vmx_max_exit_handlers) 5888 goto unexpected_vmexit; 5889 #ifdef CONFIG_RETPOLINE 5890 if (exit_reason == EXIT_REASON_MSR_WRITE) 5891 return kvm_emulate_wrmsr(vcpu); 5892 else if (exit_reason == EXIT_REASON_PREEMPTION_TIMER) 5893 return handle_preemption_timer(vcpu); 5894 else if (exit_reason == EXIT_REASON_INTERRUPT_WINDOW) 5895 return handle_interrupt_window(vcpu); 5896 else if (exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 5897 return handle_external_interrupt(vcpu); 5898 else if (exit_reason == EXIT_REASON_HLT) 5899 return kvm_emulate_halt(vcpu); 5900 else if (exit_reason == EXIT_REASON_EPT_MISCONFIG) 5901 return handle_ept_misconfig(vcpu); 5902 #endif 5903 5904 exit_reason = array_index_nospec(exit_reason, 5905 kvm_vmx_max_exit_handlers); 5906 if (!kvm_vmx_exit_handlers[exit_reason]) 5907 goto unexpected_vmexit; 5908 5909 return kvm_vmx_exit_handlers[exit_reason](vcpu); 5910 5911 unexpected_vmexit: 5912 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n", exit_reason); 5913 dump_vmcs(); 5914 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR; 5915 vcpu->run->internal.suberror = 5916 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON; 5917 vcpu->run->internal.ndata = 1; 5918 vcpu->run->internal.data[0] = exit_reason; 5919 return 0; 5920 } 5921 5922 /* 5923 * Software based L1D cache flush which is used when microcode providing 5924 * the cache control MSR is not loaded. 5925 * 5926 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to 5927 * flush it is required to read in 64 KiB because the replacement algorithm 5928 * is not exactly LRU. This could be sized at runtime via topology 5929 * information but as all relevant affected CPUs have 32KiB L1D cache size 5930 * there is no point in doing so. 5931 */ 5932 static void vmx_l1d_flush(struct kvm_vcpu *vcpu) 5933 { 5934 int size = PAGE_SIZE << L1D_CACHE_ORDER; 5935 5936 /* 5937 * This code is only executed when the the flush mode is 'cond' or 5938 * 'always' 5939 */ 5940 if (static_branch_likely(&vmx_l1d_flush_cond)) { 5941 bool flush_l1d; 5942 5943 /* 5944 * Clear the per-vcpu flush bit, it gets set again 5945 * either from vcpu_run() or from one of the unsafe 5946 * VMEXIT handlers. 5947 */ 5948 flush_l1d = vcpu->arch.l1tf_flush_l1d; 5949 vcpu->arch.l1tf_flush_l1d = false; 5950 5951 /* 5952 * Clear the per-cpu flush bit, it gets set again from 5953 * the interrupt handlers. 5954 */ 5955 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d(); 5956 kvm_clear_cpu_l1tf_flush_l1d(); 5957 5958 if (!flush_l1d) 5959 return; 5960 } 5961 5962 vcpu->stat.l1d_flush++; 5963 5964 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { 5965 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH); 5966 return; 5967 } 5968 5969 asm volatile( 5970 /* First ensure the pages are in the TLB */ 5971 "xorl %%eax, %%eax\n" 5972 ".Lpopulate_tlb:\n\t" 5973 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5974 "addl $4096, %%eax\n\t" 5975 "cmpl %%eax, %[size]\n\t" 5976 "jne .Lpopulate_tlb\n\t" 5977 "xorl %%eax, %%eax\n\t" 5978 "cpuid\n\t" 5979 /* Now fill the cache */ 5980 "xorl %%eax, %%eax\n" 5981 ".Lfill_cache:\n" 5982 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t" 5983 "addl $64, %%eax\n\t" 5984 "cmpl %%eax, %[size]\n\t" 5985 "jne .Lfill_cache\n\t" 5986 "lfence\n" 5987 :: [flush_pages] "r" (vmx_l1d_flush_pages), 5988 [size] "r" (size) 5989 : "eax", "ebx", "ecx", "edx"); 5990 } 5991 5992 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) 5993 { 5994 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 5995 int tpr_threshold; 5996 5997 if (is_guest_mode(vcpu) && 5998 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) 5999 return; 6000 6001 tpr_threshold = (irr == -1 || tpr < irr) ? 0 : irr; 6002 if (is_guest_mode(vcpu)) 6003 to_vmx(vcpu)->nested.l1_tpr_threshold = tpr_threshold; 6004 else 6005 vmcs_write32(TPR_THRESHOLD, tpr_threshold); 6006 } 6007 6008 void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) 6009 { 6010 struct vcpu_vmx *vmx = to_vmx(vcpu); 6011 u32 sec_exec_control; 6012 6013 if (!lapic_in_kernel(vcpu)) 6014 return; 6015 6016 if (!flexpriority_enabled && 6017 !cpu_has_vmx_virtualize_x2apic_mode()) 6018 return; 6019 6020 /* Postpone execution until vmcs01 is the current VMCS. */ 6021 if (is_guest_mode(vcpu)) { 6022 vmx->nested.change_vmcs01_virtual_apic_mode = true; 6023 return; 6024 } 6025 6026 sec_exec_control = secondary_exec_controls_get(vmx); 6027 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6028 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE); 6029 6030 switch (kvm_get_apic_mode(vcpu)) { 6031 case LAPIC_MODE_INVALID: 6032 WARN_ONCE(true, "Invalid local APIC state"); 6033 case LAPIC_MODE_DISABLED: 6034 break; 6035 case LAPIC_MODE_XAPIC: 6036 if (flexpriority_enabled) { 6037 sec_exec_control |= 6038 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES; 6039 vmx_flush_tlb(vcpu, true); 6040 } 6041 break; 6042 case LAPIC_MODE_X2APIC: 6043 if (cpu_has_vmx_virtualize_x2apic_mode()) 6044 sec_exec_control |= 6045 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE; 6046 break; 6047 } 6048 secondary_exec_controls_set(vmx, sec_exec_control); 6049 6050 vmx_update_msr_bitmap(vcpu); 6051 } 6052 6053 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa) 6054 { 6055 if (!is_guest_mode(vcpu)) { 6056 vmcs_write64(APIC_ACCESS_ADDR, hpa); 6057 vmx_flush_tlb(vcpu, true); 6058 } 6059 } 6060 6061 static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr) 6062 { 6063 u16 status; 6064 u8 old; 6065 6066 if (max_isr == -1) 6067 max_isr = 0; 6068 6069 status = vmcs_read16(GUEST_INTR_STATUS); 6070 old = status >> 8; 6071 if (max_isr != old) { 6072 status &= 0xff; 6073 status |= max_isr << 8; 6074 vmcs_write16(GUEST_INTR_STATUS, status); 6075 } 6076 } 6077 6078 static void vmx_set_rvi(int vector) 6079 { 6080 u16 status; 6081 u8 old; 6082 6083 if (vector == -1) 6084 vector = 0; 6085 6086 status = vmcs_read16(GUEST_INTR_STATUS); 6087 old = (u8)status & 0xff; 6088 if ((u8)vector != old) { 6089 status &= ~0xff; 6090 status |= (u8)vector; 6091 vmcs_write16(GUEST_INTR_STATUS, status); 6092 } 6093 } 6094 6095 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr) 6096 { 6097 /* 6098 * When running L2, updating RVI is only relevant when 6099 * vmcs12 virtual-interrupt-delivery enabled. 6100 * However, it can be enabled only when L1 also 6101 * intercepts external-interrupts and in that case 6102 * we should not update vmcs02 RVI but instead intercept 6103 * interrupt. Therefore, do nothing when running L2. 6104 */ 6105 if (!is_guest_mode(vcpu)) 6106 vmx_set_rvi(max_irr); 6107 } 6108 6109 static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu) 6110 { 6111 struct vcpu_vmx *vmx = to_vmx(vcpu); 6112 int max_irr; 6113 bool max_irr_updated; 6114 6115 WARN_ON(!vcpu->arch.apicv_active); 6116 if (pi_test_on(&vmx->pi_desc)) { 6117 pi_clear_on(&vmx->pi_desc); 6118 /* 6119 * IOMMU can write to PID.ON, so the barrier matters even on UP. 6120 * But on x86 this is just a compiler barrier anyway. 6121 */ 6122 smp_mb__after_atomic(); 6123 max_irr_updated = 6124 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr); 6125 6126 /* 6127 * If we are running L2 and L1 has a new pending interrupt 6128 * which can be injected, we should re-evaluate 6129 * what should be done with this new L1 interrupt. 6130 * If L1 intercepts external-interrupts, we should 6131 * exit from L2 to L1. Otherwise, interrupt should be 6132 * delivered directly to L2. 6133 */ 6134 if (is_guest_mode(vcpu) && max_irr_updated) { 6135 if (nested_exit_on_intr(vcpu)) 6136 kvm_vcpu_exiting_guest_mode(vcpu); 6137 else 6138 kvm_make_request(KVM_REQ_EVENT, vcpu); 6139 } 6140 } else { 6141 max_irr = kvm_lapic_find_highest_irr(vcpu); 6142 } 6143 vmx_hwapic_irr_update(vcpu, max_irr); 6144 return max_irr; 6145 } 6146 6147 static bool vmx_dy_apicv_has_pending_interrupt(struct kvm_vcpu *vcpu) 6148 { 6149 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 6150 6151 return pi_test_on(pi_desc) || 6152 (pi_test_sn(pi_desc) && !pi_is_pir_empty(pi_desc)); 6153 } 6154 6155 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap) 6156 { 6157 if (!kvm_vcpu_apicv_active(vcpu)) 6158 return; 6159 6160 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]); 6161 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]); 6162 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]); 6163 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]); 6164 } 6165 6166 static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu) 6167 { 6168 struct vcpu_vmx *vmx = to_vmx(vcpu); 6169 6170 pi_clear_on(&vmx->pi_desc); 6171 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir)); 6172 } 6173 6174 static void handle_exception_nmi_irqoff(struct vcpu_vmx *vmx) 6175 { 6176 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6177 6178 /* if exit due to PF check for async PF */ 6179 if (is_page_fault(vmx->exit_intr_info)) 6180 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason(); 6181 6182 /* Handle machine checks before interrupts are enabled */ 6183 if (is_machine_check(vmx->exit_intr_info)) 6184 kvm_machine_check(); 6185 6186 /* We need to handle NMIs before interrupts are enabled */ 6187 if (is_nmi(vmx->exit_intr_info)) { 6188 kvm_before_interrupt(&vmx->vcpu); 6189 asm("int $2"); 6190 kvm_after_interrupt(&vmx->vcpu); 6191 } 6192 } 6193 6194 static void handle_external_interrupt_irqoff(struct kvm_vcpu *vcpu) 6195 { 6196 unsigned int vector; 6197 unsigned long entry; 6198 #ifdef CONFIG_X86_64 6199 unsigned long tmp; 6200 #endif 6201 gate_desc *desc; 6202 u32 intr_info; 6203 6204 intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6205 if (WARN_ONCE(!is_external_intr(intr_info), 6206 "KVM: unexpected VM-Exit interrupt info: 0x%x", intr_info)) 6207 return; 6208 6209 vector = intr_info & INTR_INFO_VECTOR_MASK; 6210 desc = (gate_desc *)host_idt_base + vector; 6211 entry = gate_offset(desc); 6212 6213 kvm_before_interrupt(vcpu); 6214 6215 asm volatile( 6216 #ifdef CONFIG_X86_64 6217 "mov %%" _ASM_SP ", %[sp]\n\t" 6218 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t" 6219 "push $%c[ss]\n\t" 6220 "push %[sp]\n\t" 6221 #endif 6222 "pushf\n\t" 6223 __ASM_SIZE(push) " $%c[cs]\n\t" 6224 CALL_NOSPEC 6225 : 6226 #ifdef CONFIG_X86_64 6227 [sp]"=&r"(tmp), 6228 #endif 6229 ASM_CALL_CONSTRAINT 6230 : 6231 THUNK_TARGET(entry), 6232 [ss]"i"(__KERNEL_DS), 6233 [cs]"i"(__KERNEL_CS) 6234 ); 6235 6236 kvm_after_interrupt(vcpu); 6237 } 6238 STACK_FRAME_NON_STANDARD(handle_external_interrupt_irqoff); 6239 6240 static void vmx_handle_exit_irqoff(struct kvm_vcpu *vcpu, 6241 enum exit_fastpath_completion *exit_fastpath) 6242 { 6243 struct vcpu_vmx *vmx = to_vmx(vcpu); 6244 6245 if (vmx->exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT) 6246 handle_external_interrupt_irqoff(vcpu); 6247 else if (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI) 6248 handle_exception_nmi_irqoff(vmx); 6249 else if (!is_guest_mode(vcpu) && 6250 vmx->exit_reason == EXIT_REASON_MSR_WRITE) 6251 *exit_fastpath = handle_fastpath_set_msr_irqoff(vcpu); 6252 } 6253 6254 static bool vmx_has_emulated_msr(int index) 6255 { 6256 switch (index) { 6257 case MSR_IA32_SMBASE: 6258 /* 6259 * We cannot do SMM unless we can run the guest in big 6260 * real mode. 6261 */ 6262 return enable_unrestricted_guest || emulate_invalid_guest_state; 6263 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC: 6264 return nested; 6265 case MSR_AMD64_VIRT_SPEC_CTRL: 6266 /* This is AMD only. */ 6267 return false; 6268 default: 6269 return true; 6270 } 6271 } 6272 6273 static bool vmx_pt_supported(void) 6274 { 6275 return pt_mode == PT_MODE_HOST_GUEST; 6276 } 6277 6278 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx) 6279 { 6280 u32 exit_intr_info; 6281 bool unblock_nmi; 6282 u8 vector; 6283 bool idtv_info_valid; 6284 6285 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6286 6287 if (enable_vnmi) { 6288 if (vmx->loaded_vmcs->nmi_known_unmasked) 6289 return; 6290 /* 6291 * Can't use vmx->exit_intr_info since we're not sure what 6292 * the exit reason is. 6293 */ 6294 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO); 6295 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0; 6296 vector = exit_intr_info & INTR_INFO_VECTOR_MASK; 6297 /* 6298 * SDM 3: 27.7.1.2 (September 2008) 6299 * Re-set bit "block by NMI" before VM entry if vmexit caused by 6300 * a guest IRET fault. 6301 * SDM 3: 23.2.2 (September 2008) 6302 * Bit 12 is undefined in any of the following cases: 6303 * If the VM exit sets the valid bit in the IDT-vectoring 6304 * information field. 6305 * If the VM exit is due to a double fault. 6306 */ 6307 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi && 6308 vector != DF_VECTOR && !idtv_info_valid) 6309 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, 6310 GUEST_INTR_STATE_NMI); 6311 else 6312 vmx->loaded_vmcs->nmi_known_unmasked = 6313 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) 6314 & GUEST_INTR_STATE_NMI); 6315 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked)) 6316 vmx->loaded_vmcs->vnmi_blocked_time += 6317 ktime_to_ns(ktime_sub(ktime_get(), 6318 vmx->loaded_vmcs->entry_time)); 6319 } 6320 6321 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu, 6322 u32 idt_vectoring_info, 6323 int instr_len_field, 6324 int error_code_field) 6325 { 6326 u8 vector; 6327 int type; 6328 bool idtv_info_valid; 6329 6330 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK; 6331 6332 vcpu->arch.nmi_injected = false; 6333 kvm_clear_exception_queue(vcpu); 6334 kvm_clear_interrupt_queue(vcpu); 6335 6336 if (!idtv_info_valid) 6337 return; 6338 6339 kvm_make_request(KVM_REQ_EVENT, vcpu); 6340 6341 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK; 6342 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK; 6343 6344 switch (type) { 6345 case INTR_TYPE_NMI_INTR: 6346 vcpu->arch.nmi_injected = true; 6347 /* 6348 * SDM 3: 27.7.1.2 (September 2008) 6349 * Clear bit "block by NMI" before VM entry if a NMI 6350 * delivery faulted. 6351 */ 6352 vmx_set_nmi_mask(vcpu, false); 6353 break; 6354 case INTR_TYPE_SOFT_EXCEPTION: 6355 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6356 /* fall through */ 6357 case INTR_TYPE_HARD_EXCEPTION: 6358 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) { 6359 u32 err = vmcs_read32(error_code_field); 6360 kvm_requeue_exception_e(vcpu, vector, err); 6361 } else 6362 kvm_requeue_exception(vcpu, vector); 6363 break; 6364 case INTR_TYPE_SOFT_INTR: 6365 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field); 6366 /* fall through */ 6367 case INTR_TYPE_EXT_INTR: 6368 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR); 6369 break; 6370 default: 6371 break; 6372 } 6373 } 6374 6375 static void vmx_complete_interrupts(struct vcpu_vmx *vmx) 6376 { 6377 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info, 6378 VM_EXIT_INSTRUCTION_LEN, 6379 IDT_VECTORING_ERROR_CODE); 6380 } 6381 6382 static void vmx_cancel_injection(struct kvm_vcpu *vcpu) 6383 { 6384 __vmx_complete_interrupts(vcpu, 6385 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD), 6386 VM_ENTRY_INSTRUCTION_LEN, 6387 VM_ENTRY_EXCEPTION_ERROR_CODE); 6388 6389 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); 6390 } 6391 6392 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx) 6393 { 6394 int i, nr_msrs; 6395 struct perf_guest_switch_msr *msrs; 6396 6397 msrs = perf_guest_get_msrs(&nr_msrs); 6398 6399 if (!msrs) 6400 return; 6401 6402 for (i = 0; i < nr_msrs; i++) 6403 if (msrs[i].host == msrs[i].guest) 6404 clear_atomic_switch_msr(vmx, msrs[i].msr); 6405 else 6406 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest, 6407 msrs[i].host, false); 6408 } 6409 6410 static void atomic_switch_umwait_control_msr(struct vcpu_vmx *vmx) 6411 { 6412 u32 host_umwait_control; 6413 6414 if (!vmx_has_waitpkg(vmx)) 6415 return; 6416 6417 host_umwait_control = get_umwait_control_msr(); 6418 6419 if (vmx->msr_ia32_umwait_control != host_umwait_control) 6420 add_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL, 6421 vmx->msr_ia32_umwait_control, 6422 host_umwait_control, false); 6423 else 6424 clear_atomic_switch_msr(vmx, MSR_IA32_UMWAIT_CONTROL); 6425 } 6426 6427 static void vmx_update_hv_timer(struct kvm_vcpu *vcpu) 6428 { 6429 struct vcpu_vmx *vmx = to_vmx(vcpu); 6430 u64 tscl; 6431 u32 delta_tsc; 6432 6433 if (vmx->req_immediate_exit) { 6434 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, 0); 6435 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6436 } else if (vmx->hv_deadline_tsc != -1) { 6437 tscl = rdtsc(); 6438 if (vmx->hv_deadline_tsc > tscl) 6439 /* set_hv_timer ensures the delta fits in 32-bits */ 6440 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >> 6441 cpu_preemption_timer_multi); 6442 else 6443 delta_tsc = 0; 6444 6445 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, delta_tsc); 6446 vmx->loaded_vmcs->hv_timer_soft_disabled = false; 6447 } else if (!vmx->loaded_vmcs->hv_timer_soft_disabled) { 6448 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, -1); 6449 vmx->loaded_vmcs->hv_timer_soft_disabled = true; 6450 } 6451 } 6452 6453 void vmx_update_host_rsp(struct vcpu_vmx *vmx, unsigned long host_rsp) 6454 { 6455 if (unlikely(host_rsp != vmx->loaded_vmcs->host_state.rsp)) { 6456 vmx->loaded_vmcs->host_state.rsp = host_rsp; 6457 vmcs_writel(HOST_RSP, host_rsp); 6458 } 6459 } 6460 6461 bool __vmx_vcpu_run(struct vcpu_vmx *vmx, unsigned long *regs, bool launched); 6462 6463 static void vmx_vcpu_run(struct kvm_vcpu *vcpu) 6464 { 6465 struct vcpu_vmx *vmx = to_vmx(vcpu); 6466 unsigned long cr3, cr4; 6467 6468 /* Record the guest's net vcpu time for enforced NMI injections. */ 6469 if (unlikely(!enable_vnmi && 6470 vmx->loaded_vmcs->soft_vnmi_blocked)) 6471 vmx->loaded_vmcs->entry_time = ktime_get(); 6472 6473 /* Don't enter VMX if guest state is invalid, let the exit handler 6474 start emulation until we arrive back to a valid state */ 6475 if (vmx->emulation_required) 6476 return; 6477 6478 if (vmx->ple_window_dirty) { 6479 vmx->ple_window_dirty = false; 6480 vmcs_write32(PLE_WINDOW, vmx->ple_window); 6481 } 6482 6483 if (vmx->nested.need_vmcs12_to_shadow_sync) 6484 nested_sync_vmcs12_to_shadow(vcpu); 6485 6486 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RSP)) 6487 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]); 6488 if (kvm_register_is_dirty(vcpu, VCPU_REGS_RIP)) 6489 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]); 6490 6491 cr3 = __get_current_cr3_fast(); 6492 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) { 6493 vmcs_writel(HOST_CR3, cr3); 6494 vmx->loaded_vmcs->host_state.cr3 = cr3; 6495 } 6496 6497 cr4 = cr4_read_shadow(); 6498 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) { 6499 vmcs_writel(HOST_CR4, cr4); 6500 vmx->loaded_vmcs->host_state.cr4 = cr4; 6501 } 6502 6503 /* When single-stepping over STI and MOV SS, we must clear the 6504 * corresponding interruptibility bits in the guest state. Otherwise 6505 * vmentry fails as it then expects bit 14 (BS) in pending debug 6506 * exceptions being set, but that's not correct for the guest debugging 6507 * case. */ 6508 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) 6509 vmx_set_interrupt_shadow(vcpu, 0); 6510 6511 kvm_load_guest_xsave_state(vcpu); 6512 6513 if (static_cpu_has(X86_FEATURE_PKU) && 6514 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) && 6515 vcpu->arch.pkru != vmx->host_pkru) 6516 __write_pkru(vcpu->arch.pkru); 6517 6518 pt_guest_enter(vmx); 6519 6520 atomic_switch_perf_msrs(vmx); 6521 atomic_switch_umwait_control_msr(vmx); 6522 6523 if (enable_preemption_timer) 6524 vmx_update_hv_timer(vcpu); 6525 6526 if (lapic_in_kernel(vcpu) && 6527 vcpu->arch.apic->lapic_timer.timer_advance_ns) 6528 kvm_wait_lapic_expire(vcpu); 6529 6530 /* 6531 * If this vCPU has touched SPEC_CTRL, restore the guest's value if 6532 * it's non-zero. Since vmentry is serialising on affected CPUs, there 6533 * is no need to worry about the conditional branch over the wrmsr 6534 * being speculatively taken. 6535 */ 6536 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0); 6537 6538 /* L1D Flush includes CPU buffer clear to mitigate MDS */ 6539 if (static_branch_unlikely(&vmx_l1d_should_flush)) 6540 vmx_l1d_flush(vcpu); 6541 else if (static_branch_unlikely(&mds_user_clear)) 6542 mds_clear_cpu_buffers(); 6543 6544 if (vcpu->arch.cr2 != read_cr2()) 6545 write_cr2(vcpu->arch.cr2); 6546 6547 vmx->fail = __vmx_vcpu_run(vmx, (unsigned long *)&vcpu->arch.regs, 6548 vmx->loaded_vmcs->launched); 6549 6550 vcpu->arch.cr2 = read_cr2(); 6551 6552 /* 6553 * We do not use IBRS in the kernel. If this vCPU has used the 6554 * SPEC_CTRL MSR it may have left it on; save the value and 6555 * turn it off. This is much more efficient than blindly adding 6556 * it to the atomic save/restore list. Especially as the former 6557 * (Saving guest MSRs on vmexit) doesn't even exist in KVM. 6558 * 6559 * For non-nested case: 6560 * If the L01 MSR bitmap does not intercept the MSR, then we need to 6561 * save it. 6562 * 6563 * For nested case: 6564 * If the L02 MSR bitmap does not intercept the MSR, then we need to 6565 * save it. 6566 */ 6567 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL))) 6568 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL); 6569 6570 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0); 6571 6572 /* All fields are clean at this point */ 6573 if (static_branch_unlikely(&enable_evmcs)) 6574 current_evmcs->hv_clean_fields |= 6575 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL; 6576 6577 if (static_branch_unlikely(&enable_evmcs)) 6578 current_evmcs->hv_vp_id = vcpu->arch.hyperv.vp_index; 6579 6580 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */ 6581 if (vmx->host_debugctlmsr) 6582 update_debugctlmsr(vmx->host_debugctlmsr); 6583 6584 #ifndef CONFIG_X86_64 6585 /* 6586 * The sysexit path does not restore ds/es, so we must set them to 6587 * a reasonable value ourselves. 6588 * 6589 * We can't defer this to vmx_prepare_switch_to_host() since that 6590 * function may be executed in interrupt context, which saves and 6591 * restore segments around it, nullifying its effect. 6592 */ 6593 loadsegment(ds, __USER_DS); 6594 loadsegment(es, __USER_DS); 6595 #endif 6596 6597 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP) 6598 | (1 << VCPU_EXREG_RFLAGS) 6599 | (1 << VCPU_EXREG_PDPTR) 6600 | (1 << VCPU_EXREG_SEGMENTS) 6601 | (1 << VCPU_EXREG_CR3)); 6602 vcpu->arch.regs_dirty = 0; 6603 6604 pt_guest_exit(vmx); 6605 6606 /* 6607 * eager fpu is enabled if PKEY is supported and CR4 is switched 6608 * back on host, so it is safe to read guest PKRU from current 6609 * XSAVE. 6610 */ 6611 if (static_cpu_has(X86_FEATURE_PKU) && 6612 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) { 6613 vcpu->arch.pkru = rdpkru(); 6614 if (vcpu->arch.pkru != vmx->host_pkru) 6615 __write_pkru(vmx->host_pkru); 6616 } 6617 6618 kvm_load_host_xsave_state(vcpu); 6619 6620 vmx->nested.nested_run_pending = 0; 6621 vmx->idt_vectoring_info = 0; 6622 6623 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON); 6624 if ((u16)vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY) 6625 kvm_machine_check(); 6626 6627 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) 6628 return; 6629 6630 vmx->loaded_vmcs->launched = 1; 6631 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD); 6632 6633 vmx_recover_nmi_blocking(vmx); 6634 vmx_complete_interrupts(vmx); 6635 } 6636 6637 static struct kvm *vmx_vm_alloc(void) 6638 { 6639 struct kvm_vmx *kvm_vmx = __vmalloc(sizeof(struct kvm_vmx), 6640 GFP_KERNEL_ACCOUNT | __GFP_ZERO, 6641 PAGE_KERNEL); 6642 return &kvm_vmx->kvm; 6643 } 6644 6645 static void vmx_vm_free(struct kvm *kvm) 6646 { 6647 kfree(kvm->arch.hyperv.hv_pa_pg); 6648 vfree(to_kvm_vmx(kvm)); 6649 } 6650 6651 static void vmx_free_vcpu(struct kvm_vcpu *vcpu) 6652 { 6653 struct vcpu_vmx *vmx = to_vmx(vcpu); 6654 6655 if (enable_pml) 6656 vmx_destroy_pml_buffer(vmx); 6657 free_vpid(vmx->vpid); 6658 nested_vmx_free_vcpu(vcpu); 6659 free_loaded_vmcs(vmx->loaded_vmcs); 6660 } 6661 6662 static int vmx_create_vcpu(struct kvm_vcpu *vcpu) 6663 { 6664 struct vcpu_vmx *vmx; 6665 unsigned long *msr_bitmap; 6666 int i, cpu, err; 6667 6668 BUILD_BUG_ON(offsetof(struct vcpu_vmx, vcpu) != 0); 6669 vmx = to_vmx(vcpu); 6670 6671 err = -ENOMEM; 6672 6673 vmx->vpid = allocate_vpid(); 6674 6675 /* 6676 * If PML is turned on, failure on enabling PML just results in failure 6677 * of creating the vcpu, therefore we can simplify PML logic (by 6678 * avoiding dealing with cases, such as enabling PML partially on vcpus 6679 * for the guest), etc. 6680 */ 6681 if (enable_pml) { 6682 vmx->pml_pg = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO); 6683 if (!vmx->pml_pg) 6684 goto free_vpid; 6685 } 6686 6687 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) != NR_SHARED_MSRS); 6688 6689 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) { 6690 u32 index = vmx_msr_index[i]; 6691 u32 data_low, data_high; 6692 int j = vmx->nmsrs; 6693 6694 if (rdmsr_safe(index, &data_low, &data_high) < 0) 6695 continue; 6696 if (wrmsr_safe(index, data_low, data_high) < 0) 6697 continue; 6698 6699 vmx->guest_msrs[j].index = i; 6700 vmx->guest_msrs[j].data = 0; 6701 switch (index) { 6702 case MSR_IA32_TSX_CTRL: 6703 /* 6704 * No need to pass TSX_CTRL_CPUID_CLEAR through, so 6705 * let's avoid changing CPUID bits under the host 6706 * kernel's feet. 6707 */ 6708 vmx->guest_msrs[j].mask = ~(u64)TSX_CTRL_CPUID_CLEAR; 6709 break; 6710 default: 6711 vmx->guest_msrs[j].mask = -1ull; 6712 break; 6713 } 6714 ++vmx->nmsrs; 6715 } 6716 6717 err = alloc_loaded_vmcs(&vmx->vmcs01); 6718 if (err < 0) 6719 goto free_pml; 6720 6721 msr_bitmap = vmx->vmcs01.msr_bitmap; 6722 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_TSC, MSR_TYPE_R); 6723 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW); 6724 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW); 6725 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW); 6726 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW); 6727 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW); 6728 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW); 6729 if (kvm_cstate_in_guest(vcpu->kvm)) { 6730 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C1_RES, MSR_TYPE_R); 6731 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C3_RESIDENCY, MSR_TYPE_R); 6732 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C6_RESIDENCY, MSR_TYPE_R); 6733 vmx_disable_intercept_for_msr(msr_bitmap, MSR_CORE_C7_RESIDENCY, MSR_TYPE_R); 6734 } 6735 vmx->msr_bitmap_mode = 0; 6736 6737 vmx->loaded_vmcs = &vmx->vmcs01; 6738 cpu = get_cpu(); 6739 vmx_vcpu_load(vcpu, cpu); 6740 vcpu->cpu = cpu; 6741 init_vmcs(vmx); 6742 vmx_vcpu_put(vcpu); 6743 put_cpu(); 6744 if (cpu_need_virtualize_apic_accesses(vcpu)) { 6745 err = alloc_apic_access_page(vcpu->kvm); 6746 if (err) 6747 goto free_vmcs; 6748 } 6749 6750 if (enable_ept && !enable_unrestricted_guest) { 6751 err = init_rmode_identity_map(vcpu->kvm); 6752 if (err) 6753 goto free_vmcs; 6754 } 6755 6756 if (nested) 6757 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs, 6758 vmx_capability.ept, 6759 kvm_vcpu_apicv_active(vcpu)); 6760 else 6761 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs)); 6762 6763 vmx->nested.posted_intr_nv = -1; 6764 vmx->nested.current_vmptr = -1ull; 6765 6766 vmx->msr_ia32_feature_control_valid_bits = FEAT_CTL_LOCKED; 6767 6768 /* 6769 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR 6770 * or POSTED_INTR_WAKEUP_VECTOR. 6771 */ 6772 vmx->pi_desc.nv = POSTED_INTR_VECTOR; 6773 vmx->pi_desc.sn = 1; 6774 6775 vmx->ept_pointer = INVALID_PAGE; 6776 6777 return 0; 6778 6779 free_vmcs: 6780 free_loaded_vmcs(vmx->loaded_vmcs); 6781 free_pml: 6782 vmx_destroy_pml_buffer(vmx); 6783 free_vpid: 6784 free_vpid(vmx->vpid); 6785 return err; 6786 } 6787 6788 #define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6789 #define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/hw-vuln/l1tf.html for details.\n" 6790 6791 static int vmx_vm_init(struct kvm *kvm) 6792 { 6793 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock); 6794 6795 if (!ple_gap) 6796 kvm->arch.pause_in_guest = true; 6797 6798 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) { 6799 switch (l1tf_mitigation) { 6800 case L1TF_MITIGATION_OFF: 6801 case L1TF_MITIGATION_FLUSH_NOWARN: 6802 /* 'I explicitly don't care' is set */ 6803 break; 6804 case L1TF_MITIGATION_FLUSH: 6805 case L1TF_MITIGATION_FLUSH_NOSMT: 6806 case L1TF_MITIGATION_FULL: 6807 /* 6808 * Warn upon starting the first VM in a potentially 6809 * insecure environment. 6810 */ 6811 if (sched_smt_active()) 6812 pr_warn_once(L1TF_MSG_SMT); 6813 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER) 6814 pr_warn_once(L1TF_MSG_L1D); 6815 break; 6816 case L1TF_MITIGATION_FULL_FORCE: 6817 /* Flush is enforced */ 6818 break; 6819 } 6820 } 6821 kvm_apicv_init(kvm, enable_apicv); 6822 return 0; 6823 } 6824 6825 static int __init vmx_check_processor_compat(void) 6826 { 6827 struct vmcs_config vmcs_conf; 6828 struct vmx_capability vmx_cap; 6829 6830 if (!this_cpu_has(X86_FEATURE_MSR_IA32_FEAT_CTL) || 6831 !this_cpu_has(X86_FEATURE_VMX)) { 6832 pr_err("kvm: VMX is disabled on CPU %d\n", smp_processor_id()); 6833 return -EIO; 6834 } 6835 6836 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0) 6837 return -EIO; 6838 if (nested) 6839 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept, 6840 enable_apicv); 6841 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) { 6842 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n", 6843 smp_processor_id()); 6844 return -EIO; 6845 } 6846 return 0; 6847 } 6848 6849 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio) 6850 { 6851 u8 cache; 6852 u64 ipat = 0; 6853 6854 /* For VT-d and EPT combination 6855 * 1. MMIO: always map as UC 6856 * 2. EPT with VT-d: 6857 * a. VT-d without snooping control feature: can't guarantee the 6858 * result, try to trust guest. 6859 * b. VT-d with snooping control feature: snooping control feature of 6860 * VT-d engine can guarantee the cache correctness. Just set it 6861 * to WB to keep consistent with host. So the same as item 3. 6862 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep 6863 * consistent with host MTRR 6864 */ 6865 if (is_mmio) { 6866 cache = MTRR_TYPE_UNCACHABLE; 6867 goto exit; 6868 } 6869 6870 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) { 6871 ipat = VMX_EPT_IPAT_BIT; 6872 cache = MTRR_TYPE_WRBACK; 6873 goto exit; 6874 } 6875 6876 if (kvm_read_cr0(vcpu) & X86_CR0_CD) { 6877 ipat = VMX_EPT_IPAT_BIT; 6878 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED)) 6879 cache = MTRR_TYPE_WRBACK; 6880 else 6881 cache = MTRR_TYPE_UNCACHABLE; 6882 goto exit; 6883 } 6884 6885 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn); 6886 6887 exit: 6888 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat; 6889 } 6890 6891 static int vmx_get_lpage_level(void) 6892 { 6893 if (enable_ept && !cpu_has_vmx_ept_1g_page()) 6894 return PT_DIRECTORY_LEVEL; 6895 else 6896 /* For shadow and EPT supported 1GB page */ 6897 return PT_PDPE_LEVEL; 6898 } 6899 6900 static void vmcs_set_secondary_exec_control(struct vcpu_vmx *vmx) 6901 { 6902 /* 6903 * These bits in the secondary execution controls field 6904 * are dynamic, the others are mostly based on the hypervisor 6905 * architecture and the guest's CPUID. Do not touch the 6906 * dynamic bits. 6907 */ 6908 u32 mask = 6909 SECONDARY_EXEC_SHADOW_VMCS | 6910 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | 6911 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | 6912 SECONDARY_EXEC_DESC; 6913 6914 u32 new_ctl = vmx->secondary_exec_control; 6915 u32 cur_ctl = secondary_exec_controls_get(vmx); 6916 6917 secondary_exec_controls_set(vmx, (new_ctl & ~mask) | (cur_ctl & mask)); 6918 } 6919 6920 /* 6921 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits 6922 * (indicating "allowed-1") if they are supported in the guest's CPUID. 6923 */ 6924 static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu) 6925 { 6926 struct vcpu_vmx *vmx = to_vmx(vcpu); 6927 struct kvm_cpuid_entry2 *entry; 6928 6929 vmx->nested.msrs.cr0_fixed1 = 0xffffffff; 6930 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE; 6931 6932 #define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \ 6933 if (entry && (entry->_reg & (_cpuid_mask))) \ 6934 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \ 6935 } while (0) 6936 6937 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0); 6938 cr4_fixed1_update(X86_CR4_VME, edx, feature_bit(VME)); 6939 cr4_fixed1_update(X86_CR4_PVI, edx, feature_bit(VME)); 6940 cr4_fixed1_update(X86_CR4_TSD, edx, feature_bit(TSC)); 6941 cr4_fixed1_update(X86_CR4_DE, edx, feature_bit(DE)); 6942 cr4_fixed1_update(X86_CR4_PSE, edx, feature_bit(PSE)); 6943 cr4_fixed1_update(X86_CR4_PAE, edx, feature_bit(PAE)); 6944 cr4_fixed1_update(X86_CR4_MCE, edx, feature_bit(MCE)); 6945 cr4_fixed1_update(X86_CR4_PGE, edx, feature_bit(PGE)); 6946 cr4_fixed1_update(X86_CR4_OSFXSR, edx, feature_bit(FXSR)); 6947 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, feature_bit(XMM)); 6948 cr4_fixed1_update(X86_CR4_VMXE, ecx, feature_bit(VMX)); 6949 cr4_fixed1_update(X86_CR4_SMXE, ecx, feature_bit(SMX)); 6950 cr4_fixed1_update(X86_CR4_PCIDE, ecx, feature_bit(PCID)); 6951 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, feature_bit(XSAVE)); 6952 6953 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0); 6954 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, feature_bit(FSGSBASE)); 6955 cr4_fixed1_update(X86_CR4_SMEP, ebx, feature_bit(SMEP)); 6956 cr4_fixed1_update(X86_CR4_SMAP, ebx, feature_bit(SMAP)); 6957 cr4_fixed1_update(X86_CR4_PKE, ecx, feature_bit(PKU)); 6958 cr4_fixed1_update(X86_CR4_UMIP, ecx, feature_bit(UMIP)); 6959 cr4_fixed1_update(X86_CR4_LA57, ecx, feature_bit(LA57)); 6960 6961 #undef cr4_fixed1_update 6962 } 6963 6964 static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu) 6965 { 6966 struct vcpu_vmx *vmx = to_vmx(vcpu); 6967 6968 if (kvm_mpx_supported()) { 6969 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX); 6970 6971 if (mpx_enabled) { 6972 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS; 6973 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS; 6974 } else { 6975 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS; 6976 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS; 6977 } 6978 } 6979 } 6980 6981 static void update_intel_pt_cfg(struct kvm_vcpu *vcpu) 6982 { 6983 struct vcpu_vmx *vmx = to_vmx(vcpu); 6984 struct kvm_cpuid_entry2 *best = NULL; 6985 int i; 6986 6987 for (i = 0; i < PT_CPUID_LEAVES; i++) { 6988 best = kvm_find_cpuid_entry(vcpu, 0x14, i); 6989 if (!best) 6990 return; 6991 vmx->pt_desc.caps[CPUID_EAX + i*PT_CPUID_REGS_NUM] = best->eax; 6992 vmx->pt_desc.caps[CPUID_EBX + i*PT_CPUID_REGS_NUM] = best->ebx; 6993 vmx->pt_desc.caps[CPUID_ECX + i*PT_CPUID_REGS_NUM] = best->ecx; 6994 vmx->pt_desc.caps[CPUID_EDX + i*PT_CPUID_REGS_NUM] = best->edx; 6995 } 6996 6997 /* Get the number of configurable Address Ranges for filtering */ 6998 vmx->pt_desc.addr_range = intel_pt_validate_cap(vmx->pt_desc.caps, 6999 PT_CAP_num_address_ranges); 7000 7001 /* Initialize and clear the no dependency bits */ 7002 vmx->pt_desc.ctl_bitmask = ~(RTIT_CTL_TRACEEN | RTIT_CTL_OS | 7003 RTIT_CTL_USR | RTIT_CTL_TSC_EN | RTIT_CTL_DISRETC); 7004 7005 /* 7006 * If CPUID.(EAX=14H,ECX=0):EBX[0]=1 CR3Filter can be set otherwise 7007 * will inject an #GP 7008 */ 7009 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_cr3_filtering)) 7010 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_CR3EN; 7011 7012 /* 7013 * If CPUID.(EAX=14H,ECX=0):EBX[1]=1 CYCEn, CycThresh and 7014 * PSBFreq can be set 7015 */ 7016 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_psb_cyc)) 7017 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_CYCLEACC | 7018 RTIT_CTL_CYC_THRESH | RTIT_CTL_PSB_FREQ); 7019 7020 /* 7021 * If CPUID.(EAX=14H,ECX=0):EBX[3]=1 MTCEn BranchEn and 7022 * MTCFreq can be set 7023 */ 7024 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_mtc)) 7025 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_MTC_EN | 7026 RTIT_CTL_BRANCH_EN | RTIT_CTL_MTC_RANGE); 7027 7028 /* If CPUID.(EAX=14H,ECX=0):EBX[4]=1 FUPonPTW and PTWEn can be set */ 7029 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_ptwrite)) 7030 vmx->pt_desc.ctl_bitmask &= ~(RTIT_CTL_FUP_ON_PTW | 7031 RTIT_CTL_PTW_EN); 7032 7033 /* If CPUID.(EAX=14H,ECX=0):EBX[5]=1 PwrEvEn can be set */ 7034 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_power_event_trace)) 7035 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_PWR_EVT_EN; 7036 7037 /* If CPUID.(EAX=14H,ECX=0):ECX[0]=1 ToPA can be set */ 7038 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_topa_output)) 7039 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_TOPA; 7040 7041 /* If CPUID.(EAX=14H,ECX=0):ECX[3]=1 FabircEn can be set */ 7042 if (intel_pt_validate_cap(vmx->pt_desc.caps, PT_CAP_output_subsys)) 7043 vmx->pt_desc.ctl_bitmask &= ~RTIT_CTL_FABRIC_EN; 7044 7045 /* unmask address range configure area */ 7046 for (i = 0; i < vmx->pt_desc.addr_range; i++) 7047 vmx->pt_desc.ctl_bitmask &= ~(0xfULL << (32 + i * 4)); 7048 } 7049 7050 static void vmx_cpuid_update(struct kvm_vcpu *vcpu) 7051 { 7052 struct vcpu_vmx *vmx = to_vmx(vcpu); 7053 7054 /* xsaves_enabled is recomputed in vmx_compute_secondary_exec_control(). */ 7055 vcpu->arch.xsaves_enabled = false; 7056 7057 if (cpu_has_secondary_exec_ctrls()) { 7058 vmx_compute_secondary_exec_control(vmx); 7059 vmcs_set_secondary_exec_control(vmx); 7060 } 7061 7062 if (nested_vmx_allowed(vcpu)) 7063 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7064 FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7065 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX; 7066 else 7067 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7068 ~(FEAT_CTL_VMX_ENABLED_INSIDE_SMX | 7069 FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX); 7070 7071 if (nested_vmx_allowed(vcpu)) { 7072 nested_vmx_cr_fixed1_bits_update(vcpu); 7073 nested_vmx_entry_exit_ctls_update(vcpu); 7074 } 7075 7076 if (boot_cpu_has(X86_FEATURE_INTEL_PT) && 7077 guest_cpuid_has(vcpu, X86_FEATURE_INTEL_PT)) 7078 update_intel_pt_cfg(vcpu); 7079 7080 if (boot_cpu_has(X86_FEATURE_RTM)) { 7081 struct shared_msr_entry *msr; 7082 msr = find_msr_entry(vmx, MSR_IA32_TSX_CTRL); 7083 if (msr) { 7084 bool enabled = guest_cpuid_has(vcpu, X86_FEATURE_RTM); 7085 vmx_set_guest_msr(vmx, msr, enabled ? 0 : TSX_CTRL_RTM_DISABLE); 7086 } 7087 } 7088 } 7089 7090 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry) 7091 { 7092 if (func == 1 && nested) 7093 entry->ecx |= feature_bit(VMX); 7094 } 7095 7096 static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu) 7097 { 7098 to_vmx(vcpu)->req_immediate_exit = true; 7099 } 7100 7101 static int vmx_check_intercept(struct kvm_vcpu *vcpu, 7102 struct x86_instruction_info *info, 7103 enum x86_intercept_stage stage) 7104 { 7105 struct vmcs12 *vmcs12 = get_vmcs12(vcpu); 7106 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt; 7107 7108 /* 7109 * RDPID causes #UD if disabled through secondary execution controls. 7110 * Because it is marked as EmulateOnUD, we need to intercept it here. 7111 */ 7112 if (info->intercept == x86_intercept_rdtscp && 7113 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) { 7114 ctxt->exception.vector = UD_VECTOR; 7115 ctxt->exception.error_code_valid = false; 7116 return X86EMUL_PROPAGATE_FAULT; 7117 } 7118 7119 /* TODO: check more intercepts... */ 7120 return X86EMUL_CONTINUE; 7121 } 7122 7123 #ifdef CONFIG_X86_64 7124 /* (a << shift) / divisor, return 1 if overflow otherwise 0 */ 7125 static inline int u64_shl_div_u64(u64 a, unsigned int shift, 7126 u64 divisor, u64 *result) 7127 { 7128 u64 low = a << shift, high = a >> (64 - shift); 7129 7130 /* To avoid the overflow on divq */ 7131 if (high >= divisor) 7132 return 1; 7133 7134 /* Low hold the result, high hold rem which is discarded */ 7135 asm("divq %2\n\t" : "=a" (low), "=d" (high) : 7136 "rm" (divisor), "0" (low), "1" (high)); 7137 *result = low; 7138 7139 return 0; 7140 } 7141 7142 static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc, 7143 bool *expired) 7144 { 7145 struct vcpu_vmx *vmx; 7146 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles; 7147 struct kvm_timer *ktimer = &vcpu->arch.apic->lapic_timer; 7148 7149 if (kvm_mwait_in_guest(vcpu->kvm) || 7150 kvm_can_post_timer_interrupt(vcpu)) 7151 return -EOPNOTSUPP; 7152 7153 vmx = to_vmx(vcpu); 7154 tscl = rdtsc(); 7155 guest_tscl = kvm_read_l1_tsc(vcpu, tscl); 7156 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl; 7157 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, 7158 ktimer->timer_advance_ns); 7159 7160 if (delta_tsc > lapic_timer_advance_cycles) 7161 delta_tsc -= lapic_timer_advance_cycles; 7162 else 7163 delta_tsc = 0; 7164 7165 /* Convert to host delta tsc if tsc scaling is enabled */ 7166 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio && 7167 delta_tsc && u64_shl_div_u64(delta_tsc, 7168 kvm_tsc_scaling_ratio_frac_bits, 7169 vcpu->arch.tsc_scaling_ratio, &delta_tsc)) 7170 return -ERANGE; 7171 7172 /* 7173 * If the delta tsc can't fit in the 32 bit after the multi shift, 7174 * we can't use the preemption timer. 7175 * It's possible that it fits on later vmentries, but checking 7176 * on every vmentry is costly so we just use an hrtimer. 7177 */ 7178 if (delta_tsc >> (cpu_preemption_timer_multi + 32)) 7179 return -ERANGE; 7180 7181 vmx->hv_deadline_tsc = tscl + delta_tsc; 7182 *expired = !delta_tsc; 7183 return 0; 7184 } 7185 7186 static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu) 7187 { 7188 to_vmx(vcpu)->hv_deadline_tsc = -1; 7189 } 7190 #endif 7191 7192 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu) 7193 { 7194 if (!kvm_pause_in_guest(vcpu->kvm)) 7195 shrink_ple_window(vcpu); 7196 } 7197 7198 static void vmx_slot_enable_log_dirty(struct kvm *kvm, 7199 struct kvm_memory_slot *slot) 7200 { 7201 kvm_mmu_slot_leaf_clear_dirty(kvm, slot); 7202 kvm_mmu_slot_largepage_remove_write_access(kvm, slot); 7203 } 7204 7205 static void vmx_slot_disable_log_dirty(struct kvm *kvm, 7206 struct kvm_memory_slot *slot) 7207 { 7208 kvm_mmu_slot_set_dirty(kvm, slot); 7209 } 7210 7211 static void vmx_flush_log_dirty(struct kvm *kvm) 7212 { 7213 kvm_flush_pml_buffers(kvm); 7214 } 7215 7216 static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu) 7217 { 7218 struct vmcs12 *vmcs12; 7219 struct vcpu_vmx *vmx = to_vmx(vcpu); 7220 gpa_t gpa, dst; 7221 7222 if (is_guest_mode(vcpu)) { 7223 WARN_ON_ONCE(vmx->nested.pml_full); 7224 7225 /* 7226 * Check if PML is enabled for the nested guest. 7227 * Whether eptp bit 6 is set is already checked 7228 * as part of A/D emulation. 7229 */ 7230 vmcs12 = get_vmcs12(vcpu); 7231 if (!nested_cpu_has_pml(vmcs12)) 7232 return 0; 7233 7234 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) { 7235 vmx->nested.pml_full = true; 7236 return 1; 7237 } 7238 7239 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull; 7240 dst = vmcs12->pml_address + sizeof(u64) * vmcs12->guest_pml_index; 7241 7242 if (kvm_write_guest_page(vcpu->kvm, gpa_to_gfn(dst), &gpa, 7243 offset_in_page(dst), sizeof(gpa))) 7244 return 0; 7245 7246 vmcs12->guest_pml_index--; 7247 } 7248 7249 return 0; 7250 } 7251 7252 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm, 7253 struct kvm_memory_slot *memslot, 7254 gfn_t offset, unsigned long mask) 7255 { 7256 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask); 7257 } 7258 7259 static void __pi_post_block(struct kvm_vcpu *vcpu) 7260 { 7261 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7262 struct pi_desc old, new; 7263 unsigned int dest; 7264 7265 do { 7266 old.control = new.control = pi_desc->control; 7267 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR, 7268 "Wakeup handler not enabled while the VCPU is blocked\n"); 7269 7270 dest = cpu_physical_id(vcpu->cpu); 7271 7272 if (x2apic_enabled()) 7273 new.ndst = dest; 7274 else 7275 new.ndst = (dest << 8) & 0xFF00; 7276 7277 /* set 'NV' to 'notification vector' */ 7278 new.nv = POSTED_INTR_VECTOR; 7279 } while (cmpxchg64(&pi_desc->control, old.control, 7280 new.control) != old.control); 7281 7282 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) { 7283 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7284 list_del(&vcpu->blocked_vcpu_list); 7285 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7286 vcpu->pre_pcpu = -1; 7287 } 7288 } 7289 7290 /* 7291 * This routine does the following things for vCPU which is going 7292 * to be blocked if VT-d PI is enabled. 7293 * - Store the vCPU to the wakeup list, so when interrupts happen 7294 * we can find the right vCPU to wake up. 7295 * - Change the Posted-interrupt descriptor as below: 7296 * 'NDST' <-- vcpu->pre_pcpu 7297 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR 7298 * - If 'ON' is set during this process, which means at least one 7299 * interrupt is posted for this vCPU, we cannot block it, in 7300 * this case, return 1, otherwise, return 0. 7301 * 7302 */ 7303 static int pi_pre_block(struct kvm_vcpu *vcpu) 7304 { 7305 unsigned int dest; 7306 struct pi_desc old, new; 7307 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu); 7308 7309 if (!kvm_arch_has_assigned_device(vcpu->kvm) || 7310 !irq_remapping_cap(IRQ_POSTING_CAP) || 7311 !kvm_vcpu_apicv_active(vcpu)) 7312 return 0; 7313 7314 WARN_ON(irqs_disabled()); 7315 local_irq_disable(); 7316 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) { 7317 vcpu->pre_pcpu = vcpu->cpu; 7318 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7319 list_add_tail(&vcpu->blocked_vcpu_list, 7320 &per_cpu(blocked_vcpu_on_cpu, 7321 vcpu->pre_pcpu)); 7322 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu)); 7323 } 7324 7325 do { 7326 old.control = new.control = pi_desc->control; 7327 7328 WARN((pi_desc->sn == 1), 7329 "Warning: SN field of posted-interrupts " 7330 "is set before blocking\n"); 7331 7332 /* 7333 * Since vCPU can be preempted during this process, 7334 * vcpu->cpu could be different with pre_pcpu, we 7335 * need to set pre_pcpu as the destination of wakeup 7336 * notification event, then we can find the right vCPU 7337 * to wakeup in wakeup handler if interrupts happen 7338 * when the vCPU is in blocked state. 7339 */ 7340 dest = cpu_physical_id(vcpu->pre_pcpu); 7341 7342 if (x2apic_enabled()) 7343 new.ndst = dest; 7344 else 7345 new.ndst = (dest << 8) & 0xFF00; 7346 7347 /* set 'NV' to 'wakeup vector' */ 7348 new.nv = POSTED_INTR_WAKEUP_VECTOR; 7349 } while (cmpxchg64(&pi_desc->control, old.control, 7350 new.control) != old.control); 7351 7352 /* We should not block the vCPU if an interrupt is posted for it. */ 7353 if (pi_test_on(pi_desc) == 1) 7354 __pi_post_block(vcpu); 7355 7356 local_irq_enable(); 7357 return (vcpu->pre_pcpu == -1); 7358 } 7359 7360 static int vmx_pre_block(struct kvm_vcpu *vcpu) 7361 { 7362 if (pi_pre_block(vcpu)) 7363 return 1; 7364 7365 if (kvm_lapic_hv_timer_in_use(vcpu)) 7366 kvm_lapic_switch_to_sw_timer(vcpu); 7367 7368 return 0; 7369 } 7370 7371 static void pi_post_block(struct kvm_vcpu *vcpu) 7372 { 7373 if (vcpu->pre_pcpu == -1) 7374 return; 7375 7376 WARN_ON(irqs_disabled()); 7377 local_irq_disable(); 7378 __pi_post_block(vcpu); 7379 local_irq_enable(); 7380 } 7381 7382 static void vmx_post_block(struct kvm_vcpu *vcpu) 7383 { 7384 if (kvm_x86_ops->set_hv_timer) 7385 kvm_lapic_switch_to_hv_timer(vcpu); 7386 7387 pi_post_block(vcpu); 7388 } 7389 7390 /* 7391 * vmx_update_pi_irte - set IRTE for Posted-Interrupts 7392 * 7393 * @kvm: kvm 7394 * @host_irq: host irq of the interrupt 7395 * @guest_irq: gsi of the interrupt 7396 * @set: set or unset PI 7397 * returns 0 on success, < 0 on failure 7398 */ 7399 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq, 7400 uint32_t guest_irq, bool set) 7401 { 7402 struct kvm_kernel_irq_routing_entry *e; 7403 struct kvm_irq_routing_table *irq_rt; 7404 struct kvm_lapic_irq irq; 7405 struct kvm_vcpu *vcpu; 7406 struct vcpu_data vcpu_info; 7407 int idx, ret = 0; 7408 7409 if (!kvm_arch_has_assigned_device(kvm) || 7410 !irq_remapping_cap(IRQ_POSTING_CAP) || 7411 !kvm_vcpu_apicv_active(kvm->vcpus[0])) 7412 return 0; 7413 7414 idx = srcu_read_lock(&kvm->irq_srcu); 7415 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu); 7416 if (guest_irq >= irq_rt->nr_rt_entries || 7417 hlist_empty(&irq_rt->map[guest_irq])) { 7418 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n", 7419 guest_irq, irq_rt->nr_rt_entries); 7420 goto out; 7421 } 7422 7423 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) { 7424 if (e->type != KVM_IRQ_ROUTING_MSI) 7425 continue; 7426 /* 7427 * VT-d PI cannot support posting multicast/broadcast 7428 * interrupts to a vCPU, we still use interrupt remapping 7429 * for these kind of interrupts. 7430 * 7431 * For lowest-priority interrupts, we only support 7432 * those with single CPU as the destination, e.g. user 7433 * configures the interrupts via /proc/irq or uses 7434 * irqbalance to make the interrupts single-CPU. 7435 * 7436 * We will support full lowest-priority interrupt later. 7437 * 7438 * In addition, we can only inject generic interrupts using 7439 * the PI mechanism, refuse to route others through it. 7440 */ 7441 7442 kvm_set_msi_irq(kvm, e, &irq); 7443 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu) || 7444 !kvm_irq_is_postable(&irq)) { 7445 /* 7446 * Make sure the IRTE is in remapped mode if 7447 * we don't handle it in posted mode. 7448 */ 7449 ret = irq_set_vcpu_affinity(host_irq, NULL); 7450 if (ret < 0) { 7451 printk(KERN_INFO 7452 "failed to back to remapped mode, irq: %u\n", 7453 host_irq); 7454 goto out; 7455 } 7456 7457 continue; 7458 } 7459 7460 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu)); 7461 vcpu_info.vector = irq.vector; 7462 7463 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi, 7464 vcpu_info.vector, vcpu_info.pi_desc_addr, set); 7465 7466 if (set) 7467 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info); 7468 else 7469 ret = irq_set_vcpu_affinity(host_irq, NULL); 7470 7471 if (ret < 0) { 7472 printk(KERN_INFO "%s: failed to update PI IRTE\n", 7473 __func__); 7474 goto out; 7475 } 7476 } 7477 7478 ret = 0; 7479 out: 7480 srcu_read_unlock(&kvm->irq_srcu, idx); 7481 return ret; 7482 } 7483 7484 static void vmx_setup_mce(struct kvm_vcpu *vcpu) 7485 { 7486 if (vcpu->arch.mcg_cap & MCG_LMCE_P) 7487 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |= 7488 FEAT_CTL_LMCE_ENABLED; 7489 else 7490 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &= 7491 ~FEAT_CTL_LMCE_ENABLED; 7492 } 7493 7494 static int vmx_smi_allowed(struct kvm_vcpu *vcpu) 7495 { 7496 /* we need a nested vmexit to enter SMM, postpone if run is pending */ 7497 if (to_vmx(vcpu)->nested.nested_run_pending) 7498 return 0; 7499 return 1; 7500 } 7501 7502 static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate) 7503 { 7504 struct vcpu_vmx *vmx = to_vmx(vcpu); 7505 7506 vmx->nested.smm.guest_mode = is_guest_mode(vcpu); 7507 if (vmx->nested.smm.guest_mode) 7508 nested_vmx_vmexit(vcpu, -1, 0, 0); 7509 7510 vmx->nested.smm.vmxon = vmx->nested.vmxon; 7511 vmx->nested.vmxon = false; 7512 vmx_clear_hlt(vcpu); 7513 return 0; 7514 } 7515 7516 static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate) 7517 { 7518 struct vcpu_vmx *vmx = to_vmx(vcpu); 7519 int ret; 7520 7521 if (vmx->nested.smm.vmxon) { 7522 vmx->nested.vmxon = true; 7523 vmx->nested.smm.vmxon = false; 7524 } 7525 7526 if (vmx->nested.smm.guest_mode) { 7527 ret = nested_vmx_enter_non_root_mode(vcpu, false); 7528 if (ret) 7529 return ret; 7530 7531 vmx->nested.smm.guest_mode = false; 7532 } 7533 return 0; 7534 } 7535 7536 static int enable_smi_window(struct kvm_vcpu *vcpu) 7537 { 7538 return 0; 7539 } 7540 7541 static bool vmx_need_emulation_on_page_fault(struct kvm_vcpu *vcpu) 7542 { 7543 return false; 7544 } 7545 7546 static bool vmx_apic_init_signal_blocked(struct kvm_vcpu *vcpu) 7547 { 7548 return to_vmx(vcpu)->nested.vmxon; 7549 } 7550 7551 static __init int hardware_setup(void) 7552 { 7553 unsigned long host_bndcfgs; 7554 struct desc_ptr dt; 7555 int r, i; 7556 7557 rdmsrl_safe(MSR_EFER, &host_efer); 7558 7559 store_idt(&dt); 7560 host_idt_base = dt.address; 7561 7562 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) 7563 kvm_define_shared_msr(i, vmx_msr_index[i]); 7564 7565 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0) 7566 return -EIO; 7567 7568 if (boot_cpu_has(X86_FEATURE_NX)) 7569 kvm_enable_efer_bits(EFER_NX); 7570 7571 if (boot_cpu_has(X86_FEATURE_MPX)) { 7572 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs); 7573 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost"); 7574 } 7575 7576 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() || 7577 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global())) 7578 enable_vpid = 0; 7579 7580 if (!cpu_has_vmx_ept() || 7581 !cpu_has_vmx_ept_4levels() || 7582 !cpu_has_vmx_ept_mt_wb() || 7583 !cpu_has_vmx_invept_global()) 7584 enable_ept = 0; 7585 7586 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept) 7587 enable_ept_ad_bits = 0; 7588 7589 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept) 7590 enable_unrestricted_guest = 0; 7591 7592 if (!cpu_has_vmx_flexpriority()) 7593 flexpriority_enabled = 0; 7594 7595 if (!cpu_has_virtual_nmis()) 7596 enable_vnmi = 0; 7597 7598 /* 7599 * set_apic_access_page_addr() is used to reload apic access 7600 * page upon invalidation. No need to do anything if not 7601 * using the APIC_ACCESS_ADDR VMCS field. 7602 */ 7603 if (!flexpriority_enabled) 7604 kvm_x86_ops->set_apic_access_page_addr = NULL; 7605 7606 if (!cpu_has_vmx_tpr_shadow()) 7607 kvm_x86_ops->update_cr8_intercept = NULL; 7608 7609 if (enable_ept && !cpu_has_vmx_ept_2m_page()) 7610 kvm_disable_largepages(); 7611 7612 #if IS_ENABLED(CONFIG_HYPERV) 7613 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH 7614 && enable_ept) { 7615 kvm_x86_ops->tlb_remote_flush = hv_remote_flush_tlb; 7616 kvm_x86_ops->tlb_remote_flush_with_range = 7617 hv_remote_flush_tlb_with_range; 7618 } 7619 #endif 7620 7621 if (!cpu_has_vmx_ple()) { 7622 ple_gap = 0; 7623 ple_window = 0; 7624 ple_window_grow = 0; 7625 ple_window_max = 0; 7626 ple_window_shrink = 0; 7627 } 7628 7629 if (!cpu_has_vmx_apicv()) { 7630 enable_apicv = 0; 7631 kvm_x86_ops->sync_pir_to_irr = NULL; 7632 } 7633 7634 if (cpu_has_vmx_tsc_scaling()) { 7635 kvm_has_tsc_control = true; 7636 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX; 7637 kvm_tsc_scaling_ratio_frac_bits = 48; 7638 } 7639 7640 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */ 7641 7642 if (enable_ept) 7643 vmx_enable_tdp(); 7644 else 7645 kvm_disable_tdp(); 7646 7647 /* 7648 * Only enable PML when hardware supports PML feature, and both EPT 7649 * and EPT A/D bit features are enabled -- PML depends on them to work. 7650 */ 7651 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml()) 7652 enable_pml = 0; 7653 7654 if (!enable_pml) { 7655 kvm_x86_ops->slot_enable_log_dirty = NULL; 7656 kvm_x86_ops->slot_disable_log_dirty = NULL; 7657 kvm_x86_ops->flush_log_dirty = NULL; 7658 kvm_x86_ops->enable_log_dirty_pt_masked = NULL; 7659 } 7660 7661 if (!cpu_has_vmx_preemption_timer()) 7662 enable_preemption_timer = false; 7663 7664 if (enable_preemption_timer) { 7665 u64 use_timer_freq = 5000ULL * 1000 * 1000; 7666 u64 vmx_msr; 7667 7668 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr); 7669 cpu_preemption_timer_multi = 7670 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK; 7671 7672 if (tsc_khz) 7673 use_timer_freq = (u64)tsc_khz * 1000; 7674 use_timer_freq >>= cpu_preemption_timer_multi; 7675 7676 /* 7677 * KVM "disables" the preemption timer by setting it to its max 7678 * value. Don't use the timer if it might cause spurious exits 7679 * at a rate faster than 0.1 Hz (of uninterrupted guest time). 7680 */ 7681 if (use_timer_freq > 0xffffffffu / 10) 7682 enable_preemption_timer = false; 7683 } 7684 7685 if (!enable_preemption_timer) { 7686 kvm_x86_ops->set_hv_timer = NULL; 7687 kvm_x86_ops->cancel_hv_timer = NULL; 7688 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit; 7689 } 7690 7691 kvm_set_posted_intr_wakeup_handler(wakeup_handler); 7692 7693 kvm_mce_cap_supported |= MCG_LMCE_P; 7694 7695 if (pt_mode != PT_MODE_SYSTEM && pt_mode != PT_MODE_HOST_GUEST) 7696 return -EINVAL; 7697 if (!enable_ept || !cpu_has_vmx_intel_pt()) 7698 pt_mode = PT_MODE_SYSTEM; 7699 7700 if (nested) { 7701 nested_vmx_setup_ctls_msrs(&vmcs_config.nested, 7702 vmx_capability.ept, enable_apicv); 7703 7704 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers); 7705 if (r) 7706 return r; 7707 } 7708 7709 r = alloc_kvm_area(); 7710 if (r) 7711 nested_vmx_hardware_unsetup(); 7712 return r; 7713 } 7714 7715 static __exit void hardware_unsetup(void) 7716 { 7717 if (nested) 7718 nested_vmx_hardware_unsetup(); 7719 7720 free_kvm_area(); 7721 } 7722 7723 static bool vmx_check_apicv_inhibit_reasons(ulong bit) 7724 { 7725 ulong supported = BIT(APICV_INHIBIT_REASON_DISABLE) | 7726 BIT(APICV_INHIBIT_REASON_HYPERV); 7727 7728 return supported & BIT(bit); 7729 } 7730 7731 static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { 7732 .cpu_has_kvm_support = cpu_has_kvm_support, 7733 .disabled_by_bios = vmx_disabled_by_bios, 7734 .hardware_setup = hardware_setup, 7735 .hardware_unsetup = hardware_unsetup, 7736 .check_processor_compatibility = vmx_check_processor_compat, 7737 .hardware_enable = hardware_enable, 7738 .hardware_disable = hardware_disable, 7739 .cpu_has_accelerated_tpr = report_flexpriority, 7740 .has_emulated_msr = vmx_has_emulated_msr, 7741 7742 .vm_init = vmx_vm_init, 7743 .vm_alloc = vmx_vm_alloc, 7744 .vm_free = vmx_vm_free, 7745 7746 .vcpu_create = vmx_create_vcpu, 7747 .vcpu_free = vmx_free_vcpu, 7748 .vcpu_reset = vmx_vcpu_reset, 7749 7750 .prepare_guest_switch = vmx_prepare_switch_to_guest, 7751 .vcpu_load = vmx_vcpu_load, 7752 .vcpu_put = vmx_vcpu_put, 7753 7754 .update_bp_intercept = update_exception_bitmap, 7755 .get_msr_feature = vmx_get_msr_feature, 7756 .get_msr = vmx_get_msr, 7757 .set_msr = vmx_set_msr, 7758 .get_segment_base = vmx_get_segment_base, 7759 .get_segment = vmx_get_segment, 7760 .set_segment = vmx_set_segment, 7761 .get_cpl = vmx_get_cpl, 7762 .get_cs_db_l_bits = vmx_get_cs_db_l_bits, 7763 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits, 7764 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits, 7765 .set_cr0 = vmx_set_cr0, 7766 .set_cr3 = vmx_set_cr3, 7767 .set_cr4 = vmx_set_cr4, 7768 .set_efer = vmx_set_efer, 7769 .get_idt = vmx_get_idt, 7770 .set_idt = vmx_set_idt, 7771 .get_gdt = vmx_get_gdt, 7772 .set_gdt = vmx_set_gdt, 7773 .get_dr6 = vmx_get_dr6, 7774 .set_dr6 = vmx_set_dr6, 7775 .set_dr7 = vmx_set_dr7, 7776 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs, 7777 .cache_reg = vmx_cache_reg, 7778 .get_rflags = vmx_get_rflags, 7779 .set_rflags = vmx_set_rflags, 7780 7781 .tlb_flush = vmx_flush_tlb, 7782 .tlb_flush_gva = vmx_flush_tlb_gva, 7783 7784 .run = vmx_vcpu_run, 7785 .handle_exit = vmx_handle_exit, 7786 .skip_emulated_instruction = skip_emulated_instruction, 7787 .set_interrupt_shadow = vmx_set_interrupt_shadow, 7788 .get_interrupt_shadow = vmx_get_interrupt_shadow, 7789 .patch_hypercall = vmx_patch_hypercall, 7790 .set_irq = vmx_inject_irq, 7791 .set_nmi = vmx_inject_nmi, 7792 .queue_exception = vmx_queue_exception, 7793 .cancel_injection = vmx_cancel_injection, 7794 .interrupt_allowed = vmx_interrupt_allowed, 7795 .nmi_allowed = vmx_nmi_allowed, 7796 .get_nmi_mask = vmx_get_nmi_mask, 7797 .set_nmi_mask = vmx_set_nmi_mask, 7798 .enable_nmi_window = enable_nmi_window, 7799 .enable_irq_window = enable_irq_window, 7800 .update_cr8_intercept = update_cr8_intercept, 7801 .set_virtual_apic_mode = vmx_set_virtual_apic_mode, 7802 .set_apic_access_page_addr = vmx_set_apic_access_page_addr, 7803 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl, 7804 .load_eoi_exitmap = vmx_load_eoi_exitmap, 7805 .apicv_post_state_restore = vmx_apicv_post_state_restore, 7806 .check_apicv_inhibit_reasons = vmx_check_apicv_inhibit_reasons, 7807 .hwapic_irr_update = vmx_hwapic_irr_update, 7808 .hwapic_isr_update = vmx_hwapic_isr_update, 7809 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt, 7810 .sync_pir_to_irr = vmx_sync_pir_to_irr, 7811 .deliver_posted_interrupt = vmx_deliver_posted_interrupt, 7812 .dy_apicv_has_pending_interrupt = vmx_dy_apicv_has_pending_interrupt, 7813 7814 .set_tss_addr = vmx_set_tss_addr, 7815 .set_identity_map_addr = vmx_set_identity_map_addr, 7816 .get_tdp_level = get_ept_level, 7817 .get_mt_mask = vmx_get_mt_mask, 7818 7819 .get_exit_info = vmx_get_exit_info, 7820 7821 .get_lpage_level = vmx_get_lpage_level, 7822 7823 .cpuid_update = vmx_cpuid_update, 7824 7825 .rdtscp_supported = vmx_rdtscp_supported, 7826 .invpcid_supported = vmx_invpcid_supported, 7827 7828 .set_supported_cpuid = vmx_set_supported_cpuid, 7829 7830 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit, 7831 7832 .read_l1_tsc_offset = vmx_read_l1_tsc_offset, 7833 .write_l1_tsc_offset = vmx_write_l1_tsc_offset, 7834 7835 .set_tdp_cr3 = vmx_set_cr3, 7836 7837 .check_intercept = vmx_check_intercept, 7838 .handle_exit_irqoff = vmx_handle_exit_irqoff, 7839 .mpx_supported = vmx_mpx_supported, 7840 .xsaves_supported = vmx_xsaves_supported, 7841 .umip_emulated = vmx_umip_emulated, 7842 .pt_supported = vmx_pt_supported, 7843 .pku_supported = vmx_pku_supported, 7844 7845 .request_immediate_exit = vmx_request_immediate_exit, 7846 7847 .sched_in = vmx_sched_in, 7848 7849 .slot_enable_log_dirty = vmx_slot_enable_log_dirty, 7850 .slot_disable_log_dirty = vmx_slot_disable_log_dirty, 7851 .flush_log_dirty = vmx_flush_log_dirty, 7852 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked, 7853 .write_log_dirty = vmx_write_pml_buffer, 7854 7855 .pre_block = vmx_pre_block, 7856 .post_block = vmx_post_block, 7857 7858 .pmu_ops = &intel_pmu_ops, 7859 7860 .update_pi_irte = vmx_update_pi_irte, 7861 7862 #ifdef CONFIG_X86_64 7863 .set_hv_timer = vmx_set_hv_timer, 7864 .cancel_hv_timer = vmx_cancel_hv_timer, 7865 #endif 7866 7867 .setup_mce = vmx_setup_mce, 7868 7869 .smi_allowed = vmx_smi_allowed, 7870 .pre_enter_smm = vmx_pre_enter_smm, 7871 .pre_leave_smm = vmx_pre_leave_smm, 7872 .enable_smi_window = enable_smi_window, 7873 7874 .check_nested_events = NULL, 7875 .get_nested_state = NULL, 7876 .set_nested_state = NULL, 7877 .get_vmcs12_pages = NULL, 7878 .nested_enable_evmcs = NULL, 7879 .nested_get_evmcs_version = NULL, 7880 .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, 7881 .apic_init_signal_blocked = vmx_apic_init_signal_blocked, 7882 }; 7883 7884 static void vmx_cleanup_l1d_flush(void) 7885 { 7886 if (vmx_l1d_flush_pages) { 7887 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER); 7888 vmx_l1d_flush_pages = NULL; 7889 } 7890 /* Restore state so sysfs ignores VMX */ 7891 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO; 7892 } 7893 7894 static void vmx_exit(void) 7895 { 7896 #ifdef CONFIG_KEXEC_CORE 7897 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL); 7898 synchronize_rcu(); 7899 #endif 7900 7901 kvm_exit(); 7902 7903 #if IS_ENABLED(CONFIG_HYPERV) 7904 if (static_branch_unlikely(&enable_evmcs)) { 7905 int cpu; 7906 struct hv_vp_assist_page *vp_ap; 7907 /* 7908 * Reset everything to support using non-enlightened VMCS 7909 * access later (e.g. when we reload the module with 7910 * enlightened_vmcs=0) 7911 */ 7912 for_each_online_cpu(cpu) { 7913 vp_ap = hv_get_vp_assist_page(cpu); 7914 7915 if (!vp_ap) 7916 continue; 7917 7918 vp_ap->nested_control.features.directhypercall = 0; 7919 vp_ap->current_nested_vmcs = 0; 7920 vp_ap->enlighten_vmentry = 0; 7921 } 7922 7923 static_branch_disable(&enable_evmcs); 7924 } 7925 #endif 7926 vmx_cleanup_l1d_flush(); 7927 } 7928 module_exit(vmx_exit); 7929 7930 static int __init vmx_init(void) 7931 { 7932 int r; 7933 7934 #if IS_ENABLED(CONFIG_HYPERV) 7935 /* 7936 * Enlightened VMCS usage should be recommended and the host needs 7937 * to support eVMCS v1 or above. We can also disable eVMCS support 7938 * with module parameter. 7939 */ 7940 if (enlightened_vmcs && 7941 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED && 7942 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >= 7943 KVM_EVMCS_VERSION) { 7944 int cpu; 7945 7946 /* Check that we have assist pages on all online CPUs */ 7947 for_each_online_cpu(cpu) { 7948 if (!hv_get_vp_assist_page(cpu)) { 7949 enlightened_vmcs = false; 7950 break; 7951 } 7952 } 7953 7954 if (enlightened_vmcs) { 7955 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n"); 7956 static_branch_enable(&enable_evmcs); 7957 } 7958 7959 if (ms_hyperv.nested_features & HV_X64_NESTED_DIRECT_FLUSH) 7960 vmx_x86_ops.enable_direct_tlbflush 7961 = hv_enable_direct_tlbflush; 7962 7963 } else { 7964 enlightened_vmcs = false; 7965 } 7966 #endif 7967 7968 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), 7969 __alignof__(struct vcpu_vmx), THIS_MODULE); 7970 if (r) 7971 return r; 7972 7973 /* 7974 * Must be called after kvm_init() so enable_ept is properly set 7975 * up. Hand the parameter mitigation value in which was stored in 7976 * the pre module init parser. If no parameter was given, it will 7977 * contain 'auto' which will be turned into the default 'cond' 7978 * mitigation mode. 7979 */ 7980 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param); 7981 if (r) { 7982 vmx_exit(); 7983 return r; 7984 } 7985 7986 #ifdef CONFIG_KEXEC_CORE 7987 rcu_assign_pointer(crash_vmclear_loaded_vmcss, 7988 crash_vmclear_local_loaded_vmcss); 7989 #endif 7990 vmx_check_vmcs12_offsets(); 7991 7992 return 0; 7993 } 7994 module_init(vmx_init); 7995