1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Fast Ethernet Controller (ENET) PTP driver for MX6x. 4 * 5 * Copyright (C) 2012 Freescale Semiconductor, Inc. 6 */ 7 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/module.h> 11 #include <linux/kernel.h> 12 #include <linux/string.h> 13 #include <linux/ptrace.h> 14 #include <linux/errno.h> 15 #include <linux/ioport.h> 16 #include <linux/slab.h> 17 #include <linux/interrupt.h> 18 #include <linux/pci.h> 19 #include <linux/delay.h> 20 #include <linux/netdevice.h> 21 #include <linux/etherdevice.h> 22 #include <linux/skbuff.h> 23 #include <linux/spinlock.h> 24 #include <linux/workqueue.h> 25 #include <linux/bitops.h> 26 #include <linux/io.h> 27 #include <linux/irq.h> 28 #include <linux/clk.h> 29 #include <linux/platform_device.h> 30 #include <linux/phy.h> 31 #include <linux/fec.h> 32 #include <linux/of.h> 33 #include <linux/of_device.h> 34 #include <linux/of_gpio.h> 35 #include <linux/of_net.h> 36 37 #include "fec.h" 38 39 /* FEC 1588 register bits */ 40 #define FEC_T_CTRL_SLAVE 0x00002000 41 #define FEC_T_CTRL_CAPTURE 0x00000800 42 #define FEC_T_CTRL_RESTART 0x00000200 43 #define FEC_T_CTRL_PERIOD_RST 0x00000030 44 #define FEC_T_CTRL_PERIOD_EN 0x00000010 45 #define FEC_T_CTRL_ENABLE 0x00000001 46 47 #define FEC_T_INC_MASK 0x0000007f 48 #define FEC_T_INC_OFFSET 0 49 #define FEC_T_INC_CORR_MASK 0x00007f00 50 #define FEC_T_INC_CORR_OFFSET 8 51 52 #define FEC_T_CTRL_PINPER 0x00000080 53 #define FEC_T_TF0_MASK 0x00000001 54 #define FEC_T_TF0_OFFSET 0 55 #define FEC_T_TF1_MASK 0x00000002 56 #define FEC_T_TF1_OFFSET 1 57 #define FEC_T_TF2_MASK 0x00000004 58 #define FEC_T_TF2_OFFSET 2 59 #define FEC_T_TF3_MASK 0x00000008 60 #define FEC_T_TF3_OFFSET 3 61 #define FEC_T_TDRE_MASK 0x00000001 62 #define FEC_T_TDRE_OFFSET 0 63 #define FEC_T_TMODE_MASK 0x0000003C 64 #define FEC_T_TMODE_OFFSET 2 65 #define FEC_T_TIE_MASK 0x00000040 66 #define FEC_T_TIE_OFFSET 6 67 #define FEC_T_TF_MASK 0x00000080 68 #define FEC_T_TF_OFFSET 7 69 70 #define FEC_ATIME_CTRL 0x400 71 #define FEC_ATIME 0x404 72 #define FEC_ATIME_EVT_OFFSET 0x408 73 #define FEC_ATIME_EVT_PERIOD 0x40c 74 #define FEC_ATIME_CORR 0x410 75 #define FEC_ATIME_INC 0x414 76 #define FEC_TS_TIMESTAMP 0x418 77 78 #define FEC_TGSR 0x604 79 #define FEC_TCSR(n) (0x608 + n * 0x08) 80 #define FEC_TCCR(n) (0x60C + n * 0x08) 81 #define MAX_TIMER_CHANNEL 3 82 #define FEC_TMODE_TOGGLE 0x05 83 #define FEC_HIGH_PULSE 0x0F 84 85 #define FEC_CC_MULT (1 << 31) 86 #define FEC_COUNTER_PERIOD (1 << 31) 87 #define PPS_OUPUT_RELOAD_PERIOD NSEC_PER_SEC 88 #define FEC_CHANNLE_0 0 89 #define DEFAULT_PPS_CHANNEL FEC_CHANNLE_0 90 91 /** 92 * fec_ptp_enable_pps 93 * @fep: the fec_enet_private structure handle 94 * @enable: enable the channel pps output 95 * 96 * This function enble the PPS ouput on the timer channel. 97 */ 98 static int fec_ptp_enable_pps(struct fec_enet_private *fep, uint enable) 99 { 100 unsigned long flags; 101 u32 val, tempval; 102 struct timespec64 ts; 103 u64 ns; 104 val = 0; 105 106 if (!(fep->hwts_tx_en || fep->hwts_rx_en)) { 107 dev_err(&fep->pdev->dev, "No ptp stack is running\n"); 108 return -EINVAL; 109 } 110 111 if (fep->pps_enable == enable) 112 return 0; 113 114 fep->pps_channel = DEFAULT_PPS_CHANNEL; 115 fep->reload_period = PPS_OUPUT_RELOAD_PERIOD; 116 117 spin_lock_irqsave(&fep->tmreg_lock, flags); 118 119 if (enable) { 120 /* clear capture or output compare interrupt status if have. 121 */ 122 writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel)); 123 124 /* It is recommended to double check the TMODE field in the 125 * TCSR register to be cleared before the first compare counter 126 * is written into TCCR register. Just add a double check. 127 */ 128 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); 129 do { 130 val &= ~(FEC_T_TMODE_MASK); 131 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); 132 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); 133 } while (val & FEC_T_TMODE_MASK); 134 135 /* Dummy read counter to update the counter */ 136 timecounter_read(&fep->tc); 137 /* We want to find the first compare event in the next 138 * second point. So we need to know what the ptp time 139 * is now and how many nanoseconds is ahead to get next second. 140 * The remaining nanosecond ahead before the next second would be 141 * NSEC_PER_SEC - ts.tv_nsec. Add the remaining nanoseconds 142 * to current timer would be next second. 143 */ 144 tempval = readl(fep->hwp + FEC_ATIME_CTRL); 145 tempval |= FEC_T_CTRL_CAPTURE; 146 writel(tempval, fep->hwp + FEC_ATIME_CTRL); 147 148 tempval = readl(fep->hwp + FEC_ATIME); 149 /* Convert the ptp local counter to 1588 timestamp */ 150 ns = timecounter_cyc2time(&fep->tc, tempval); 151 ts = ns_to_timespec64(ns); 152 153 /* The tempval is less than 3 seconds, and so val is less than 154 * 4 seconds. No overflow for 32bit calculation. 155 */ 156 val = NSEC_PER_SEC - (u32)ts.tv_nsec + tempval; 157 158 /* Need to consider the situation that the current time is 159 * very close to the second point, which means NSEC_PER_SEC 160 * - ts.tv_nsec is close to be zero(For example 20ns); Since the timer 161 * is still running when we calculate the first compare event, it is 162 * possible that the remaining nanoseonds run out before the compare 163 * counter is calculated and written into TCCR register. To avoid 164 * this possibility, we will set the compare event to be the next 165 * of next second. The current setting is 31-bit timer and wrap 166 * around over 2 seconds. So it is okay to set the next of next 167 * seond for the timer. 168 */ 169 val += NSEC_PER_SEC; 170 171 /* We add (2 * NSEC_PER_SEC - (u32)ts.tv_nsec) to current 172 * ptp counter, which maybe cause 32-bit wrap. Since the 173 * (NSEC_PER_SEC - (u32)ts.tv_nsec) is less than 2 second. 174 * We can ensure the wrap will not cause issue. If the offset 175 * is bigger than fep->cc.mask would be a error. 176 */ 177 val &= fep->cc.mask; 178 writel(val, fep->hwp + FEC_TCCR(fep->pps_channel)); 179 180 /* Calculate the second the compare event timestamp */ 181 fep->next_counter = (val + fep->reload_period) & fep->cc.mask; 182 183 /* * Enable compare event when overflow */ 184 val = readl(fep->hwp + FEC_ATIME_CTRL); 185 val |= FEC_T_CTRL_PINPER; 186 writel(val, fep->hwp + FEC_ATIME_CTRL); 187 188 /* Compare channel setting. */ 189 val = readl(fep->hwp + FEC_TCSR(fep->pps_channel)); 190 val |= (1 << FEC_T_TF_OFFSET | 1 << FEC_T_TIE_OFFSET); 191 val &= ~(1 << FEC_T_TDRE_OFFSET); 192 val &= ~(FEC_T_TMODE_MASK); 193 val |= (FEC_HIGH_PULSE << FEC_T_TMODE_OFFSET); 194 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); 195 196 /* Write the second compare event timestamp and calculate 197 * the third timestamp. Refer the TCCR register detail in the spec. 198 */ 199 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel)); 200 fep->next_counter = (fep->next_counter + fep->reload_period) & fep->cc.mask; 201 } else { 202 writel(0, fep->hwp + FEC_TCSR(fep->pps_channel)); 203 } 204 205 fep->pps_enable = enable; 206 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 207 208 return 0; 209 } 210 211 /** 212 * fec_ptp_read - read raw cycle counter (to be used by time counter) 213 * @cc: the cyclecounter structure 214 * 215 * this function reads the cyclecounter registers and is called by the 216 * cyclecounter structure used to construct a ns counter from the 217 * arbitrary fixed point registers 218 */ 219 static u64 fec_ptp_read(const struct cyclecounter *cc) 220 { 221 struct fec_enet_private *fep = 222 container_of(cc, struct fec_enet_private, cc); 223 const struct platform_device_id *id_entry = 224 platform_get_device_id(fep->pdev); 225 u32 tempval; 226 227 tempval = readl(fep->hwp + FEC_ATIME_CTRL); 228 tempval |= FEC_T_CTRL_CAPTURE; 229 writel(tempval, fep->hwp + FEC_ATIME_CTRL); 230 231 if (id_entry->driver_data & FEC_QUIRK_BUG_CAPTURE) 232 udelay(1); 233 234 return readl(fep->hwp + FEC_ATIME); 235 } 236 237 /** 238 * fec_ptp_start_cyclecounter - create the cycle counter from hw 239 * @ndev: network device 240 * 241 * this function initializes the timecounter and cyclecounter 242 * structures for use in generated a ns counter from the arbitrary 243 * fixed point cycles registers in the hardware. 244 */ 245 void fec_ptp_start_cyclecounter(struct net_device *ndev) 246 { 247 struct fec_enet_private *fep = netdev_priv(ndev); 248 unsigned long flags; 249 int inc; 250 251 inc = 1000000000 / fep->cycle_speed; 252 253 /* grab the ptp lock */ 254 spin_lock_irqsave(&fep->tmreg_lock, flags); 255 256 /* 1ns counter */ 257 writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC); 258 259 /* use 31-bit timer counter */ 260 writel(FEC_COUNTER_PERIOD, fep->hwp + FEC_ATIME_EVT_PERIOD); 261 262 writel(FEC_T_CTRL_ENABLE | FEC_T_CTRL_PERIOD_RST, 263 fep->hwp + FEC_ATIME_CTRL); 264 265 memset(&fep->cc, 0, sizeof(fep->cc)); 266 fep->cc.read = fec_ptp_read; 267 fep->cc.mask = CLOCKSOURCE_MASK(31); 268 fep->cc.shift = 31; 269 fep->cc.mult = FEC_CC_MULT; 270 271 /* reset the ns time counter */ 272 timecounter_init(&fep->tc, &fep->cc, ktime_to_ns(ktime_get_real())); 273 274 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 275 } 276 277 /** 278 * fec_ptp_adjfreq - adjust ptp cycle frequency 279 * @ptp: the ptp clock structure 280 * @ppb: parts per billion adjustment from base 281 * 282 * Adjust the frequency of the ptp cycle counter by the 283 * indicated ppb from the base frequency. 284 * 285 * Because ENET hardware frequency adjust is complex, 286 * using software method to do that. 287 */ 288 static int fec_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb) 289 { 290 unsigned long flags; 291 int neg_adj = 0; 292 u32 i, tmp; 293 u32 corr_inc, corr_period; 294 u32 corr_ns; 295 u64 lhs, rhs; 296 297 struct fec_enet_private *fep = 298 container_of(ptp, struct fec_enet_private, ptp_caps); 299 300 if (ppb == 0) 301 return 0; 302 303 if (ppb < 0) { 304 ppb = -ppb; 305 neg_adj = 1; 306 } 307 308 /* In theory, corr_inc/corr_period = ppb/NSEC_PER_SEC; 309 * Try to find the corr_inc between 1 to fep->ptp_inc to 310 * meet adjustment requirement. 311 */ 312 lhs = NSEC_PER_SEC; 313 rhs = (u64)ppb * (u64)fep->ptp_inc; 314 for (i = 1; i <= fep->ptp_inc; i++) { 315 if (lhs >= rhs) { 316 corr_inc = i; 317 corr_period = div_u64(lhs, rhs); 318 break; 319 } 320 lhs += NSEC_PER_SEC; 321 } 322 /* Not found? Set it to high value - double speed 323 * correct in every clock step. 324 */ 325 if (i > fep->ptp_inc) { 326 corr_inc = fep->ptp_inc; 327 corr_period = 1; 328 } 329 330 if (neg_adj) 331 corr_ns = fep->ptp_inc - corr_inc; 332 else 333 corr_ns = fep->ptp_inc + corr_inc; 334 335 spin_lock_irqsave(&fep->tmreg_lock, flags); 336 337 tmp = readl(fep->hwp + FEC_ATIME_INC) & FEC_T_INC_MASK; 338 tmp |= corr_ns << FEC_T_INC_CORR_OFFSET; 339 writel(tmp, fep->hwp + FEC_ATIME_INC); 340 corr_period = corr_period > 1 ? corr_period - 1 : corr_period; 341 writel(corr_period, fep->hwp + FEC_ATIME_CORR); 342 /* dummy read to update the timer. */ 343 timecounter_read(&fep->tc); 344 345 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 346 347 return 0; 348 } 349 350 /** 351 * fec_ptp_adjtime 352 * @ptp: the ptp clock structure 353 * @delta: offset to adjust the cycle counter by 354 * 355 * adjust the timer by resetting the timecounter structure. 356 */ 357 static int fec_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) 358 { 359 struct fec_enet_private *fep = 360 container_of(ptp, struct fec_enet_private, ptp_caps); 361 unsigned long flags; 362 363 spin_lock_irqsave(&fep->tmreg_lock, flags); 364 timecounter_adjtime(&fep->tc, delta); 365 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 366 367 return 0; 368 } 369 370 /** 371 * fec_ptp_gettime 372 * @ptp: the ptp clock structure 373 * @ts: timespec structure to hold the current time value 374 * 375 * read the timecounter and return the correct value on ns, 376 * after converting it into a struct timespec. 377 */ 378 static int fec_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts) 379 { 380 struct fec_enet_private *adapter = 381 container_of(ptp, struct fec_enet_private, ptp_caps); 382 u64 ns; 383 unsigned long flags; 384 385 spin_lock_irqsave(&adapter->tmreg_lock, flags); 386 ns = timecounter_read(&adapter->tc); 387 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 388 389 *ts = ns_to_timespec64(ns); 390 391 return 0; 392 } 393 394 /** 395 * fec_ptp_settime 396 * @ptp: the ptp clock structure 397 * @ts: the timespec containing the new time for the cycle counter 398 * 399 * reset the timecounter to use a new base value instead of the kernel 400 * wall timer value. 401 */ 402 static int fec_ptp_settime(struct ptp_clock_info *ptp, 403 const struct timespec64 *ts) 404 { 405 struct fec_enet_private *fep = 406 container_of(ptp, struct fec_enet_private, ptp_caps); 407 408 u64 ns; 409 unsigned long flags; 410 u32 counter; 411 412 mutex_lock(&fep->ptp_clk_mutex); 413 /* Check the ptp clock */ 414 if (!fep->ptp_clk_on) { 415 mutex_unlock(&fep->ptp_clk_mutex); 416 return -EINVAL; 417 } 418 419 ns = timespec64_to_ns(ts); 420 /* Get the timer value based on timestamp. 421 * Update the counter with the masked value. 422 */ 423 counter = ns & fep->cc.mask; 424 425 spin_lock_irqsave(&fep->tmreg_lock, flags); 426 writel(counter, fep->hwp + FEC_ATIME); 427 timecounter_init(&fep->tc, &fep->cc, ns); 428 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 429 mutex_unlock(&fep->ptp_clk_mutex); 430 return 0; 431 } 432 433 /** 434 * fec_ptp_enable 435 * @ptp: the ptp clock structure 436 * @rq: the requested feature to change 437 * @on: whether to enable or disable the feature 438 * 439 */ 440 static int fec_ptp_enable(struct ptp_clock_info *ptp, 441 struct ptp_clock_request *rq, int on) 442 { 443 struct fec_enet_private *fep = 444 container_of(ptp, struct fec_enet_private, ptp_caps); 445 int ret = 0; 446 447 if (rq->type == PTP_CLK_REQ_PPS) { 448 ret = fec_ptp_enable_pps(fep, on); 449 450 return ret; 451 } 452 return -EOPNOTSUPP; 453 } 454 455 int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr) 456 { 457 struct fec_enet_private *fep = netdev_priv(ndev); 458 459 struct hwtstamp_config config; 460 461 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 462 return -EFAULT; 463 464 /* reserved for future extensions */ 465 if (config.flags) 466 return -EINVAL; 467 468 switch (config.tx_type) { 469 case HWTSTAMP_TX_OFF: 470 fep->hwts_tx_en = 0; 471 break; 472 case HWTSTAMP_TX_ON: 473 fep->hwts_tx_en = 1; 474 break; 475 default: 476 return -ERANGE; 477 } 478 479 switch (config.rx_filter) { 480 case HWTSTAMP_FILTER_NONE: 481 if (fep->hwts_rx_en) 482 fep->hwts_rx_en = 0; 483 config.rx_filter = HWTSTAMP_FILTER_NONE; 484 break; 485 486 default: 487 fep->hwts_rx_en = 1; 488 config.rx_filter = HWTSTAMP_FILTER_ALL; 489 break; 490 } 491 492 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 493 -EFAULT : 0; 494 } 495 496 int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr) 497 { 498 struct fec_enet_private *fep = netdev_priv(ndev); 499 struct hwtstamp_config config; 500 501 config.flags = 0; 502 config.tx_type = fep->hwts_tx_en ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 503 config.rx_filter = (fep->hwts_rx_en ? 504 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE); 505 506 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 507 -EFAULT : 0; 508 } 509 510 /** 511 * fec_time_keep - call timecounter_read every second to avoid timer overrun 512 * because ENET just support 32bit counter, will timeout in 4s 513 */ 514 static void fec_time_keep(struct work_struct *work) 515 { 516 struct delayed_work *dwork = to_delayed_work(work); 517 struct fec_enet_private *fep = container_of(dwork, struct fec_enet_private, time_keep); 518 u64 ns; 519 unsigned long flags; 520 521 mutex_lock(&fep->ptp_clk_mutex); 522 if (fep->ptp_clk_on) { 523 spin_lock_irqsave(&fep->tmreg_lock, flags); 524 ns = timecounter_read(&fep->tc); 525 spin_unlock_irqrestore(&fep->tmreg_lock, flags); 526 } 527 mutex_unlock(&fep->ptp_clk_mutex); 528 529 schedule_delayed_work(&fep->time_keep, HZ); 530 } 531 532 /* This function checks the pps event and reloads the timer compare counter. */ 533 static irqreturn_t fec_pps_interrupt(int irq, void *dev_id) 534 { 535 struct net_device *ndev = dev_id; 536 struct fec_enet_private *fep = netdev_priv(ndev); 537 u32 val; 538 u8 channel = fep->pps_channel; 539 struct ptp_clock_event event; 540 541 val = readl(fep->hwp + FEC_TCSR(channel)); 542 if (val & FEC_T_TF_MASK) { 543 /* Write the next next compare(not the next according the spec) 544 * value to the register 545 */ 546 writel(fep->next_counter, fep->hwp + FEC_TCCR(channel)); 547 do { 548 writel(val, fep->hwp + FEC_TCSR(channel)); 549 } while (readl(fep->hwp + FEC_TCSR(channel)) & FEC_T_TF_MASK); 550 551 /* Update the counter; */ 552 fep->next_counter = (fep->next_counter + fep->reload_period) & 553 fep->cc.mask; 554 555 event.type = PTP_CLOCK_PPS; 556 ptp_clock_event(fep->ptp_clock, &event); 557 return IRQ_HANDLED; 558 } 559 560 return IRQ_NONE; 561 } 562 563 /** 564 * fec_ptp_init 565 * @ndev: The FEC network adapter 566 * 567 * This function performs the required steps for enabling ptp 568 * support. If ptp support has already been loaded it simply calls the 569 * cyclecounter init routine and exits. 570 */ 571 572 void fec_ptp_init(struct platform_device *pdev, int irq_idx) 573 { 574 struct net_device *ndev = platform_get_drvdata(pdev); 575 struct fec_enet_private *fep = netdev_priv(ndev); 576 int irq; 577 int ret; 578 579 fep->ptp_caps.owner = THIS_MODULE; 580 snprintf(fep->ptp_caps.name, 16, "fec ptp"); 581 582 fep->ptp_caps.max_adj = 250000000; 583 fep->ptp_caps.n_alarm = 0; 584 fep->ptp_caps.n_ext_ts = 0; 585 fep->ptp_caps.n_per_out = 0; 586 fep->ptp_caps.n_pins = 0; 587 fep->ptp_caps.pps = 1; 588 fep->ptp_caps.adjfreq = fec_ptp_adjfreq; 589 fep->ptp_caps.adjtime = fec_ptp_adjtime; 590 fep->ptp_caps.gettime64 = fec_ptp_gettime; 591 fep->ptp_caps.settime64 = fec_ptp_settime; 592 fep->ptp_caps.enable = fec_ptp_enable; 593 594 fep->cycle_speed = clk_get_rate(fep->clk_ptp); 595 fep->ptp_inc = NSEC_PER_SEC / fep->cycle_speed; 596 597 spin_lock_init(&fep->tmreg_lock); 598 599 fec_ptp_start_cyclecounter(ndev); 600 601 INIT_DELAYED_WORK(&fep->time_keep, fec_time_keep); 602 603 irq = platform_get_irq_byname_optional(pdev, "pps"); 604 if (irq < 0) 605 irq = platform_get_irq_optional(pdev, irq_idx); 606 /* Failure to get an irq is not fatal, 607 * only the PTP_CLOCK_PPS clock events should stop 608 */ 609 if (irq >= 0) { 610 ret = devm_request_irq(&pdev->dev, irq, fec_pps_interrupt, 611 0, pdev->name, ndev); 612 if (ret < 0) 613 dev_warn(&pdev->dev, "request for pps irq failed(%d)\n", 614 ret); 615 } 616 617 fep->ptp_clock = ptp_clock_register(&fep->ptp_caps, &pdev->dev); 618 if (IS_ERR(fep->ptp_clock)) { 619 fep->ptp_clock = NULL; 620 dev_err(&pdev->dev, "ptp_clock_register failed\n"); 621 } 622 623 schedule_delayed_work(&fep->time_keep, HZ); 624 } 625 626 void fec_ptp_stop(struct platform_device *pdev) 627 { 628 struct net_device *ndev = platform_get_drvdata(pdev); 629 struct fec_enet_private *fep = netdev_priv(ndev); 630 631 cancel_delayed_work_sync(&fep->time_keep); 632 if (fep->ptp_clock) 633 ptp_clock_unregister(fep->ptp_clock); 634 } 635