1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2016 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 */ 6 7 #ifndef __MESON_DRV_H 8 #define __MESON_DRV_H 9 10 #include <linux/device.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/regmap.h> 14 15 struct drm_crtc; 16 struct drm_device; 17 struct drm_plane; 18 struct meson_drm; 19 struct meson_afbcd_ops; 20 21 enum vpu_compatible { 22 VPU_COMPATIBLE_GXBB = 0, 23 VPU_COMPATIBLE_GXL = 1, 24 VPU_COMPATIBLE_GXM = 2, 25 VPU_COMPATIBLE_G12A = 3, 26 }; 27 28 struct meson_drm_match_data { 29 enum vpu_compatible compat; 30 struct meson_afbcd_ops *afbcd_ops; 31 }; 32 33 struct meson_drm { 34 struct device *dev; 35 enum vpu_compatible compat; 36 void __iomem *io_base; 37 struct regmap *hhi; 38 int vsync_irq; 39 40 struct meson_canvas *canvas; 41 u8 canvas_id_osd1; 42 u8 canvas_id_vd1_0; 43 u8 canvas_id_vd1_1; 44 u8 canvas_id_vd1_2; 45 46 struct drm_device *drm; 47 struct drm_crtc *crtc; 48 struct drm_plane *primary_plane; 49 struct drm_plane *overlay_plane; 50 51 /* Components Data */ 52 struct { 53 bool osd1_enabled; 54 bool osd1_interlace; 55 bool osd1_commit; 56 bool osd1_afbcd; 57 uint32_t osd1_ctrl_stat; 58 uint32_t osd1_ctrl_stat2; 59 uint32_t osd1_blk0_cfg[5]; 60 uint32_t osd1_blk1_cfg4; 61 uint32_t osd1_blk2_cfg4; 62 uint32_t osd1_addr; 63 uint32_t osd1_stride; 64 uint32_t osd1_height; 65 uint32_t osd1_width; 66 uint32_t osd_sc_ctrl0; 67 uint32_t osd_sc_i_wh_m1; 68 uint32_t osd_sc_o_h_start_end; 69 uint32_t osd_sc_o_v_start_end; 70 uint32_t osd_sc_v_ini_phase; 71 uint32_t osd_sc_v_phase_step; 72 uint32_t osd_sc_h_ini_phase; 73 uint32_t osd_sc_h_phase_step; 74 uint32_t osd_sc_h_ctrl0; 75 uint32_t osd_sc_v_ctrl0; 76 uint32_t osd_blend_din0_scope_h; 77 uint32_t osd_blend_din0_scope_v; 78 uint32_t osb_blend0_size; 79 uint32_t osb_blend1_size; 80 81 bool vd1_enabled; 82 bool vd1_commit; 83 unsigned int vd1_planes; 84 uint32_t vd1_if0_gen_reg; 85 uint32_t vd1_if0_luma_x0; 86 uint32_t vd1_if0_luma_y0; 87 uint32_t vd1_if0_chroma_x0; 88 uint32_t vd1_if0_chroma_y0; 89 uint32_t vd1_if0_repeat_loop; 90 uint32_t vd1_if0_luma0_rpt_pat; 91 uint32_t vd1_if0_chroma0_rpt_pat; 92 uint32_t vd1_range_map_y; 93 uint32_t vd1_range_map_cb; 94 uint32_t vd1_range_map_cr; 95 uint32_t viu_vd1_fmt_w; 96 uint32_t vd1_if0_canvas0; 97 uint32_t vd1_if0_gen_reg2; 98 uint32_t viu_vd1_fmt_ctrl; 99 uint32_t vd1_addr0; 100 uint32_t vd1_addr1; 101 uint32_t vd1_addr2; 102 uint32_t vd1_stride0; 103 uint32_t vd1_stride1; 104 uint32_t vd1_stride2; 105 uint32_t vd1_height0; 106 uint32_t vd1_height1; 107 uint32_t vd1_height2; 108 uint32_t vpp_pic_in_height; 109 uint32_t vpp_postblend_vd1_h_start_end; 110 uint32_t vpp_postblend_vd1_v_start_end; 111 uint32_t vpp_hsc_region12_startp; 112 uint32_t vpp_hsc_region34_startp; 113 uint32_t vpp_hsc_region4_endp; 114 uint32_t vpp_hsc_start_phase_step; 115 uint32_t vpp_hsc_region1_phase_slope; 116 uint32_t vpp_hsc_region3_phase_slope; 117 uint32_t vpp_line_in_length; 118 uint32_t vpp_preblend_h_size; 119 uint32_t vpp_vsc_region12_startp; 120 uint32_t vpp_vsc_region34_startp; 121 uint32_t vpp_vsc_region4_endp; 122 uint32_t vpp_vsc_start_phase_step; 123 uint32_t vpp_vsc_ini_phase; 124 uint32_t vpp_vsc_phase_ctrl; 125 uint32_t vpp_hsc_phase_ctrl; 126 uint32_t vpp_blend_vd2_h_start_end; 127 uint32_t vpp_blend_vd2_v_start_end; 128 } viu; 129 130 struct { 131 unsigned int current_mode; 132 bool hdmi_repeat; 133 bool venc_repeat; 134 bool hdmi_use_enci; 135 } venc; 136 137 struct { 138 dma_addr_t addr_dma; 139 uint32_t *addr; 140 unsigned int offset; 141 } rdma; 142 143 struct { 144 struct meson_afbcd_ops *ops; 145 u64 modifier; 146 u32 format; 147 } afbcd; 148 }; 149 150 static inline int meson_vpu_is_compatible(struct meson_drm *priv, 151 enum vpu_compatible family) 152 { 153 return priv->compat == family; 154 } 155 156 #endif /* __MESON_DRV_H */ 157