1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn20_dsc.h" 28 #include "dsc/dscc_types.h" 29 30 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps); 31 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, 32 struct dsc_optc_config *dsc_optc_cfg); 33 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals); 34 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params); 35 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals); 36 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple); 37 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth); 38 39 /* Object I/F functions */ 40 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); 41 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s); 42 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg); 43 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 44 struct dsc_optc_config *dsc_optc_cfg); 45 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps); 46 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe); 47 static void dsc2_disable(struct display_stream_compressor *dsc); 48 49 const struct dsc_funcs dcn20_dsc_funcs = { 50 .dsc_get_enc_caps = dsc2_get_enc_caps, 51 .dsc_read_state = dsc2_read_state, 52 .dsc_validate_stream = dsc2_validate_stream, 53 .dsc_set_config = dsc2_set_config, 54 .dsc_get_packed_pps = dsc2_get_packed_pps, 55 .dsc_enable = dsc2_enable, 56 .dsc_disable = dsc2_disable, 57 }; 58 59 /* Macro definitios for REG_SET macros*/ 60 #define CTX \ 61 dsc20->base.ctx 62 63 #define REG(reg)\ 64 dsc20->dsc_regs->reg 65 66 #undef FN 67 #define FN(reg_name, field_name) \ 68 dsc20->dsc_shift->field_name, dsc20->dsc_mask->field_name 69 #define DC_LOGGER \ 70 dsc->ctx->logger 71 72 enum dsc_bits_per_comp { 73 DSC_BPC_8 = 8, 74 DSC_BPC_10 = 10, 75 DSC_BPC_12 = 12, 76 DSC_BPC_UNKNOWN 77 }; 78 79 /* API functions (external or via structure->function_pointer) */ 80 81 void dsc2_construct(struct dcn20_dsc *dsc, 82 struct dc_context *ctx, 83 int inst, 84 const struct dcn20_dsc_registers *dsc_regs, 85 const struct dcn20_dsc_shift *dsc_shift, 86 const struct dcn20_dsc_mask *dsc_mask) 87 { 88 dsc->base.ctx = ctx; 89 dsc->base.inst = inst; 90 dsc->base.funcs = &dcn20_dsc_funcs; 91 92 dsc->dsc_regs = dsc_regs; 93 dsc->dsc_shift = dsc_shift; 94 dsc->dsc_mask = dsc_mask; 95 96 dsc->max_image_width = 5184; 97 } 98 99 100 #define DCN20_MAX_PIXEL_CLOCK_Mhz 1188 101 #define DCN20_MAX_DISPLAY_CLOCK_Mhz 1200 102 103 /* This returns the capabilities for a single DSC encoder engine. Number of slices and total throughput 104 * can be doubled, tripled etc. by using additional DSC engines. 105 */ 106 static void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz) 107 { 108 dsc_enc_caps->dsc_version = 0x21; /* v1.2 - DP spec defined it in reverse order and we kept it */ 109 110 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 1; 111 dsc_enc_caps->slice_caps.bits.NUM_SLICES_2 = 1; 112 dsc_enc_caps->slice_caps.bits.NUM_SLICES_3 = 1; 113 dsc_enc_caps->slice_caps.bits.NUM_SLICES_4 = 1; 114 115 dsc_enc_caps->lb_bit_depth = 13; 116 dsc_enc_caps->is_block_pred_supported = true; 117 118 dsc_enc_caps->color_formats.bits.RGB = 1; 119 dsc_enc_caps->color_formats.bits.YCBCR_444 = 1; 120 dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1; 121 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0; 122 dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1; 123 124 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1; 125 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_10_BPC = 1; 126 dsc_enc_caps->color_depth.bits.COLOR_DEPTH_12_BPC = 1; 127 128 /* Maximum total throughput with all the slices combined. This is different from how DP spec specifies it. 129 * Our decoder's total throughput in Pix/s is equal to DISPCLK. This is then shared between slices. 130 * The value below is the absolute maximum value. The actual throughput may be lower, but it'll always 131 * be sufficient to process the input pixel rate fed into a single DSC engine. 132 */ 133 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz; 134 135 /* For pixel clock bigger than a single-pipe limit we'll need two engines, which then doubles our 136 * throughput and number of slices, but also introduces a lower limit of 2 slices 137 */ 138 if (pixel_clock_100Hz >= DCN20_MAX_PIXEL_CLOCK_Mhz*10000) { 139 dsc_enc_caps->slice_caps.bits.NUM_SLICES_1 = 0; 140 dsc_enc_caps->slice_caps.bits.NUM_SLICES_8 = 1; 141 dsc_enc_caps->max_total_throughput_mps = DCN20_MAX_DISPLAY_CLOCK_Mhz * 2; 142 } 143 144 // TODO DSC: This is actually image width limitation, not a slice width. This should be added to the criteria to use ODM. 145 dsc_enc_caps->max_slice_width = 5184; /* (including 64 overlap pixels for eDP MSO mode) */ 146 dsc_enc_caps->bpp_increment_div = 16; /* 1/16th of a bit */ 147 } 148 149 150 /* this function read dsc related register fields to be logged later in dcn10_log_hw_state 151 * into a dcn_dsc_state struct. 152 */ 153 static void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s) 154 { 155 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 156 157 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &s->dsc_clock_en); 158 REG_GET(DSCC_PPS_CONFIG3, SLICE_WIDTH, &s->dsc_slice_width); 159 REG_GET(DSCC_PPS_CONFIG1, BITS_PER_PIXEL, &s->dsc_bytes_per_pixel); 160 } 161 162 163 static bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg) 164 { 165 struct dsc_optc_config dsc_optc_cfg; 166 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 167 168 if (dsc_cfg->pic_width > dsc20->max_image_width) 169 return false; 170 171 return dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, &dsc_optc_cfg); 172 } 173 174 175 static void dsc_config_log(struct display_stream_compressor *dsc, const struct dsc_config *config) 176 { 177 DC_LOG_DSC("\tnum_slices_h %d", config->dc_dsc_cfg.num_slices_h); 178 DC_LOG_DSC("\tnum_slices_v %d", config->dc_dsc_cfg.num_slices_v); 179 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", 180 config->dc_dsc_cfg.bits_per_pixel, 181 config->dc_dsc_cfg.bits_per_pixel / 16, 182 ((config->dc_dsc_cfg.bits_per_pixel % 16) * 10000) / 16); 183 DC_LOG_DSC("\tcolor_depth %d", config->color_depth); 184 } 185 186 static void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, 187 struct dsc_optc_config *dsc_optc_cfg) 188 { 189 bool is_config_ok; 190 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 191 192 DC_LOG_DSC(" "); 193 DC_LOG_DSC("Setting DSC Config at DSC inst %d", dsc->inst); 194 dsc_config_log(dsc, dsc_cfg); 195 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc20->reg_vals, dsc_optc_cfg); 196 ASSERT(is_config_ok); 197 DC_LOG_DSC("programming DSC Picture Parameter Set (PPS):"); 198 dsc_log_pps(dsc, &dsc20->reg_vals.pps); 199 dsc_write_to_registers(dsc, &dsc20->reg_vals); 200 } 201 202 203 static bool dsc2_get_packed_pps(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg, uint8_t *dsc_packed_pps) 204 { 205 bool is_config_ok; 206 struct dsc_reg_values dsc_reg_vals; 207 struct dsc_optc_config dsc_optc_cfg; 208 209 memset(&dsc_reg_vals, 0, sizeof(dsc_reg_vals)); 210 memset(&dsc_optc_cfg, 0, sizeof(dsc_optc_cfg)); 211 212 DC_LOG_DSC("Getting packed DSC PPS for DSC Config:"); 213 dsc_config_log(dsc, dsc_cfg); 214 DC_LOG_DSC("DSC Picture Parameter Set (PPS):"); 215 is_config_ok = dsc_prepare_config(dsc_cfg, &dsc_reg_vals, &dsc_optc_cfg); 216 ASSERT(is_config_ok); 217 drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps); 218 dsc_log_pps(dsc, &dsc_reg_vals.pps); 219 220 return is_config_ok; 221 } 222 223 224 static void dsc2_enable(struct display_stream_compressor *dsc, int opp_pipe) 225 { 226 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 227 int dsc_clock_en; 228 int dsc_fw_config; 229 int enabled_opp_pipe; 230 231 DC_LOG_DSC("enable DSC %d at opp pipe %d", dsc->inst, opp_pipe); 232 233 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 234 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 235 if ((dsc_clock_en || dsc_fw_config) && enabled_opp_pipe != opp_pipe) { 236 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already enabled!", dsc->inst, enabled_opp_pipe); 237 ASSERT(0); 238 } 239 240 REG_UPDATE(DSC_TOP_CONTROL, 241 DSC_CLOCK_EN, 1); 242 243 REG_UPDATE_2(DSCRM_DSC_FORWARD_CONFIG, 244 DSCRM_DSC_FORWARD_EN, 1, 245 DSCRM_DSC_OPP_PIPE_SOURCE, opp_pipe); 246 } 247 248 249 static void dsc2_disable(struct display_stream_compressor *dsc) 250 { 251 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 252 int dsc_clock_en; 253 int dsc_fw_config; 254 int enabled_opp_pipe; 255 256 DC_LOG_DSC("disable DSC %d", dsc->inst); 257 258 REG_GET(DSC_TOP_CONTROL, DSC_CLOCK_EN, &dsc_clock_en); 259 REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &dsc_fw_config, DSCRM_DSC_OPP_PIPE_SOURCE, &enabled_opp_pipe); 260 if (!dsc_clock_en || !dsc_fw_config) { 261 DC_LOG_DSC("ERROR: DSC %d at opp pipe %d already disabled!", dsc->inst, enabled_opp_pipe); 262 ASSERT(0); 263 } 264 265 REG_UPDATE(DSCRM_DSC_FORWARD_CONFIG, 266 DSCRM_DSC_FORWARD_EN, 0); 267 268 REG_UPDATE(DSC_TOP_CONTROL, 269 DSC_CLOCK_EN, 0); 270 } 271 272 273 /* This module's internal functions */ 274 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps) 275 { 276 int i; 277 int bits_per_pixel = pps->bits_per_pixel; 278 279 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major); 280 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor); 281 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component); 282 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); 283 DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); 284 DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); 285 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); 286 DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); 287 DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16); 288 DC_LOG_DSC("\tpic_height %d", pps->pic_height); 289 DC_LOG_DSC("\tpic_width %d", pps->pic_width); 290 DC_LOG_DSC("\tslice_height %d", pps->slice_height); 291 DC_LOG_DSC("\tslice_width %d", pps->slice_width); 292 DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size); 293 DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay); 294 DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay); 295 DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value); 296 DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval); 297 DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval); 298 DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset); 299 DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset); 300 DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset); 301 DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); 302 DC_LOG_DSC("\tfinal_offset %d", pps->final_offset); 303 DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp); 304 DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp); 305 /* DC_LOG_DSC("\trc_parameter_set %d", pps->rc_parameter_set); */ 306 DC_LOG_DSC("\tnative_420 %d", pps->native_420); 307 DC_LOG_DSC("\tnative_422 %d", pps->native_422); 308 DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset); 309 DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset); 310 DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj); 311 DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size); 312 DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor); 313 DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0); 314 DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1); 315 DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high); 316 DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low); 317 318 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 319 DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]); 320 321 for (i = 0; i < NUM_BUF_RANGES; i++) { 322 DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp); 323 DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp); 324 DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset); 325 } 326 } 327 328 static bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values *dsc_reg_vals, 329 struct dsc_optc_config *dsc_optc_cfg) 330 { 331 struct dsc_parameters dsc_params; 332 333 /* Validate input parameters */ 334 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_h); 335 ASSERT(dsc_cfg->dc_dsc_cfg.num_slices_v); 336 ASSERT(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2); 337 ASSERT(dsc_cfg->pic_width); 338 ASSERT(dsc_cfg->pic_height); 339 ASSERT((dsc_cfg->dc_dsc_cfg.version_minor == 1 && 340 (8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13)) || 341 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && 342 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 343 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))); 344 ASSERT(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff); // 6.0 <= bits_per_pixel <= 63.9375 345 346 if (!dsc_cfg->dc_dsc_cfg.num_slices_v || !dsc_cfg->dc_dsc_cfg.num_slices_h || 347 !(dsc_cfg->dc_dsc_cfg.version_minor == 1 || dsc_cfg->dc_dsc_cfg.version_minor == 2) || 348 !dsc_cfg->pic_width || !dsc_cfg->pic_height || 349 !((dsc_cfg->dc_dsc_cfg.version_minor == 1 && // v1.1 line buffer depth range: 350 8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 13) || 351 (dsc_cfg->dc_dsc_cfg.version_minor == 2 && // v1.2 line buffer depth range: 352 ((8 <= dsc_cfg->dc_dsc_cfg.linebuf_depth && dsc_cfg->dc_dsc_cfg.linebuf_depth <= 15) || 353 dsc_cfg->dc_dsc_cfg.linebuf_depth == 0))) || 354 !(96 <= dsc_cfg->dc_dsc_cfg.bits_per_pixel && dsc_cfg->dc_dsc_cfg.bits_per_pixel <= 0x3ff)) { 355 dm_output_to_console("%s: Invalid parameters\n", __func__); 356 return false; 357 } 358 359 dsc_init_reg_values(dsc_reg_vals); 360 361 /* Copy input config */ 362 dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple); 363 dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h; 364 dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v; 365 dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; 366 dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; 367 dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; 368 dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); 369 dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; 370 dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; 371 dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1; 372 373 // TODO: in addition to validating slice height (pic height must be divisible by slice height), 374 // see what happens when the same condition doesn't apply for slice_width/pic_width. 375 dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; 376 dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; 377 378 ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); 379 if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { 380 dm_output_to_console("%s: pix height %d not divisible by num_slices_v %d\n\n", __func__, dsc_cfg->pic_height, dsc_cfg->dc_dsc_cfg.num_slices_v); 381 return false; 382 } 383 384 dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1; 385 if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 386 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32; 387 else 388 dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1; 389 390 dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; 391 dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); 392 dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); 393 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); 394 395 if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) { 396 dm_output_to_console("%s: DSC config failed\n", __func__); 397 return false; 398 } 399 400 dsc_update_from_dsc_parameters(dsc_reg_vals, &dsc_params); 401 402 dsc_optc_cfg->bytes_per_pixel = dsc_params.bytes_per_pixel; 403 dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width; 404 dsc_optc_cfg->is_pixel_format_444 = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB || 405 dsc_reg_vals->pixel_format == DSC_PIXFMT_YCBCR444 || 406 dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422; 407 408 return true; 409 } 410 411 412 static enum dsc_pixel_format dsc_dc_pixel_encoding_to_dsc_pixel_format(enum dc_pixel_encoding dc_pix_enc, bool is_ycbcr422_simple) 413 { 414 enum dsc_pixel_format dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 415 416 /* NOTE: We don't support DSC_PIXFMT_SIMPLE_YCBCR422 */ 417 418 switch (dc_pix_enc) { 419 case PIXEL_ENCODING_RGB: 420 dsc_pix_fmt = DSC_PIXFMT_RGB; 421 break; 422 case PIXEL_ENCODING_YCBCR422: 423 if (is_ycbcr422_simple) 424 dsc_pix_fmt = DSC_PIXFMT_SIMPLE_YCBCR422; 425 else 426 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR422; 427 break; 428 case PIXEL_ENCODING_YCBCR444: 429 dsc_pix_fmt = DSC_PIXFMT_YCBCR444; 430 break; 431 case PIXEL_ENCODING_YCBCR420: 432 dsc_pix_fmt = DSC_PIXFMT_NATIVE_YCBCR420; 433 break; 434 default: 435 dsc_pix_fmt = DSC_PIXFMT_UNKNOWN; 436 break; 437 } 438 439 ASSERT(dsc_pix_fmt != DSC_PIXFMT_UNKNOWN); 440 return dsc_pix_fmt; 441 } 442 443 444 static enum dsc_bits_per_comp dsc_dc_color_depth_to_dsc_bits_per_comp(enum dc_color_depth dc_color_depth) 445 { 446 enum dsc_bits_per_comp bpc = DSC_BPC_UNKNOWN; 447 448 switch (dc_color_depth) { 449 case COLOR_DEPTH_888: 450 bpc = DSC_BPC_8; 451 break; 452 case COLOR_DEPTH_101010: 453 bpc = DSC_BPC_10; 454 break; 455 case COLOR_DEPTH_121212: 456 bpc = DSC_BPC_12; 457 break; 458 default: 459 bpc = DSC_BPC_UNKNOWN; 460 break; 461 } 462 463 return bpc; 464 } 465 466 467 static void dsc_init_reg_values(struct dsc_reg_values *reg_vals) 468 { 469 int i; 470 471 memset(reg_vals, 0, sizeof(struct dsc_reg_values)); 472 473 /* Non-PPS values */ 474 reg_vals->dsc_clock_enable = 1; 475 reg_vals->dsc_clock_gating_disable = 0; 476 reg_vals->underflow_recovery_en = 0; 477 reg_vals->underflow_occurred_int_en = 0; 478 reg_vals->underflow_occurred_status = 0; 479 reg_vals->ich_reset_at_eol = 0; 480 reg_vals->alternate_ich_encoding_en = 0; 481 reg_vals->rc_buffer_model_size = 0; 482 /*reg_vals->disable_ich = 0;*/ 483 reg_vals->dsc_dbg_en = 0; 484 485 for (i = 0; i < 4; i++) 486 reg_vals->rc_buffer_model_overflow_int_en[i] = 0; 487 488 /* PPS values */ 489 reg_vals->pps.dsc_version_minor = 2; 490 reg_vals->pps.dsc_version_major = 1; 491 reg_vals->pps.line_buf_depth = 9; 492 reg_vals->pps.bits_per_component = 8; 493 reg_vals->pps.block_pred_enable = 1; 494 reg_vals->pps.slice_chunk_size = 0; 495 reg_vals->pps.pic_width = 0; 496 reg_vals->pps.pic_height = 0; 497 reg_vals->pps.slice_width = 0; 498 reg_vals->pps.slice_height = 0; 499 reg_vals->pps.initial_xmit_delay = 170; 500 reg_vals->pps.initial_dec_delay = 0; 501 reg_vals->pps.initial_scale_value = 0; 502 reg_vals->pps.scale_increment_interval = 0; 503 reg_vals->pps.scale_decrement_interval = 0; 504 reg_vals->pps.nfl_bpg_offset = 0; 505 reg_vals->pps.slice_bpg_offset = 0; 506 reg_vals->pps.nsl_bpg_offset = 0; 507 reg_vals->pps.initial_offset = 6144; 508 reg_vals->pps.final_offset = 0; 509 reg_vals->pps.flatness_min_qp = 3; 510 reg_vals->pps.flatness_max_qp = 12; 511 reg_vals->pps.rc_model_size = 8192; 512 reg_vals->pps.rc_edge_factor = 6; 513 reg_vals->pps.rc_quant_incr_limit0 = 11; 514 reg_vals->pps.rc_quant_incr_limit1 = 11; 515 reg_vals->pps.rc_tgt_offset_low = 3; 516 reg_vals->pps.rc_tgt_offset_high = 3; 517 } 518 519 /* Updates dsc_reg_values::reg_vals::xxx fields based on the values from computed params. 520 * This is required because dscc_compute_dsc_parameters returns a modified PPS, which in turn 521 * affects non-PPS register values. 522 */ 523 static void dsc_update_from_dsc_parameters(struct dsc_reg_values *reg_vals, const struct dsc_parameters *dsc_params) 524 { 525 int i; 526 527 reg_vals->pps = dsc_params->pps; 528 529 // pps_computed will have the "expanded" values; need to shift them to make them fit for regs. 530 for (i = 0; i < NUM_BUF_RANGES - 1; i++) 531 reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6; 532 533 reg_vals->rc_buffer_model_size = dsc_params->rc_buffer_model_size; 534 reg_vals->ich_reset_at_eol = reg_vals->num_slices_h == 1 ? 0 : 0xf; 535 } 536 537 static void dsc_write_to_registers(struct display_stream_compressor *dsc, const struct dsc_reg_values *reg_vals) 538 { 539 uint32_t temp_int; 540 struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc); 541 542 REG_SET(DSC_DEBUG_CONTROL, 0, 543 DSC_DBG_EN, reg_vals->dsc_dbg_en); 544 545 // dsccif registers 546 REG_SET_5(DSCCIF_CONFIG0, 0, 547 INPUT_INTERFACE_UNDERFLOW_RECOVERY_EN, reg_vals->underflow_recovery_en, 548 INPUT_INTERFACE_UNDERFLOW_OCCURRED_INT_EN, reg_vals->underflow_occurred_int_en, 549 INPUT_INTERFACE_UNDERFLOW_OCCURRED_STATUS, reg_vals->underflow_occurred_status, 550 INPUT_PIXEL_FORMAT, reg_vals->pixel_format, 551 DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 552 553 REG_SET_2(DSCCIF_CONFIG1, 0, 554 PIC_WIDTH, reg_vals->pps.pic_width, 555 PIC_HEIGHT, reg_vals->pps.pic_height); 556 557 // dscc registers 558 REG_SET_4(DSCC_CONFIG0, 0, 559 ICH_RESET_AT_END_OF_LINE, reg_vals->ich_reset_at_eol, 560 NUMBER_OF_SLICES_PER_LINE, reg_vals->num_slices_h - 1, 561 ALTERNATE_ICH_ENCODING_EN, reg_vals->alternate_ich_encoding_en, 562 NUMBER_OF_SLICES_IN_VERTICAL_DIRECTION, reg_vals->num_slices_v - 1); 563 564 REG_SET(DSCC_CONFIG1, 0, 565 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size); 566 /*REG_SET_2(DSCC_CONFIG1, 0, 567 DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, reg_vals->rc_buffer_model_size, 568 DSCC_DISABLE_ICH, reg_vals->disable_ich);*/ 569 570 REG_SET_4(DSCC_INTERRUPT_CONTROL_STATUS, 0, 571 DSCC_RATE_CONTROL_BUFFER_MODEL0_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[0], 572 DSCC_RATE_CONTROL_BUFFER_MODEL1_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[1], 573 DSCC_RATE_CONTROL_BUFFER_MODEL2_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[2], 574 DSCC_RATE_CONTROL_BUFFER_MODEL3_OVERFLOW_OCCURRED_INT_EN, reg_vals->rc_buffer_model_overflow_int_en[3]); 575 576 REG_SET_3(DSCC_PPS_CONFIG0, 0, 577 DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, 578 LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, 579 DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); 580 581 if (reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422) 582 temp_int = reg_vals->bpp_x32; 583 else 584 temp_int = reg_vals->bpp_x32 >> 1; 585 586 REG_SET_7(DSCC_PPS_CONFIG1, 0, 587 BITS_PER_PIXEL, temp_int, 588 SIMPLE_422, reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422, 589 CONVERT_RGB, reg_vals->pixel_format == DSC_PIXFMT_RGB, 590 BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, 591 NATIVE_422, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422, 592 NATIVE_420, reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420, 593 CHUNK_SIZE, reg_vals->pps.slice_chunk_size); 594 595 REG_SET_2(DSCC_PPS_CONFIG2, 0, 596 PIC_WIDTH, reg_vals->pps.pic_width, 597 PIC_HEIGHT, reg_vals->pps.pic_height); 598 599 REG_SET_2(DSCC_PPS_CONFIG3, 0, 600 SLICE_WIDTH, reg_vals->pps.slice_width, 601 SLICE_HEIGHT, reg_vals->pps.slice_height); 602 603 REG_SET(DSCC_PPS_CONFIG4, 0, 604 INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay); 605 606 REG_SET_2(DSCC_PPS_CONFIG5, 0, 607 INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value, 608 SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval); 609 610 REG_SET_3(DSCC_PPS_CONFIG6, 0, 611 SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval, 612 FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, 613 SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset); 614 615 REG_SET_2(DSCC_PPS_CONFIG7, 0, 616 NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, 617 SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); 618 619 REG_SET_2(DSCC_PPS_CONFIG8, 0, 620 NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, 621 SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj); 622 623 REG_SET_2(DSCC_PPS_CONFIG9, 0, 624 INITIAL_OFFSET, reg_vals->pps.initial_offset, 625 FINAL_OFFSET, reg_vals->pps.final_offset); 626 627 REG_SET_3(DSCC_PPS_CONFIG10, 0, 628 FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp, 629 FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp, 630 RC_MODEL_SIZE, reg_vals->pps.rc_model_size); 631 632 REG_SET_5(DSCC_PPS_CONFIG11, 0, 633 RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor, 634 RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, 635 RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, 636 RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low, 637 RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high); 638 639 REG_SET_4(DSCC_PPS_CONFIG12, 0, 640 RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0], 641 RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1], 642 RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2], 643 RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]); 644 645 REG_SET_4(DSCC_PPS_CONFIG13, 0, 646 RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4], 647 RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5], 648 RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6], 649 RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]); 650 651 REG_SET_4(DSCC_PPS_CONFIG14, 0, 652 RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8], 653 RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9], 654 RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10], 655 RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]); 656 657 REG_SET_5(DSCC_PPS_CONFIG15, 0, 658 RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12], 659 RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13], 660 RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, 661 RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, 662 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); 663 664 REG_SET_6(DSCC_PPS_CONFIG16, 0, 665 RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, 666 RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, 667 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, 668 RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, 669 RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, 670 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); 671 672 REG_SET_6(DSCC_PPS_CONFIG17, 0, 673 RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, 674 RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, 675 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, 676 RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, 677 RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, 678 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); 679 680 REG_SET_6(DSCC_PPS_CONFIG18, 0, 681 RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, 682 RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, 683 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, 684 RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, 685 RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, 686 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); 687 688 REG_SET_6(DSCC_PPS_CONFIG19, 0, 689 RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, 690 RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, 691 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, 692 RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, 693 RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, 694 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); 695 696 REG_SET_6(DSCC_PPS_CONFIG20, 0, 697 RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, 698 RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, 699 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, 700 RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, 701 RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, 702 RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); 703 704 REG_SET_6(DSCC_PPS_CONFIG21, 0, 705 RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, 706 RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, 707 RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, 708 RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, 709 RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, 710 RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); 711 712 REG_SET_6(DSCC_PPS_CONFIG22, 0, 713 RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, 714 RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, 715 RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, 716 RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, 717 RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, 718 RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); 719 720 if (IS_FPGA_MAXIMUS_DC(dsc20->base.ctx->dce_environment)) { 721 /* It's safe to do this as long as debug bus is not being used in DAL Diag environment. 722 * 723 * This is because DSCC_PPS_CONFIG4.INITIAL_DEC_DELAY is a read-only register field (because it's a decoder 724 * value not required by DSC encoder). However, since decoding fails when this value is missing from PPS, it's 725 * required to communicate this value to the PPS header. When testing on FPGA, the values for PPS header are 726 * being read from Diag register dump. The register below is used in place of a scratch register to make 727 * 'initial_dec_delay' available. 728 */ 729 730 temp_int = reg_vals->pps.initial_dec_delay; 731 REG_SET_4(DSCC_TEST_DEBUG_BUS_ROTATE, 0, 732 DSCC_TEST_DEBUG_BUS0_ROTATE, temp_int & 0x1f, 733 DSCC_TEST_DEBUG_BUS1_ROTATE, temp_int >> 5 & 0x1f, 734 DSCC_TEST_DEBUG_BUS2_ROTATE, temp_int >> 10 & 0x1f, 735 DSCC_TEST_DEBUG_BUS3_ROTATE, temp_int >> 15 & 0x1); 736 } 737 } 738 739