1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/reset-controller/mt8183-resets.h> 12#include "mt8183-pinfunc.h" 13 14/ { 15 compatible = "mediatek,mt8183"; 16 interrupt-parent = <&sysirq>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 i2c0 = &i2c0; 22 i2c1 = &i2c1; 23 i2c2 = &i2c2; 24 i2c3 = &i2c3; 25 i2c4 = &i2c4; 26 i2c5 = &i2c5; 27 i2c6 = &i2c6; 28 i2c7 = &i2c7; 29 i2c8 = &i2c8; 30 i2c9 = &i2c9; 31 i2c10 = &i2c10; 32 i2c11 = &i2c11; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu-map { 40 cluster0 { 41 core0 { 42 cpu = <&cpu0>; 43 }; 44 core1 { 45 cpu = <&cpu1>; 46 }; 47 core2 { 48 cpu = <&cpu2>; 49 }; 50 core3 { 51 cpu = <&cpu3>; 52 }; 53 }; 54 55 cluster1 { 56 core0 { 57 cpu = <&cpu4>; 58 }; 59 core1 { 60 cpu = <&cpu5>; 61 }; 62 core2 { 63 cpu = <&cpu6>; 64 }; 65 core3 { 66 cpu = <&cpu7>; 67 }; 68 }; 69 }; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x000>; 75 enable-method = "psci"; 76 capacity-dmips-mhz = <741>; 77 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 78 dynamic-power-coefficient = <84>; 79 #cooling-cells = <2>; 80 }; 81 82 cpu1: cpu@1 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x001>; 86 enable-method = "psci"; 87 capacity-dmips-mhz = <741>; 88 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 89 dynamic-power-coefficient = <84>; 90 #cooling-cells = <2>; 91 }; 92 93 cpu2: cpu@2 { 94 device_type = "cpu"; 95 compatible = "arm,cortex-a53"; 96 reg = <0x002>; 97 enable-method = "psci"; 98 capacity-dmips-mhz = <741>; 99 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 100 dynamic-power-coefficient = <84>; 101 #cooling-cells = <2>; 102 }; 103 104 cpu3: cpu@3 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a53"; 107 reg = <0x003>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <741>; 110 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 111 dynamic-power-coefficient = <84>; 112 #cooling-cells = <2>; 113 }; 114 115 cpu4: cpu@100 { 116 device_type = "cpu"; 117 compatible = "arm,cortex-a73"; 118 reg = <0x100>; 119 enable-method = "psci"; 120 capacity-dmips-mhz = <1024>; 121 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 122 dynamic-power-coefficient = <211>; 123 #cooling-cells = <2>; 124 }; 125 126 cpu5: cpu@101 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a73"; 129 reg = <0x101>; 130 enable-method = "psci"; 131 capacity-dmips-mhz = <1024>; 132 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 133 dynamic-power-coefficient = <211>; 134 #cooling-cells = <2>; 135 }; 136 137 cpu6: cpu@102 { 138 device_type = "cpu"; 139 compatible = "arm,cortex-a73"; 140 reg = <0x102>; 141 enable-method = "psci"; 142 capacity-dmips-mhz = <1024>; 143 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 144 dynamic-power-coefficient = <211>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu7: cpu@103 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a73"; 151 reg = <0x103>; 152 enable-method = "psci"; 153 capacity-dmips-mhz = <1024>; 154 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 155 dynamic-power-coefficient = <211>; 156 #cooling-cells = <2>; 157 }; 158 159 idle-states { 160 entry-method = "psci"; 161 162 CPU_SLEEP: cpu-sleep { 163 compatible = "arm,idle-state"; 164 local-timer-stop; 165 arm,psci-suspend-param = <0x00010001>; 166 entry-latency-us = <200>; 167 exit-latency-us = <200>; 168 min-residency-us = <800>; 169 }; 170 171 CLUSTER_SLEEP0: cluster-sleep@0 { 172 compatible = "arm,idle-state"; 173 local-timer-stop; 174 arm,psci-suspend-param = <0x01010001>; 175 entry-latency-us = <250>; 176 exit-latency-us = <400>; 177 min-residency-us = <1000>; 178 }; 179 CLUSTER_SLEEP1: cluster-sleep@1 { 180 compatible = "arm,idle-state"; 181 local-timer-stop; 182 arm,psci-suspend-param = <0x01010001>; 183 entry-latency-us = <250>; 184 exit-latency-us = <400>; 185 min-residency-us = <1300>; 186 }; 187 }; 188 }; 189 190 pmu-a53 { 191 compatible = "arm,cortex-a53-pmu"; 192 interrupt-parent = <&gic>; 193 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 194 }; 195 196 pmu-a73 { 197 compatible = "arm,cortex-a73-pmu"; 198 interrupt-parent = <&gic>; 199 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 200 }; 201 202 psci { 203 compatible = "arm,psci-1.0"; 204 method = "smc"; 205 }; 206 207 clk26m: oscillator { 208 compatible = "fixed-clock"; 209 #clock-cells = <0>; 210 clock-frequency = <26000000>; 211 clock-output-names = "clk26m"; 212 }; 213 214 timer { 215 compatible = "arm,armv8-timer"; 216 interrupt-parent = <&gic>; 217 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 218 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 219 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 220 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 221 }; 222 223 soc { 224 #address-cells = <2>; 225 #size-cells = <2>; 226 compatible = "simple-bus"; 227 ranges; 228 229 soc_data: soc_data@8000000 { 230 compatible = "mediatek,mt8183-efuse", 231 "mediatek,efuse"; 232 reg = <0 0x08000000 0 0x0010>; 233 #address-cells = <1>; 234 #size-cells = <1>; 235 status = "disabled"; 236 }; 237 238 gic: interrupt-controller@c000000 { 239 compatible = "arm,gic-v3"; 240 #interrupt-cells = <4>; 241 interrupt-parent = <&gic>; 242 interrupt-controller; 243 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 244 <0 0x0c100000 0 0x200000>, /* GICR */ 245 <0 0x0c400000 0 0x2000>, /* GICC */ 246 <0 0x0c410000 0 0x1000>, /* GICH */ 247 <0 0x0c420000 0 0x2000>; /* GICV */ 248 249 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 250 ppi-partitions { 251 ppi_cluster0: interrupt-partition-0 { 252 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 253 }; 254 ppi_cluster1: interrupt-partition-1 { 255 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 256 }; 257 }; 258 }; 259 260 mcucfg: syscon@c530000 { 261 compatible = "mediatek,mt8183-mcucfg", "syscon"; 262 reg = <0 0x0c530000 0 0x1000>; 263 #clock-cells = <1>; 264 }; 265 266 sysirq: interrupt-controller@c530a80 { 267 compatible = "mediatek,mt8183-sysirq", 268 "mediatek,mt6577-sysirq"; 269 interrupt-controller; 270 #interrupt-cells = <3>; 271 interrupt-parent = <&gic>; 272 reg = <0 0x0c530a80 0 0x50>; 273 }; 274 275 topckgen: syscon@10000000 { 276 compatible = "mediatek,mt8183-topckgen", "syscon"; 277 reg = <0 0x10000000 0 0x1000>; 278 #clock-cells = <1>; 279 }; 280 281 infracfg: syscon@10001000 { 282 compatible = "mediatek,mt8183-infracfg", "syscon"; 283 reg = <0 0x10001000 0 0x1000>; 284 #clock-cells = <1>; 285 #reset-cells = <1>; 286 }; 287 288 pio: pinctrl@10005000 { 289 compatible = "mediatek,mt8183-pinctrl"; 290 reg = <0 0x10005000 0 0x1000>, 291 <0 0x11f20000 0 0x1000>, 292 <0 0x11e80000 0 0x1000>, 293 <0 0x11e70000 0 0x1000>, 294 <0 0x11e90000 0 0x1000>, 295 <0 0x11d30000 0 0x1000>, 296 <0 0x11d20000 0 0x1000>, 297 <0 0x11c50000 0 0x1000>, 298 <0 0x11f30000 0 0x1000>, 299 <0 0x1000b000 0 0x1000>; 300 reg-names = "iocfg0", "iocfg1", "iocfg2", 301 "iocfg3", "iocfg4", "iocfg5", 302 "iocfg6", "iocfg7", "iocfg8", 303 "eint"; 304 gpio-controller; 305 #gpio-cells = <2>; 306 gpio-ranges = <&pio 0 0 192>; 307 interrupt-controller; 308 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 309 #interrupt-cells = <2>; 310 }; 311 312 watchdog: watchdog@10007000 { 313 compatible = "mediatek,mt8183-wdt", 314 "mediatek,mt6589-wdt"; 315 reg = <0 0x10007000 0 0x100>; 316 #reset-cells = <1>; 317 }; 318 319 apmixedsys: syscon@1000c000 { 320 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 321 reg = <0 0x1000c000 0 0x1000>; 322 #clock-cells = <1>; 323 }; 324 325 pwrap: pwrap@1000d000 { 326 compatible = "mediatek,mt8183-pwrap"; 327 reg = <0 0x1000d000 0 0x1000>; 328 reg-names = "pwrap"; 329 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 331 <&infracfg CLK_INFRA_PMIC_AP>; 332 clock-names = "spi", "wrap"; 333 }; 334 335 systimer: timer@10017000 { 336 compatible = "mediatek,mt8183-timer", 337 "mediatek,mt6765-timer"; 338 reg = <0 0x10017000 0 0x1000>; 339 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&topckgen CLK_TOP_CLK13M>; 341 clock-names = "clk13m"; 342 }; 343 344 gce: mailbox@10238000 { 345 compatible = "mediatek,mt8183-gce"; 346 reg = <0 0x10238000 0 0x4000>; 347 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 348 #mbox-cells = <3>; 349 clocks = <&infracfg CLK_INFRA_GCE>; 350 clock-names = "gce"; 351 }; 352 353 auxadc: auxadc@11001000 { 354 compatible = "mediatek,mt8183-auxadc", 355 "mediatek,mt8173-auxadc"; 356 reg = <0 0x11001000 0 0x1000>; 357 clocks = <&infracfg CLK_INFRA_AUXADC>; 358 clock-names = "main"; 359 #io-channel-cells = <1>; 360 status = "disabled"; 361 }; 362 363 uart0: serial@11002000 { 364 compatible = "mediatek,mt8183-uart", 365 "mediatek,mt6577-uart"; 366 reg = <0 0x11002000 0 0x1000>; 367 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 368 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 369 clock-names = "baud", "bus"; 370 status = "disabled"; 371 }; 372 373 uart1: serial@11003000 { 374 compatible = "mediatek,mt8183-uart", 375 "mediatek,mt6577-uart"; 376 reg = <0 0x11003000 0 0x1000>; 377 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 378 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 379 clock-names = "baud", "bus"; 380 status = "disabled"; 381 }; 382 383 uart2: serial@11004000 { 384 compatible = "mediatek,mt8183-uart", 385 "mediatek,mt6577-uart"; 386 reg = <0 0x11004000 0 0x1000>; 387 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 388 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 389 clock-names = "baud", "bus"; 390 status = "disabled"; 391 }; 392 393 i2c6: i2c@11005000 { 394 compatible = "mediatek,mt8183-i2c"; 395 reg = <0 0x11005000 0 0x1000>, 396 <0 0x11000600 0 0x80>; 397 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 398 clocks = <&infracfg CLK_INFRA_I2C6>, 399 <&infracfg CLK_INFRA_AP_DMA>; 400 clock-names = "main", "dma"; 401 clock-div = <1>; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 status = "disabled"; 405 }; 406 407 i2c0: i2c@11007000 { 408 compatible = "mediatek,mt8183-i2c"; 409 reg = <0 0x11007000 0 0x1000>, 410 <0 0x11000080 0 0x80>; 411 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 412 clocks = <&infracfg CLK_INFRA_I2C0>, 413 <&infracfg CLK_INFRA_AP_DMA>; 414 clock-names = "main", "dma"; 415 clock-div = <1>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 status = "disabled"; 419 }; 420 421 i2c4: i2c@11008000 { 422 compatible = "mediatek,mt8183-i2c"; 423 reg = <0 0x11008000 0 0x1000>, 424 <0 0x11000100 0 0x80>; 425 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 426 clocks = <&infracfg CLK_INFRA_I2C1>, 427 <&infracfg CLK_INFRA_AP_DMA>, 428 <&infracfg CLK_INFRA_I2C1_ARBITER>; 429 clock-names = "main", "dma","arb"; 430 clock-div = <1>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 status = "disabled"; 434 }; 435 436 i2c2: i2c@11009000 { 437 compatible = "mediatek,mt8183-i2c"; 438 reg = <0 0x11009000 0 0x1000>, 439 <0 0x11000280 0 0x80>; 440 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 441 clocks = <&infracfg CLK_INFRA_I2C2>, 442 <&infracfg CLK_INFRA_AP_DMA>, 443 <&infracfg CLK_INFRA_I2C2_ARBITER>; 444 clock-names = "main", "dma", "arb"; 445 clock-div = <1>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 status = "disabled"; 449 }; 450 451 spi0: spi@1100a000 { 452 compatible = "mediatek,mt8183-spi"; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 reg = <0 0x1100a000 0 0x1000>; 456 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 457 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 458 <&topckgen CLK_TOP_MUX_SPI>, 459 <&infracfg CLK_INFRA_SPI0>; 460 clock-names = "parent-clk", "sel-clk", "spi-clk"; 461 status = "disabled"; 462 }; 463 464 i2c3: i2c@1100f000 { 465 compatible = "mediatek,mt8183-i2c"; 466 reg = <0 0x1100f000 0 0x1000>, 467 <0 0x11000400 0 0x80>; 468 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 469 clocks = <&infracfg CLK_INFRA_I2C3>, 470 <&infracfg CLK_INFRA_AP_DMA>; 471 clock-names = "main", "dma"; 472 clock-div = <1>; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 status = "disabled"; 476 }; 477 478 spi1: spi@11010000 { 479 compatible = "mediatek,mt8183-spi"; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 reg = <0 0x11010000 0 0x1000>; 483 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 484 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 485 <&topckgen CLK_TOP_MUX_SPI>, 486 <&infracfg CLK_INFRA_SPI1>; 487 clock-names = "parent-clk", "sel-clk", "spi-clk"; 488 status = "disabled"; 489 }; 490 491 i2c1: i2c@11011000 { 492 compatible = "mediatek,mt8183-i2c"; 493 reg = <0 0x11011000 0 0x1000>, 494 <0 0x11000480 0 0x80>; 495 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 496 clocks = <&infracfg CLK_INFRA_I2C4>, 497 <&infracfg CLK_INFRA_AP_DMA>; 498 clock-names = "main", "dma"; 499 clock-div = <1>; 500 #address-cells = <1>; 501 #size-cells = <0>; 502 status = "disabled"; 503 }; 504 505 spi2: spi@11012000 { 506 compatible = "mediatek,mt8183-spi"; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 reg = <0 0x11012000 0 0x1000>; 510 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 511 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 512 <&topckgen CLK_TOP_MUX_SPI>, 513 <&infracfg CLK_INFRA_SPI2>; 514 clock-names = "parent-clk", "sel-clk", "spi-clk"; 515 status = "disabled"; 516 }; 517 518 spi3: spi@11013000 { 519 compatible = "mediatek,mt8183-spi"; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 reg = <0 0x11013000 0 0x1000>; 523 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 524 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 525 <&topckgen CLK_TOP_MUX_SPI>, 526 <&infracfg CLK_INFRA_SPI3>; 527 clock-names = "parent-clk", "sel-clk", "spi-clk"; 528 status = "disabled"; 529 }; 530 531 i2c9: i2c@11014000 { 532 compatible = "mediatek,mt8183-i2c"; 533 reg = <0 0x11014000 0 0x1000>, 534 <0 0x11000180 0 0x80>; 535 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 536 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 537 <&infracfg CLK_INFRA_AP_DMA>, 538 <&infracfg CLK_INFRA_I2C1_ARBITER>; 539 clock-names = "main", "dma", "arb"; 540 clock-div = <1>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 546 i2c10: i2c@11015000 { 547 compatible = "mediatek,mt8183-i2c"; 548 reg = <0 0x11015000 0 0x1000>, 549 <0 0x11000300 0 0x80>; 550 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 551 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 552 <&infracfg CLK_INFRA_AP_DMA>, 553 <&infracfg CLK_INFRA_I2C2_ARBITER>; 554 clock-names = "main", "dma", "arb"; 555 clock-div = <1>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 status = "disabled"; 559 }; 560 561 i2c5: i2c@11016000 { 562 compatible = "mediatek,mt8183-i2c"; 563 reg = <0 0x11016000 0 0x1000>, 564 <0 0x11000500 0 0x80>; 565 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 566 clocks = <&infracfg CLK_INFRA_I2C5>, 567 <&infracfg CLK_INFRA_AP_DMA>, 568 <&infracfg CLK_INFRA_I2C5_ARBITER>; 569 clock-names = "main", "dma", "arb"; 570 clock-div = <1>; 571 #address-cells = <1>; 572 #size-cells = <0>; 573 status = "disabled"; 574 }; 575 576 i2c11: i2c@11017000 { 577 compatible = "mediatek,mt8183-i2c"; 578 reg = <0 0x11017000 0 0x1000>, 579 <0 0x11000580 0 0x80>; 580 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 581 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 582 <&infracfg CLK_INFRA_AP_DMA>, 583 <&infracfg CLK_INFRA_I2C5_ARBITER>; 584 clock-names = "main", "dma", "arb"; 585 clock-div = <1>; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 status = "disabled"; 589 }; 590 591 spi4: spi@11018000 { 592 compatible = "mediatek,mt8183-spi"; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 reg = <0 0x11018000 0 0x1000>; 596 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 597 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 598 <&topckgen CLK_TOP_MUX_SPI>, 599 <&infracfg CLK_INFRA_SPI4>; 600 clock-names = "parent-clk", "sel-clk", "spi-clk"; 601 status = "disabled"; 602 }; 603 604 spi5: spi@11019000 { 605 compatible = "mediatek,mt8183-spi"; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 reg = <0 0x11019000 0 0x1000>; 609 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 610 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 611 <&topckgen CLK_TOP_MUX_SPI>, 612 <&infracfg CLK_INFRA_SPI5>; 613 clock-names = "parent-clk", "sel-clk", "spi-clk"; 614 status = "disabled"; 615 }; 616 617 i2c7: i2c@1101a000 { 618 compatible = "mediatek,mt8183-i2c"; 619 reg = <0 0x1101a000 0 0x1000>, 620 <0 0x11000680 0 0x80>; 621 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 622 clocks = <&infracfg CLK_INFRA_I2C7>, 623 <&infracfg CLK_INFRA_AP_DMA>; 624 clock-names = "main", "dma"; 625 clock-div = <1>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 i2c8: i2c@1101b000 { 632 compatible = "mediatek,mt8183-i2c"; 633 reg = <0 0x1101b000 0 0x1000>, 634 <0 0x11000700 0 0x80>; 635 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 636 clocks = <&infracfg CLK_INFRA_I2C8>, 637 <&infracfg CLK_INFRA_AP_DMA>; 638 clock-names = "main", "dma"; 639 clock-div = <1>; 640 #address-cells = <1>; 641 #size-cells = <0>; 642 status = "disabled"; 643 }; 644 645 audiosys: syscon@11220000 { 646 compatible = "mediatek,mt8183-audiosys", "syscon"; 647 reg = <0 0x11220000 0 0x1000>; 648 #clock-cells = <1>; 649 }; 650 651 mmc0: mmc@11230000 { 652 compatible = "mediatek,mt8183-mmc"; 653 reg = <0 0x11230000 0 0x1000>, 654 <0 0x11f50000 0 0x1000>; 655 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 656 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 657 <&infracfg CLK_INFRA_MSDC0>, 658 <&infracfg CLK_INFRA_MSDC0_SCK>; 659 clock-names = "source", "hclk", "source_cg"; 660 status = "disabled"; 661 }; 662 663 mmc1: mmc@11240000 { 664 compatible = "mediatek,mt8183-mmc"; 665 reg = <0 0x11240000 0 0x1000>, 666 <0 0x11e10000 0 0x1000>; 667 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 668 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 669 <&infracfg CLK_INFRA_MSDC1>, 670 <&infracfg CLK_INFRA_MSDC1_SCK>; 671 clock-names = "source", "hclk", "source_cg"; 672 status = "disabled"; 673 }; 674 675 efuse: efuse@11f10000 { 676 compatible = "mediatek,mt8183-efuse", 677 "mediatek,efuse"; 678 reg = <0 0x11f10000 0 0x1000>; 679 }; 680 681 mfgcfg: syscon@13000000 { 682 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 683 reg = <0 0x13000000 0 0x1000>; 684 #clock-cells = <1>; 685 }; 686 687 mmsys: syscon@14000000 { 688 compatible = "mediatek,mt8183-mmsys", "syscon"; 689 reg = <0 0x14000000 0 0x1000>; 690 #clock-cells = <1>; 691 }; 692 693 imgsys: syscon@15020000 { 694 compatible = "mediatek,mt8183-imgsys", "syscon"; 695 reg = <0 0x15020000 0 0x1000>; 696 #clock-cells = <1>; 697 }; 698 699 vdecsys: syscon@16000000 { 700 compatible = "mediatek,mt8183-vdecsys", "syscon"; 701 reg = <0 0x16000000 0 0x1000>; 702 #clock-cells = <1>; 703 }; 704 705 vencsys: syscon@17000000 { 706 compatible = "mediatek,mt8183-vencsys", "syscon"; 707 reg = <0 0x17000000 0 0x1000>; 708 #clock-cells = <1>; 709 }; 710 711 ipu_conn: syscon@19000000 { 712 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 713 reg = <0 0x19000000 0 0x1000>; 714 #clock-cells = <1>; 715 }; 716 717 ipu_adl: syscon@19010000 { 718 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 719 reg = <0 0x19010000 0 0x1000>; 720 #clock-cells = <1>; 721 }; 722 723 ipu_core0: syscon@19180000 { 724 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 725 reg = <0 0x19180000 0 0x1000>; 726 #clock-cells = <1>; 727 }; 728 729 ipu_core1: syscon@19280000 { 730 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 731 reg = <0 0x19280000 0 0x1000>; 732 #clock-cells = <1>; 733 }; 734 735 camsys: syscon@1a000000 { 736 compatible = "mediatek,mt8183-camsys", "syscon"; 737 reg = <0 0x1a000000 0 0x1000>; 738 #clock-cells = <1>; 739 }; 740 }; 741}; 742