1 #include <linux/kernel.h> 2 #include <linux/module.h> 3 #include <linux/platform_device.h> 4 #include <linux/pci.h> 5 6 #include "mt7615.h" 7 #include "regs.h" 8 #include "mac.h" 9 #include "../trace.h" 10 11 const u32 mt7615e_reg_map[] = { 12 [MT_TOP_CFG_BASE] = 0x01000, 13 [MT_HW_BASE] = 0x01000, 14 [MT_PCIE_REMAP_2] = 0x02504, 15 [MT_ARB_BASE] = 0x20c00, 16 [MT_HIF_BASE] = 0x04000, 17 [MT_CSR_BASE] = 0x07000, 18 [MT_PLE_BASE] = 0x08000, 19 [MT_PSE_BASE] = 0x0c000, 20 [MT_PHY_BASE] = 0x10000, 21 [MT_CFG_BASE] = 0x20200, 22 [MT_AGG_BASE] = 0x20a00, 23 [MT_TMAC_BASE] = 0x21000, 24 [MT_RMAC_BASE] = 0x21200, 25 [MT_DMA_BASE] = 0x21800, 26 [MT_PF_BASE] = 0x22000, 27 [MT_WTBL_BASE_ON] = 0x23000, 28 [MT_WTBL_BASE_OFF] = 0x23400, 29 [MT_LPON_BASE] = 0x24200, 30 [MT_MIB_BASE] = 0x24800, 31 [MT_WTBL_BASE_ADDR] = 0x30000, 32 [MT_PCIE_REMAP_BASE2] = 0x80000, 33 [MT_TOP_MISC_BASE] = 0xc0000, 34 [MT_EFUSE_ADDR_BASE] = 0x81070000, 35 }; 36 37 const u32 mt7663e_reg_map[] = { 38 [MT_TOP_CFG_BASE] = 0x01000, 39 [MT_HW_BASE] = 0x02000, 40 [MT_DMA_SHDL_BASE] = 0x06000, 41 [MT_PCIE_REMAP_2] = 0x0700c, 42 [MT_ARB_BASE] = 0x20c00, 43 [MT_HIF_BASE] = 0x04000, 44 [MT_CSR_BASE] = 0x07000, 45 [MT_PLE_BASE] = 0x08000, 46 [MT_PSE_BASE] = 0x0c000, 47 [MT_PHY_BASE] = 0x10000, 48 [MT_CFG_BASE] = 0x20000, 49 [MT_AGG_BASE] = 0x22000, 50 [MT_TMAC_BASE] = 0x24000, 51 [MT_RMAC_BASE] = 0x25000, 52 [MT_DMA_BASE] = 0x27000, 53 [MT_PF_BASE] = 0x28000, 54 [MT_WTBL_BASE_ON] = 0x29000, 55 [MT_WTBL_BASE_OFF] = 0x29800, 56 [MT_LPON_BASE] = 0x2b000, 57 [MT_MIB_BASE] = 0x2d000, 58 [MT_WTBL_BASE_ADDR] = 0x30000, 59 [MT_PCIE_REMAP_BASE2] = 0x90000, 60 [MT_TOP_MISC_BASE] = 0xc0000, 61 [MT_EFUSE_ADDR_BASE] = 0x78011000, 62 }; 63 64 u32 mt7615_reg_map(struct mt7615_dev *dev, u32 addr) 65 { 66 u32 base, offset; 67 68 if (is_mt7663(&dev->mt76)) { 69 base = addr & MT7663_MCU_PCIE_REMAP_2_BASE; 70 offset = addr & MT7663_MCU_PCIE_REMAP_2_OFFSET; 71 } else { 72 base = addr & MT_MCU_PCIE_REMAP_2_BASE; 73 offset = addr & MT_MCU_PCIE_REMAP_2_OFFSET; 74 } 75 mt76_wr(dev, MT_MCU_PCIE_REMAP_2, base); 76 77 return MT_PCIE_REMAP_BASE_2 + offset; 78 } 79 80 static void 81 mt7615_rx_poll_complete(struct mt76_dev *mdev, enum mt76_rxq_id q) 82 { 83 struct mt7615_dev *dev = container_of(mdev, struct mt7615_dev, mt76); 84 85 mt7615_irq_enable(dev, MT_INT_RX_DONE(q)); 86 } 87 88 static irqreturn_t mt7615_irq_handler(int irq, void *dev_instance) 89 { 90 struct mt7615_dev *dev = dev_instance; 91 92 mt76_wr(dev, MT_INT_MASK_CSR, 0); 93 94 if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state)) 95 return IRQ_NONE; 96 97 tasklet_schedule(&dev->irq_tasklet); 98 99 return IRQ_HANDLED; 100 } 101 102 static void mt7615_irq_tasklet(unsigned long data) 103 { 104 struct mt7615_dev *dev = (struct mt7615_dev *)data; 105 u32 intr, mask = 0; 106 107 mt76_wr(dev, MT_INT_MASK_CSR, 0); 108 109 intr = mt76_rr(dev, MT_INT_SOURCE_CSR); 110 mt76_wr(dev, MT_INT_SOURCE_CSR, intr); 111 112 trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask); 113 intr &= dev->mt76.mmio.irqmask; 114 115 if (intr & MT_INT_TX_DONE_ALL) { 116 mask |= MT_INT_TX_DONE_ALL; 117 napi_schedule(&dev->mt76.tx_napi); 118 } 119 120 if (intr & MT_INT_RX_DONE(0)) { 121 mask |= MT_INT_RX_DONE(0); 122 napi_schedule(&dev->mt76.napi[0]); 123 } 124 125 if (intr & MT_INT_RX_DONE(1)) { 126 mask |= MT_INT_RX_DONE(1); 127 napi_schedule(&dev->mt76.napi[1]); 128 } 129 130 if (intr & MT_INT_MCU_CMD) { 131 u32 val = mt76_rr(dev, MT_MCU_CMD); 132 133 if (val & MT_MCU_CMD_ERROR_MASK) { 134 dev->reset_state = val; 135 ieee80211_queue_work(mt76_hw(dev), &dev->reset_work); 136 wake_up(&dev->reset_wait); 137 } 138 } 139 140 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0); 141 } 142 143 int mt7615_mmio_probe(struct device *pdev, void __iomem *mem_base, 144 int irq, const u32 *map) 145 { 146 static const struct mt76_driver_ops drv_ops = { 147 /* txwi_size = txd size + txp size */ 148 .txwi_size = MT_TXD_SIZE + sizeof(struct mt7615_txp_common), 149 .drv_flags = MT_DRV_TXWI_NO_FREE, 150 .survey_flags = SURVEY_INFO_TIME_TX | 151 SURVEY_INFO_TIME_RX | 152 SURVEY_INFO_TIME_BSS_RX, 153 .tx_prepare_skb = mt7615_tx_prepare_skb, 154 .tx_complete_skb = mt7615_tx_complete_skb, 155 .rx_skb = mt7615_queue_rx_skb, 156 .rx_poll_complete = mt7615_rx_poll_complete, 157 .sta_ps = mt7615_sta_ps, 158 .sta_add = mt7615_mac_sta_add, 159 .sta_remove = mt7615_mac_sta_remove, 160 .update_survey = mt7615_update_channel, 161 }; 162 struct ieee80211_ops *ops; 163 struct mt7615_dev *dev; 164 struct mt76_dev *mdev; 165 int ret; 166 167 ops = devm_kmemdup(pdev, &mt7615_ops, sizeof(mt7615_ops), GFP_KERNEL); 168 if (!ops) 169 return -ENOMEM; 170 171 mdev = mt76_alloc_device(pdev, sizeof(*dev), ops, &drv_ops); 172 if (!mdev) 173 return -ENOMEM; 174 175 dev = container_of(mdev, struct mt7615_dev, mt76); 176 mt76_mmio_init(&dev->mt76, mem_base); 177 tasklet_init(&dev->irq_tasklet, mt7615_irq_tasklet, (unsigned long)dev); 178 179 dev->reg_map = map; 180 dev->ops = ops; 181 mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) | 182 (mt76_rr(dev, MT_HW_REV) & 0xff); 183 dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev); 184 185 ret = devm_request_irq(mdev->dev, irq, mt7615_irq_handler, 186 IRQF_SHARED, KBUILD_MODNAME, dev); 187 if (ret) 188 goto error; 189 190 if (is_mt7663(mdev)) 191 mt76_wr(dev, MT_PCIE_IRQ_ENABLE, 1); 192 193 ret = mt7615_register_device(dev); 194 if (ret) 195 goto error; 196 197 return 0; 198 error: 199 ieee80211_free_hw(mt76_hw(dev)); 200 return ret; 201 } 202 203 static int __init mt7615_init(void) 204 { 205 int ret; 206 207 ret = pci_register_driver(&mt7615_pci_driver); 208 if (ret) 209 return ret; 210 211 if (IS_ENABLED(CONFIG_MT7622_WMAC)) { 212 ret = platform_driver_register(&mt7622_wmac_driver); 213 if (ret) 214 pci_unregister_driver(&mt7615_pci_driver); 215 } 216 217 return ret; 218 } 219 220 static void __exit mt7615_exit(void) 221 { 222 if (IS_ENABLED(CONFIG_MT7622_WMAC)) 223 platform_driver_unregister(&mt7622_wmac_driver); 224 pci_unregister_driver(&mt7615_pci_driver); 225 } 226 227 module_init(mt7615_init); 228 module_exit(mt7615_exit); 229 MODULE_LICENSE("Dual BSD/GPL"); 230