1[
2	{
3		"Unit": "CPU-M-CF",
4		"EventCode": "128",
5		"EventName": "L1D_RO_EXCL_WRITES",
6		"BriefDescription": "L1D Read-only Exclusive Writes",
7		"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
8	},
9	{
10		"Unit": "CPU-M-CF",
11		"EventCode": "129",
12		"EventName": "DTLB2_WRITES",
13		"BriefDescription": "DTLB2 Writes",
14		"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the data cache"
15	},
16	{
17		"Unit": "CPU-M-CF",
18		"EventCode": "130",
19		"EventName": "DTLB2_MISSES",
20		"BriefDescription": "DTLB2 Misses",
21		"PublicDescription": "A TLB2 miss is in progress for a request made by the data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle"
22	},
23	{
24		"Unit": "CPU-M-CF",
25		"EventCode": "131",
26		"EventName": "DTLB2_HPAGE_WRITES",
27		"BriefDescription": "DTLB2 One-Megabyte Page Writes",
28		"PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page"
29	},
30	{
31		"Unit": "CPU-M-CF",
32		"EventCode": "132",
33		"EventName": "DTLB2_GPAGE_WRITES",
34		"BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
35		"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB"
36	},
37	{
38		"Unit": "CPU-M-CF",
39		"EventCode": "133",
40		"EventName": "L1D_L2D_SOURCED_WRITES",
41		"BriefDescription": "L1D L2D Sourced Writes",
42		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache"
43	},
44	{
45		"Unit": "CPU-M-CF",
46		"EventCode": "134",
47		"EventName": "ITLB2_WRITES",
48		"BriefDescription": "ITLB2 Writes",
49		"PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache"
50	},
51	{
52		"Unit": "CPU-M-CF",
53		"EventCode": "135",
54		"EventName": "ITLB2_MISSES",
55		"BriefDescription": "ITLB2 Misses",
56		"PublicDescription": "A TLB2 miss is in progress for a request made by the instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle"
57	},
58	{
59		"Unit": "CPU-M-CF",
60		"EventCode": "136",
61		"EventName": "L1I_L2I_SOURCED_WRITES",
62		"BriefDescription": "L1I L2I Sourced Writes",
63		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache"
64	},
65	{
66		"Unit": "CPU-M-CF",
67		"EventCode": "137",
68		"EventName": "TLB2_PTE_WRITES",
69		"BriefDescription": "TLB2 PTE Writes",
70		"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB"
71	},
72	{
73		"Unit": "CPU-M-CF",
74		"EventCode": "138",
75		"EventName": "TLB2_CRSTE_WRITES",
76		"BriefDescription": "TLB2 CRSTE Writes",
77		"PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB"
78	},
79	{
80		"Unit": "CPU-M-CF",
81		"EventCode": "139",
82		"EventName": "TLB2_ENGINES_BUSY",
83		"BriefDescription": "TLB2 Engines Busy",
84		"PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle"
85	},
86	{
87		"Unit": "CPU-M-CF",
88		"EventCode": "140",
89		"EventName": "TX_C_TEND",
90		"BriefDescription": "Completed TEND instructions in constrained TX mode",
91		"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode"
92	},
93	{
94		"Unit": "CPU-M-CF",
95		"EventCode": "141",
96		"EventName": "TX_NC_TEND",
97		"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
98		"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode"
99	},
100	{
101		"Unit": "CPU-M-CF",
102		"EventCode": "143",
103		"EventName": "L1C_TLB2_MISSES",
104		"BriefDescription": "L1C TLB2 Misses",
105		"PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress"
106	},
107	{
108		"Unit": "CPU-M-CF",
109		"EventCode": "144",
110		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
111		"BriefDescription": "L1D On-Chip L3 Sourced Writes",
112		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention"
113	},
114	{
115		"Unit": "CPU-M-CF",
116		"EventCode": "145",
117		"EventName": "L1D_ONCHIP_MEMORY_SOURCED_WRITES",
118		"BriefDescription": "L1D On-Chip Memory Sourced Writes",
119		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory"
120	},
121	{
122		"Unit": "CPU-M-CF",
123		"EventCode": "146",
124		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
125		"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
126		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention"
127	},
128	{
129		"Unit": "CPU-M-CF",
130		"EventCode": "147",
131		"EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES",
132		"BriefDescription": "L1D On-Cluster L3 Sourced Writes",
133		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Cluster Level-3 cache withountervention"
134	},
135	{
136		"Unit": "CPU-M-CF",
137		"EventCode": "148",
138		"EventName": "L1D_ONCLUSTER_MEMORY_SOURCED_WRITES",
139		"BriefDescription": "L1D On-Cluster Memory Sourced Writes",
140		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster memory"
141	},
142	{
143		"Unit": "CPU-M-CF",
144		"EventCode": "149",
145		"EventName": "L1D_ONCLUSTER_L3_SOURCED_WRITES_IV",
146		"BriefDescription": "L1D On-Cluster L3 Sourced Writes with Intervention",
147		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache with intervention"
148	},
149	{
150		"Unit": "CPU-M-CF",
151		"EventCode": "150",
152		"EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES",
153		"BriefDescription": "L1D Off-Cluster L3 Sourced Writes",
154		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
155	},
156	{
157		"Unit": "CPU-M-CF",
158		"EventCode": "151",
159		"EventName": "L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES",
160		"BriefDescription": "L1D Off-Cluster Memory Sourced Writes",
161		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Cluster memory"
162	},
163	{
164		"Unit": "CPU-M-CF",
165		"EventCode": "152",
166		"EventName": "L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV",
167		"BriefDescription": "L1D Off-Cluster L3 Sourced Writes with Intervention",
168		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
169	},
170	{
171		"Unit": "CPU-M-CF",
172		"EventCode": "153",
173		"EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES",
174		"BriefDescription": "L1D Off-Drawer L3 Sourced Writes",
175		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
176	},
177	{
178		"Unit": "CPU-M-CF",
179		"EventCode": "154",
180		"EventName": "L1D_OFFDRAWER_MEMORY_SOURCED_WRITES",
181		"BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
182		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory"
183	},
184	{
185		"Unit": "CPU-M-CF",
186		"EventCode": "155",
187		"EventName": "L1D_OFFDRAWER_L3_SOURCED_WRITES_IV",
188		"BriefDescription": "L1D Off-Drawer L3 Sourced Writes with Intervention",
189		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
190	},
191	{
192		"Unit": "CPU-M-CF",
193		"EventCode": "156",
194		"EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
195		"BriefDescription": "L1D On-Drawer L4 Sourced Writes",
196		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
197	},
198	{
199		"Unit": "CPU-M-CF",
200		"EventCode": "157",
201		"EventName": "L1D_OFFDRAWER_L4_SOURCED_WRITES",
202		"BriefDescription": "L1D Off-Drawer L4 Sourced Writes",
203		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
204	},
205	{
206		"Unit": "CPU-M-CF",
207		"EventCode": "158",
208		"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_RO",
209		"BriefDescription": "L1D On-Chip L3 Sourced Writes read-only",
210		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip L3 but a read-only invalidate was done to remove other copies of the cache line"
211	},
212	{
213		"Unit": "CPU-M-CF",
214		"EventCode": "162",
215		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
216		"BriefDescription": "L1I On-Chip L3 Sourced Writes",
217		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache without intervention"
218	},
219	{
220		"Unit": "CPU-M-CF",
221		"EventCode": "163",
222		"EventName": "L1I_ONCHIP_MEMORY_SOURCED_WRITES",
223		"BriefDescription": "L1I On-Chip Memory Sourced Writes",
224		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from On-Chip memory"
225	},
226	{
227		"Unit": "CPU-M-CF",
228		"EventCode": "164",
229		"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
230		"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
231		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache ine was sourced from an On-Chip Level-3 cache with intervention"
232	},
233	{
234		"Unit": "CPU-M-CF",
235		"EventCode": "165",
236		"EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES",
237		"BriefDescription": "L1I On-Cluster L3 Sourced Writes",
238		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster Level-3 cache without intervention"
239	},
240	{
241		"Unit": "CPU-M-CF",
242		"EventCode": "166",
243		"EventName": "L1I_ONCLUSTER_MEMORY_SOURCED_WRITES",
244		"BriefDescription": "L1I On-Cluster Memory Sourced Writes",
245		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Cluster memory"
246	},
247	{
248		"Unit": "CPU-M-CF",
249		"EventCode": "167",
250		"EventName": "L1I_ONCLUSTER_L3_SOURCED_WRITES_IV",
251		"BriefDescription": "L1I On-Cluster L3 Sourced Writes with Intervention",
252		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Cluster Level-3 cache with intervention"
253	},
254	{
255		"Unit": "CPU-M-CF",
256		"EventCode": "168",
257		"EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES",
258		"BriefDescription": "L1I Off-Cluster L3 Sourced Writes",
259		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache without intervention"
260	},
261	{
262		"Unit": "CPU-M-CF",
263		"EventCode": "169",
264		"EventName": "L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES",
265		"BriefDescription": "L1I Off-Cluster Memory Sourced Writes",
266		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Cluster memory"
267	},
268	{
269		"Unit": "CPU-M-CF",
270		"EventCode": "170",
271		"EventName": "L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV",
272		"BriefDescription": "L1I Off-Cluster L3 Sourced Writes with Intervention",
273		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Cluster Level-3 cache with intervention"
274	},
275	{
276		"Unit": "CPU-M-CF",
277		"EventCode": "171",
278		"EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES",
279		"BriefDescription": "L1I Off-Drawer L3 Sourced Writes",
280		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache without intervention"
281	},
282	{
283		"Unit": "CPU-M-CF",
284		"EventCode": "172",
285		"EventName": "L1I_OFFDRAWER_MEMORY_SOURCED_WRITES",
286		"BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
287		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory"
288	},
289	{
290		"Unit": "CPU-M-CF",
291		"EventCode": "173",
292		"EventName": "L1I_OFFDRAWER_L3_SOURCED_WRITES_IV",
293		"BriefDescription": "L1I Off-Drawer L3 Sourced Writes with Intervention",
294		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-3 cache with intervention"
295	},
296	{
297		"Unit": "CPU-M-CF",
298		"EventCode": "174",
299		"EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
300		"BriefDescription": "L1I On-Drawer L4 Sourced Writes",
301		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer Level-4 cache"
302	},
303	{
304		"Unit": "CPU-M-CF",
305		"EventCode": "175",
306		"EventName": "L1I_OFFDRAWER_L4_SOURCED_WRITES",
307		"BriefDescription": "L1I Off-Drawer L4 Sourced Writes",
308		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer Level-4 cache"
309	},
310	{
311		"Unit": "CPU-M-CF",
312		"EventCode": "224",
313		"EventName": "BCD_DFP_EXECUTION_SLOTS",
314		"BriefDescription": "BCD DFP Execution Slots",
315		"PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT"
316	},
317	{
318		"Unit": "CPU-M-CF",
319		"EventCode": "225",
320		"EventName": "VX_BCD_EXECUTION_SLOTS",
321		"BriefDescription": "VX BCD Execution Slots",
322		"PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMPVMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOPVCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVDVCVDG"
323	},
324	{
325		"Unit": "CPU-M-CF",
326		"EventCode": "226",
327		"EventName": "DECIMAL_INSTRUCTIONS",
328		"BriefDescription": "Decimal Instructions",
329		"PublicDescription": "Decimal instructions dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP"
330	},
331	{
332		"Unit": "CPU-M-CF",
333		"EventCode": "232",
334		"EventName": "LAST_HOST_TRANSLATIONS",
335		"BriefDescription": "Last host translation done",
336		"PublicDescription": "Last Host Translation done"
337	},
338	{
339		"Unit": "CPU-M-CF",
340		"EventCode": "243",
341		"EventName": "TX_NC_TABORT",
342		"BriefDescription": "Aborted transactions in non-constrained TX mode",
343		"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode"
344	},
345	{
346		"Unit": "CPU-M-CF",
347		"EventCode": "244",
348		"EventName": "TX_C_TABORT_NO_SPECIAL",
349		"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
350		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete"
351	},
352	{
353		"Unit": "CPU-M-CF",
354		"EventCode": "245",
355		"EventName": "TX_C_TABORT_SPECIAL",
356		"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
357		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete"
358	},
359	{
360		"Unit": "CPU-M-CF",
361		"EventCode": "247",
362		"EventName": "DFLT_ACCESS",
363		"BriefDescription": "Cycles CPU spent obtaining access to Deflate unit",
364		"PublicDescription": "Cycles CPU spent obtaining access to Deflate unit"
365	},
366	{
367		"Unit": "CPU-M-CF",
368		"EventCode": "252",
369		"EventName": "DFLT_CYCLES",
370		"BriefDescription": "Cycles CPU is using Deflate unit",
371		"PublicDescription": "Cycles CPU is using Deflate unit"
372	},
373	{
374		"Unit": "CPU-M-CF",
375		"EventCode": "264",
376		"EventName": "DFLT_CC",
377		"BriefDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed",
378		"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed"
379	},
380	{
381		"Unit": "CPU-M-CF",
382		"EventCode": "265",
383		"EventName": "DFLT_CCERROR",
384		"BriefDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2",
385		"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2"
386	},
387	{
388		"Unit": "CPU-M-CF",
389		"EventCode": "448",
390		"EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
391		"BriefDescription": "Cycle count with one thread active",
392		"PublicDescription": "Cycle count with one thread active"
393	},
394	{
395		"Unit": "CPU-M-CF",
396		"EventCode": "449",
397		"EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
398		"BriefDescription": "Cycle count with two threads active",
399		"PublicDescription": "Cycle count with two threads active"
400	},
401]
402