1 /* 2 * Header for MultiMediaCard (MMC) 3 * 4 * Copyright 2002 Hewlett-Packard Company 5 * 6 * Use consistent with the GNU GPL is permitted, 7 * provided that this copyright notice is 8 * preserved in its entirety in all copies and derived works. 9 * 10 * HEWLETT-PACKARD COMPANY MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, 11 * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS 12 * FITNESS FOR ANY PARTICULAR PURPOSE. 13 * 14 * Many thanks to Alessandro Rubini and Jonathan Corbet! 15 * 16 * Based strongly on code by: 17 * 18 * Author: Yong-iL Joh <tolkien@mizi.com> 19 * 20 * Author: Andrew Christian 21 * 15 May 2002 22 */ 23 24 #ifndef LINUX_MMC_MMC_H 25 #define LINUX_MMC_MMC_H 26 27 #include <linux/types.h> 28 29 /* Standard MMC commands (4.1) type argument response */ 30 /* class 1 */ 31 #define MMC_GO_IDLE_STATE 0 /* bc */ 32 #define MMC_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */ 33 #define MMC_ALL_SEND_CID 2 /* bcr R2 */ 34 #define MMC_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */ 35 #define MMC_SET_DSR 4 /* bc [31:16] RCA */ 36 #define MMC_SLEEP_AWAKE 5 /* ac [31:16] RCA 15:flg R1b */ 37 #define MMC_SWITCH 6 /* ac [31:0] See below R1b */ 38 #define MMC_SELECT_CARD 7 /* ac [31:16] RCA R1 */ 39 #define MMC_SEND_EXT_CSD 8 /* adtc R1 */ 40 #define MMC_SEND_CSD 9 /* ac [31:16] RCA R2 */ 41 #define MMC_SEND_CID 10 /* ac [31:16] RCA R2 */ 42 #define MMC_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */ 43 #define MMC_STOP_TRANSMISSION 12 /* ac R1b */ 44 #define MMC_SEND_STATUS 13 /* ac [31:16] RCA R1 */ 45 #define MMC_BUS_TEST_R 14 /* adtc R1 */ 46 #define MMC_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */ 47 #define MMC_BUS_TEST_W 19 /* adtc R1 */ 48 #define MMC_SPI_READ_OCR 58 /* spi spi_R3 */ 49 #define MMC_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */ 50 51 /* class 2 */ 52 #define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */ 53 #define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */ 54 #define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */ 55 #define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */ 56 #define MMC_SEND_TUNING_BLOCK_HS200 21 /* adtc R1 */ 57 58 /* class 3 */ 59 #define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */ 60 61 /* class 4 */ 62 #define MMC_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */ 63 #define MMC_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */ 64 #define MMC_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */ 65 #define MMC_PROGRAM_CID 26 /* adtc R1 */ 66 #define MMC_PROGRAM_CSD 27 /* adtc R1 */ 67 68 /* class 6 */ 69 #define MMC_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */ 70 #define MMC_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */ 71 #define MMC_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */ 72 73 /* class 5 */ 74 #define MMC_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */ 75 #define MMC_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */ 76 #define MMC_ERASE 38 /* ac R1b */ 77 78 /* class 9 */ 79 #define MMC_FAST_IO 39 /* ac <Complex> R4 */ 80 #define MMC_GO_IRQ_STATE 40 /* bcr R5 */ 81 82 /* class 7 */ 83 #define MMC_LOCK_UNLOCK 42 /* adtc R1b */ 84 85 /* class 8 */ 86 #define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */ 87 #define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */ 88 89 /* class 11 */ 90 #define MMC_QUE_TASK_PARAMS 44 /* ac [20:16] task id R1 */ 91 #define MMC_QUE_TASK_ADDR 45 /* ac [31:0] data addr R1 */ 92 #define MMC_EXECUTE_READ_TASK 46 /* adtc [20:16] task id R1 */ 93 #define MMC_EXECUTE_WRITE_TASK 47 /* adtc [20:16] task id R1 */ 94 #define MMC_CMDQ_TASK_MGMT 48 /* ac [20:16] task id R1b */ 95 96 static inline bool mmc_op_multi(u32 opcode) 97 { 98 return opcode == MMC_WRITE_MULTIPLE_BLOCK || 99 opcode == MMC_READ_MULTIPLE_BLOCK; 100 } 101 102 /* 103 * MMC_SWITCH argument format: 104 * 105 * [31:26] Always 0 106 * [25:24] Access Mode 107 * [23:16] Location of target Byte in EXT_CSD 108 * [15:08] Value Byte 109 * [07:03] Always 0 110 * [02:00] Command Set 111 */ 112 113 /* 114 MMC status in R1, for native mode (SPI bits are different) 115 Type 116 e : error bit 117 s : status bit 118 r : detected and set for the actual command response 119 x : detected and set during command execution. the host must poll 120 the card by sending status command in order to read these bits. 121 Clear condition 122 a : according to the card state 123 b : always related to the previous command. Reception of 124 a valid command will clear it (with a delay of one command) 125 c : clear by read 126 */ 127 128 #define R1_OUT_OF_RANGE (1 << 31) /* er, c */ 129 #define R1_ADDRESS_ERROR (1 << 30) /* erx, c */ 130 #define R1_BLOCK_LEN_ERROR (1 << 29) /* er, c */ 131 #define R1_ERASE_SEQ_ERROR (1 << 28) /* er, c */ 132 #define R1_ERASE_PARAM (1 << 27) /* ex, c */ 133 #define R1_WP_VIOLATION (1 << 26) /* erx, c */ 134 #define R1_CARD_IS_LOCKED (1 << 25) /* sx, a */ 135 #define R1_LOCK_UNLOCK_FAILED (1 << 24) /* erx, c */ 136 #define R1_COM_CRC_ERROR (1 << 23) /* er, b */ 137 #define R1_ILLEGAL_COMMAND (1 << 22) /* er, b */ 138 #define R1_CARD_ECC_FAILED (1 << 21) /* ex, c */ 139 #define R1_CC_ERROR (1 << 20) /* erx, c */ 140 #define R1_ERROR (1 << 19) /* erx, c */ 141 #define R1_UNDERRUN (1 << 18) /* ex, c */ 142 #define R1_OVERRUN (1 << 17) /* ex, c */ 143 #define R1_CID_CSD_OVERWRITE (1 << 16) /* erx, c, CID/CSD overwrite */ 144 #define R1_WP_ERASE_SKIP (1 << 15) /* sx, c */ 145 #define R1_CARD_ECC_DISABLED (1 << 14) /* sx, a */ 146 #define R1_ERASE_RESET (1 << 13) /* sr, c */ 147 #define R1_STATUS(x) (x & 0xFFF9A000) 148 #define R1_CURRENT_STATE(x) ((x & 0x00001E00) >> 9) /* sx, b (4 bits) */ 149 #define R1_READY_FOR_DATA (1 << 8) /* sx, a */ 150 #define R1_SWITCH_ERROR (1 << 7) /* sx, c */ 151 #define R1_EXCEPTION_EVENT (1 << 6) /* sr, a */ 152 #define R1_APP_CMD (1 << 5) /* sr, c */ 153 154 #define R1_STATE_IDLE 0 155 #define R1_STATE_READY 1 156 #define R1_STATE_IDENT 2 157 #define R1_STATE_STBY 3 158 #define R1_STATE_TRAN 4 159 #define R1_STATE_DATA 5 160 #define R1_STATE_RCV 6 161 #define R1_STATE_PRG 7 162 #define R1_STATE_DIS 8 163 164 static inline bool mmc_ready_for_data(u32 status) 165 { 166 /* 167 * Some cards mishandle the status bits, so make sure to check both the 168 * busy indication and the card state. 169 */ 170 return status & R1_READY_FOR_DATA && 171 R1_CURRENT_STATE(status) == R1_STATE_TRAN; 172 } 173 174 /* 175 * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS 176 * R1 is the low order byte; R2 is the next highest byte, when present. 177 */ 178 #define R1_SPI_IDLE (1 << 0) 179 #define R1_SPI_ERASE_RESET (1 << 1) 180 #define R1_SPI_ILLEGAL_COMMAND (1 << 2) 181 #define R1_SPI_COM_CRC (1 << 3) 182 #define R1_SPI_ERASE_SEQ (1 << 4) 183 #define R1_SPI_ADDRESS (1 << 5) 184 #define R1_SPI_PARAMETER (1 << 6) 185 /* R1 bit 7 is always zero */ 186 #define R2_SPI_CARD_LOCKED (1 << 8) 187 #define R2_SPI_WP_ERASE_SKIP (1 << 9) /* or lock/unlock fail */ 188 #define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP 189 #define R2_SPI_ERROR (1 << 10) 190 #define R2_SPI_CC_ERROR (1 << 11) 191 #define R2_SPI_CARD_ECC_ERROR (1 << 12) 192 #define R2_SPI_WP_VIOLATION (1 << 13) 193 #define R2_SPI_ERASE_PARAM (1 << 14) 194 #define R2_SPI_OUT_OF_RANGE (1 << 15) /* or CSD overwrite */ 195 #define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE 196 197 /* 198 * OCR bits are mostly in host.h 199 */ 200 #define MMC_CARD_BUSY 0x80000000 /* Card Power up status bit */ 201 202 /* 203 * Card Command Classes (CCC) 204 */ 205 #define CCC_BASIC (1<<0) /* (0) Basic protocol functions */ 206 /* (CMD0,1,2,3,4,7,9,10,12,13,15) */ 207 /* (and for SPI, CMD58,59) */ 208 #define CCC_STREAM_READ (1<<1) /* (1) Stream read commands */ 209 /* (CMD11) */ 210 #define CCC_BLOCK_READ (1<<2) /* (2) Block read commands */ 211 /* (CMD16,17,18) */ 212 #define CCC_STREAM_WRITE (1<<3) /* (3) Stream write commands */ 213 /* (CMD20) */ 214 #define CCC_BLOCK_WRITE (1<<4) /* (4) Block write commands */ 215 /* (CMD16,24,25,26,27) */ 216 #define CCC_ERASE (1<<5) /* (5) Ability to erase blocks */ 217 /* (CMD32,33,34,35,36,37,38,39) */ 218 #define CCC_WRITE_PROT (1<<6) /* (6) Able to write protect blocks */ 219 /* (CMD28,29,30) */ 220 #define CCC_LOCK_CARD (1<<7) /* (7) Able to lock down card */ 221 /* (CMD16,CMD42) */ 222 #define CCC_APP_SPEC (1<<8) /* (8) Application specific */ 223 /* (CMD55,56,57,ACMD*) */ 224 #define CCC_IO_MODE (1<<9) /* (9) I/O mode */ 225 /* (CMD5,39,40,52,53) */ 226 #define CCC_SWITCH (1<<10) /* (10) High speed switch */ 227 /* (CMD6,34,35,36,37,50) */ 228 /* (11) Reserved */ 229 /* (CMD?) */ 230 231 /* 232 * CSD field definitions 233 */ 234 235 #define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */ 236 #define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */ 237 #define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */ 238 #define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */ 239 240 #define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */ 241 #define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */ 242 #define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */ 243 #define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */ 244 #define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */ 245 246 /* 247 * EXT_CSD fields 248 */ 249 250 #define EXT_CSD_CMDQ_MODE_EN 15 /* R/W */ 251 #define EXT_CSD_FLUSH_CACHE 32 /* W */ 252 #define EXT_CSD_CACHE_CTRL 33 /* R/W */ 253 #define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W */ 254 #define EXT_CSD_PACKED_FAILURE_INDEX 35 /* RO */ 255 #define EXT_CSD_PACKED_CMD_STATUS 36 /* RO */ 256 #define EXT_CSD_EXP_EVENTS_STATUS 54 /* RO, 2 bytes */ 257 #define EXT_CSD_EXP_EVENTS_CTRL 56 /* R/W, 2 bytes */ 258 #define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */ 259 #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */ 260 #define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */ 261 #define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */ 262 #define EXT_CSD_PARTITION_SUPPORT 160 /* RO */ 263 #define EXT_CSD_HPI_MGMT 161 /* R/W */ 264 #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ 265 #define EXT_CSD_BKOPS_EN 163 /* R/W */ 266 #define EXT_CSD_BKOPS_START 164 /* W */ 267 #define EXT_CSD_SANITIZE_START 165 /* W */ 268 #define EXT_CSD_WR_REL_PARAM 166 /* RO */ 269 #define EXT_CSD_RPMB_MULT 168 /* RO */ 270 #define EXT_CSD_FW_CONFIG 169 /* R/W */ 271 #define EXT_CSD_BOOT_WP 173 /* R/W */ 272 #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */ 273 #define EXT_CSD_PART_CONFIG 179 /* R/W */ 274 #define EXT_CSD_ERASED_MEM_CONT 181 /* RO */ 275 #define EXT_CSD_BUS_WIDTH 183 /* R/W */ 276 #define EXT_CSD_STROBE_SUPPORT 184 /* RO */ 277 #define EXT_CSD_HS_TIMING 185 /* R/W */ 278 #define EXT_CSD_POWER_CLASS 187 /* R/W */ 279 #define EXT_CSD_REV 192 /* RO */ 280 #define EXT_CSD_STRUCTURE 194 /* RO */ 281 #define EXT_CSD_CARD_TYPE 196 /* RO */ 282 #define EXT_CSD_DRIVER_STRENGTH 197 /* RO */ 283 #define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* RO */ 284 #define EXT_CSD_PART_SWITCH_TIME 199 /* RO */ 285 #define EXT_CSD_PWR_CL_52_195 200 /* RO */ 286 #define EXT_CSD_PWR_CL_26_195 201 /* RO */ 287 #define EXT_CSD_PWR_CL_52_360 202 /* RO */ 288 #define EXT_CSD_PWR_CL_26_360 203 /* RO */ 289 #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ 290 #define EXT_CSD_S_A_TIMEOUT 217 /* RO */ 291 #define EXT_CSD_REL_WR_SEC_C 222 /* RO */ 292 #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ 293 #define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */ 294 #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */ 295 #define EXT_CSD_BOOT_MULT 226 /* RO */ 296 #define EXT_CSD_SEC_TRIM_MULT 229 /* RO */ 297 #define EXT_CSD_SEC_ERASE_MULT 230 /* RO */ 298 #define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ 299 #define EXT_CSD_TRIM_MULT 232 /* RO */ 300 #define EXT_CSD_PWR_CL_200_195 236 /* RO */ 301 #define EXT_CSD_PWR_CL_200_360 237 /* RO */ 302 #define EXT_CSD_PWR_CL_DDR_52_195 238 /* RO */ 303 #define EXT_CSD_PWR_CL_DDR_52_360 239 /* RO */ 304 #define EXT_CSD_BKOPS_STATUS 246 /* RO */ 305 #define EXT_CSD_POWER_OFF_LONG_TIME 247 /* RO */ 306 #define EXT_CSD_GENERIC_CMD6_TIME 248 /* RO */ 307 #define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ 308 #define EXT_CSD_PWR_CL_DDR_200_360 253 /* RO */ 309 #define EXT_CSD_FIRMWARE_VERSION 254 /* RO, 8 bytes */ 310 #define EXT_CSD_PRE_EOL_INFO 267 /* RO */ 311 #define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* RO */ 312 #define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* RO */ 313 #define EXT_CSD_CMDQ_DEPTH 307 /* RO */ 314 #define EXT_CSD_CMDQ_SUPPORT 308 /* RO */ 315 #define EXT_CSD_SUPPORTED_MODE 493 /* RO */ 316 #define EXT_CSD_TAG_UNIT_SIZE 498 /* RO */ 317 #define EXT_CSD_DATA_TAG_SUPPORT 499 /* RO */ 318 #define EXT_CSD_MAX_PACKED_WRITES 500 /* RO */ 319 #define EXT_CSD_MAX_PACKED_READS 501 /* RO */ 320 #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */ 321 #define EXT_CSD_HPI_FEATURES 503 /* RO */ 322 323 /* 324 * EXT_CSD field definitions 325 */ 326 327 #define EXT_CSD_WR_REL_PARAM_EN (1<<2) 328 329 #define EXT_CSD_BOOT_WP_B_PWR_WP_DIS (0x40) 330 #define EXT_CSD_BOOT_WP_B_PERM_WP_DIS (0x10) 331 #define EXT_CSD_BOOT_WP_B_PERM_WP_EN (0x04) 332 #define EXT_CSD_BOOT_WP_B_PWR_WP_EN (0x01) 333 334 #define EXT_CSD_PART_CONFIG_ACC_MASK (0x7) 335 #define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1) 336 #define EXT_CSD_PART_CONFIG_ACC_RPMB (0x3) 337 #define EXT_CSD_PART_CONFIG_ACC_GP0 (0x4) 338 339 #define EXT_CSD_PART_SETTING_COMPLETED (0x1) 340 #define EXT_CSD_PART_SUPPORT_PART_EN (0x1) 341 342 #define EXT_CSD_CMD_SET_NORMAL (1<<0) 343 #define EXT_CSD_CMD_SET_SECURE (1<<1) 344 #define EXT_CSD_CMD_SET_CPSECURE (1<<2) 345 346 #define EXT_CSD_CARD_TYPE_HS_26 (1<<0) /* Card can run at 26MHz */ 347 #define EXT_CSD_CARD_TYPE_HS_52 (1<<1) /* Card can run at 52MHz */ 348 #define EXT_CSD_CARD_TYPE_HS (EXT_CSD_CARD_TYPE_HS_26 | \ 349 EXT_CSD_CARD_TYPE_HS_52) 350 #define EXT_CSD_CARD_TYPE_DDR_1_8V (1<<2) /* Card can run at 52MHz */ 351 /* DDR mode @1.8V or 3V I/O */ 352 #define EXT_CSD_CARD_TYPE_DDR_1_2V (1<<3) /* Card can run at 52MHz */ 353 /* DDR mode @1.2V I/O */ 354 #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \ 355 | EXT_CSD_CARD_TYPE_DDR_1_2V) 356 #define EXT_CSD_CARD_TYPE_HS200_1_8V (1<<4) /* Card can run at 200MHz */ 357 #define EXT_CSD_CARD_TYPE_HS200_1_2V (1<<5) /* Card can run at 200MHz */ 358 /* SDR mode @1.2V I/O */ 359 #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \ 360 EXT_CSD_CARD_TYPE_HS200_1_2V) 361 #define EXT_CSD_CARD_TYPE_HS400_1_8V (1<<6) /* Card can run at 200MHz DDR, 1.8V */ 362 #define EXT_CSD_CARD_TYPE_HS400_1_2V (1<<7) /* Card can run at 200MHz DDR, 1.2V */ 363 #define EXT_CSD_CARD_TYPE_HS400 (EXT_CSD_CARD_TYPE_HS400_1_8V | \ 364 EXT_CSD_CARD_TYPE_HS400_1_2V) 365 #define EXT_CSD_CARD_TYPE_HS400ES (1<<8) /* Card can run at HS400ES */ 366 367 #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */ 368 #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */ 369 #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */ 370 #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */ 371 #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */ 372 #define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */ 373 374 #define EXT_CSD_TIMING_BC 0 /* Backwards compatility */ 375 #define EXT_CSD_TIMING_HS 1 /* High speed */ 376 #define EXT_CSD_TIMING_HS200 2 /* HS200 */ 377 #define EXT_CSD_TIMING_HS400 3 /* HS400 */ 378 #define EXT_CSD_DRV_STR_SHIFT 4 /* Driver Strength shift */ 379 380 #define EXT_CSD_SEC_ER_EN BIT(0) 381 #define EXT_CSD_SEC_BD_BLK_EN BIT(2) 382 #define EXT_CSD_SEC_GB_CL_EN BIT(4) 383 #define EXT_CSD_SEC_SANITIZE BIT(6) /* v4.5 only */ 384 385 #define EXT_CSD_RST_N_EN_MASK 0x3 386 #define EXT_CSD_RST_N_ENABLED 1 /* RST_n is enabled on card */ 387 388 #define EXT_CSD_NO_POWER_NOTIFICATION 0 389 #define EXT_CSD_POWER_ON 1 390 #define EXT_CSD_POWER_OFF_SHORT 2 391 #define EXT_CSD_POWER_OFF_LONG 3 392 393 #define EXT_CSD_PWR_CL_8BIT_MASK 0xF0 /* 8 bit PWR CLS */ 394 #define EXT_CSD_PWR_CL_4BIT_MASK 0x0F /* 8 bit PWR CLS */ 395 #define EXT_CSD_PWR_CL_8BIT_SHIFT 4 396 #define EXT_CSD_PWR_CL_4BIT_SHIFT 0 397 398 #define EXT_CSD_PACKED_EVENT_EN BIT(3) 399 400 /* 401 * EXCEPTION_EVENT_STATUS field 402 */ 403 #define EXT_CSD_URGENT_BKOPS BIT(0) 404 #define EXT_CSD_DYNCAP_NEEDED BIT(1) 405 #define EXT_CSD_SYSPOOL_EXHAUSTED BIT(2) 406 #define EXT_CSD_PACKED_FAILURE BIT(3) 407 408 #define EXT_CSD_PACKED_GENERIC_ERROR BIT(0) 409 #define EXT_CSD_PACKED_INDEXED_ERROR BIT(1) 410 411 /* 412 * BKOPS status level 413 */ 414 #define EXT_CSD_BKOPS_LEVEL_2 0x2 415 416 /* 417 * BKOPS modes 418 */ 419 #define EXT_CSD_MANUAL_BKOPS_MASK 0x01 420 #define EXT_CSD_AUTO_BKOPS_MASK 0x02 421 422 /* 423 * Command Queue 424 */ 425 #define EXT_CSD_CMDQ_MODE_ENABLED BIT(0) 426 #define EXT_CSD_CMDQ_DEPTH_MASK GENMASK(4, 0) 427 #define EXT_CSD_CMDQ_SUPPORTED BIT(0) 428 429 /* 430 * MMC_SWITCH access modes 431 */ 432 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */ 433 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits which are 1 in value */ 434 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits which are 1 in value */ 435 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */ 436 437 /* 438 * Erase/trim/discard 439 */ 440 #define MMC_ERASE_ARG 0x00000000 441 #define MMC_SECURE_ERASE_ARG 0x80000000 442 #define MMC_TRIM_ARG 0x00000001 443 #define MMC_DISCARD_ARG 0x00000003 444 #define MMC_SECURE_TRIM1_ARG 0x80000001 445 #define MMC_SECURE_TRIM2_ARG 0x80008000 446 #define MMC_SECURE_ARGS 0x80000000 447 #define MMC_TRIM_ARGS 0x00008001 448 449 #define mmc_driver_type_mask(n) (1 << (n)) 450 451 #endif /* LINUX_MMC_MMC_H */ 452