1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 16 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 17 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 18 * USE OR OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 */ 25 /* 26 * Authors: Dave Airlie <airlied@redhat.com> 27 */ 28 29 #include <linux/pci.h> 30 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_crtc_helper.h> 33 #include <drm/drm_gem.h> 34 #include <drm/drm_gem_framebuffer_helper.h> 35 #include <drm/drm_gem_vram_helper.h> 36 37 #include "ast_drv.h" 38 39 void ast_set_index_reg_mask(struct ast_private *ast, 40 uint32_t base, uint8_t index, 41 uint8_t mask, uint8_t val) 42 { 43 u8 tmp; 44 ast_io_write8(ast, base, index); 45 tmp = (ast_io_read8(ast, base + 1) & mask) | val; 46 ast_set_index_reg(ast, base, index, tmp); 47 } 48 49 uint8_t ast_get_index_reg(struct ast_private *ast, 50 uint32_t base, uint8_t index) 51 { 52 uint8_t ret; 53 ast_io_write8(ast, base, index); 54 ret = ast_io_read8(ast, base + 1); 55 return ret; 56 } 57 58 uint8_t ast_get_index_reg_mask(struct ast_private *ast, 59 uint32_t base, uint8_t index, uint8_t mask) 60 { 61 uint8_t ret; 62 ast_io_write8(ast, base, index); 63 ret = ast_io_read8(ast, base + 1) & mask; 64 return ret; 65 } 66 67 static void ast_detect_config_mode(struct drm_device *dev, u32 *scu_rev) 68 { 69 struct device_node *np = dev->pdev->dev.of_node; 70 struct ast_private *ast = dev->dev_private; 71 uint32_t data, jregd0, jregd1; 72 73 /* Defaults */ 74 ast->config_mode = ast_use_defaults; 75 *scu_rev = 0xffffffff; 76 77 /* Check if we have device-tree properties */ 78 if (np && !of_property_read_u32(np, "aspeed,scu-revision-id", 79 scu_rev)) { 80 /* We do, disable P2A access */ 81 ast->config_mode = ast_use_dt; 82 DRM_INFO("Using device-tree for configuration\n"); 83 return; 84 } 85 86 /* Not all families have a P2A bridge */ 87 if (dev->pdev->device != PCI_CHIP_AST2000) 88 return; 89 90 /* 91 * The BMC will set SCU 0x40 D[12] to 1 if the P2 bridge 92 * is disabled. We force using P2A if VGA only mode bit 93 * is set D[7] 94 */ 95 jregd0 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 96 jregd1 = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 97 if (!(jregd0 & 0x80) || !(jregd1 & 0x10)) { 98 /* Double check it's actually working */ 99 data = ast_read32(ast, 0xf004); 100 if (data != 0xFFFFFFFF) { 101 /* P2A works, grab silicon revision */ 102 ast->config_mode = ast_use_p2a; 103 104 DRM_INFO("Using P2A bridge for configuration\n"); 105 106 /* Read SCU7c (silicon revision register) */ 107 ast_write32(ast, 0xf004, 0x1e6e0000); 108 ast_write32(ast, 0xf000, 0x1); 109 *scu_rev = ast_read32(ast, 0x1207c); 110 return; 111 } 112 } 113 114 /* We have a P2A bridge but it's disabled */ 115 DRM_INFO("P2A bridge disabled, using default configuration\n"); 116 } 117 118 static int ast_detect_chip(struct drm_device *dev, bool *need_post) 119 { 120 struct ast_private *ast = dev->dev_private; 121 uint32_t jreg, scu_rev; 122 123 /* 124 * If VGA isn't enabled, we need to enable now or subsequent 125 * access to the scratch registers will fail. We also inform 126 * our caller that it needs to POST the chip 127 * (Assumption: VGA not enabled -> need to POST) 128 */ 129 if (!ast_is_vga_enabled(dev)) { 130 ast_enable_vga(dev); 131 DRM_INFO("VGA not enabled on entry, requesting chip POST\n"); 132 *need_post = true; 133 } else 134 *need_post = false; 135 136 137 /* Enable extended register access */ 138 ast_open_key(ast); 139 ast_enable_mmio(dev); 140 141 /* Find out whether P2A works or whether to use device-tree */ 142 ast_detect_config_mode(dev, &scu_rev); 143 144 /* Identify chipset */ 145 if (dev->pdev->device == PCI_CHIP_AST1180) { 146 ast->chip = AST1100; 147 DRM_INFO("AST 1180 detected\n"); 148 } else { 149 if (dev->pdev->revision >= 0x40) { 150 ast->chip = AST2500; 151 DRM_INFO("AST 2500 detected\n"); 152 } else if (dev->pdev->revision >= 0x30) { 153 ast->chip = AST2400; 154 DRM_INFO("AST 2400 detected\n"); 155 } else if (dev->pdev->revision >= 0x20) { 156 ast->chip = AST2300; 157 DRM_INFO("AST 2300 detected\n"); 158 } else if (dev->pdev->revision >= 0x10) { 159 switch (scu_rev & 0x0300) { 160 case 0x0200: 161 ast->chip = AST1100; 162 DRM_INFO("AST 1100 detected\n"); 163 break; 164 case 0x0100: 165 ast->chip = AST2200; 166 DRM_INFO("AST 2200 detected\n"); 167 break; 168 case 0x0000: 169 ast->chip = AST2150; 170 DRM_INFO("AST 2150 detected\n"); 171 break; 172 default: 173 ast->chip = AST2100; 174 DRM_INFO("AST 2100 detected\n"); 175 break; 176 } 177 ast->vga2_clone = false; 178 } else { 179 ast->chip = AST2000; 180 DRM_INFO("AST 2000 detected\n"); 181 } 182 } 183 184 /* Check if we support wide screen */ 185 switch (ast->chip) { 186 case AST1180: 187 ast->support_wide_screen = true; 188 break; 189 case AST2000: 190 ast->support_wide_screen = false; 191 break; 192 default: 193 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff); 194 if (!(jreg & 0x80)) 195 ast->support_wide_screen = true; 196 else if (jreg & 0x01) 197 ast->support_wide_screen = true; 198 else { 199 ast->support_wide_screen = false; 200 if (ast->chip == AST2300 && 201 (scu_rev & 0x300) == 0x0) /* ast1300 */ 202 ast->support_wide_screen = true; 203 if (ast->chip == AST2400 && 204 (scu_rev & 0x300) == 0x100) /* ast1400 */ 205 ast->support_wide_screen = true; 206 if (ast->chip == AST2500 && 207 scu_rev == 0x100) /* ast2510 */ 208 ast->support_wide_screen = true; 209 } 210 break; 211 } 212 213 /* Check 3rd Tx option (digital output afaik) */ 214 ast->tx_chip_type = AST_TX_NONE; 215 216 /* 217 * VGACRA3 Enhanced Color Mode Register, check if DVO is already 218 * enabled, in that case, assume we have a SIL164 TMDS transmitter 219 * 220 * Don't make that assumption if we the chip wasn't enabled and 221 * is at power-on reset, otherwise we'll incorrectly "detect" a 222 * SIL164 when there is none. 223 */ 224 if (!*need_post) { 225 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff); 226 if (jreg & 0x80) 227 ast->tx_chip_type = AST_TX_SIL164; 228 } 229 230 if ((ast->chip == AST2300) || (ast->chip == AST2400)) { 231 /* 232 * On AST2300 and 2400, look the configuration set by the SoC in 233 * the SOC scratch register #1 bits 11:8 (interestingly marked 234 * as "reserved" in the spec) 235 */ 236 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff); 237 switch (jreg) { 238 case 0x04: 239 ast->tx_chip_type = AST_TX_SIL164; 240 break; 241 case 0x08: 242 ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL); 243 if (ast->dp501_fw_addr) { 244 /* backup firmware */ 245 if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) { 246 kfree(ast->dp501_fw_addr); 247 ast->dp501_fw_addr = NULL; 248 } 249 } 250 /* fallthrough */ 251 case 0x0c: 252 ast->tx_chip_type = AST_TX_DP501; 253 } 254 } 255 256 /* Print stuff for diagnostic purposes */ 257 switch(ast->tx_chip_type) { 258 case AST_TX_SIL164: 259 DRM_INFO("Using Sil164 TMDS transmitter\n"); 260 break; 261 case AST_TX_DP501: 262 DRM_INFO("Using DP501 DisplayPort transmitter\n"); 263 break; 264 default: 265 DRM_INFO("Analog VGA only\n"); 266 } 267 return 0; 268 } 269 270 static int ast_get_dram_info(struct drm_device *dev) 271 { 272 struct device_node *np = dev->pdev->dev.of_node; 273 struct ast_private *ast = dev->dev_private; 274 uint32_t mcr_cfg, mcr_scu_mpll, mcr_scu_strap; 275 uint32_t denum, num, div, ref_pll, dsel; 276 277 switch (ast->config_mode) { 278 case ast_use_dt: 279 /* 280 * If some properties are missing, use reasonable 281 * defaults for AST2400 282 */ 283 if (of_property_read_u32(np, "aspeed,mcr-configuration", 284 &mcr_cfg)) 285 mcr_cfg = 0x00000577; 286 if (of_property_read_u32(np, "aspeed,mcr-scu-mpll", 287 &mcr_scu_mpll)) 288 mcr_scu_mpll = 0x000050C0; 289 if (of_property_read_u32(np, "aspeed,mcr-scu-strap", 290 &mcr_scu_strap)) 291 mcr_scu_strap = 0; 292 break; 293 case ast_use_p2a: 294 ast_write32(ast, 0xf004, 0x1e6e0000); 295 ast_write32(ast, 0xf000, 0x1); 296 mcr_cfg = ast_read32(ast, 0x10004); 297 mcr_scu_mpll = ast_read32(ast, 0x10120); 298 mcr_scu_strap = ast_read32(ast, 0x10170); 299 break; 300 case ast_use_defaults: 301 default: 302 ast->dram_bus_width = 16; 303 ast->dram_type = AST_DRAM_1Gx16; 304 if (ast->chip == AST2500) 305 ast->mclk = 800; 306 else 307 ast->mclk = 396; 308 return 0; 309 } 310 311 if (mcr_cfg & 0x40) 312 ast->dram_bus_width = 16; 313 else 314 ast->dram_bus_width = 32; 315 316 if (ast->chip == AST2500) { 317 switch (mcr_cfg & 0x03) { 318 case 0: 319 ast->dram_type = AST_DRAM_1Gx16; 320 break; 321 default: 322 case 1: 323 ast->dram_type = AST_DRAM_2Gx16; 324 break; 325 case 2: 326 ast->dram_type = AST_DRAM_4Gx16; 327 break; 328 case 3: 329 ast->dram_type = AST_DRAM_8Gx16; 330 break; 331 } 332 } else if (ast->chip == AST2300 || ast->chip == AST2400) { 333 switch (mcr_cfg & 0x03) { 334 case 0: 335 ast->dram_type = AST_DRAM_512Mx16; 336 break; 337 default: 338 case 1: 339 ast->dram_type = AST_DRAM_1Gx16; 340 break; 341 case 2: 342 ast->dram_type = AST_DRAM_2Gx16; 343 break; 344 case 3: 345 ast->dram_type = AST_DRAM_4Gx16; 346 break; 347 } 348 } else { 349 switch (mcr_cfg & 0x0c) { 350 case 0: 351 case 4: 352 ast->dram_type = AST_DRAM_512Mx16; 353 break; 354 case 8: 355 if (mcr_cfg & 0x40) 356 ast->dram_type = AST_DRAM_1Gx16; 357 else 358 ast->dram_type = AST_DRAM_512Mx32; 359 break; 360 case 0xc: 361 ast->dram_type = AST_DRAM_1Gx32; 362 break; 363 } 364 } 365 366 if (mcr_scu_strap & 0x2000) 367 ref_pll = 14318; 368 else 369 ref_pll = 12000; 370 371 denum = mcr_scu_mpll & 0x1f; 372 num = (mcr_scu_mpll & 0x3fe0) >> 5; 373 dsel = (mcr_scu_mpll & 0xc000) >> 14; 374 switch (dsel) { 375 case 3: 376 div = 0x4; 377 break; 378 case 2: 379 case 1: 380 div = 0x2; 381 break; 382 default: 383 div = 0x1; 384 break; 385 } 386 ast->mclk = ref_pll * (num + 2) / ((denum + 2) * (div * 1000)); 387 return 0; 388 } 389 390 static const struct drm_mode_config_funcs ast_mode_funcs = { 391 .fb_create = drm_gem_fb_create, 392 .mode_valid = drm_vram_helper_mode_valid, 393 .atomic_check = drm_atomic_helper_check, 394 .atomic_commit = drm_atomic_helper_commit, 395 }; 396 397 static u32 ast_get_vram_info(struct drm_device *dev) 398 { 399 struct ast_private *ast = dev->dev_private; 400 u8 jreg; 401 u32 vram_size; 402 ast_open_key(ast); 403 404 vram_size = AST_VIDMEM_DEFAULT_SIZE; 405 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff); 406 switch (jreg & 3) { 407 case 0: vram_size = AST_VIDMEM_SIZE_8M; break; 408 case 1: vram_size = AST_VIDMEM_SIZE_16M; break; 409 case 2: vram_size = AST_VIDMEM_SIZE_32M; break; 410 case 3: vram_size = AST_VIDMEM_SIZE_64M; break; 411 } 412 413 jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff); 414 switch (jreg & 0x03) { 415 case 1: 416 vram_size -= 0x100000; 417 break; 418 case 2: 419 vram_size -= 0x200000; 420 break; 421 case 3: 422 vram_size -= 0x400000; 423 break; 424 } 425 426 return vram_size; 427 } 428 429 int ast_driver_load(struct drm_device *dev, unsigned long flags) 430 { 431 struct ast_private *ast; 432 bool need_post; 433 int ret = 0; 434 435 ast = kzalloc(sizeof(struct ast_private), GFP_KERNEL); 436 if (!ast) 437 return -ENOMEM; 438 439 dev->dev_private = ast; 440 ast->dev = dev; 441 442 ast->regs = pci_iomap(dev->pdev, 1, 0); 443 if (!ast->regs) { 444 ret = -EIO; 445 goto out_free; 446 } 447 448 /* 449 * If we don't have IO space at all, use MMIO now and 450 * assume the chip has MMIO enabled by default (rev 0x20 451 * and higher). 452 */ 453 if (!(pci_resource_flags(dev->pdev, 2) & IORESOURCE_IO)) { 454 DRM_INFO("platform has no IO space, trying MMIO\n"); 455 ast->ioregs = ast->regs + AST_IO_MM_OFFSET; 456 } 457 458 /* "map" IO regs if the above hasn't done so already */ 459 if (!ast->ioregs) { 460 ast->ioregs = pci_iomap(dev->pdev, 2, 0); 461 if (!ast->ioregs) { 462 ret = -EIO; 463 goto out_free; 464 } 465 } 466 467 ast_detect_chip(dev, &need_post); 468 469 if (need_post) 470 ast_post_gpu(dev); 471 472 if (ast->chip != AST1180) { 473 ret = ast_get_dram_info(dev); 474 if (ret) 475 goto out_free; 476 ast->vram_size = ast_get_vram_info(dev); 477 DRM_INFO("dram MCLK=%u Mhz type=%d bus_width=%d size=%08x\n", 478 ast->mclk, ast->dram_type, 479 ast->dram_bus_width, ast->vram_size); 480 } 481 482 ret = ast_mm_init(ast); 483 if (ret) 484 goto out_free; 485 486 drm_mode_config_init(dev); 487 488 dev->mode_config.funcs = (void *)&ast_mode_funcs; 489 dev->mode_config.min_width = 0; 490 dev->mode_config.min_height = 0; 491 dev->mode_config.preferred_depth = 24; 492 dev->mode_config.prefer_shadow = 1; 493 dev->mode_config.fb_base = pci_resource_start(ast->dev->pdev, 0); 494 495 if (ast->chip == AST2100 || 496 ast->chip == AST2200 || 497 ast->chip == AST2300 || 498 ast->chip == AST2400 || 499 ast->chip == AST2500 || 500 ast->chip == AST1180) { 501 dev->mode_config.max_width = 1920; 502 dev->mode_config.max_height = 2048; 503 } else { 504 dev->mode_config.max_width = 1600; 505 dev->mode_config.max_height = 1200; 506 } 507 508 ret = ast_mode_init(dev); 509 if (ret) 510 goto out_free; 511 512 drm_mode_config_reset(dev); 513 514 return 0; 515 out_free: 516 kfree(ast); 517 dev->dev_private = NULL; 518 return ret; 519 } 520 521 void ast_driver_unload(struct drm_device *dev) 522 { 523 struct ast_private *ast = dev->dev_private; 524 525 /* enable standard VGA decode */ 526 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x04); 527 528 ast_release_firmware(dev); 529 kfree(ast->dp501_fw_addr); 530 ast_mode_fini(dev); 531 drm_mode_config_cleanup(dev); 532 533 ast_mm_fini(ast); 534 if (ast->ioregs != ast->regs + AST_IO_MM_OFFSET) 535 pci_iounmap(dev->pdev, ast->ioregs); 536 pci_iounmap(dev->pdev, ast->regs); 537 kfree(ast); 538 } 539