1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 */ 5 6 #ifndef MLX5_IB_H 7 #define MLX5_IB_H 8 9 #include <linux/kernel.h> 10 #include <linux/sched.h> 11 #include <rdma/ib_verbs.h> 12 #include <rdma/ib_umem.h> 13 #include <rdma/ib_smi.h> 14 #include <linux/mlx5/driver.h> 15 #include <linux/mlx5/cq.h> 16 #include <linux/mlx5/fs.h> 17 #include <linux/mlx5/qp.h> 18 #include <linux/types.h> 19 #include <linux/mlx5/transobj.h> 20 #include <rdma/ib_user_verbs.h> 21 #include <rdma/mlx5-abi.h> 22 #include <rdma/uverbs_ioctl.h> 23 #include <rdma/mlx5_user_ioctl_cmds.h> 24 #include <rdma/mlx5_user_ioctl_verbs.h> 25 26 #include "srq.h" 27 28 #define mlx5_ib_dbg(_dev, format, arg...) \ 29 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 30 __LINE__, current->pid, ##arg) 31 32 #define mlx5_ib_err(_dev, format, arg...) \ 33 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 34 __LINE__, current->pid, ##arg) 35 36 #define mlx5_ib_warn(_dev, format, arg...) \ 37 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 38 __LINE__, current->pid, ##arg) 39 40 #define MLX5_IB_DEFAULT_UIDX 0xffffff 41 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 42 43 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size) 44 45 enum { 46 MLX5_IB_MMAP_OFFSET_START = 9, 47 MLX5_IB_MMAP_OFFSET_END = 255, 48 }; 49 50 enum { 51 MLX5_IB_MMAP_CMD_SHIFT = 8, 52 MLX5_IB_MMAP_CMD_MASK = 0xff, 53 }; 54 55 enum { 56 MLX5_RES_SCAT_DATA32_CQE = 0x1, 57 MLX5_RES_SCAT_DATA64_CQE = 0x2, 58 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 59 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 60 }; 61 62 enum mlx5_ib_mad_ifc_flags { 63 MLX5_MAD_IFC_IGNORE_MKEY = 1, 64 MLX5_MAD_IFC_IGNORE_BKEY = 2, 65 MLX5_MAD_IFC_NET_VIEW = 4, 66 }; 67 68 enum { 69 MLX5_CROSS_CHANNEL_BFREG = 0, 70 }; 71 72 enum { 73 MLX5_CQE_VERSION_V0, 74 MLX5_CQE_VERSION_V1, 75 }; 76 77 enum { 78 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 79 MLX5_TM_MAX_SGE = 1, 80 }; 81 82 enum { 83 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 84 MLX5_IB_INVALID_BFREG = BIT(31), 85 }; 86 87 enum { 88 MLX5_MAX_MEMIC_PAGES = 0x100, 89 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 90 }; 91 92 enum { 93 MLX5_MEMIC_BASE_ALIGN = 6, 94 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 95 }; 96 97 enum mlx5_ib_mmap_type { 98 MLX5_IB_MMAP_TYPE_MEMIC = 1, 99 MLX5_IB_MMAP_TYPE_VAR = 2, 100 MLX5_IB_MMAP_TYPE_UAR_WC = 3, 101 MLX5_IB_MMAP_TYPE_UAR_NC = 4, 102 }; 103 104 struct mlx5_bfreg_info { 105 u32 *sys_pages; 106 int num_low_latency_bfregs; 107 unsigned int *count; 108 109 /* 110 * protect bfreg allocation data structs 111 */ 112 struct mutex lock; 113 u32 ver; 114 u8 lib_uar_4k : 1; 115 u8 lib_uar_dyn : 1; 116 u32 num_sys_pages; 117 u32 num_static_sys_pages; 118 u32 total_num_bfregs; 119 u32 num_dyn_bfregs; 120 }; 121 122 struct mlx5_ib_ucontext { 123 struct ib_ucontext ibucontext; 124 struct list_head db_page_list; 125 126 /* protect doorbell record alloc/free 127 */ 128 struct mutex db_page_mutex; 129 struct mlx5_bfreg_info bfregi; 130 u8 cqe_version; 131 /* Transport Domain number */ 132 u32 tdn; 133 134 u64 lib_caps; 135 u16 devx_uid; 136 /* For RoCE LAG TX affinity */ 137 atomic_t tx_port_affinity; 138 }; 139 140 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 141 { 142 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 143 } 144 145 struct mlx5_ib_pd { 146 struct ib_pd ibpd; 147 u32 pdn; 148 u16 uid; 149 }; 150 151 enum { 152 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 153 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 154 MLX5_IB_FLOW_ACTION_DECAP, 155 }; 156 157 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 158 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 159 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 160 #error "Invalid number of bypass priorities" 161 #endif 162 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 163 164 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 165 #define MLX5_IB_NUM_SNIFFER_FTS 2 166 #define MLX5_IB_NUM_EGRESS_FTS 1 167 struct mlx5_ib_flow_prio { 168 struct mlx5_flow_table *flow_table; 169 unsigned int refcount; 170 }; 171 172 struct mlx5_ib_flow_handler { 173 struct list_head list; 174 struct ib_flow ibflow; 175 struct mlx5_ib_flow_prio *prio; 176 struct mlx5_flow_handle *rule; 177 struct ib_counters *ibcounters; 178 struct mlx5_ib_dev *dev; 179 struct mlx5_ib_flow_matcher *flow_matcher; 180 }; 181 182 struct mlx5_ib_flow_matcher { 183 struct mlx5_ib_match_params matcher_mask; 184 int mask_len; 185 enum mlx5_ib_flow_type flow_type; 186 enum mlx5_flow_namespace_type ns_type; 187 u16 priority; 188 struct mlx5_core_dev *mdev; 189 atomic_t usecnt; 190 u8 match_criteria_enable; 191 }; 192 193 struct mlx5_ib_pp { 194 u16 index; 195 struct mlx5_core_dev *mdev; 196 }; 197 198 struct mlx5_ib_flow_db { 199 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 200 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 201 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 202 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 203 struct mlx5_ib_flow_prio fdb; 204 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 205 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT]; 206 struct mlx5_flow_table *lag_demux_ft; 207 /* Protect flow steering bypass flow tables 208 * when add/del flow rules. 209 * only single add/removal of flow steering rule could be done 210 * simultaneously. 211 */ 212 struct mutex lock; 213 }; 214 215 /* Use macros here so that don't have to duplicate 216 * enum ib_send_flags and enum ib_qp_type for low-level driver 217 */ 218 219 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0) 220 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1) 221 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2) 222 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3) 223 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4) 224 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END 225 226 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 227 /* 228 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 229 * creates the actual hardware QP. 230 */ 231 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 232 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 233 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 234 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 235 236 #define MLX5_IB_UMR_OCTOWORD 16 237 #define MLX5_IB_UMR_XLT_ALIGNMENT 64 238 239 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 240 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 241 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 242 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 243 #define MLX5_IB_UPD_XLT_PD BIT(4) 244 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 245 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 246 247 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 248 * 249 * These flags are intended for internal use by the mlx5_ib driver, and they 250 * rely on the range reserved for that use in the ib_qp_create_flags enum. 251 */ 252 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 253 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1) 254 255 struct wr_list { 256 u16 opcode; 257 u16 next; 258 }; 259 260 enum mlx5_ib_rq_flags { 261 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 262 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 263 }; 264 265 struct mlx5_ib_wq { 266 struct mlx5_frag_buf_ctrl fbc; 267 u64 *wrid; 268 u32 *wr_data; 269 struct wr_list *w_list; 270 unsigned *wqe_head; 271 u16 unsig_count; 272 273 /* serialize post to the work queue 274 */ 275 spinlock_t lock; 276 int wqe_cnt; 277 int max_post; 278 int max_gs; 279 int offset; 280 int wqe_shift; 281 unsigned head; 282 unsigned tail; 283 u16 cur_post; 284 u16 last_poll; 285 void *cur_edge; 286 }; 287 288 enum mlx5_ib_wq_flags { 289 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 290 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 291 }; 292 293 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 294 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 295 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 296 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 297 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 298 299 struct mlx5_ib_rwq { 300 struct ib_wq ibwq; 301 struct mlx5_core_qp core_qp; 302 u32 rq_num_pas; 303 u32 log_rq_stride; 304 u32 log_rq_size; 305 u32 rq_page_offset; 306 u32 log_page_size; 307 u32 log_num_strides; 308 u32 two_byte_shift_en; 309 u32 single_stride_log_num_of_bytes; 310 struct ib_umem *umem; 311 size_t buf_size; 312 unsigned int page_shift; 313 struct mlx5_db db; 314 u32 user_index; 315 u32 wqe_count; 316 u32 wqe_shift; 317 int wq_sig; 318 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 319 }; 320 321 struct mlx5_ib_rwq_ind_table { 322 struct ib_rwq_ind_table ib_rwq_ind_tbl; 323 u32 rqtn; 324 u16 uid; 325 }; 326 327 struct mlx5_ib_ubuffer { 328 struct ib_umem *umem; 329 int buf_size; 330 u64 buf_addr; 331 }; 332 333 struct mlx5_ib_qp_base { 334 struct mlx5_ib_qp *container_mibqp; 335 struct mlx5_core_qp mqp; 336 struct mlx5_ib_ubuffer ubuffer; 337 }; 338 339 struct mlx5_ib_qp_trans { 340 struct mlx5_ib_qp_base base; 341 u16 xrcdn; 342 u8 alt_port; 343 u8 atomic_rd_en; 344 u8 resp_depth; 345 }; 346 347 struct mlx5_ib_rss_qp { 348 u32 tirn; 349 }; 350 351 struct mlx5_ib_rq { 352 struct mlx5_ib_qp_base base; 353 struct mlx5_ib_wq *rq; 354 struct mlx5_ib_ubuffer ubuffer; 355 struct mlx5_db *doorbell; 356 u32 tirn; 357 u8 state; 358 u32 flags; 359 }; 360 361 struct mlx5_ib_sq { 362 struct mlx5_ib_qp_base base; 363 struct mlx5_ib_wq *sq; 364 struct mlx5_ib_ubuffer ubuffer; 365 struct mlx5_db *doorbell; 366 struct mlx5_flow_handle *flow_rule; 367 u32 tisn; 368 u8 state; 369 }; 370 371 struct mlx5_ib_raw_packet_qp { 372 struct mlx5_ib_sq sq; 373 struct mlx5_ib_rq rq; 374 }; 375 376 struct mlx5_bf { 377 int buf_size; 378 unsigned long offset; 379 struct mlx5_sq_bfreg *bfreg; 380 }; 381 382 struct mlx5_ib_dct { 383 struct mlx5_core_dct mdct; 384 u32 *in; 385 }; 386 387 struct mlx5_ib_qp { 388 struct ib_qp ibqp; 389 union { 390 struct mlx5_ib_qp_trans trans_qp; 391 struct mlx5_ib_raw_packet_qp raw_packet_qp; 392 struct mlx5_ib_rss_qp rss_qp; 393 struct mlx5_ib_dct dct; 394 }; 395 struct mlx5_frag_buf buf; 396 397 struct mlx5_db db; 398 struct mlx5_ib_wq rq; 399 400 u8 sq_signal_bits; 401 u8 next_fence; 402 struct mlx5_ib_wq sq; 403 404 /* serialize qp state modifications 405 */ 406 struct mutex mutex; 407 /* cached variant of create_flags from struct ib_qp_init_attr */ 408 u32 flags; 409 u8 port; 410 u8 state; 411 int max_inline_data; 412 struct mlx5_bf bf; 413 u8 has_rq:1; 414 u8 is_rss:1; 415 416 /* only for user space QPs. For kernel 417 * we have it from the bf object 418 */ 419 int bfregn; 420 421 struct list_head qps_list; 422 struct list_head cq_recv_list; 423 struct list_head cq_send_list; 424 struct mlx5_rate_limit rl; 425 u32 underlay_qpn; 426 u32 flags_en; 427 /* 428 * IB/core doesn't store low-level QP types, so 429 * store both MLX and IBTA types in the field below. 430 * IB_QPT_DRIVER will be break to DCI/DCT subtypes. 431 */ 432 enum ib_qp_type type; 433 /* A flag to indicate if there's a new counter is configured 434 * but not take effective 435 */ 436 u32 counter_pending; 437 u16 gsi_lag_port; 438 }; 439 440 struct mlx5_ib_cq_buf { 441 struct mlx5_frag_buf_ctrl fbc; 442 struct mlx5_frag_buf frag_buf; 443 struct ib_umem *umem; 444 int cqe_size; 445 int nent; 446 }; 447 448 struct mlx5_umr_wr { 449 struct ib_send_wr wr; 450 u64 virt_addr; 451 u64 offset; 452 struct ib_pd *pd; 453 unsigned int page_shift; 454 unsigned int xlt_size; 455 u64 length; 456 int access_flags; 457 u32 mkey; 458 u8 ignore_free_state:1; 459 }; 460 461 static inline const struct mlx5_umr_wr *umr_wr(const struct ib_send_wr *wr) 462 { 463 return container_of(wr, struct mlx5_umr_wr, wr); 464 } 465 466 struct mlx5_shared_mr_info { 467 int mr_id; 468 struct ib_umem *umem; 469 }; 470 471 enum mlx5_ib_cq_pr_flags { 472 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 473 }; 474 475 struct mlx5_ib_cq { 476 struct ib_cq ibcq; 477 struct mlx5_core_cq mcq; 478 struct mlx5_ib_cq_buf buf; 479 struct mlx5_db db; 480 481 /* serialize access to the CQ 482 */ 483 spinlock_t lock; 484 485 /* protect resize cq 486 */ 487 struct mutex resize_mutex; 488 struct mlx5_ib_cq_buf *resize_buf; 489 struct ib_umem *resize_umem; 490 int cqe_size; 491 struct list_head list_send_qp; 492 struct list_head list_recv_qp; 493 u32 create_flags; 494 struct list_head wc_list; 495 enum ib_cq_notify_flags notify_flags; 496 struct work_struct notify_work; 497 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 498 }; 499 500 struct mlx5_ib_wc { 501 struct ib_wc wc; 502 struct list_head list; 503 }; 504 505 struct mlx5_ib_srq { 506 struct ib_srq ibsrq; 507 struct mlx5_core_srq msrq; 508 struct mlx5_frag_buf buf; 509 struct mlx5_db db; 510 struct mlx5_frag_buf_ctrl fbc; 511 u64 *wrid; 512 /* protect SRQ hanlding 513 */ 514 spinlock_t lock; 515 int head; 516 int tail; 517 u16 wqe_ctr; 518 struct ib_umem *umem; 519 /* serialize arming a SRQ 520 */ 521 struct mutex mutex; 522 int wq_sig; 523 }; 524 525 struct mlx5_ib_xrcd { 526 struct ib_xrcd ibxrcd; 527 u32 xrcdn; 528 }; 529 530 enum mlx5_ib_mtt_access_flags { 531 MLX5_IB_MTT_READ = (1 << 0), 532 MLX5_IB_MTT_WRITE = (1 << 1), 533 }; 534 535 struct mlx5_user_mmap_entry { 536 struct rdma_user_mmap_entry rdma_entry; 537 u8 mmap_flag; 538 u64 address; 539 u32 page_idx; 540 }; 541 542 struct mlx5_ib_dm { 543 struct ib_dm ibdm; 544 phys_addr_t dev_addr; 545 u32 type; 546 size_t size; 547 union { 548 struct { 549 u32 obj_id; 550 } icm_dm; 551 /* other dm types specific params should be added here */ 552 }; 553 struct mlx5_user_mmap_entry mentry; 554 }; 555 556 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 557 558 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 559 IB_ACCESS_REMOTE_WRITE |\ 560 IB_ACCESS_REMOTE_READ |\ 561 IB_ACCESS_REMOTE_ATOMIC |\ 562 IB_ZERO_BASED) 563 564 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 565 IB_ACCESS_REMOTE_WRITE |\ 566 IB_ACCESS_REMOTE_READ |\ 567 IB_ZERO_BASED) 568 569 #define mlx5_update_odp_stats(mr, counter_name, value) \ 570 atomic64_add(value, &((mr)->odp_stats.counter_name)) 571 572 struct mlx5_ib_mr { 573 struct ib_mr ibmr; 574 void *descs; 575 dma_addr_t desc_map; 576 int ndescs; 577 int data_length; 578 int meta_ndescs; 579 int meta_length; 580 int max_descs; 581 int desc_size; 582 int access_mode; 583 struct mlx5_core_mkey mmkey; 584 struct ib_umem *umem; 585 struct mlx5_shared_mr_info *smr_info; 586 struct list_head list; 587 unsigned int order; 588 struct mlx5_cache_ent *cache_ent; 589 int npages; 590 struct mlx5_ib_dev *dev; 591 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 592 struct mlx5_core_sig_ctx *sig; 593 void *descs_alloc; 594 int access_flags; /* Needed for rereg MR */ 595 596 struct mlx5_ib_mr *parent; 597 /* Needed for IB_MR_TYPE_INTEGRITY */ 598 struct mlx5_ib_mr *pi_mr; 599 struct mlx5_ib_mr *klm_mr; 600 struct mlx5_ib_mr *mtt_mr; 601 u64 data_iova; 602 u64 pi_iova; 603 604 /* For ODP and implicit */ 605 atomic_t num_deferred_work; 606 wait_queue_head_t q_deferred_work; 607 struct xarray implicit_children; 608 union { 609 struct rcu_head rcu; 610 struct list_head elm; 611 struct work_struct work; 612 } odp_destroy; 613 struct ib_odp_counters odp_stats; 614 bool is_odp_implicit; 615 616 struct mlx5_async_work cb_work; 617 }; 618 619 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 620 { 621 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 622 mr->umem->is_odp; 623 } 624 625 struct mlx5_ib_mw { 626 struct ib_mw ibmw; 627 struct mlx5_core_mkey mmkey; 628 int ndescs; 629 }; 630 631 struct mlx5_ib_devx_mr { 632 struct mlx5_core_mkey mmkey; 633 int ndescs; 634 }; 635 636 struct mlx5_ib_umr_context { 637 struct ib_cqe cqe; 638 enum ib_wc_status status; 639 struct completion done; 640 }; 641 642 struct umr_common { 643 struct ib_pd *pd; 644 struct ib_cq *cq; 645 struct ib_qp *qp; 646 /* control access to UMR QP 647 */ 648 struct semaphore sem; 649 }; 650 651 struct mlx5_cache_ent { 652 struct list_head head; 653 /* sync access to the cahce entry 654 */ 655 spinlock_t lock; 656 657 658 char name[4]; 659 u32 order; 660 u32 xlt; 661 u32 access_mode; 662 u32 page; 663 664 u8 disabled:1; 665 u8 fill_to_high_water:1; 666 667 /* 668 * - available_mrs is the length of list head, ie the number of MRs 669 * available for immediate allocation. 670 * - total_mrs is available_mrs plus all in use MRs that could be 671 * returned to the cache. 672 * - limit is the low water mark for available_mrs, 2* limit is the 673 * upper water mark. 674 * - pending is the number of MRs currently being created 675 */ 676 u32 total_mrs; 677 u32 available_mrs; 678 u32 limit; 679 u32 pending; 680 681 /* Statistics */ 682 u32 miss; 683 684 struct mlx5_ib_dev *dev; 685 struct work_struct work; 686 struct delayed_work dwork; 687 }; 688 689 struct mlx5_mr_cache { 690 struct workqueue_struct *wq; 691 struct mlx5_cache_ent ent[MAX_MR_CACHE_ENTRIES]; 692 struct dentry *root; 693 unsigned long last_add; 694 }; 695 696 struct mlx5_ib_gsi_qp; 697 698 struct mlx5_ib_port_resources { 699 struct mlx5_ib_resources *devr; 700 struct mlx5_ib_gsi_qp *gsi; 701 struct work_struct pkey_change_work; 702 }; 703 704 struct mlx5_ib_resources { 705 struct ib_cq *c0; 706 u32 xrcdn0; 707 u32 xrcdn1; 708 struct ib_pd *p0; 709 struct ib_srq *s0; 710 struct ib_srq *s1; 711 struct mlx5_ib_port_resources ports[2]; 712 /* Protects changes to the port resources */ 713 struct mutex mutex; 714 }; 715 716 struct mlx5_ib_counters { 717 const char **names; 718 size_t *offsets; 719 u32 num_q_counters; 720 u32 num_cong_counters; 721 u32 num_ext_ppcnt_counters; 722 u16 set_id; 723 }; 724 725 struct mlx5_ib_multiport_info; 726 727 struct mlx5_ib_multiport { 728 struct mlx5_ib_multiport_info *mpi; 729 /* To be held when accessing the multiport info */ 730 spinlock_t mpi_lock; 731 }; 732 733 struct mlx5_roce { 734 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 735 * netdev pointer 736 */ 737 rwlock_t netdev_lock; 738 struct net_device *netdev; 739 struct notifier_block nb; 740 atomic_t tx_port_affinity; 741 enum ib_port_state last_port_state; 742 struct mlx5_ib_dev *dev; 743 u8 native_port_num; 744 }; 745 746 struct mlx5_ib_port { 747 struct mlx5_ib_counters cnts; 748 struct mlx5_ib_multiport mp; 749 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 750 struct mlx5_roce roce; 751 struct mlx5_eswitch_rep *rep; 752 }; 753 754 struct mlx5_ib_dbg_param { 755 int offset; 756 struct mlx5_ib_dev *dev; 757 struct dentry *dentry; 758 u8 port_num; 759 }; 760 761 enum mlx5_ib_dbg_cc_types { 762 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 763 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 764 MLX5_IB_DBG_CC_RP_TIME_RESET, 765 MLX5_IB_DBG_CC_RP_BYTE_RESET, 766 MLX5_IB_DBG_CC_RP_THRESHOLD, 767 MLX5_IB_DBG_CC_RP_AI_RATE, 768 MLX5_IB_DBG_CC_RP_MAX_RATE, 769 MLX5_IB_DBG_CC_RP_HAI_RATE, 770 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 771 MLX5_IB_DBG_CC_RP_MIN_RATE, 772 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 773 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 774 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 775 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 776 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 777 MLX5_IB_DBG_CC_RP_GD, 778 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS, 779 MLX5_IB_DBG_CC_NP_CNP_DSCP, 780 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 781 MLX5_IB_DBG_CC_NP_CNP_PRIO, 782 MLX5_IB_DBG_CC_MAX, 783 }; 784 785 struct mlx5_ib_dbg_cc_params { 786 struct dentry *root; 787 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 788 }; 789 790 enum { 791 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 792 }; 793 794 struct mlx5_ib_delay_drop { 795 struct mlx5_ib_dev *dev; 796 struct work_struct delay_drop_work; 797 /* serialize setting of delay drop */ 798 struct mutex lock; 799 u32 timeout; 800 bool activate; 801 atomic_t events_cnt; 802 atomic_t rqs_cnt; 803 struct dentry *dir_debugfs; 804 }; 805 806 enum mlx5_ib_stages { 807 MLX5_IB_STAGE_INIT, 808 MLX5_IB_STAGE_FS, 809 MLX5_IB_STAGE_CAPS, 810 MLX5_IB_STAGE_NON_DEFAULT_CB, 811 MLX5_IB_STAGE_ROCE, 812 MLX5_IB_STAGE_QP, 813 MLX5_IB_STAGE_SRQ, 814 MLX5_IB_STAGE_DEVICE_RESOURCES, 815 MLX5_IB_STAGE_DEVICE_NOTIFIER, 816 MLX5_IB_STAGE_ODP, 817 MLX5_IB_STAGE_COUNTERS, 818 MLX5_IB_STAGE_CONG_DEBUGFS, 819 MLX5_IB_STAGE_UAR, 820 MLX5_IB_STAGE_BFREG, 821 MLX5_IB_STAGE_PRE_IB_REG_UMR, 822 MLX5_IB_STAGE_WHITELIST_UID, 823 MLX5_IB_STAGE_IB_REG, 824 MLX5_IB_STAGE_POST_IB_REG_UMR, 825 MLX5_IB_STAGE_DELAY_DROP, 826 MLX5_IB_STAGE_RESTRACK, 827 MLX5_IB_STAGE_MAX, 828 }; 829 830 struct mlx5_ib_stage { 831 int (*init)(struct mlx5_ib_dev *dev); 832 void (*cleanup)(struct mlx5_ib_dev *dev); 833 }; 834 835 #define STAGE_CREATE(_stage, _init, _cleanup) \ 836 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 837 838 struct mlx5_ib_profile { 839 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 840 }; 841 842 struct mlx5_ib_multiport_info { 843 struct list_head list; 844 struct mlx5_ib_dev *ibdev; 845 struct mlx5_core_dev *mdev; 846 struct notifier_block mdev_events; 847 struct completion unref_comp; 848 u64 sys_image_guid; 849 u32 mdev_refcnt; 850 bool is_master; 851 bool unaffiliate; 852 }; 853 854 struct mlx5_ib_flow_action { 855 struct ib_flow_action ib_action; 856 union { 857 struct { 858 u64 ib_flags; 859 struct mlx5_accel_esp_xfrm *ctx; 860 } esp_aes_gcm; 861 struct { 862 struct mlx5_ib_dev *dev; 863 u32 sub_type; 864 union { 865 struct mlx5_modify_hdr *modify_hdr; 866 struct mlx5_pkt_reformat *pkt_reformat; 867 }; 868 } flow_action_raw; 869 }; 870 }; 871 872 struct mlx5_dm { 873 struct mlx5_core_dev *dev; 874 /* This lock is used to protect the access to the shared 875 * allocation map when concurrent requests by different 876 * processes are handled. 877 */ 878 spinlock_t lock; 879 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 880 }; 881 882 struct mlx5_read_counters_attr { 883 struct mlx5_fc *hw_cntrs_hndl; 884 u64 *out; 885 u32 flags; 886 }; 887 888 enum mlx5_ib_counters_type { 889 MLX5_IB_COUNTERS_FLOW, 890 }; 891 892 struct mlx5_ib_mcounters { 893 struct ib_counters ibcntrs; 894 enum mlx5_ib_counters_type type; 895 /* number of counters supported for this counters type */ 896 u32 counters_num; 897 struct mlx5_fc *hw_cntrs_hndl; 898 /* read function for this counters type */ 899 int (*read_counters)(struct ib_device *ibdev, 900 struct mlx5_read_counters_attr *read_attr); 901 /* max index set as part of create_flow */ 902 u32 cntrs_max_index; 903 /* number of counters data entries (<description,index> pair) */ 904 u32 ncounters; 905 /* counters data array for descriptions and indexes */ 906 struct mlx5_ib_flow_counters_desc *counters_data; 907 /* protects access to mcounters internal data */ 908 struct mutex mcntrs_mutex; 909 }; 910 911 static inline struct mlx5_ib_mcounters * 912 to_mcounters(struct ib_counters *ibcntrs) 913 { 914 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 915 } 916 917 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 918 bool is_egress, 919 struct mlx5_flow_act *action); 920 struct mlx5_ib_lb_state { 921 /* protect the user_td */ 922 struct mutex mutex; 923 u32 user_td; 924 int qps; 925 bool enabled; 926 }; 927 928 struct mlx5_ib_pf_eq { 929 struct notifier_block irq_nb; 930 struct mlx5_ib_dev *dev; 931 struct mlx5_eq *core; 932 struct work_struct work; 933 spinlock_t lock; /* Pagefaults spinlock */ 934 struct workqueue_struct *wq; 935 mempool_t *pool; 936 }; 937 938 struct mlx5_devx_event_table { 939 struct mlx5_nb devx_nb; 940 /* serialize updating the event_xa */ 941 struct mutex event_xa_lock; 942 struct xarray event_xa; 943 }; 944 945 struct mlx5_var_table { 946 /* serialize updating the bitmap */ 947 struct mutex bitmap_lock; 948 unsigned long *bitmap; 949 u64 hw_start_addr; 950 u32 stride_size; 951 u64 num_var_hw_entries; 952 }; 953 954 struct mlx5_ib_dev { 955 struct ib_device ib_dev; 956 struct mlx5_core_dev *mdev; 957 struct notifier_block mdev_events; 958 int num_ports; 959 /* serialize update of capability mask 960 */ 961 struct mutex cap_mask_mutex; 962 u8 ib_active:1; 963 u8 is_rep:1; 964 u8 lag_active:1; 965 u8 wc_support:1; 966 u8 fill_delay; 967 struct umr_common umrc; 968 /* sync used page count stats 969 */ 970 struct mlx5_ib_resources devr; 971 972 atomic_t mkey_var; 973 struct mlx5_mr_cache cache; 974 struct timer_list delay_timer; 975 /* Prevents soft lock on massive reg MRs */ 976 struct mutex slow_path_mutex; 977 struct ib_odp_caps odp_caps; 978 u64 odp_max_size; 979 struct mlx5_ib_pf_eq odp_pf_eq; 980 981 /* 982 * Sleepable RCU that prevents destruction of MRs while they are still 983 * being used by a page fault handler. 984 */ 985 struct srcu_struct odp_srcu; 986 struct xarray odp_mkeys; 987 988 u32 null_mkey; 989 struct mlx5_ib_flow_db *flow_db; 990 /* protect resources needed as part of reset flow */ 991 spinlock_t reset_flow_resource_lock; 992 struct list_head qp_list; 993 /* Array with num_ports elements */ 994 struct mlx5_ib_port *port; 995 struct mlx5_sq_bfreg bfreg; 996 struct mlx5_sq_bfreg wc_bfreg; 997 struct mlx5_sq_bfreg fp_bfreg; 998 struct mlx5_ib_delay_drop delay_drop; 999 const struct mlx5_ib_profile *profile; 1000 1001 struct mlx5_ib_lb_state lb; 1002 u8 umr_fence; 1003 struct list_head ib_dev_list; 1004 u64 sys_image_guid; 1005 struct mlx5_dm dm; 1006 u16 devx_whitelist_uid; 1007 struct mlx5_srq_table srq_table; 1008 struct mlx5_qp_table qp_table; 1009 struct mlx5_async_ctx async_ctx; 1010 struct mlx5_devx_event_table devx_event_table; 1011 struct mlx5_var_table var_table; 1012 1013 struct xarray sig_mrs; 1014 }; 1015 1016 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1017 { 1018 return container_of(mcq, struct mlx5_ib_cq, mcq); 1019 } 1020 1021 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1022 { 1023 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1024 } 1025 1026 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1027 { 1028 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1029 } 1030 1031 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1032 { 1033 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1034 udata, struct mlx5_ib_ucontext, ibucontext); 1035 1036 return to_mdev(context->ibucontext.device); 1037 } 1038 1039 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1040 { 1041 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1042 } 1043 1044 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1045 { 1046 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1047 } 1048 1049 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1050 { 1051 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1052 } 1053 1054 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1055 { 1056 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1057 } 1058 1059 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1060 { 1061 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1062 } 1063 1064 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1065 { 1066 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1067 } 1068 1069 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1070 { 1071 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1072 } 1073 1074 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1075 { 1076 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1077 } 1078 1079 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1080 { 1081 return container_of(msrq, struct mlx5_ib_srq, msrq); 1082 } 1083 1084 static inline struct mlx5_ib_dm *to_mdm(struct ib_dm *ibdm) 1085 { 1086 return container_of(ibdm, struct mlx5_ib_dm, ibdm); 1087 } 1088 1089 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1090 { 1091 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1092 } 1093 1094 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1095 { 1096 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1097 } 1098 1099 static inline struct mlx5_ib_flow_action * 1100 to_mflow_act(struct ib_flow_action *ibact) 1101 { 1102 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1103 } 1104 1105 static inline struct mlx5_user_mmap_entry * 1106 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1107 { 1108 return container_of(rdma_entry, 1109 struct mlx5_user_mmap_entry, rdma_entry); 1110 } 1111 1112 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, 1113 struct ib_udata *udata, unsigned long virt, 1114 struct mlx5_db *db); 1115 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1116 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1117 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1118 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1119 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1120 struct ib_udata *udata); 1121 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); 1122 void mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags); 1123 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1124 struct ib_udata *udata); 1125 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1126 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1127 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1128 void mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1129 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1130 const struct ib_recv_wr **bad_wr); 1131 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1132 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1133 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd, 1134 struct ib_qp_init_attr *init_attr, 1135 struct ib_udata *udata); 1136 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1137 int attr_mask, struct ib_udata *udata); 1138 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1139 struct ib_qp_init_attr *qp_init_attr); 1140 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1141 void mlx5_ib_drain_sq(struct ib_qp *qp); 1142 void mlx5_ib_drain_rq(struct ib_qp *qp); 1143 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1144 size_t buflen, size_t *bc); 1145 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1146 size_t buflen, size_t *bc); 1147 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1148 size_t buflen, size_t *bc); 1149 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1150 struct ib_udata *udata); 1151 void mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1152 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1153 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1154 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1155 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1156 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1157 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1158 u64 virt_addr, int access_flags, 1159 struct ib_udata *udata); 1160 int mlx5_ib_advise_mr(struct ib_pd *pd, 1161 enum ib_uverbs_advise_mr_advice advice, 1162 u32 flags, 1163 struct ib_sge *sg_list, 1164 u32 num_sge, 1165 struct uverbs_attr_bundle *attrs); 1166 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, 1167 struct ib_udata *udata); 1168 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1169 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages, 1170 int page_shift, int flags); 1171 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1172 struct ib_udata *udata, 1173 int access_flags); 1174 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr); 1175 void mlx5_ib_fence_odp_mr(struct mlx5_ib_mr *mr); 1176 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1177 u64 length, u64 virt_addr, int access_flags, 1178 struct ib_pd *pd, struct ib_udata *udata); 1179 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1180 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1181 u32 max_num_sg); 1182 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1183 u32 max_num_sg, 1184 u32 max_num_meta_sg); 1185 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1186 unsigned int *sg_offset); 1187 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1188 int data_sg_nents, unsigned int *data_sg_offset, 1189 struct scatterlist *meta_sg, int meta_sg_nents, 1190 unsigned int *meta_sg_offset); 1191 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u8 port_num, 1192 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1193 const struct ib_mad *in, struct ib_mad *out, 1194 size_t *out_mad_size, u16 *out_mad_pkey_index); 1195 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1196 void mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1197 int mlx5_ib_get_buf_offset(u64 addr, int page_shift, u32 *offset); 1198 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, u8 port); 1199 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device *ibdev, 1200 struct ib_smp *out_mad); 1201 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1202 __be64 *sys_image_guid); 1203 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1204 u16 *max_pkeys); 1205 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1206 u32 *vendor_id); 1207 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1208 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1209 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u8 port, u16 index, 1210 u16 *pkey); 1211 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u8 port, int index, 1212 union ib_gid *gid); 1213 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u8 port, 1214 struct ib_port_attr *props); 1215 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 1216 struct ib_port_attr *props); 1217 void mlx5_ib_cont_pages(struct ib_umem *umem, u64 addr, 1218 unsigned long max_page_shift, 1219 int *count, int *shift, 1220 int *ncont, int *order); 1221 void __mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1222 int page_shift, size_t offset, size_t num_pages, 1223 __be64 *pas, int access_flags); 1224 void mlx5_ib_populate_pas(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1225 int page_shift, __be64 *pas, int access_flags); 1226 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num); 1227 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1228 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev); 1229 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev); 1230 1231 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 1232 unsigned int entry); 1233 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr); 1234 int mlx5_mr_cache_invalidate(struct mlx5_ib_mr *mr); 1235 1236 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1237 struct ib_mr_status *mr_status); 1238 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1239 struct ib_wq_init_attr *init_attr, 1240 struct ib_udata *udata); 1241 void mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1242 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1243 u32 wq_attr_mask, struct ib_udata *udata); 1244 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device, 1245 struct ib_rwq_ind_table_init_attr *init_attr, 1246 struct ib_udata *udata); 1247 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1248 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev, 1249 struct ib_ucontext *context, 1250 struct ib_dm_alloc_attr *attr, 1251 struct uverbs_attr_bundle *attrs); 1252 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm, struct uverbs_attr_bundle *attrs); 1253 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1254 struct ib_dm_mr_attr *attr, 1255 struct uverbs_attr_bundle *attrs); 1256 1257 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1258 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev); 1259 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1260 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1261 int __init mlx5_ib_odp_init(void); 1262 void mlx5_ib_odp_cleanup(void); 1263 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent); 1264 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1265 struct mlx5_ib_mr *mr, int flags); 1266 1267 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1268 enum ib_uverbs_advise_mr_advice advice, 1269 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1270 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1271 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev) 1272 { 1273 return; 1274 } 1275 1276 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } 1277 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} 1278 static inline int mlx5_ib_odp_init(void) { return 0; } 1279 static inline void mlx5_ib_odp_cleanup(void) {} 1280 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent) {} 1281 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1282 struct mlx5_ib_mr *mr, int flags) {} 1283 1284 static inline int 1285 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1286 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1287 struct ib_sge *sg_list, u32 num_sge) 1288 { 1289 return -EOPNOTSUPP; 1290 } 1291 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1292 1293 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1294 1295 /* Needed for rep profile */ 1296 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1297 const struct mlx5_ib_profile *profile, 1298 int stage); 1299 void *__mlx5_ib_add(struct mlx5_ib_dev *dev, 1300 const struct mlx5_ib_profile *profile); 1301 1302 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1303 u8 port, struct ifla_vf_info *info); 1304 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1305 u8 port, int state); 1306 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1307 u8 port, struct ifla_vf_stats *stats); 1308 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u8 port, 1309 struct ifla_vf_guid *node_guid, 1310 struct ifla_vf_guid *port_guid); 1311 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u8 port, 1312 u64 guid, int type); 1313 1314 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 1315 const struct ib_gid_attr *attr); 1316 1317 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1318 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u8 port_num); 1319 1320 /* GSI QP helper functions */ 1321 struct ib_qp *mlx5_ib_gsi_create_qp(struct ib_pd *pd, 1322 struct ib_qp_init_attr *init_attr); 1323 int mlx5_ib_gsi_destroy_qp(struct ib_qp *qp); 1324 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1325 int attr_mask); 1326 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1327 int qp_attr_mask, 1328 struct ib_qp_init_attr *qp_init_attr); 1329 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1330 const struct ib_send_wr **bad_wr); 1331 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1332 const struct ib_recv_wr **bad_wr); 1333 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1334 1335 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1336 1337 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1338 int bfregn); 1339 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1340 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1341 u8 ib_port_num, 1342 u8 *native_port_num); 1343 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1344 u8 port_num); 1345 1346 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1347 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1348 extern const struct uapi_definition mlx5_ib_qos_defs[]; 1349 extern const struct uapi_definition mlx5_ib_std_types_defs[]; 1350 1351 static inline void init_query_mad(struct ib_smp *mad) 1352 { 1353 mad->base_version = 1; 1354 mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED; 1355 mad->class_version = 1; 1356 mad->method = IB_MGMT_METHOD_GET; 1357 } 1358 1359 static inline int is_qp1(enum ib_qp_type qp_type) 1360 { 1361 return qp_type == MLX5_IB_QPT_HW_GSI; 1362 } 1363 1364 #define MLX5_MAX_UMR_SHIFT 16 1365 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT) 1366 1367 static inline u32 check_cq_create_flags(u32 flags) 1368 { 1369 /* 1370 * It returns non-zero value for unsupported CQ 1371 * create flags, otherwise it returns zero. 1372 */ 1373 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1374 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1375 } 1376 1377 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1378 u32 *user_index) 1379 { 1380 if (cqe_version) { 1381 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1382 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1383 return -EINVAL; 1384 *user_index = cmd_uidx; 1385 } else { 1386 *user_index = MLX5_IB_DEFAULT_UIDX; 1387 } 1388 1389 return 0; 1390 } 1391 1392 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1393 struct mlx5_ib_create_qp *ucmd, 1394 int inlen, 1395 u32 *user_index) 1396 { 1397 u8 cqe_version = ucontext->cqe_version; 1398 1399 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1400 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1401 return 0; 1402 1403 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1404 return -EINVAL; 1405 1406 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1407 } 1408 1409 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1410 struct mlx5_ib_create_srq *ucmd, 1411 int inlen, 1412 u32 *user_index) 1413 { 1414 u8 cqe_version = ucontext->cqe_version; 1415 1416 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1417 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1418 return 0; 1419 1420 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1421 return -EINVAL; 1422 1423 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1424 } 1425 1426 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1427 { 1428 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1429 MLX5_UARS_IN_PAGE : 1; 1430 } 1431 1432 static inline int get_num_static_uars(struct mlx5_ib_dev *dev, 1433 struct mlx5_bfreg_info *bfregi) 1434 { 1435 return get_uars_per_sys_page(dev, bfregi->lib_uar_4k) * bfregi->num_static_sys_pages; 1436 } 1437 1438 unsigned long mlx5_ib_get_xlt_emergency_page(void); 1439 void mlx5_ib_put_xlt_emergency_page(void); 1440 1441 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1442 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1443 bool dyn_bfreg); 1444 1445 static inline bool mlx5_ib_can_use_umr(struct mlx5_ib_dev *dev, 1446 bool do_modify_atomic, int access_flags) 1447 { 1448 if (MLX5_CAP_GEN(dev->mdev, umr_modify_entity_size_disabled)) 1449 return false; 1450 1451 if (do_modify_atomic && 1452 MLX5_CAP_GEN(dev->mdev, atomic) && 1453 MLX5_CAP_GEN(dev->mdev, umr_modify_atomic_disabled)) 1454 return false; 1455 1456 if (access_flags & IB_ACCESS_RELAXED_ORDERING && 1457 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write) && 1458 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_write_umr)) 1459 return false; 1460 1461 if (access_flags & IB_ACCESS_RELAXED_ORDERING && 1462 MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read) && 1463 !MLX5_CAP_GEN(dev->mdev, relaxed_ordering_read_umr)) 1464 return false; 1465 1466 return true; 1467 } 1468 1469 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev); 1470 1471 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) 1472 { 1473 return dev->lag_active || 1474 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && 1475 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity)); 1476 } 1477 #endif /* MLX5_IB_H */ 1478