1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2014 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8 /* 9 * Table for showing the current message id in use for particular level 10 * Change this table for addition of log/debug messages. 11 * ---------------------------------------------------------------------- 12 * | Level | Last Value Used | Holes | 13 * ---------------------------------------------------------------------- 14 * | Module Init and Probe | 0x0193 | 0x0146 | 15 * | | | 0x015b-0x0160 | 16 * | | | 0x016e | 17 * | Mailbox commands | 0x1206 | 0x11a2-0x11ff | 18 * | Device Discovery | 0x2134 | 0x210e-0x2116 | 19 * | | | 0x211a | 20 * | | | 0x211c-0x2128 | 21 * | | | 0x212a-0x2134 | 22 * | Queue Command and IO tracing | 0x3074 | 0x300b | 23 * | | | 0x3027-0x3028 | 24 * | | | 0x303d-0x3041 | 25 * | | | 0x302d,0x3033 | 26 * | | | 0x3036,0x3038 | 27 * | | | 0x303a | 28 * | DPC Thread | 0x4023 | 0x4002,0x4013 | 29 * | Async Events | 0x5090 | 0x502b-0x502f | 30 * | | | 0x5047 | 31 * | | | 0x5084,0x5075 | 32 * | | | 0x503d,0x5044 | 33 * | | | 0x505f | 34 * | Timer Routines | 0x6012 | | 35 * | User Space Interactions | 0x70e3 | 0x7018,0x702e | 36 * | | | 0x7020,0x7024 | 37 * | | | 0x7039,0x7045 | 38 * | | | 0x7073-0x7075 | 39 * | | | 0x70a5-0x70a6 | 40 * | | | 0x70a8,0x70ab | 41 * | | | 0x70ad-0x70ae | 42 * | | | 0x70d0-0x70d6 | 43 * | | | 0x70d7-0x70db | 44 * | Task Management | 0x8042 | 0x8000 | 45 * | | | 0x8019 | 46 * | | | 0x8025,0x8026 | 47 * | | | 0x8031,0x8032 | 48 * | | | 0x8039,0x803c | 49 * | AER/EEH | 0x9011 | | 50 * | Virtual Port | 0xa007 | | 51 * | ISP82XX Specific | 0xb157 | 0xb002,0xb024 | 52 * | | | 0xb09e,0xb0ae | 53 * | | | 0xb0c3,0xb0c6 | 54 * | | | 0xb0e0-0xb0ef | 55 * | | | 0xb085,0xb0dc | 56 * | | | 0xb107,0xb108 | 57 * | | | 0xb111,0xb11e | 58 * | | | 0xb12c,0xb12d | 59 * | | | 0xb13a,0xb142 | 60 * | | | 0xb13c-0xb140 | 61 * | | | 0xb149 | 62 * | MultiQ | 0xc010 | | 63 * | Misc | 0xd303 | 0xd031-0xd0ff | 64 * | | | 0xd101-0xd1fe | 65 * | | | 0xd214-0xd2fe | 66 * | Target Mode | 0xe081 | | 67 * | Target Mode Management | 0xf09b | 0xf002 | 68 * | | | 0xf046-0xf049 | 69 * | Target Mode Task Management | 0x1000d | | 70 * ---------------------------------------------------------------------- 71 */ 72 73 #include "qla_def.h" 74 75 #include <linux/delay.h> 76 #define CREATE_TRACE_POINTS 77 #include <trace/events/qla.h> 78 79 static uint32_t ql_dbg_offset = 0x800; 80 81 static inline void 82 qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) 83 { 84 fw_dump->fw_major_version = htonl(ha->fw_major_version); 85 fw_dump->fw_minor_version = htonl(ha->fw_minor_version); 86 fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); 87 fw_dump->fw_attributes = htonl(ha->fw_attributes); 88 89 fw_dump->vendor = htonl(ha->pdev->vendor); 90 fw_dump->device = htonl(ha->pdev->device); 91 fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); 92 fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); 93 } 94 95 static inline void * 96 qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) 97 { 98 struct req_que *req = ha->req_q_map[0]; 99 struct rsp_que *rsp = ha->rsp_q_map[0]; 100 /* Request queue. */ 101 memcpy(ptr, req->ring, req->length * 102 sizeof(request_t)); 103 104 /* Response queue. */ 105 ptr += req->length * sizeof(request_t); 106 memcpy(ptr, rsp->ring, rsp->length * 107 sizeof(response_t)); 108 109 return ptr + (rsp->length * sizeof(response_t)); 110 } 111 112 int 113 qla27xx_dump_mpi_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, 114 uint32_t ram_dwords, void **nxt) 115 { 116 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 117 dma_addr_t dump_dma = ha->gid_list_dma; 118 uint32_t *chunk = (uint32_t *)ha->gid_list; 119 uint32_t dwords = qla2x00_gid_list_size(ha) / 4; 120 uint32_t stat; 121 ulong i, j, timer = 6000000; 122 int rval = QLA_FUNCTION_FAILED; 123 124 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 125 for (i = 0; i < ram_dwords; i += dwords, addr += dwords) { 126 if (i + dwords > ram_dwords) 127 dwords = ram_dwords - i; 128 129 wrt_reg_word(®->mailbox0, MBC_LOAD_DUMP_MPI_RAM); 130 wrt_reg_word(®->mailbox1, LSW(addr)); 131 wrt_reg_word(®->mailbox8, MSW(addr)); 132 133 wrt_reg_word(®->mailbox2, MSW(LSD(dump_dma))); 134 wrt_reg_word(®->mailbox3, LSW(LSD(dump_dma))); 135 wrt_reg_word(®->mailbox6, MSW(MSD(dump_dma))); 136 wrt_reg_word(®->mailbox7, LSW(MSD(dump_dma))); 137 138 wrt_reg_word(®->mailbox4, MSW(dwords)); 139 wrt_reg_word(®->mailbox5, LSW(dwords)); 140 141 wrt_reg_word(®->mailbox9, 0); 142 wrt_reg_dword(®->hccr, HCCRX_SET_HOST_INT); 143 144 ha->flags.mbox_int = 0; 145 while (timer--) { 146 udelay(5); 147 148 stat = rd_reg_dword(®->host_status); 149 /* Check for pending interrupts. */ 150 if (!(stat & HSRX_RISC_INT)) 151 continue; 152 153 stat &= 0xff; 154 if (stat != 0x1 && stat != 0x2 && 155 stat != 0x10 && stat != 0x11) { 156 157 /* Clear this intr; it wasn't a mailbox intr */ 158 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT); 159 rd_reg_dword(®->hccr); 160 continue; 161 } 162 163 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 164 rval = rd_reg_word(®->mailbox0) & MBS_MASK; 165 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT); 166 rd_reg_dword(®->hccr); 167 break; 168 } 169 ha->flags.mbox_int = 1; 170 *nxt = ram + i; 171 172 if (!test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 173 /* no interrupt, timed out*/ 174 return rval; 175 } 176 if (rval) { 177 /* error completion status */ 178 return rval; 179 } 180 for (j = 0; j < dwords; j++) { 181 ram[i + j] = 182 (IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? 183 chunk[j] : swab32(chunk[j]); 184 } 185 } 186 187 *nxt = ram + i; 188 return QLA_SUCCESS; 189 } 190 191 int 192 qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, __be32 *ram, 193 uint32_t ram_dwords, void **nxt) 194 { 195 int rval = QLA_FUNCTION_FAILED; 196 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 197 dma_addr_t dump_dma = ha->gid_list_dma; 198 uint32_t *chunk = (uint32_t *)ha->gid_list; 199 uint32_t dwords = qla2x00_gid_list_size(ha) / 4; 200 uint32_t stat; 201 ulong i, j, timer = 6000000; 202 203 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 204 205 for (i = 0; i < ram_dwords; i += dwords, addr += dwords) { 206 if (i + dwords > ram_dwords) 207 dwords = ram_dwords - i; 208 209 wrt_reg_word(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); 210 wrt_reg_word(®->mailbox1, LSW(addr)); 211 wrt_reg_word(®->mailbox8, MSW(addr)); 212 213 wrt_reg_word(®->mailbox2, MSW(LSD(dump_dma))); 214 wrt_reg_word(®->mailbox3, LSW(LSD(dump_dma))); 215 wrt_reg_word(®->mailbox6, MSW(MSD(dump_dma))); 216 wrt_reg_word(®->mailbox7, LSW(MSD(dump_dma))); 217 218 wrt_reg_word(®->mailbox4, MSW(dwords)); 219 wrt_reg_word(®->mailbox5, LSW(dwords)); 220 wrt_reg_dword(®->hccr, HCCRX_SET_HOST_INT); 221 222 ha->flags.mbox_int = 0; 223 while (timer--) { 224 udelay(5); 225 stat = rd_reg_dword(®->host_status); 226 227 /* Check for pending interrupts. */ 228 if (!(stat & HSRX_RISC_INT)) 229 continue; 230 231 stat &= 0xff; 232 if (stat != 0x1 && stat != 0x2 && 233 stat != 0x10 && stat != 0x11) { 234 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT); 235 rd_reg_dword(®->hccr); 236 continue; 237 } 238 239 set_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 240 rval = rd_reg_word(®->mailbox0) & MBS_MASK; 241 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_INT); 242 rd_reg_dword(®->hccr); 243 break; 244 } 245 ha->flags.mbox_int = 1; 246 *nxt = ram + i; 247 248 if (!test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 249 /* no interrupt, timed out*/ 250 return rval; 251 } 252 if (rval) { 253 /* error completion status */ 254 return rval; 255 } 256 for (j = 0; j < dwords; j++) { 257 ram[i + j] = (__force __be32) 258 ((IS_QLA27XX(ha) || IS_QLA28XX(ha)) ? 259 chunk[j] : swab32(chunk[j])); 260 } 261 } 262 263 *nxt = ram + i; 264 return QLA_SUCCESS; 265 } 266 267 static int 268 qla24xx_dump_memory(struct qla_hw_data *ha, __be32 *code_ram, 269 uint32_t cram_size, void **nxt) 270 { 271 int rval; 272 273 /* Code RAM. */ 274 rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); 275 if (rval != QLA_SUCCESS) 276 return rval; 277 278 set_bit(RISC_SRAM_DUMP_CMPL, &ha->fw_dump_cap_flags); 279 280 /* External Memory. */ 281 rval = qla24xx_dump_ram(ha, 0x100000, *nxt, 282 ha->fw_memory_size - 0x100000 + 1, nxt); 283 if (rval == QLA_SUCCESS) 284 set_bit(RISC_EXT_MEM_DUMP_CMPL, &ha->fw_dump_cap_flags); 285 286 return rval; 287 } 288 289 static __be32 * 290 qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, 291 uint32_t count, __be32 *buf) 292 { 293 __le32 __iomem *dmp_reg; 294 295 wrt_reg_dword(®->iobase_addr, iobase); 296 dmp_reg = ®->iobase_window; 297 for ( ; count--; dmp_reg++) 298 *buf++ = htonl(rd_reg_dword(dmp_reg)); 299 300 return buf; 301 } 302 303 void 304 qla24xx_pause_risc(struct device_reg_24xx __iomem *reg, struct qla_hw_data *ha) 305 { 306 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_PAUSE); 307 308 /* 100 usec delay is sufficient enough for hardware to pause RISC */ 309 udelay(100); 310 if (rd_reg_dword(®->host_status) & HSRX_RISC_PAUSED) 311 set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags); 312 } 313 314 int 315 qla24xx_soft_reset(struct qla_hw_data *ha) 316 { 317 int rval = QLA_SUCCESS; 318 uint32_t cnt; 319 uint16_t wd; 320 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 321 322 /* 323 * Reset RISC. The delay is dependent on system architecture. 324 * Driver can proceed with the reset sequence after waiting 325 * for a timeout period. 326 */ 327 wrt_reg_dword(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 328 for (cnt = 0; cnt < 30000; cnt++) { 329 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 330 break; 331 332 udelay(10); 333 } 334 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)) 335 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); 336 337 wrt_reg_dword(®->ctrl_status, 338 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 339 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 340 341 udelay(100); 342 343 /* Wait for soft-reset to complete. */ 344 for (cnt = 0; cnt < 30000; cnt++) { 345 if ((rd_reg_dword(®->ctrl_status) & 346 CSRX_ISP_SOFT_RESET) == 0) 347 break; 348 349 udelay(10); 350 } 351 if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) 352 set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags); 353 354 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_RESET); 355 rd_reg_dword(®->hccr); /* PCI Posting. */ 356 357 for (cnt = 10000; rd_reg_word(®->mailbox0) != 0 && 358 rval == QLA_SUCCESS; cnt--) { 359 if (cnt) 360 udelay(10); 361 else 362 rval = QLA_FUNCTION_TIMEOUT; 363 } 364 if (rval == QLA_SUCCESS) 365 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); 366 367 return rval; 368 } 369 370 static int 371 qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, __be16 *ram, 372 uint32_t ram_words, void **nxt) 373 { 374 int rval; 375 uint32_t cnt, stat, timer, words, idx; 376 uint16_t mb0; 377 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 378 dma_addr_t dump_dma = ha->gid_list_dma; 379 __le16 *dump = (__force __le16 *)ha->gid_list; 380 381 rval = QLA_SUCCESS; 382 mb0 = 0; 383 384 WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); 385 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 386 387 words = qla2x00_gid_list_size(ha) / 2; 388 for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; 389 cnt += words, addr += words) { 390 if (cnt + words > ram_words) 391 words = ram_words - cnt; 392 393 WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); 394 WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); 395 396 WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); 397 WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); 398 WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); 399 WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); 400 401 WRT_MAILBOX_REG(ha, reg, 4, words); 402 wrt_reg_word(®->hccr, HCCR_SET_HOST_INT); 403 404 for (timer = 6000000; timer; timer--) { 405 /* Check for pending interrupts. */ 406 stat = rd_reg_dword(®->u.isp2300.host_status); 407 if (stat & HSR_RISC_INT) { 408 stat &= 0xff; 409 410 if (stat == 0x1 || stat == 0x2) { 411 set_bit(MBX_INTERRUPT, 412 &ha->mbx_cmd_flags); 413 414 mb0 = RD_MAILBOX_REG(ha, reg, 0); 415 416 /* Release mailbox registers. */ 417 wrt_reg_word(®->semaphore, 0); 418 wrt_reg_word(®->hccr, 419 HCCR_CLR_RISC_INT); 420 rd_reg_word(®->hccr); 421 break; 422 } else if (stat == 0x10 || stat == 0x11) { 423 set_bit(MBX_INTERRUPT, 424 &ha->mbx_cmd_flags); 425 426 mb0 = RD_MAILBOX_REG(ha, reg, 0); 427 428 wrt_reg_word(®->hccr, 429 HCCR_CLR_RISC_INT); 430 rd_reg_word(®->hccr); 431 break; 432 } 433 434 /* clear this intr; it wasn't a mailbox intr */ 435 wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT); 436 rd_reg_word(®->hccr); 437 } 438 udelay(5); 439 } 440 441 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 442 rval = mb0 & MBS_MASK; 443 for (idx = 0; idx < words; idx++) 444 ram[cnt + idx] = 445 cpu_to_be16(le16_to_cpu(dump[idx])); 446 } else { 447 rval = QLA_FUNCTION_FAILED; 448 } 449 } 450 451 *nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL; 452 return rval; 453 } 454 455 static inline void 456 qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, 457 __be16 *buf) 458 { 459 __le16 __iomem *dmp_reg = ®->u.isp2300.fb_cmd; 460 461 for ( ; count--; dmp_reg++) 462 *buf++ = htons(rd_reg_word(dmp_reg)); 463 } 464 465 static inline void * 466 qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) 467 { 468 if (!ha->eft) 469 return ptr; 470 471 memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); 472 return ptr + ntohl(ha->fw_dump->eft_size); 473 } 474 475 static inline void * 476 qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, __be32 **last_chain) 477 { 478 uint32_t cnt; 479 __be32 *iter_reg; 480 struct qla2xxx_fce_chain *fcec = ptr; 481 482 if (!ha->fce) 483 return ptr; 484 485 *last_chain = &fcec->type; 486 fcec->type = htonl(DUMP_CHAIN_FCE); 487 fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + 488 fce_calc_size(ha->fce_bufs)); 489 fcec->size = htonl(fce_calc_size(ha->fce_bufs)); 490 fcec->addr_l = htonl(LSD(ha->fce_dma)); 491 fcec->addr_h = htonl(MSD(ha->fce_dma)); 492 493 iter_reg = fcec->eregs; 494 for (cnt = 0; cnt < 8; cnt++) 495 *iter_reg++ = htonl(ha->fce_mb[cnt]); 496 497 memcpy(iter_reg, ha->fce, ntohl(fcec->size)); 498 499 return (char *)iter_reg + ntohl(fcec->size); 500 } 501 502 static inline void * 503 qla25xx_copy_exlogin(struct qla_hw_data *ha, void *ptr, __be32 **last_chain) 504 { 505 struct qla2xxx_offld_chain *c = ptr; 506 507 if (!ha->exlogin_buf) 508 return ptr; 509 510 *last_chain = &c->type; 511 512 c->type = cpu_to_be32(DUMP_CHAIN_EXLOGIN); 513 c->chain_size = cpu_to_be32(sizeof(struct qla2xxx_offld_chain) + 514 ha->exlogin_size); 515 c->size = cpu_to_be32(ha->exlogin_size); 516 c->addr = cpu_to_be64(ha->exlogin_buf_dma); 517 518 ptr += sizeof(struct qla2xxx_offld_chain); 519 memcpy(ptr, ha->exlogin_buf, ha->exlogin_size); 520 521 return (char *)ptr + be32_to_cpu(c->size); 522 } 523 524 static inline void * 525 qla81xx_copy_exchoffld(struct qla_hw_data *ha, void *ptr, __be32 **last_chain) 526 { 527 struct qla2xxx_offld_chain *c = ptr; 528 529 if (!ha->exchoffld_buf) 530 return ptr; 531 532 *last_chain = &c->type; 533 534 c->type = cpu_to_be32(DUMP_CHAIN_EXCHG); 535 c->chain_size = cpu_to_be32(sizeof(struct qla2xxx_offld_chain) + 536 ha->exchoffld_size); 537 c->size = cpu_to_be32(ha->exchoffld_size); 538 c->addr = cpu_to_be64(ha->exchoffld_buf_dma); 539 540 ptr += sizeof(struct qla2xxx_offld_chain); 541 memcpy(ptr, ha->exchoffld_buf, ha->exchoffld_size); 542 543 return (char *)ptr + be32_to_cpu(c->size); 544 } 545 546 static inline void * 547 qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr, 548 __be32 **last_chain) 549 { 550 struct qla2xxx_mqueue_chain *q; 551 struct qla2xxx_mqueue_header *qh; 552 uint32_t num_queues; 553 int que; 554 struct { 555 int length; 556 void *ring; 557 } aq, *aqp; 558 559 if (!ha->tgt.atio_ring) 560 return ptr; 561 562 num_queues = 1; 563 aqp = &aq; 564 aqp->length = ha->tgt.atio_q_length; 565 aqp->ring = ha->tgt.atio_ring; 566 567 for (que = 0; que < num_queues; que++) { 568 /* aqp = ha->atio_q_map[que]; */ 569 q = ptr; 570 *last_chain = &q->type; 571 q->type = htonl(DUMP_CHAIN_QUEUE); 572 q->chain_size = htonl( 573 sizeof(struct qla2xxx_mqueue_chain) + 574 sizeof(struct qla2xxx_mqueue_header) + 575 (aqp->length * sizeof(request_t))); 576 ptr += sizeof(struct qla2xxx_mqueue_chain); 577 578 /* Add header. */ 579 qh = ptr; 580 qh->queue = htonl(TYPE_ATIO_QUEUE); 581 qh->number = htonl(que); 582 qh->size = htonl(aqp->length * sizeof(request_t)); 583 ptr += sizeof(struct qla2xxx_mqueue_header); 584 585 /* Add data. */ 586 memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t)); 587 588 ptr += aqp->length * sizeof(request_t); 589 } 590 591 return ptr; 592 } 593 594 static inline void * 595 qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, __be32 **last_chain) 596 { 597 struct qla2xxx_mqueue_chain *q; 598 struct qla2xxx_mqueue_header *qh; 599 struct req_que *req; 600 struct rsp_que *rsp; 601 int que; 602 603 if (!ha->mqenable) 604 return ptr; 605 606 /* Request queues */ 607 for (que = 1; que < ha->max_req_queues; que++) { 608 req = ha->req_q_map[que]; 609 if (!req) 610 break; 611 612 /* Add chain. */ 613 q = ptr; 614 *last_chain = &q->type; 615 q->type = htonl(DUMP_CHAIN_QUEUE); 616 q->chain_size = htonl( 617 sizeof(struct qla2xxx_mqueue_chain) + 618 sizeof(struct qla2xxx_mqueue_header) + 619 (req->length * sizeof(request_t))); 620 ptr += sizeof(struct qla2xxx_mqueue_chain); 621 622 /* Add header. */ 623 qh = ptr; 624 qh->queue = htonl(TYPE_REQUEST_QUEUE); 625 qh->number = htonl(que); 626 qh->size = htonl(req->length * sizeof(request_t)); 627 ptr += sizeof(struct qla2xxx_mqueue_header); 628 629 /* Add data. */ 630 memcpy(ptr, req->ring, req->length * sizeof(request_t)); 631 ptr += req->length * sizeof(request_t); 632 } 633 634 /* Response queues */ 635 for (que = 1; que < ha->max_rsp_queues; que++) { 636 rsp = ha->rsp_q_map[que]; 637 if (!rsp) 638 break; 639 640 /* Add chain. */ 641 q = ptr; 642 *last_chain = &q->type; 643 q->type = htonl(DUMP_CHAIN_QUEUE); 644 q->chain_size = htonl( 645 sizeof(struct qla2xxx_mqueue_chain) + 646 sizeof(struct qla2xxx_mqueue_header) + 647 (rsp->length * sizeof(response_t))); 648 ptr += sizeof(struct qla2xxx_mqueue_chain); 649 650 /* Add header. */ 651 qh = ptr; 652 qh->queue = htonl(TYPE_RESPONSE_QUEUE); 653 qh->number = htonl(que); 654 qh->size = htonl(rsp->length * sizeof(response_t)); 655 ptr += sizeof(struct qla2xxx_mqueue_header); 656 657 /* Add data. */ 658 memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t)); 659 ptr += rsp->length * sizeof(response_t); 660 } 661 662 return ptr; 663 } 664 665 static inline void * 666 qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, __be32 **last_chain) 667 { 668 uint32_t cnt, que_idx; 669 uint8_t que_cnt; 670 struct qla2xxx_mq_chain *mq = ptr; 671 device_reg_t *reg; 672 673 if (!ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 674 IS_QLA28XX(ha)) 675 return ptr; 676 677 mq = ptr; 678 *last_chain = &mq->type; 679 mq->type = htonl(DUMP_CHAIN_MQ); 680 mq->chain_size = htonl(sizeof(struct qla2xxx_mq_chain)); 681 682 que_cnt = ha->max_req_queues > ha->max_rsp_queues ? 683 ha->max_req_queues : ha->max_rsp_queues; 684 mq->count = htonl(que_cnt); 685 for (cnt = 0; cnt < que_cnt; cnt++) { 686 reg = ISP_QUE_REG(ha, cnt); 687 que_idx = cnt * 4; 688 mq->qregs[que_idx] = 689 htonl(rd_reg_dword(®->isp25mq.req_q_in)); 690 mq->qregs[que_idx+1] = 691 htonl(rd_reg_dword(®->isp25mq.req_q_out)); 692 mq->qregs[que_idx+2] = 693 htonl(rd_reg_dword(®->isp25mq.rsp_q_in)); 694 mq->qregs[que_idx+3] = 695 htonl(rd_reg_dword(®->isp25mq.rsp_q_out)); 696 } 697 698 return ptr + sizeof(struct qla2xxx_mq_chain); 699 } 700 701 void 702 qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) 703 { 704 struct qla_hw_data *ha = vha->hw; 705 706 if (rval != QLA_SUCCESS) { 707 ql_log(ql_log_warn, vha, 0xd000, 708 "Failed to dump firmware (%x), dump status flags (0x%lx).\n", 709 rval, ha->fw_dump_cap_flags); 710 ha->fw_dumped = false; 711 } else { 712 ql_log(ql_log_info, vha, 0xd001, 713 "Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n", 714 vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags); 715 ha->fw_dumped = true; 716 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 717 } 718 } 719 720 void qla2xxx_dump_fw(scsi_qla_host_t *vha) 721 { 722 unsigned long flags; 723 724 spin_lock_irqsave(&vha->hw->hardware_lock, flags); 725 vha->hw->isp_ops->fw_dump(vha); 726 spin_unlock_irqrestore(&vha->hw->hardware_lock, flags); 727 } 728 729 /** 730 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. 731 * @vha: HA context 732 */ 733 void 734 qla2300_fw_dump(scsi_qla_host_t *vha) 735 { 736 int rval; 737 uint32_t cnt; 738 struct qla_hw_data *ha = vha->hw; 739 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 740 __le16 __iomem *dmp_reg; 741 struct qla2300_fw_dump *fw; 742 void *nxt; 743 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 744 745 lockdep_assert_held(&ha->hardware_lock); 746 747 if (!ha->fw_dump) { 748 ql_log(ql_log_warn, vha, 0xd002, 749 "No buffer available for dump.\n"); 750 return; 751 } 752 753 if (ha->fw_dumped) { 754 ql_log(ql_log_warn, vha, 0xd003, 755 "Firmware has been previously dumped (%p) " 756 "-- ignoring request.\n", 757 ha->fw_dump); 758 return; 759 } 760 fw = &ha->fw_dump->isp.isp23; 761 qla2xxx_prep_dump(ha, ha->fw_dump); 762 763 rval = QLA_SUCCESS; 764 fw->hccr = htons(rd_reg_word(®->hccr)); 765 766 /* Pause RISC. */ 767 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 768 if (IS_QLA2300(ha)) { 769 for (cnt = 30000; 770 (rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0 && 771 rval == QLA_SUCCESS; cnt--) { 772 if (cnt) 773 udelay(100); 774 else 775 rval = QLA_FUNCTION_TIMEOUT; 776 } 777 } else { 778 rd_reg_word(®->hccr); /* PCI Posting. */ 779 udelay(10); 780 } 781 782 if (rval == QLA_SUCCESS) { 783 dmp_reg = ®->flash_address; 784 for (cnt = 0; cnt < ARRAY_SIZE(fw->pbiu_reg); cnt++, dmp_reg++) 785 fw->pbiu_reg[cnt] = htons(rd_reg_word(dmp_reg)); 786 787 dmp_reg = ®->u.isp2300.req_q_in; 788 for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_host_reg); 789 cnt++, dmp_reg++) 790 fw->risc_host_reg[cnt] = htons(rd_reg_word(dmp_reg)); 791 792 dmp_reg = ®->u.isp2300.mailbox0; 793 for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); 794 cnt++, dmp_reg++) 795 fw->mailbox_reg[cnt] = htons(rd_reg_word(dmp_reg)); 796 797 wrt_reg_word(®->ctrl_status, 0x40); 798 qla2xxx_read_window(reg, 32, fw->resp_dma_reg); 799 800 wrt_reg_word(®->ctrl_status, 0x50); 801 qla2xxx_read_window(reg, 48, fw->dma_reg); 802 803 wrt_reg_word(®->ctrl_status, 0x00); 804 dmp_reg = ®->risc_hw; 805 for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_hdw_reg); 806 cnt++, dmp_reg++) 807 fw->risc_hdw_reg[cnt] = htons(rd_reg_word(dmp_reg)); 808 809 wrt_reg_word(®->pcr, 0x2000); 810 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 811 812 wrt_reg_word(®->pcr, 0x2200); 813 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 814 815 wrt_reg_word(®->pcr, 0x2400); 816 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 817 818 wrt_reg_word(®->pcr, 0x2600); 819 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 820 821 wrt_reg_word(®->pcr, 0x2800); 822 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 823 824 wrt_reg_word(®->pcr, 0x2A00); 825 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 826 827 wrt_reg_word(®->pcr, 0x2C00); 828 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 829 830 wrt_reg_word(®->pcr, 0x2E00); 831 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 832 833 wrt_reg_word(®->ctrl_status, 0x10); 834 qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); 835 836 wrt_reg_word(®->ctrl_status, 0x20); 837 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 838 839 wrt_reg_word(®->ctrl_status, 0x30); 840 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 841 842 /* Reset RISC. */ 843 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 844 for (cnt = 0; cnt < 30000; cnt++) { 845 if ((rd_reg_word(®->ctrl_status) & 846 CSR_ISP_SOFT_RESET) == 0) 847 break; 848 849 udelay(10); 850 } 851 } 852 853 if (!IS_QLA2300(ha)) { 854 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 855 rval == QLA_SUCCESS; cnt--) { 856 if (cnt) 857 udelay(100); 858 else 859 rval = QLA_FUNCTION_TIMEOUT; 860 } 861 } 862 863 /* Get RISC SRAM. */ 864 if (rval == QLA_SUCCESS) 865 rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, 866 ARRAY_SIZE(fw->risc_ram), &nxt); 867 868 /* Get stack SRAM. */ 869 if (rval == QLA_SUCCESS) 870 rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, 871 ARRAY_SIZE(fw->stack_ram), &nxt); 872 873 /* Get data SRAM. */ 874 if (rval == QLA_SUCCESS) 875 rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, 876 ha->fw_memory_size - 0x11000 + 1, &nxt); 877 878 if (rval == QLA_SUCCESS) 879 qla2xxx_copy_queues(ha, nxt); 880 881 qla2xxx_dump_post_process(base_vha, rval); 882 } 883 884 /** 885 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. 886 * @vha: HA context 887 */ 888 void 889 qla2100_fw_dump(scsi_qla_host_t *vha) 890 { 891 int rval; 892 uint32_t cnt, timer; 893 uint16_t risc_address = 0; 894 uint16_t mb0 = 0, mb2 = 0; 895 struct qla_hw_data *ha = vha->hw; 896 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 897 __le16 __iomem *dmp_reg; 898 struct qla2100_fw_dump *fw; 899 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 900 901 lockdep_assert_held(&ha->hardware_lock); 902 903 if (!ha->fw_dump) { 904 ql_log(ql_log_warn, vha, 0xd004, 905 "No buffer available for dump.\n"); 906 return; 907 } 908 909 if (ha->fw_dumped) { 910 ql_log(ql_log_warn, vha, 0xd005, 911 "Firmware has been previously dumped (%p) " 912 "-- ignoring request.\n", 913 ha->fw_dump); 914 return; 915 } 916 fw = &ha->fw_dump->isp.isp21; 917 qla2xxx_prep_dump(ha, ha->fw_dump); 918 919 rval = QLA_SUCCESS; 920 fw->hccr = htons(rd_reg_word(®->hccr)); 921 922 /* Pause RISC. */ 923 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 924 for (cnt = 30000; (rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0 && 925 rval == QLA_SUCCESS; cnt--) { 926 if (cnt) 927 udelay(100); 928 else 929 rval = QLA_FUNCTION_TIMEOUT; 930 } 931 if (rval == QLA_SUCCESS) { 932 dmp_reg = ®->flash_address; 933 for (cnt = 0; cnt < ARRAY_SIZE(fw->pbiu_reg); cnt++, dmp_reg++) 934 fw->pbiu_reg[cnt] = htons(rd_reg_word(dmp_reg)); 935 936 dmp_reg = ®->u.isp2100.mailbox0; 937 for (cnt = 0; cnt < ha->mbx_count; cnt++, dmp_reg++) { 938 if (cnt == 8) 939 dmp_reg = ®->u_end.isp2200.mailbox8; 940 941 fw->mailbox_reg[cnt] = htons(rd_reg_word(dmp_reg)); 942 } 943 944 dmp_reg = ®->u.isp2100.unused_2[0]; 945 for (cnt = 0; cnt < ARRAY_SIZE(fw->dma_reg); cnt++, dmp_reg++) 946 fw->dma_reg[cnt] = htons(rd_reg_word(dmp_reg)); 947 948 wrt_reg_word(®->ctrl_status, 0x00); 949 dmp_reg = ®->risc_hw; 950 for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_hdw_reg); cnt++, dmp_reg++) 951 fw->risc_hdw_reg[cnt] = htons(rd_reg_word(dmp_reg)); 952 953 wrt_reg_word(®->pcr, 0x2000); 954 qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); 955 956 wrt_reg_word(®->pcr, 0x2100); 957 qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); 958 959 wrt_reg_word(®->pcr, 0x2200); 960 qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); 961 962 wrt_reg_word(®->pcr, 0x2300); 963 qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); 964 965 wrt_reg_word(®->pcr, 0x2400); 966 qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); 967 968 wrt_reg_word(®->pcr, 0x2500); 969 qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); 970 971 wrt_reg_word(®->pcr, 0x2600); 972 qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); 973 974 wrt_reg_word(®->pcr, 0x2700); 975 qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); 976 977 wrt_reg_word(®->ctrl_status, 0x10); 978 qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); 979 980 wrt_reg_word(®->ctrl_status, 0x20); 981 qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); 982 983 wrt_reg_word(®->ctrl_status, 0x30); 984 qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); 985 986 /* Reset the ISP. */ 987 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 988 } 989 990 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && 991 rval == QLA_SUCCESS; cnt--) { 992 if (cnt) 993 udelay(100); 994 else 995 rval = QLA_FUNCTION_TIMEOUT; 996 } 997 998 /* Pause RISC. */ 999 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && 1000 (rd_reg_word(®->mctr) & (BIT_1 | BIT_0)) != 0))) { 1001 1002 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 1003 for (cnt = 30000; 1004 (rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0 && 1005 rval == QLA_SUCCESS; cnt--) { 1006 if (cnt) 1007 udelay(100); 1008 else 1009 rval = QLA_FUNCTION_TIMEOUT; 1010 } 1011 if (rval == QLA_SUCCESS) { 1012 /* Set memory configuration and timing. */ 1013 if (IS_QLA2100(ha)) 1014 wrt_reg_word(®->mctr, 0xf1); 1015 else 1016 wrt_reg_word(®->mctr, 0xf2); 1017 rd_reg_word(®->mctr); /* PCI Posting. */ 1018 1019 /* Release RISC. */ 1020 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 1021 } 1022 } 1023 1024 if (rval == QLA_SUCCESS) { 1025 /* Get RISC SRAM. */ 1026 risc_address = 0x1000; 1027 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); 1028 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); 1029 } 1030 for (cnt = 0; cnt < ARRAY_SIZE(fw->risc_ram) && rval == QLA_SUCCESS; 1031 cnt++, risc_address++) { 1032 WRT_MAILBOX_REG(ha, reg, 1, risc_address); 1033 wrt_reg_word(®->hccr, HCCR_SET_HOST_INT); 1034 1035 for (timer = 6000000; timer != 0; timer--) { 1036 /* Check for pending interrupts. */ 1037 if (rd_reg_word(®->istatus) & ISR_RISC_INT) { 1038 if (rd_reg_word(®->semaphore) & BIT_0) { 1039 set_bit(MBX_INTERRUPT, 1040 &ha->mbx_cmd_flags); 1041 1042 mb0 = RD_MAILBOX_REG(ha, reg, 0); 1043 mb2 = RD_MAILBOX_REG(ha, reg, 2); 1044 1045 wrt_reg_word(®->semaphore, 0); 1046 wrt_reg_word(®->hccr, 1047 HCCR_CLR_RISC_INT); 1048 rd_reg_word(®->hccr); 1049 break; 1050 } 1051 wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT); 1052 rd_reg_word(®->hccr); 1053 } 1054 udelay(5); 1055 } 1056 1057 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { 1058 rval = mb0 & MBS_MASK; 1059 fw->risc_ram[cnt] = htons(mb2); 1060 } else { 1061 rval = QLA_FUNCTION_FAILED; 1062 } 1063 } 1064 1065 if (rval == QLA_SUCCESS) 1066 qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); 1067 1068 qla2xxx_dump_post_process(base_vha, rval); 1069 } 1070 1071 void 1072 qla24xx_fw_dump(scsi_qla_host_t *vha) 1073 { 1074 int rval; 1075 uint32_t cnt; 1076 struct qla_hw_data *ha = vha->hw; 1077 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1078 __le32 __iomem *dmp_reg; 1079 __be32 *iter_reg; 1080 __le16 __iomem *mbx_reg; 1081 struct qla24xx_fw_dump *fw; 1082 void *nxt; 1083 void *nxt_chain; 1084 __be32 *last_chain = NULL; 1085 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1086 1087 lockdep_assert_held(&ha->hardware_lock); 1088 1089 if (IS_P3P_TYPE(ha)) 1090 return; 1091 1092 ha->fw_dump_cap_flags = 0; 1093 1094 if (!ha->fw_dump) { 1095 ql_log(ql_log_warn, vha, 0xd006, 1096 "No buffer available for dump.\n"); 1097 return; 1098 } 1099 1100 if (ha->fw_dumped) { 1101 ql_log(ql_log_warn, vha, 0xd007, 1102 "Firmware has been previously dumped (%p) " 1103 "-- ignoring request.\n", 1104 ha->fw_dump); 1105 return; 1106 } 1107 QLA_FW_STOPPED(ha); 1108 fw = &ha->fw_dump->isp.isp24; 1109 qla2xxx_prep_dump(ha, ha->fw_dump); 1110 1111 fw->host_status = htonl(rd_reg_dword(®->host_status)); 1112 1113 /* 1114 * Pause RISC. No need to track timeout, as resetting the chip 1115 * is the right approach incase of pause timeout 1116 */ 1117 qla24xx_pause_risc(reg, ha); 1118 1119 /* Host interface registers. */ 1120 dmp_reg = ®->flash_addr; 1121 for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++) 1122 fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg)); 1123 1124 /* Disable interrupts. */ 1125 wrt_reg_dword(®->ictrl, 0); 1126 rd_reg_dword(®->ictrl); 1127 1128 /* Shadow registers. */ 1129 wrt_reg_dword(®->iobase_addr, 0x0F70); 1130 rd_reg_dword(®->iobase_addr); 1131 wrt_reg_dword(®->iobase_select, 0xB0000000); 1132 fw->shadow_reg[0] = htonl(rd_reg_dword(®->iobase_sdata)); 1133 1134 wrt_reg_dword(®->iobase_select, 0xB0100000); 1135 fw->shadow_reg[1] = htonl(rd_reg_dword(®->iobase_sdata)); 1136 1137 wrt_reg_dword(®->iobase_select, 0xB0200000); 1138 fw->shadow_reg[2] = htonl(rd_reg_dword(®->iobase_sdata)); 1139 1140 wrt_reg_dword(®->iobase_select, 0xB0300000); 1141 fw->shadow_reg[3] = htonl(rd_reg_dword(®->iobase_sdata)); 1142 1143 wrt_reg_dword(®->iobase_select, 0xB0400000); 1144 fw->shadow_reg[4] = htonl(rd_reg_dword(®->iobase_sdata)); 1145 1146 wrt_reg_dword(®->iobase_select, 0xB0500000); 1147 fw->shadow_reg[5] = htonl(rd_reg_dword(®->iobase_sdata)); 1148 1149 wrt_reg_dword(®->iobase_select, 0xB0600000); 1150 fw->shadow_reg[6] = htonl(rd_reg_dword(®->iobase_sdata)); 1151 1152 /* Mailbox registers. */ 1153 mbx_reg = ®->mailbox0; 1154 for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++) 1155 fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg)); 1156 1157 /* Transfer sequence registers. */ 1158 iter_reg = fw->xseq_gp_reg; 1159 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1160 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1161 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1162 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1163 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1164 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1165 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1166 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1167 1168 qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); 1169 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1170 1171 /* Receive sequence registers. */ 1172 iter_reg = fw->rseq_gp_reg; 1173 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1174 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1175 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1176 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1177 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1178 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1179 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1180 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1181 1182 qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); 1183 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1184 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1185 1186 /* Command DMA registers. */ 1187 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1188 1189 /* Queues. */ 1190 iter_reg = fw->req0_dma_reg; 1191 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1192 dmp_reg = ®->iobase_q; 1193 for (cnt = 0; cnt < 7; cnt++, dmp_reg++) 1194 *iter_reg++ = htonl(rd_reg_dword(dmp_reg)); 1195 1196 iter_reg = fw->resp0_dma_reg; 1197 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1198 dmp_reg = ®->iobase_q; 1199 for (cnt = 0; cnt < 7; cnt++, dmp_reg++) 1200 *iter_reg++ = htonl(rd_reg_dword(dmp_reg)); 1201 1202 iter_reg = fw->req1_dma_reg; 1203 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1204 dmp_reg = ®->iobase_q; 1205 for (cnt = 0; cnt < 7; cnt++, dmp_reg++) 1206 *iter_reg++ = htonl(rd_reg_dword(dmp_reg)); 1207 1208 /* Transmit DMA registers. */ 1209 iter_reg = fw->xmt0_dma_reg; 1210 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1211 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1212 1213 iter_reg = fw->xmt1_dma_reg; 1214 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1215 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1216 1217 iter_reg = fw->xmt2_dma_reg; 1218 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1219 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1220 1221 iter_reg = fw->xmt3_dma_reg; 1222 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1223 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1224 1225 iter_reg = fw->xmt4_dma_reg; 1226 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1227 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1228 1229 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1230 1231 /* Receive DMA registers. */ 1232 iter_reg = fw->rcvt0_data_dma_reg; 1233 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1234 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1235 1236 iter_reg = fw->rcvt1_data_dma_reg; 1237 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1238 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1239 1240 /* RISC registers. */ 1241 iter_reg = fw->risc_gp_reg; 1242 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1243 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1244 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1245 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1246 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1247 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1248 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1249 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1250 1251 /* Local memory controller registers. */ 1252 iter_reg = fw->lmc_reg; 1253 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1254 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1255 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1256 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1257 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1258 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1259 qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1260 1261 /* Fibre Protocol Module registers. */ 1262 iter_reg = fw->fpm_hdw_reg; 1263 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1264 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1265 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1266 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1267 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1268 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1269 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1270 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1271 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1272 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1273 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1274 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1275 1276 /* Frame Buffer registers. */ 1277 iter_reg = fw->fb_hdw_reg; 1278 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1279 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1280 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1281 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1282 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1283 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1284 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1285 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1286 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1287 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1288 qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1289 1290 rval = qla24xx_soft_reset(ha); 1291 if (rval != QLA_SUCCESS) 1292 goto qla24xx_fw_dump_failed_0; 1293 1294 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1295 &nxt); 1296 if (rval != QLA_SUCCESS) 1297 goto qla24xx_fw_dump_failed_0; 1298 1299 nxt = qla2xxx_copy_queues(ha, nxt); 1300 1301 qla24xx_copy_eft(ha, nxt); 1302 1303 nxt_chain = (void *)ha->fw_dump + ha->chain_offset; 1304 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1305 if (last_chain) { 1306 ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT); 1307 *last_chain |= htonl(DUMP_CHAIN_LAST); 1308 } 1309 1310 /* Adjust valid length. */ 1311 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1312 1313 qla24xx_fw_dump_failed_0: 1314 qla2xxx_dump_post_process(base_vha, rval); 1315 } 1316 1317 void 1318 qla25xx_fw_dump(scsi_qla_host_t *vha) 1319 { 1320 int rval; 1321 uint32_t cnt; 1322 struct qla_hw_data *ha = vha->hw; 1323 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1324 __le32 __iomem *dmp_reg; 1325 __be32 *iter_reg; 1326 __le16 __iomem *mbx_reg; 1327 struct qla25xx_fw_dump *fw; 1328 void *nxt, *nxt_chain; 1329 __be32 *last_chain = NULL; 1330 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1331 1332 lockdep_assert_held(&ha->hardware_lock); 1333 1334 ha->fw_dump_cap_flags = 0; 1335 1336 if (!ha->fw_dump) { 1337 ql_log(ql_log_warn, vha, 0xd008, 1338 "No buffer available for dump.\n"); 1339 return; 1340 } 1341 1342 if (ha->fw_dumped) { 1343 ql_log(ql_log_warn, vha, 0xd009, 1344 "Firmware has been previously dumped (%p) " 1345 "-- ignoring request.\n", 1346 ha->fw_dump); 1347 return; 1348 } 1349 QLA_FW_STOPPED(ha); 1350 fw = &ha->fw_dump->isp.isp25; 1351 qla2xxx_prep_dump(ha, ha->fw_dump); 1352 ha->fw_dump->version = htonl(2); 1353 1354 fw->host_status = htonl(rd_reg_dword(®->host_status)); 1355 1356 /* 1357 * Pause RISC. No need to track timeout, as resetting the chip 1358 * is the right approach incase of pause timeout 1359 */ 1360 qla24xx_pause_risc(reg, ha); 1361 1362 /* Host/Risc registers. */ 1363 iter_reg = fw->host_risc_reg; 1364 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1365 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1366 1367 /* PCIe registers. */ 1368 wrt_reg_dword(®->iobase_addr, 0x7C00); 1369 rd_reg_dword(®->iobase_addr); 1370 wrt_reg_dword(®->iobase_window, 0x01); 1371 dmp_reg = ®->iobase_c4; 1372 fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg)); 1373 dmp_reg++; 1374 fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg)); 1375 dmp_reg++; 1376 fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg)); 1377 fw->pcie_regs[3] = htonl(rd_reg_dword(®->iobase_window)); 1378 1379 wrt_reg_dword(®->iobase_window, 0x00); 1380 rd_reg_dword(®->iobase_window); 1381 1382 /* Host interface registers. */ 1383 dmp_reg = ®->flash_addr; 1384 for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++) 1385 fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg)); 1386 1387 /* Disable interrupts. */ 1388 wrt_reg_dword(®->ictrl, 0); 1389 rd_reg_dword(®->ictrl); 1390 1391 /* Shadow registers. */ 1392 wrt_reg_dword(®->iobase_addr, 0x0F70); 1393 rd_reg_dword(®->iobase_addr); 1394 wrt_reg_dword(®->iobase_select, 0xB0000000); 1395 fw->shadow_reg[0] = htonl(rd_reg_dword(®->iobase_sdata)); 1396 1397 wrt_reg_dword(®->iobase_select, 0xB0100000); 1398 fw->shadow_reg[1] = htonl(rd_reg_dword(®->iobase_sdata)); 1399 1400 wrt_reg_dword(®->iobase_select, 0xB0200000); 1401 fw->shadow_reg[2] = htonl(rd_reg_dword(®->iobase_sdata)); 1402 1403 wrt_reg_dword(®->iobase_select, 0xB0300000); 1404 fw->shadow_reg[3] = htonl(rd_reg_dword(®->iobase_sdata)); 1405 1406 wrt_reg_dword(®->iobase_select, 0xB0400000); 1407 fw->shadow_reg[4] = htonl(rd_reg_dword(®->iobase_sdata)); 1408 1409 wrt_reg_dword(®->iobase_select, 0xB0500000); 1410 fw->shadow_reg[5] = htonl(rd_reg_dword(®->iobase_sdata)); 1411 1412 wrt_reg_dword(®->iobase_select, 0xB0600000); 1413 fw->shadow_reg[6] = htonl(rd_reg_dword(®->iobase_sdata)); 1414 1415 wrt_reg_dword(®->iobase_select, 0xB0700000); 1416 fw->shadow_reg[7] = htonl(rd_reg_dword(®->iobase_sdata)); 1417 1418 wrt_reg_dword(®->iobase_select, 0xB0800000); 1419 fw->shadow_reg[8] = htonl(rd_reg_dword(®->iobase_sdata)); 1420 1421 wrt_reg_dword(®->iobase_select, 0xB0900000); 1422 fw->shadow_reg[9] = htonl(rd_reg_dword(®->iobase_sdata)); 1423 1424 wrt_reg_dword(®->iobase_select, 0xB0A00000); 1425 fw->shadow_reg[10] = htonl(rd_reg_dword(®->iobase_sdata)); 1426 1427 /* RISC I/O register. */ 1428 wrt_reg_dword(®->iobase_addr, 0x0010); 1429 fw->risc_io_reg = htonl(rd_reg_dword(®->iobase_window)); 1430 1431 /* Mailbox registers. */ 1432 mbx_reg = ®->mailbox0; 1433 for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++) 1434 fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg)); 1435 1436 /* Transfer sequence registers. */ 1437 iter_reg = fw->xseq_gp_reg; 1438 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1439 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1440 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1441 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1442 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1443 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1444 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1445 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1446 1447 iter_reg = fw->xseq_0_reg; 1448 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1449 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1450 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1451 1452 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1453 1454 /* Receive sequence registers. */ 1455 iter_reg = fw->rseq_gp_reg; 1456 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1457 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1458 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1459 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1460 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1461 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1462 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1463 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1464 1465 iter_reg = fw->rseq_0_reg; 1466 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1467 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1468 1469 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1470 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1471 1472 /* Auxiliary sequence registers. */ 1473 iter_reg = fw->aseq_gp_reg; 1474 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1475 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1476 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1477 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1478 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1479 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1480 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1481 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1482 1483 iter_reg = fw->aseq_0_reg; 1484 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1485 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1486 1487 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1488 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1489 1490 /* Command DMA registers. */ 1491 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1492 1493 /* Queues. */ 1494 iter_reg = fw->req0_dma_reg; 1495 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1496 dmp_reg = ®->iobase_q; 1497 for (cnt = 0; cnt < 7; cnt++, dmp_reg++) 1498 *iter_reg++ = htonl(rd_reg_dword(dmp_reg)); 1499 1500 iter_reg = fw->resp0_dma_reg; 1501 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1502 dmp_reg = ®->iobase_q; 1503 for (cnt = 0; cnt < 7; cnt++, dmp_reg++) 1504 *iter_reg++ = htonl(rd_reg_dword(dmp_reg)); 1505 1506 iter_reg = fw->req1_dma_reg; 1507 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1508 dmp_reg = ®->iobase_q; 1509 for (cnt = 0; cnt < 7; cnt++, dmp_reg++) 1510 *iter_reg++ = htonl(rd_reg_dword(dmp_reg)); 1511 1512 /* Transmit DMA registers. */ 1513 iter_reg = fw->xmt0_dma_reg; 1514 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1515 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1516 1517 iter_reg = fw->xmt1_dma_reg; 1518 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1519 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1520 1521 iter_reg = fw->xmt2_dma_reg; 1522 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1523 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1524 1525 iter_reg = fw->xmt3_dma_reg; 1526 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1527 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1528 1529 iter_reg = fw->xmt4_dma_reg; 1530 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1531 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1532 1533 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1534 1535 /* Receive DMA registers. */ 1536 iter_reg = fw->rcvt0_data_dma_reg; 1537 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1538 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1539 1540 iter_reg = fw->rcvt1_data_dma_reg; 1541 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1542 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1543 1544 /* RISC registers. */ 1545 iter_reg = fw->risc_gp_reg; 1546 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1547 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1548 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1549 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1550 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1551 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1552 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1553 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1554 1555 /* Local memory controller registers. */ 1556 iter_reg = fw->lmc_reg; 1557 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1558 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1559 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1560 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1561 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1562 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1563 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1564 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1565 1566 /* Fibre Protocol Module registers. */ 1567 iter_reg = fw->fpm_hdw_reg; 1568 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1569 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1570 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1571 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1572 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1573 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1574 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1575 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1576 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1577 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1578 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1579 qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1580 1581 /* Frame Buffer registers. */ 1582 iter_reg = fw->fb_hdw_reg; 1583 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1584 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1585 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1586 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1587 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1588 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1589 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1590 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1591 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1592 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1593 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1594 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1595 1596 /* Multi queue registers */ 1597 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 1598 &last_chain); 1599 1600 rval = qla24xx_soft_reset(ha); 1601 if (rval != QLA_SUCCESS) 1602 goto qla25xx_fw_dump_failed_0; 1603 1604 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1605 &nxt); 1606 if (rval != QLA_SUCCESS) 1607 goto qla25xx_fw_dump_failed_0; 1608 1609 nxt = qla2xxx_copy_queues(ha, nxt); 1610 1611 qla24xx_copy_eft(ha, nxt); 1612 1613 /* Chain entries -- started with MQ. */ 1614 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 1615 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 1616 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1617 nxt_chain = qla25xx_copy_exlogin(ha, nxt_chain, &last_chain); 1618 if (last_chain) { 1619 ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT); 1620 *last_chain |= htonl(DUMP_CHAIN_LAST); 1621 } 1622 1623 /* Adjust valid length. */ 1624 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1625 1626 qla25xx_fw_dump_failed_0: 1627 qla2xxx_dump_post_process(base_vha, rval); 1628 } 1629 1630 void 1631 qla81xx_fw_dump(scsi_qla_host_t *vha) 1632 { 1633 int rval; 1634 uint32_t cnt; 1635 struct qla_hw_data *ha = vha->hw; 1636 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1637 __le32 __iomem *dmp_reg; 1638 __be32 *iter_reg; 1639 __le16 __iomem *mbx_reg; 1640 struct qla81xx_fw_dump *fw; 1641 void *nxt, *nxt_chain; 1642 __be32 *last_chain = NULL; 1643 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1644 1645 lockdep_assert_held(&ha->hardware_lock); 1646 1647 ha->fw_dump_cap_flags = 0; 1648 1649 if (!ha->fw_dump) { 1650 ql_log(ql_log_warn, vha, 0xd00a, 1651 "No buffer available for dump.\n"); 1652 return; 1653 } 1654 1655 if (ha->fw_dumped) { 1656 ql_log(ql_log_warn, vha, 0xd00b, 1657 "Firmware has been previously dumped (%p) " 1658 "-- ignoring request.\n", 1659 ha->fw_dump); 1660 return; 1661 } 1662 fw = &ha->fw_dump->isp.isp81; 1663 qla2xxx_prep_dump(ha, ha->fw_dump); 1664 1665 fw->host_status = htonl(rd_reg_dword(®->host_status)); 1666 1667 /* 1668 * Pause RISC. No need to track timeout, as resetting the chip 1669 * is the right approach incase of pause timeout 1670 */ 1671 qla24xx_pause_risc(reg, ha); 1672 1673 /* Host/Risc registers. */ 1674 iter_reg = fw->host_risc_reg; 1675 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 1676 qla24xx_read_window(reg, 0x7010, 16, iter_reg); 1677 1678 /* PCIe registers. */ 1679 wrt_reg_dword(®->iobase_addr, 0x7C00); 1680 rd_reg_dword(®->iobase_addr); 1681 wrt_reg_dword(®->iobase_window, 0x01); 1682 dmp_reg = ®->iobase_c4; 1683 fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg)); 1684 dmp_reg++; 1685 fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg)); 1686 dmp_reg++; 1687 fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg)); 1688 fw->pcie_regs[3] = htonl(rd_reg_dword(®->iobase_window)); 1689 1690 wrt_reg_dword(®->iobase_window, 0x00); 1691 rd_reg_dword(®->iobase_window); 1692 1693 /* Host interface registers. */ 1694 dmp_reg = ®->flash_addr; 1695 for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++) 1696 fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg)); 1697 1698 /* Disable interrupts. */ 1699 wrt_reg_dword(®->ictrl, 0); 1700 rd_reg_dword(®->ictrl); 1701 1702 /* Shadow registers. */ 1703 wrt_reg_dword(®->iobase_addr, 0x0F70); 1704 rd_reg_dword(®->iobase_addr); 1705 wrt_reg_dword(®->iobase_select, 0xB0000000); 1706 fw->shadow_reg[0] = htonl(rd_reg_dword(®->iobase_sdata)); 1707 1708 wrt_reg_dword(®->iobase_select, 0xB0100000); 1709 fw->shadow_reg[1] = htonl(rd_reg_dword(®->iobase_sdata)); 1710 1711 wrt_reg_dword(®->iobase_select, 0xB0200000); 1712 fw->shadow_reg[2] = htonl(rd_reg_dword(®->iobase_sdata)); 1713 1714 wrt_reg_dword(®->iobase_select, 0xB0300000); 1715 fw->shadow_reg[3] = htonl(rd_reg_dword(®->iobase_sdata)); 1716 1717 wrt_reg_dword(®->iobase_select, 0xB0400000); 1718 fw->shadow_reg[4] = htonl(rd_reg_dword(®->iobase_sdata)); 1719 1720 wrt_reg_dword(®->iobase_select, 0xB0500000); 1721 fw->shadow_reg[5] = htonl(rd_reg_dword(®->iobase_sdata)); 1722 1723 wrt_reg_dword(®->iobase_select, 0xB0600000); 1724 fw->shadow_reg[6] = htonl(rd_reg_dword(®->iobase_sdata)); 1725 1726 wrt_reg_dword(®->iobase_select, 0xB0700000); 1727 fw->shadow_reg[7] = htonl(rd_reg_dword(®->iobase_sdata)); 1728 1729 wrt_reg_dword(®->iobase_select, 0xB0800000); 1730 fw->shadow_reg[8] = htonl(rd_reg_dword(®->iobase_sdata)); 1731 1732 wrt_reg_dword(®->iobase_select, 0xB0900000); 1733 fw->shadow_reg[9] = htonl(rd_reg_dword(®->iobase_sdata)); 1734 1735 wrt_reg_dword(®->iobase_select, 0xB0A00000); 1736 fw->shadow_reg[10] = htonl(rd_reg_dword(®->iobase_sdata)); 1737 1738 /* RISC I/O register. */ 1739 wrt_reg_dword(®->iobase_addr, 0x0010); 1740 fw->risc_io_reg = htonl(rd_reg_dword(®->iobase_window)); 1741 1742 /* Mailbox registers. */ 1743 mbx_reg = ®->mailbox0; 1744 for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++) 1745 fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg)); 1746 1747 /* Transfer sequence registers. */ 1748 iter_reg = fw->xseq_gp_reg; 1749 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 1750 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 1751 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 1752 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 1753 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 1754 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 1755 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 1756 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 1757 1758 iter_reg = fw->xseq_0_reg; 1759 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 1760 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 1761 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 1762 1763 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 1764 1765 /* Receive sequence registers. */ 1766 iter_reg = fw->rseq_gp_reg; 1767 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 1768 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 1769 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 1770 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 1771 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 1772 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 1773 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 1774 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 1775 1776 iter_reg = fw->rseq_0_reg; 1777 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 1778 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 1779 1780 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 1781 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 1782 1783 /* Auxiliary sequence registers. */ 1784 iter_reg = fw->aseq_gp_reg; 1785 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 1786 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 1787 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 1788 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 1789 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 1790 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 1791 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 1792 qla24xx_read_window(reg, 0xB070, 16, iter_reg); 1793 1794 iter_reg = fw->aseq_0_reg; 1795 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 1796 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 1797 1798 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 1799 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 1800 1801 /* Command DMA registers. */ 1802 qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); 1803 1804 /* Queues. */ 1805 iter_reg = fw->req0_dma_reg; 1806 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 1807 dmp_reg = ®->iobase_q; 1808 for (cnt = 0; cnt < 7; cnt++, dmp_reg++) 1809 *iter_reg++ = htonl(rd_reg_dword(dmp_reg)); 1810 1811 iter_reg = fw->resp0_dma_reg; 1812 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 1813 dmp_reg = ®->iobase_q; 1814 for (cnt = 0; cnt < 7; cnt++, dmp_reg++) 1815 *iter_reg++ = htonl(rd_reg_dword(dmp_reg)); 1816 1817 iter_reg = fw->req1_dma_reg; 1818 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 1819 dmp_reg = ®->iobase_q; 1820 for (cnt = 0; cnt < 7; cnt++, dmp_reg++) 1821 *iter_reg++ = htonl(rd_reg_dword(dmp_reg)); 1822 1823 /* Transmit DMA registers. */ 1824 iter_reg = fw->xmt0_dma_reg; 1825 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 1826 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 1827 1828 iter_reg = fw->xmt1_dma_reg; 1829 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 1830 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 1831 1832 iter_reg = fw->xmt2_dma_reg; 1833 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 1834 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 1835 1836 iter_reg = fw->xmt3_dma_reg; 1837 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 1838 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 1839 1840 iter_reg = fw->xmt4_dma_reg; 1841 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 1842 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 1843 1844 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 1845 1846 /* Receive DMA registers. */ 1847 iter_reg = fw->rcvt0_data_dma_reg; 1848 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 1849 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 1850 1851 iter_reg = fw->rcvt1_data_dma_reg; 1852 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 1853 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 1854 1855 /* RISC registers. */ 1856 iter_reg = fw->risc_gp_reg; 1857 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 1858 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 1859 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 1860 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 1861 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 1862 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 1863 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 1864 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 1865 1866 /* Local memory controller registers. */ 1867 iter_reg = fw->lmc_reg; 1868 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 1869 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 1870 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 1871 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 1872 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 1873 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 1874 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 1875 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 1876 1877 /* Fibre Protocol Module registers. */ 1878 iter_reg = fw->fpm_hdw_reg; 1879 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 1880 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 1881 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 1882 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 1883 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 1884 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 1885 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 1886 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 1887 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 1888 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 1889 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 1890 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 1891 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); 1892 qla24xx_read_window(reg, 0x40D0, 16, iter_reg); 1893 1894 /* Frame Buffer registers. */ 1895 iter_reg = fw->fb_hdw_reg; 1896 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 1897 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 1898 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 1899 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 1900 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 1901 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 1902 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 1903 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 1904 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 1905 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 1906 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 1907 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); 1908 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 1909 1910 /* Multi queue registers */ 1911 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 1912 &last_chain); 1913 1914 rval = qla24xx_soft_reset(ha); 1915 if (rval != QLA_SUCCESS) 1916 goto qla81xx_fw_dump_failed_0; 1917 1918 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 1919 &nxt); 1920 if (rval != QLA_SUCCESS) 1921 goto qla81xx_fw_dump_failed_0; 1922 1923 nxt = qla2xxx_copy_queues(ha, nxt); 1924 1925 qla24xx_copy_eft(ha, nxt); 1926 1927 /* Chain entries -- started with MQ. */ 1928 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 1929 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 1930 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 1931 nxt_chain = qla25xx_copy_exlogin(ha, nxt_chain, &last_chain); 1932 nxt_chain = qla81xx_copy_exchoffld(ha, nxt_chain, &last_chain); 1933 if (last_chain) { 1934 ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT); 1935 *last_chain |= htonl(DUMP_CHAIN_LAST); 1936 } 1937 1938 /* Adjust valid length. */ 1939 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 1940 1941 qla81xx_fw_dump_failed_0: 1942 qla2xxx_dump_post_process(base_vha, rval); 1943 } 1944 1945 void 1946 qla83xx_fw_dump(scsi_qla_host_t *vha) 1947 { 1948 int rval; 1949 uint32_t cnt; 1950 struct qla_hw_data *ha = vha->hw; 1951 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1952 __le32 __iomem *dmp_reg; 1953 __be32 *iter_reg; 1954 __le16 __iomem *mbx_reg; 1955 struct qla83xx_fw_dump *fw; 1956 void *nxt, *nxt_chain; 1957 __be32 *last_chain = NULL; 1958 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 1959 1960 lockdep_assert_held(&ha->hardware_lock); 1961 1962 ha->fw_dump_cap_flags = 0; 1963 1964 if (!ha->fw_dump) { 1965 ql_log(ql_log_warn, vha, 0xd00c, 1966 "No buffer available for dump!!!\n"); 1967 return; 1968 } 1969 1970 if (ha->fw_dumped) { 1971 ql_log(ql_log_warn, vha, 0xd00d, 1972 "Firmware has been previously dumped (%p) -- ignoring " 1973 "request...\n", ha->fw_dump); 1974 return; 1975 } 1976 QLA_FW_STOPPED(ha); 1977 fw = &ha->fw_dump->isp.isp83; 1978 qla2xxx_prep_dump(ha, ha->fw_dump); 1979 1980 fw->host_status = htonl(rd_reg_dword(®->host_status)); 1981 1982 /* 1983 * Pause RISC. No need to track timeout, as resetting the chip 1984 * is the right approach incase of pause timeout 1985 */ 1986 qla24xx_pause_risc(reg, ha); 1987 1988 wrt_reg_dword(®->iobase_addr, 0x6000); 1989 dmp_reg = ®->iobase_window; 1990 rd_reg_dword(dmp_reg); 1991 wrt_reg_dword(dmp_reg, 0); 1992 1993 dmp_reg = ®->unused_4_1[0]; 1994 rd_reg_dword(dmp_reg); 1995 wrt_reg_dword(dmp_reg, 0); 1996 1997 wrt_reg_dword(®->iobase_addr, 0x6010); 1998 dmp_reg = ®->unused_4_1[2]; 1999 rd_reg_dword(dmp_reg); 2000 wrt_reg_dword(dmp_reg, 0); 2001 2002 /* select PCR and disable ecc checking and correction */ 2003 wrt_reg_dword(®->iobase_addr, 0x0F70); 2004 rd_reg_dword(®->iobase_addr); 2005 wrt_reg_dword(®->iobase_select, 0x60000000); /* write to F0h = PCR */ 2006 2007 /* Host/Risc registers. */ 2008 iter_reg = fw->host_risc_reg; 2009 iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); 2010 iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); 2011 qla24xx_read_window(reg, 0x7040, 16, iter_reg); 2012 2013 /* PCIe registers. */ 2014 wrt_reg_dword(®->iobase_addr, 0x7C00); 2015 rd_reg_dword(®->iobase_addr); 2016 wrt_reg_dword(®->iobase_window, 0x01); 2017 dmp_reg = ®->iobase_c4; 2018 fw->pcie_regs[0] = htonl(rd_reg_dword(dmp_reg)); 2019 dmp_reg++; 2020 fw->pcie_regs[1] = htonl(rd_reg_dword(dmp_reg)); 2021 dmp_reg++; 2022 fw->pcie_regs[2] = htonl(rd_reg_dword(dmp_reg)); 2023 fw->pcie_regs[3] = htonl(rd_reg_dword(®->iobase_window)); 2024 2025 wrt_reg_dword(®->iobase_window, 0x00); 2026 rd_reg_dword(®->iobase_window); 2027 2028 /* Host interface registers. */ 2029 dmp_reg = ®->flash_addr; 2030 for (cnt = 0; cnt < ARRAY_SIZE(fw->host_reg); cnt++, dmp_reg++) 2031 fw->host_reg[cnt] = htonl(rd_reg_dword(dmp_reg)); 2032 2033 /* Disable interrupts. */ 2034 wrt_reg_dword(®->ictrl, 0); 2035 rd_reg_dword(®->ictrl); 2036 2037 /* Shadow registers. */ 2038 wrt_reg_dword(®->iobase_addr, 0x0F70); 2039 rd_reg_dword(®->iobase_addr); 2040 wrt_reg_dword(®->iobase_select, 0xB0000000); 2041 fw->shadow_reg[0] = htonl(rd_reg_dword(®->iobase_sdata)); 2042 2043 wrt_reg_dword(®->iobase_select, 0xB0100000); 2044 fw->shadow_reg[1] = htonl(rd_reg_dword(®->iobase_sdata)); 2045 2046 wrt_reg_dword(®->iobase_select, 0xB0200000); 2047 fw->shadow_reg[2] = htonl(rd_reg_dword(®->iobase_sdata)); 2048 2049 wrt_reg_dword(®->iobase_select, 0xB0300000); 2050 fw->shadow_reg[3] = htonl(rd_reg_dword(®->iobase_sdata)); 2051 2052 wrt_reg_dword(®->iobase_select, 0xB0400000); 2053 fw->shadow_reg[4] = htonl(rd_reg_dword(®->iobase_sdata)); 2054 2055 wrt_reg_dword(®->iobase_select, 0xB0500000); 2056 fw->shadow_reg[5] = htonl(rd_reg_dword(®->iobase_sdata)); 2057 2058 wrt_reg_dword(®->iobase_select, 0xB0600000); 2059 fw->shadow_reg[6] = htonl(rd_reg_dword(®->iobase_sdata)); 2060 2061 wrt_reg_dword(®->iobase_select, 0xB0700000); 2062 fw->shadow_reg[7] = htonl(rd_reg_dword(®->iobase_sdata)); 2063 2064 wrt_reg_dword(®->iobase_select, 0xB0800000); 2065 fw->shadow_reg[8] = htonl(rd_reg_dword(®->iobase_sdata)); 2066 2067 wrt_reg_dword(®->iobase_select, 0xB0900000); 2068 fw->shadow_reg[9] = htonl(rd_reg_dword(®->iobase_sdata)); 2069 2070 wrt_reg_dword(®->iobase_select, 0xB0A00000); 2071 fw->shadow_reg[10] = htonl(rd_reg_dword(®->iobase_sdata)); 2072 2073 /* RISC I/O register. */ 2074 wrt_reg_dword(®->iobase_addr, 0x0010); 2075 fw->risc_io_reg = htonl(rd_reg_dword(®->iobase_window)); 2076 2077 /* Mailbox registers. */ 2078 mbx_reg = ®->mailbox0; 2079 for (cnt = 0; cnt < ARRAY_SIZE(fw->mailbox_reg); cnt++, mbx_reg++) 2080 fw->mailbox_reg[cnt] = htons(rd_reg_word(mbx_reg)); 2081 2082 /* Transfer sequence registers. */ 2083 iter_reg = fw->xseq_gp_reg; 2084 iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); 2085 iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); 2086 iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); 2087 iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); 2088 iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); 2089 iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); 2090 iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); 2091 iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); 2092 iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); 2093 iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); 2094 iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); 2095 iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); 2096 iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); 2097 iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); 2098 iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); 2099 qla24xx_read_window(reg, 0xBF70, 16, iter_reg); 2100 2101 iter_reg = fw->xseq_0_reg; 2102 iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); 2103 iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); 2104 qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); 2105 2106 qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); 2107 2108 qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); 2109 2110 /* Receive sequence registers. */ 2111 iter_reg = fw->rseq_gp_reg; 2112 iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); 2113 iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); 2114 iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); 2115 iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); 2116 iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); 2117 iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); 2118 iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); 2119 iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); 2120 iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); 2121 iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); 2122 iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); 2123 iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); 2124 iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); 2125 iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); 2126 iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); 2127 qla24xx_read_window(reg, 0xFF70, 16, iter_reg); 2128 2129 iter_reg = fw->rseq_0_reg; 2130 iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); 2131 qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); 2132 2133 qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); 2134 qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); 2135 qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); 2136 2137 /* Auxiliary sequence registers. */ 2138 iter_reg = fw->aseq_gp_reg; 2139 iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); 2140 iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); 2141 iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); 2142 iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); 2143 iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); 2144 iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); 2145 iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); 2146 iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); 2147 iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); 2148 iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); 2149 iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); 2150 iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); 2151 iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); 2152 iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); 2153 iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); 2154 qla24xx_read_window(reg, 0xB170, 16, iter_reg); 2155 2156 iter_reg = fw->aseq_0_reg; 2157 iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); 2158 qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); 2159 2160 qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); 2161 qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); 2162 qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); 2163 2164 /* Command DMA registers. */ 2165 iter_reg = fw->cmd_dma_reg; 2166 iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); 2167 iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); 2168 iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); 2169 qla24xx_read_window(reg, 0x71F0, 16, iter_reg); 2170 2171 /* Queues. */ 2172 iter_reg = fw->req0_dma_reg; 2173 iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); 2174 dmp_reg = ®->iobase_q; 2175 for (cnt = 0; cnt < 7; cnt++, dmp_reg++) 2176 *iter_reg++ = htonl(rd_reg_dword(dmp_reg)); 2177 2178 iter_reg = fw->resp0_dma_reg; 2179 iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); 2180 dmp_reg = ®->iobase_q; 2181 for (cnt = 0; cnt < 7; cnt++, dmp_reg++) 2182 *iter_reg++ = htonl(rd_reg_dword(dmp_reg)); 2183 2184 iter_reg = fw->req1_dma_reg; 2185 iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); 2186 dmp_reg = ®->iobase_q; 2187 for (cnt = 0; cnt < 7; cnt++, dmp_reg++) 2188 *iter_reg++ = htonl(rd_reg_dword(dmp_reg)); 2189 2190 /* Transmit DMA registers. */ 2191 iter_reg = fw->xmt0_dma_reg; 2192 iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); 2193 qla24xx_read_window(reg, 0x7610, 16, iter_reg); 2194 2195 iter_reg = fw->xmt1_dma_reg; 2196 iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); 2197 qla24xx_read_window(reg, 0x7630, 16, iter_reg); 2198 2199 iter_reg = fw->xmt2_dma_reg; 2200 iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); 2201 qla24xx_read_window(reg, 0x7650, 16, iter_reg); 2202 2203 iter_reg = fw->xmt3_dma_reg; 2204 iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); 2205 qla24xx_read_window(reg, 0x7670, 16, iter_reg); 2206 2207 iter_reg = fw->xmt4_dma_reg; 2208 iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); 2209 qla24xx_read_window(reg, 0x7690, 16, iter_reg); 2210 2211 qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); 2212 2213 /* Receive DMA registers. */ 2214 iter_reg = fw->rcvt0_data_dma_reg; 2215 iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); 2216 qla24xx_read_window(reg, 0x7710, 16, iter_reg); 2217 2218 iter_reg = fw->rcvt1_data_dma_reg; 2219 iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); 2220 qla24xx_read_window(reg, 0x7730, 16, iter_reg); 2221 2222 /* RISC registers. */ 2223 iter_reg = fw->risc_gp_reg; 2224 iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); 2225 iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); 2226 iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); 2227 iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); 2228 iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); 2229 iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); 2230 iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); 2231 qla24xx_read_window(reg, 0x0F70, 16, iter_reg); 2232 2233 /* Local memory controller registers. */ 2234 iter_reg = fw->lmc_reg; 2235 iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); 2236 iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); 2237 iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); 2238 iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); 2239 iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); 2240 iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); 2241 iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); 2242 qla24xx_read_window(reg, 0x3070, 16, iter_reg); 2243 2244 /* Fibre Protocol Module registers. */ 2245 iter_reg = fw->fpm_hdw_reg; 2246 iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); 2247 iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); 2248 iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); 2249 iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); 2250 iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); 2251 iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); 2252 iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); 2253 iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); 2254 iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); 2255 iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); 2256 iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); 2257 iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); 2258 iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); 2259 iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); 2260 iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); 2261 qla24xx_read_window(reg, 0x40F0, 16, iter_reg); 2262 2263 /* RQ0 Array registers. */ 2264 iter_reg = fw->rq0_array_reg; 2265 iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); 2266 iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); 2267 iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); 2268 iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); 2269 iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); 2270 iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); 2271 iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); 2272 iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); 2273 iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); 2274 iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); 2275 iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); 2276 iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); 2277 iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); 2278 iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); 2279 iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); 2280 qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); 2281 2282 /* RQ1 Array registers. */ 2283 iter_reg = fw->rq1_array_reg; 2284 iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); 2285 iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); 2286 iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); 2287 iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); 2288 iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); 2289 iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); 2290 iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); 2291 iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); 2292 iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); 2293 iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); 2294 iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); 2295 iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); 2296 iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); 2297 iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); 2298 iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); 2299 qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); 2300 2301 /* RP0 Array registers. */ 2302 iter_reg = fw->rp0_array_reg; 2303 iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); 2304 iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); 2305 iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); 2306 iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); 2307 iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); 2308 iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); 2309 iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); 2310 iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); 2311 iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); 2312 iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); 2313 iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); 2314 iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); 2315 iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); 2316 iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); 2317 iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); 2318 qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); 2319 2320 /* RP1 Array registers. */ 2321 iter_reg = fw->rp1_array_reg; 2322 iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); 2323 iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); 2324 iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); 2325 iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); 2326 iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); 2327 iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); 2328 iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); 2329 iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); 2330 iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); 2331 iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); 2332 iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); 2333 iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); 2334 iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); 2335 iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); 2336 iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); 2337 qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); 2338 2339 iter_reg = fw->at0_array_reg; 2340 iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); 2341 iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); 2342 iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); 2343 iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); 2344 iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); 2345 iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); 2346 iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); 2347 qla24xx_read_window(reg, 0x70F0, 16, iter_reg); 2348 2349 /* I/O Queue Control registers. */ 2350 qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); 2351 2352 /* Frame Buffer registers. */ 2353 iter_reg = fw->fb_hdw_reg; 2354 iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); 2355 iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); 2356 iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); 2357 iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); 2358 iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); 2359 iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); 2360 iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); 2361 iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); 2362 iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); 2363 iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); 2364 iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); 2365 iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); 2366 iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); 2367 iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); 2368 iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); 2369 iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); 2370 iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); 2371 iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); 2372 iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); 2373 iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); 2374 iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); 2375 iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); 2376 iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); 2377 iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); 2378 iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); 2379 iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); 2380 qla24xx_read_window(reg, 0x6F00, 16, iter_reg); 2381 2382 /* Multi queue registers */ 2383 nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, 2384 &last_chain); 2385 2386 rval = qla24xx_soft_reset(ha); 2387 if (rval != QLA_SUCCESS) { 2388 ql_log(ql_log_warn, vha, 0xd00e, 2389 "SOFT RESET FAILED, forcing continuation of dump!!!\n"); 2390 rval = QLA_SUCCESS; 2391 2392 ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n"); 2393 2394 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET); 2395 rd_reg_dword(®->hccr); 2396 2397 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE); 2398 rd_reg_dword(®->hccr); 2399 2400 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_RESET); 2401 rd_reg_dword(®->hccr); 2402 2403 for (cnt = 30000; cnt && (rd_reg_word(®->mailbox0)); cnt--) 2404 udelay(5); 2405 2406 if (!cnt) { 2407 nxt = fw->code_ram; 2408 nxt += sizeof(fw->code_ram); 2409 nxt += (ha->fw_memory_size - 0x100000 + 1); 2410 goto copy_queue; 2411 } else { 2412 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); 2413 ql_log(ql_log_warn, vha, 0xd010, 2414 "bigger hammer success?\n"); 2415 } 2416 } 2417 2418 rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), 2419 &nxt); 2420 if (rval != QLA_SUCCESS) 2421 goto qla83xx_fw_dump_failed_0; 2422 2423 copy_queue: 2424 nxt = qla2xxx_copy_queues(ha, nxt); 2425 2426 qla24xx_copy_eft(ha, nxt); 2427 2428 /* Chain entries -- started with MQ. */ 2429 nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); 2430 nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); 2431 nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); 2432 nxt_chain = qla25xx_copy_exlogin(ha, nxt_chain, &last_chain); 2433 nxt_chain = qla81xx_copy_exchoffld(ha, nxt_chain, &last_chain); 2434 if (last_chain) { 2435 ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT); 2436 *last_chain |= htonl(DUMP_CHAIN_LAST); 2437 } 2438 2439 /* Adjust valid length. */ 2440 ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); 2441 2442 qla83xx_fw_dump_failed_0: 2443 qla2xxx_dump_post_process(base_vha, rval); 2444 } 2445 2446 /****************************************************************************/ 2447 /* Driver Debug Functions. */ 2448 /****************************************************************************/ 2449 2450 /* 2451 * This function is for formatting and logging debug information. 2452 * It is to be used when vha is available. It formats the message 2453 * and logs it to the messages file. 2454 * parameters: 2455 * level: The level of the debug messages to be printed. 2456 * If ql2xextended_error_logging value is correctly set, 2457 * this message will appear in the messages file. 2458 * vha: Pointer to the scsi_qla_host_t. 2459 * id: This is a unique identifier for the level. It identifies the 2460 * part of the code from where the message originated. 2461 * msg: The message to be displayed. 2462 */ 2463 void 2464 ql_dbg(uint level, scsi_qla_host_t *vha, uint id, const char *fmt, ...) 2465 { 2466 va_list va; 2467 struct va_format vaf; 2468 2469 va_start(va, fmt); 2470 2471 vaf.fmt = fmt; 2472 vaf.va = &va; 2473 2474 if (!ql_mask_match(level)) { 2475 char pbuf[64]; 2476 2477 if (vha != NULL) { 2478 const struct pci_dev *pdev = vha->hw->pdev; 2479 /* <module-name> <msg-id>:<host> Message */ 2480 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ", 2481 QL_MSGHDR, dev_name(&(pdev->dev)), id, 2482 vha->host_no); 2483 } else { 2484 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", 2485 QL_MSGHDR, "0000:00:00.0", id); 2486 } 2487 pbuf[sizeof(pbuf) - 1] = 0; 2488 trace_ql_dbg_log(pbuf, &vaf); 2489 va_end(va); 2490 return; 2491 } 2492 2493 if (vha != NULL) { 2494 const struct pci_dev *pdev = vha->hw->pdev; 2495 /* <module-name> <pci-name> <msg-id>:<host> Message */ 2496 pr_warn("%s [%s]-%04x:%ld: %pV", 2497 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, 2498 vha->host_no, &vaf); 2499 } else { 2500 pr_warn("%s [%s]-%04x: : %pV", 2501 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); 2502 } 2503 2504 va_end(va); 2505 2506 } 2507 2508 /* 2509 * This function is for formatting and logging debug information. 2510 * It is to be used when vha is not available and pci is available, 2511 * i.e., before host allocation. It formats the message and logs it 2512 * to the messages file. 2513 * parameters: 2514 * level: The level of the debug messages to be printed. 2515 * If ql2xextended_error_logging value is correctly set, 2516 * this message will appear in the messages file. 2517 * pdev: Pointer to the struct pci_dev. 2518 * id: This is a unique id for the level. It identifies the part 2519 * of the code from where the message originated. 2520 * msg: The message to be displayed. 2521 */ 2522 void 2523 ql_dbg_pci(uint level, struct pci_dev *pdev, uint id, const char *fmt, ...) 2524 { 2525 va_list va; 2526 struct va_format vaf; 2527 2528 if (pdev == NULL) 2529 return; 2530 if (!ql_mask_match(level)) 2531 return; 2532 2533 va_start(va, fmt); 2534 2535 vaf.fmt = fmt; 2536 vaf.va = &va; 2537 2538 /* <module-name> <dev-name>:<msg-id> Message */ 2539 pr_warn("%s [%s]-%04x: : %pV", 2540 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf); 2541 2542 va_end(va); 2543 } 2544 2545 /* 2546 * This function is for formatting and logging log messages. 2547 * It is to be used when vha is available. It formats the message 2548 * and logs it to the messages file. All the messages will be logged 2549 * irrespective of value of ql2xextended_error_logging. 2550 * parameters: 2551 * level: The level of the log messages to be printed in the 2552 * messages file. 2553 * vha: Pointer to the scsi_qla_host_t 2554 * id: This is a unique id for the level. It identifies the 2555 * part of the code from where the message originated. 2556 * msg: The message to be displayed. 2557 */ 2558 void 2559 ql_log(uint level, scsi_qla_host_t *vha, uint id, const char *fmt, ...) 2560 { 2561 va_list va; 2562 struct va_format vaf; 2563 char pbuf[128]; 2564 2565 if (level > ql_errlev) 2566 return; 2567 2568 if (vha != NULL) { 2569 const struct pci_dev *pdev = vha->hw->pdev; 2570 /* <module-name> <msg-id>:<host> Message */ 2571 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ", 2572 QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no); 2573 } else { 2574 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", 2575 QL_MSGHDR, "0000:00:00.0", id); 2576 } 2577 pbuf[sizeof(pbuf) - 1] = 0; 2578 2579 va_start(va, fmt); 2580 2581 vaf.fmt = fmt; 2582 vaf.va = &va; 2583 2584 switch (level) { 2585 case ql_log_fatal: /* FATAL LOG */ 2586 pr_crit("%s%pV", pbuf, &vaf); 2587 break; 2588 case ql_log_warn: 2589 pr_err("%s%pV", pbuf, &vaf); 2590 break; 2591 case ql_log_info: 2592 pr_warn("%s%pV", pbuf, &vaf); 2593 break; 2594 default: 2595 pr_info("%s%pV", pbuf, &vaf); 2596 break; 2597 } 2598 2599 va_end(va); 2600 } 2601 2602 /* 2603 * This function is for formatting and logging log messages. 2604 * It is to be used when vha is not available and pci is available, 2605 * i.e., before host allocation. It formats the message and logs 2606 * it to the messages file. All the messages are logged irrespective 2607 * of the value of ql2xextended_error_logging. 2608 * parameters: 2609 * level: The level of the log messages to be printed in the 2610 * messages file. 2611 * pdev: Pointer to the struct pci_dev. 2612 * id: This is a unique id for the level. It identifies the 2613 * part of the code from where the message originated. 2614 * msg: The message to be displayed. 2615 */ 2616 void 2617 ql_log_pci(uint level, struct pci_dev *pdev, uint id, const char *fmt, ...) 2618 { 2619 va_list va; 2620 struct va_format vaf; 2621 char pbuf[128]; 2622 2623 if (pdev == NULL) 2624 return; 2625 if (level > ql_errlev) 2626 return; 2627 2628 /* <module-name> <dev-name>:<msg-id> Message */ 2629 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", 2630 QL_MSGHDR, dev_name(&(pdev->dev)), id); 2631 pbuf[sizeof(pbuf) - 1] = 0; 2632 2633 va_start(va, fmt); 2634 2635 vaf.fmt = fmt; 2636 vaf.va = &va; 2637 2638 switch (level) { 2639 case ql_log_fatal: /* FATAL LOG */ 2640 pr_crit("%s%pV", pbuf, &vaf); 2641 break; 2642 case ql_log_warn: 2643 pr_err("%s%pV", pbuf, &vaf); 2644 break; 2645 case ql_log_info: 2646 pr_warn("%s%pV", pbuf, &vaf); 2647 break; 2648 default: 2649 pr_info("%s%pV", pbuf, &vaf); 2650 break; 2651 } 2652 2653 va_end(va); 2654 } 2655 2656 void 2657 ql_dump_regs(uint level, scsi_qla_host_t *vha, uint id) 2658 { 2659 int i; 2660 struct qla_hw_data *ha = vha->hw; 2661 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2662 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 2663 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; 2664 __le16 __iomem *mbx_reg; 2665 2666 if (!ql_mask_match(level)) 2667 return; 2668 2669 if (IS_P3P_TYPE(ha)) 2670 mbx_reg = ®82->mailbox_in[0]; 2671 else if (IS_FWI2_CAPABLE(ha)) 2672 mbx_reg = ®24->mailbox0; 2673 else 2674 mbx_reg = MAILBOX_REG(ha, reg, 0); 2675 2676 ql_dbg(level, vha, id, "Mailbox registers:\n"); 2677 for (i = 0; i < 6; i++, mbx_reg++) 2678 ql_dbg(level, vha, id, 2679 "mbox[%d] %#04x\n", i, rd_reg_word(mbx_reg)); 2680 } 2681 2682 2683 void 2684 ql_dump_buffer(uint level, scsi_qla_host_t *vha, uint id, const void *buf, 2685 uint size) 2686 { 2687 uint cnt; 2688 2689 if (!ql_mask_match(level)) 2690 return; 2691 2692 ql_dbg(level, vha, id, 2693 "%-+5d 0 1 2 3 4 5 6 7 8 9 A B C D E F\n", size); 2694 ql_dbg(level, vha, id, 2695 "----- -----------------------------------------------\n"); 2696 for (cnt = 0; cnt < size; cnt += 16) { 2697 ql_dbg(level, vha, id, "%04x: ", cnt); 2698 print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 16, 1, 2699 buf + cnt, min(16U, size - cnt), false); 2700 } 2701 } 2702 2703 /* 2704 * This function is for formatting and logging log messages. 2705 * It is to be used when vha is available. It formats the message 2706 * and logs it to the messages file. All the messages will be logged 2707 * irrespective of value of ql2xextended_error_logging. 2708 * parameters: 2709 * level: The level of the log messages to be printed in the 2710 * messages file. 2711 * vha: Pointer to the scsi_qla_host_t 2712 * id: This is a unique id for the level. It identifies the 2713 * part of the code from where the message originated. 2714 * msg: The message to be displayed. 2715 */ 2716 void 2717 ql_log_qp(uint32_t level, struct qla_qpair *qpair, int32_t id, 2718 const char *fmt, ...) 2719 { 2720 va_list va; 2721 struct va_format vaf; 2722 char pbuf[128]; 2723 2724 if (level > ql_errlev) 2725 return; 2726 2727 if (qpair != NULL) { 2728 const struct pci_dev *pdev = qpair->pdev; 2729 /* <module-name> <msg-id>:<host> Message */ 2730 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: ", 2731 QL_MSGHDR, dev_name(&(pdev->dev)), id); 2732 } else { 2733 snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", 2734 QL_MSGHDR, "0000:00:00.0", id); 2735 } 2736 pbuf[sizeof(pbuf) - 1] = 0; 2737 2738 va_start(va, fmt); 2739 2740 vaf.fmt = fmt; 2741 vaf.va = &va; 2742 2743 switch (level) { 2744 case ql_log_fatal: /* FATAL LOG */ 2745 pr_crit("%s%pV", pbuf, &vaf); 2746 break; 2747 case ql_log_warn: 2748 pr_err("%s%pV", pbuf, &vaf); 2749 break; 2750 case ql_log_info: 2751 pr_warn("%s%pV", pbuf, &vaf); 2752 break; 2753 default: 2754 pr_info("%s%pV", pbuf, &vaf); 2755 break; 2756 } 2757 2758 va_end(va); 2759 } 2760 2761 /* 2762 * This function is for formatting and logging debug information. 2763 * It is to be used when vha is available. It formats the message 2764 * and logs it to the messages file. 2765 * parameters: 2766 * level: The level of the debug messages to be printed. 2767 * If ql2xextended_error_logging value is correctly set, 2768 * this message will appear in the messages file. 2769 * vha: Pointer to the scsi_qla_host_t. 2770 * id: This is a unique identifier for the level. It identifies the 2771 * part of the code from where the message originated. 2772 * msg: The message to be displayed. 2773 */ 2774 void 2775 ql_dbg_qp(uint32_t level, struct qla_qpair *qpair, int32_t id, 2776 const char *fmt, ...) 2777 { 2778 va_list va; 2779 struct va_format vaf; 2780 2781 if (!ql_mask_match(level)) 2782 return; 2783 2784 va_start(va, fmt); 2785 2786 vaf.fmt = fmt; 2787 vaf.va = &va; 2788 2789 if (qpair != NULL) { 2790 const struct pci_dev *pdev = qpair->pdev; 2791 /* <module-name> <pci-name> <msg-id>:<host> Message */ 2792 pr_warn("%s [%s]-%04x: %pV", 2793 QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, 2794 &vaf); 2795 } else { 2796 pr_warn("%s [%s]-%04x: : %pV", 2797 QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); 2798 } 2799 2800 va_end(va); 2801 2802 } 2803