1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/jz4725b-cgu.h>
3#include <dt-bindings/clock/ingenic,tcu.h>
4
5/ {
6	#address-cells = <1>;
7	#size-cells = <1>;
8	compatible = "ingenic,jz4725b";
9
10	cpuintc: interrupt-controller {
11		#address-cells = <0>;
12		#interrupt-cells = <1>;
13		interrupt-controller;
14		compatible = "mti,cpu-interrupt-controller";
15	};
16
17	intc: interrupt-controller@10001000 {
18		compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc";
19		reg = <0x10001000 0x14>;
20
21		interrupt-controller;
22		#interrupt-cells = <1>;
23
24		interrupt-parent = <&cpuintc>;
25		interrupts = <2>;
26	};
27
28	ext: ext {
29		compatible = "fixed-clock";
30		#clock-cells = <0>;
31	};
32
33	osc32k: osc32k {
34		compatible = "fixed-clock";
35		#clock-cells = <0>;
36		clock-frequency = <32768>;
37	};
38
39	cgu: clock-controller@10000000 {
40		compatible = "ingenic,jz4725b-cgu";
41		reg = <0x10000000 0x100>;
42
43		clocks = <&ext>, <&osc32k>;
44		clock-names = "ext", "osc32k";
45
46		#clock-cells = <1>;
47	};
48
49	tcu: timer@10002000 {
50		compatible = "ingenic,jz4725b-tcu", "simple-mfd";
51		reg = <0x10002000 0x1000>;
52		#address-cells = <1>;
53		#size-cells = <1>;
54		ranges = <0x0 0x10002000 0x1000>;
55
56		#clock-cells = <1>;
57
58		clocks = <&cgu JZ4725B_CLK_RTC>,
59			 <&cgu JZ4725B_CLK_EXT>,
60			 <&cgu JZ4725B_CLK_PCLK>,
61			 <&cgu JZ4725B_CLK_TCU>;
62		clock-names = "rtc", "ext", "pclk", "tcu";
63
64		interrupt-controller;
65		#interrupt-cells = <1>;
66
67		interrupt-parent = <&intc>;
68		interrupts = <23>, <22>, <21>;
69
70		watchdog: watchdog@0 {
71			compatible = "ingenic,jz4725b-watchdog", "ingenic,jz4740-watchdog";
72			reg = <0x0 0xc>;
73
74			clocks = <&tcu TCU_CLK_WDT>;
75			clock-names = "wdt";
76		};
77
78		pwm: pwm@60 {
79			compatible = "ingenic,jz4725b-pwm";
80			reg = <0x60 0x40>;
81
82			#pwm-cells = <3>;
83
84			clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
85				 <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
86				 <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>;
87			clock-names = "timer0", "timer1", "timer2",
88				      "timer3", "timer4", "timer5";
89		};
90
91		ost: timer@e0 {
92			compatible = "ingenic,jz4725b-ost";
93			reg = <0xe0 0x20>;
94
95			clocks = <&tcu TCU_CLK_OST>;
96			clock-names = "ost";
97
98			interrupts = <15>;
99		};
100	};
101
102	rtc_dev: rtc@10003000 {
103		compatible = "ingenic,jz4725b-rtc", "ingenic,jz4740-rtc";
104		reg = <0x10003000 0x40>;
105
106		interrupt-parent = <&intc>;
107		interrupts = <6>;
108
109		clocks = <&cgu JZ4725B_CLK_RTC>;
110		clock-names = "rtc";
111	};
112
113	pinctrl: pinctrl@10010000 {
114		compatible = "ingenic,jz4725b-pinctrl";
115		reg = <0x10010000 0x400>;
116
117		#address-cells = <1>;
118		#size-cells = <0>;
119
120		gpa: gpio@0 {
121			compatible = "ingenic,jz4725b-gpio";
122			reg = <0>;
123
124			gpio-controller;
125			gpio-ranges = <&pinctrl 0 0 32>;
126			#gpio-cells = <2>;
127
128			interrupt-controller;
129			#interrupt-cells = <2>;
130
131			interrupt-parent = <&intc>;
132			interrupts = <16>;
133		};
134
135		gpb: gpio@1 {
136			compatible = "ingenic,jz4725b-gpio";
137			reg = <1>;
138
139			gpio-controller;
140			gpio-ranges = <&pinctrl 0 32 32>;
141			#gpio-cells = <2>;
142
143			interrupt-controller;
144			#interrupt-cells = <2>;
145
146			interrupt-parent = <&intc>;
147			interrupts = <15>;
148		};
149
150		gpc: gpio@2 {
151			compatible = "ingenic,jz4725b-gpio";
152			reg = <2>;
153
154			gpio-controller;
155			gpio-ranges = <&pinctrl 0 64 32>;
156			#gpio-cells = <2>;
157
158			interrupt-controller;
159			#interrupt-cells = <2>;
160
161			interrupt-parent = <&intc>;
162			interrupts = <14>;
163		};
164
165		gpd: gpio@3 {
166			compatible = "ingenic,jz4725b-gpio";
167			reg = <3>;
168
169			gpio-controller;
170			gpio-ranges = <&pinctrl 0 96 32>;
171			#gpio-cells = <2>;
172
173			interrupt-controller;
174			#interrupt-cells = <2>;
175
176			interrupt-parent = <&intc>;
177			interrupts = <13>;
178		};
179	};
180
181	aic: audio-controller@10020000 {
182		compatible = "ingenic,jz4725b-i2s", "ingenic,jz4740-i2s";
183		reg = <0x10020000 0x38>;
184
185		#sound-dai-cells = <0>;
186
187		clocks = <&cgu JZ4725B_CLK_AIC>,
188			 <&cgu JZ4725B_CLK_I2S>,
189			 <&cgu JZ4725B_CLK_EXT>,
190			 <&cgu JZ4725B_CLK_PLL_HALF>;
191		clock-names = "aic", "i2s", "ext", "pll half";
192
193		interrupt-parent = <&intc>;
194		interrupts = <10>;
195
196		dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
197		dma-names = "rx", "tx";
198	};
199
200	codec: audio-codec@100200a4 {
201		compatible = "ingenic,jz4725b-codec";
202		reg = <0x100200a4 0x8>;
203
204		#sound-dai-cells = <0>;
205
206		clocks = <&cgu JZ4725B_CLK_AIC>;
207		clock-names = "aic";
208	};
209
210	mmc0: mmc@10021000 {
211		compatible = "ingenic,jz4725b-mmc";
212		reg = <0x10021000 0x1000>;
213
214		clocks = <&cgu JZ4725B_CLK_MMC0>;
215		clock-names = "mmc";
216
217		interrupt-parent = <&intc>;
218		interrupts = <25>;
219
220		dmas = <&dmac 27 0xffffffff>, <&dmac 26 0xffffffff>;
221		dma-names = "rx", "tx";
222
223		cap-sd-highspeed;
224		cap-mmc-highspeed;
225		cap-sdio-irq;
226	};
227
228	mmc1: mmc@10022000 {
229		compatible = "ingenic,jz4725b-mmc";
230		reg = <0x10022000 0x1000>;
231
232		clocks = <&cgu JZ4725B_CLK_MMC1>;
233		clock-names = "mmc";
234
235		interrupt-parent = <&intc>;
236		interrupts = <24>;
237
238		dmas = <&dmac 31 0xffffffff>, <&dmac 30 0xffffffff>;
239		dma-names = "rx", "tx";
240
241		cap-sd-highspeed;
242		cap-mmc-highspeed;
243		cap-sdio-irq;
244	};
245
246	uart: serial@10030000 {
247		compatible = "ingenic,jz4725b-uart", "ingenic,jz4740-uart";
248		reg = <0x10030000 0x100>;
249
250		interrupt-parent = <&intc>;
251		interrupts = <9>;
252
253		clocks = <&ext>, <&cgu JZ4725B_CLK_UART>;
254		clock-names = "baud", "module";
255	};
256
257	adc: adc@10070000 {
258		compatible = "ingenic,jz4725b-adc";
259		#io-channel-cells = <1>;
260
261		reg = <0x10070000 0x30>;
262		#address-cells = <1>;
263		#size-cells = <1>;
264		ranges = <0x0 0x10070000 0x30>;
265
266		clocks = <&cgu JZ4725B_CLK_ADC>;
267		clock-names = "adc";
268
269		interrupt-parent = <&intc>;
270		interrupts = <18>;
271	};
272
273	nemc: memory-controller@13010000 {
274		compatible = "ingenic,jz4725b-nemc", "ingenic,jz4740-nemc";
275		reg = <0x13010000 0x10000>;
276		#address-cells = <2>;
277		#size-cells = <1>;
278		ranges = <1 0 0x18000000 0x4000000>, <2 0 0x14000000 0x4000000>,
279			 <3 0 0x0c000000 0x4000000>, <4 0 0x08000000 0x4000000>;
280
281		clocks = <&cgu JZ4725B_CLK_MCLK>;
282	};
283
284	dmac: dma-controller@13020000 {
285		compatible = "ingenic,jz4725b-dma";
286		reg = <0x13020000 0xd8>, <0x13020300 0x14>;
287
288		#dma-cells = <2>;
289
290		interrupt-parent = <&intc>;
291		interrupts = <29>;
292
293		clocks = <&cgu JZ4725B_CLK_DMA>;
294	};
295
296	udc: usb@13040000 {
297		compatible = "ingenic,jz4725b-musb", "ingenic,jz4740-musb";
298		reg = <0x13040000 0x10000>;
299
300		interrupt-parent = <&intc>;
301		interrupts = <27>;
302		interrupt-names = "mc";
303
304		clocks = <&cgu JZ4725B_CLK_UDC>;
305		clock-names = "udc";
306	};
307
308	lcd: lcd-controller@13050000 {
309		compatible = "ingenic,jz4725b-lcd";
310		reg = <0x13050000 0x1000>;
311
312		interrupt-parent = <&intc>;
313		interrupts = <31>;
314
315		clocks = <&cgu JZ4725B_CLK_LCD>;
316		clock-names = "lcd_pclk";
317
318		lcd_ports: ports {
319			#address-cells = <1>;
320			#size-cells = <0>;
321
322			port@8 {
323				reg = <8>;
324
325				ipu_output: endpoint {
326					remote-endpoint = <&ipu_input>;
327				};
328			};
329		};
330	};
331
332	ipu: ipu@13080000 {
333		compatible = "ingenic,jz4725b-ipu";
334		reg = <0x13080000 0x64>;
335
336		interrupt-parent = <&intc>;
337		interrupts = <30>;
338
339		clocks = <&cgu JZ4725B_CLK_IPU>;
340		clock-names = "ipu";
341
342		port {
343			ipu_input: endpoint {
344				remote-endpoint = <&ipu_output>;
345			};
346		};
347	};
348
349	bch: ecc-controller@130d0000 {
350		compatible = "ingenic,jz4725b-bch";
351		reg = <0x130d0000 0x44>;
352
353		clocks = <&cgu JZ4725B_CLK_BCH>;
354	};
355
356	rom: memory@1fc00000 {
357		compatible = "mtd-rom";
358		probe-type = "map_rom";
359		reg = <0x1fc00000 0x2000>;
360
361		bank-width = <4>;
362		device-width = <1>;
363	};
364};
365