1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Aquantia PHY 4 * 5 * Author: Shaohui Xie <Shaohui.Xie@freescale.com> 6 * 7 * Copyright 2015 Freescale Semiconductor, Inc. 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/delay.h> 13 #include <linux/bitfield.h> 14 #include <linux/phy.h> 15 16 #include "aquantia.h" 17 18 #define PHY_ID_AQ1202 0x03a1b445 19 #define PHY_ID_AQ2104 0x03a1b460 20 #define PHY_ID_AQR105 0x03a1b4a2 21 #define PHY_ID_AQR106 0x03a1b4d0 22 #define PHY_ID_AQR107 0x03a1b4e0 23 #define PHY_ID_AQCS109 0x03a1b5c2 24 #define PHY_ID_AQR405 0x03a1b4b0 25 26 #define MDIO_PHYXS_VEND_IF_STATUS 0xe812 27 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK GENMASK(7, 3) 28 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR 0 29 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI 2 30 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII 3 31 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6 32 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10 33 34 #define MDIO_AN_VEND_PROV 0xc400 35 #define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15) 36 #define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14) 37 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4) 38 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0) 39 #define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4 40 41 #define MDIO_AN_TX_VEND_STATUS1 0xc800 42 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1) 43 #define MDIO_AN_TX_VEND_STATUS1_10BASET 0 44 #define MDIO_AN_TX_VEND_STATUS1_100BASETX 1 45 #define MDIO_AN_TX_VEND_STATUS1_1000BASET 2 46 #define MDIO_AN_TX_VEND_STATUS1_10GBASET 3 47 #define MDIO_AN_TX_VEND_STATUS1_2500BASET 4 48 #define MDIO_AN_TX_VEND_STATUS1_5000BASET 5 49 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX BIT(0) 50 51 #define MDIO_AN_TX_VEND_INT_STATUS1 0xcc00 52 #define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT BIT(1) 53 54 #define MDIO_AN_TX_VEND_INT_STATUS2 0xcc01 55 56 #define MDIO_AN_TX_VEND_INT_MASK2 0xd401 57 #define MDIO_AN_TX_VEND_INT_MASK2_LINK BIT(0) 58 59 #define MDIO_AN_RX_LP_STAT1 0xe820 60 #define MDIO_AN_RX_LP_STAT1_1000BASET_FULL BIT(15) 61 #define MDIO_AN_RX_LP_STAT1_1000BASET_HALF BIT(14) 62 #define MDIO_AN_RX_LP_STAT1_SHORT_REACH BIT(13) 63 #define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT BIT(12) 64 #define MDIO_AN_RX_LP_STAT1_AQ_PHY BIT(2) 65 66 #define MDIO_AN_RX_LP_STAT4 0xe823 67 #define MDIO_AN_RX_LP_STAT4_FW_MAJOR GENMASK(15, 8) 68 #define MDIO_AN_RX_LP_STAT4_FW_MINOR GENMASK(7, 0) 69 70 #define MDIO_AN_RX_VEND_STAT3 0xe832 71 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0) 72 73 /* MDIO_MMD_C22EXT */ 74 #define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292 75 #define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294 76 #define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297 77 #define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313 78 #define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315 79 #define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317 80 #define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318 81 #define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319 82 #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a 83 #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b 84 85 /* Vendor specific 1, MDIO_MMD_VEND1 */ 86 #define VEND1_GLOBAL_FW_ID 0x0020 87 #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8) 88 #define VEND1_GLOBAL_FW_ID_MINOR GENMASK(7, 0) 89 90 #define VEND1_GLOBAL_RSVD_STAT1 0xc885 91 #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID GENMASK(7, 4) 92 #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID GENMASK(3, 0) 93 94 #define VEND1_GLOBAL_RSVD_STAT9 0xc88d 95 #define VEND1_GLOBAL_RSVD_STAT9_MODE GENMASK(7, 0) 96 #define VEND1_GLOBAL_RSVD_STAT9_1000BT2 0x23 97 98 #define VEND1_GLOBAL_INT_STD_STATUS 0xfc00 99 #define VEND1_GLOBAL_INT_VEND_STATUS 0xfc01 100 101 #define VEND1_GLOBAL_INT_STD_MASK 0xff00 102 #define VEND1_GLOBAL_INT_STD_MASK_PMA1 BIT(15) 103 #define VEND1_GLOBAL_INT_STD_MASK_PMA2 BIT(14) 104 #define VEND1_GLOBAL_INT_STD_MASK_PCS1 BIT(13) 105 #define VEND1_GLOBAL_INT_STD_MASK_PCS2 BIT(12) 106 #define VEND1_GLOBAL_INT_STD_MASK_PCS3 BIT(11) 107 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1 BIT(10) 108 #define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2 BIT(9) 109 #define VEND1_GLOBAL_INT_STD_MASK_AN1 BIT(8) 110 #define VEND1_GLOBAL_INT_STD_MASK_AN2 BIT(7) 111 #define VEND1_GLOBAL_INT_STD_MASK_GBE BIT(6) 112 #define VEND1_GLOBAL_INT_STD_MASK_ALL BIT(0) 113 114 #define VEND1_GLOBAL_INT_VEND_MASK 0xff01 115 #define VEND1_GLOBAL_INT_VEND_MASK_PMA BIT(15) 116 #define VEND1_GLOBAL_INT_VEND_MASK_PCS BIT(14) 117 #define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS BIT(13) 118 #define VEND1_GLOBAL_INT_VEND_MASK_AN BIT(12) 119 #define VEND1_GLOBAL_INT_VEND_MASK_GBE BIT(11) 120 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1 BIT(2) 121 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1) 122 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0) 123 124 struct aqr107_hw_stat { 125 const char *name; 126 int reg; 127 int size; 128 }; 129 130 #define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s } 131 static const struct aqr107_hw_stat aqr107_hw_stats[] = { 132 SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26), 133 SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26), 134 SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8), 135 SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26), 136 SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26), 137 SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8), 138 SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8), 139 SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8), 140 SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16), 141 SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22), 142 }; 143 #define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats) 144 145 struct aqr107_priv { 146 u64 sgmii_stats[AQR107_SGMII_STAT_SZ]; 147 }; 148 149 static int aqr107_get_sset_count(struct phy_device *phydev) 150 { 151 return AQR107_SGMII_STAT_SZ; 152 } 153 154 static void aqr107_get_strings(struct phy_device *phydev, u8 *data) 155 { 156 int i; 157 158 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) 159 strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name, 160 ETH_GSTRING_LEN); 161 } 162 163 static u64 aqr107_get_stat(struct phy_device *phydev, int index) 164 { 165 const struct aqr107_hw_stat *stat = aqr107_hw_stats + index; 166 int len_l = min(stat->size, 16); 167 int len_h = stat->size - len_l; 168 u64 ret; 169 int val; 170 171 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg); 172 if (val < 0) 173 return U64_MAX; 174 175 ret = val & GENMASK(len_l - 1, 0); 176 if (len_h) { 177 val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1); 178 if (val < 0) 179 return U64_MAX; 180 181 ret += (val & GENMASK(len_h - 1, 0)) << 16; 182 } 183 184 return ret; 185 } 186 187 static void aqr107_get_stats(struct phy_device *phydev, 188 struct ethtool_stats *stats, u64 *data) 189 { 190 struct aqr107_priv *priv = phydev->priv; 191 u64 val; 192 int i; 193 194 for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) { 195 val = aqr107_get_stat(phydev, i); 196 if (val == U64_MAX) 197 phydev_err(phydev, "Reading HW Statistics failed for %s\n", 198 aqr107_hw_stats[i].name); 199 else 200 priv->sgmii_stats[i] += val; 201 202 data[i] = priv->sgmii_stats[i]; 203 } 204 } 205 206 static int aqr_config_aneg(struct phy_device *phydev) 207 { 208 bool changed = false; 209 u16 reg; 210 int ret; 211 212 if (phydev->autoneg == AUTONEG_DISABLE) 213 return genphy_c45_pma_setup_forced(phydev); 214 215 ret = genphy_c45_an_config_aneg(phydev); 216 if (ret < 0) 217 return ret; 218 if (ret > 0) 219 changed = true; 220 221 /* Clause 45 has no standardized support for 1000BaseT, therefore 222 * use vendor registers for this mode. 223 */ 224 reg = 0; 225 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 226 phydev->advertising)) 227 reg |= MDIO_AN_VEND_PROV_1000BASET_FULL; 228 229 if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 230 phydev->advertising)) 231 reg |= MDIO_AN_VEND_PROV_1000BASET_HALF; 232 233 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 234 MDIO_AN_VEND_PROV_1000BASET_HALF | 235 MDIO_AN_VEND_PROV_1000BASET_FULL, reg); 236 if (ret < 0) 237 return ret; 238 if (ret > 0) 239 changed = true; 240 241 return genphy_c45_check_and_restart_aneg(phydev, changed); 242 } 243 244 static int aqr_config_intr(struct phy_device *phydev) 245 { 246 bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED; 247 int err; 248 249 err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2, 250 en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0); 251 if (err < 0) 252 return err; 253 254 err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK, 255 en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0); 256 if (err < 0) 257 return err; 258 259 return phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK, 260 en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 | 261 VEND1_GLOBAL_INT_VEND_MASK_AN : 0); 262 } 263 264 static int aqr_ack_interrupt(struct phy_device *phydev) 265 { 266 int reg; 267 268 reg = phy_read_mmd(phydev, MDIO_MMD_AN, 269 MDIO_AN_TX_VEND_INT_STATUS2); 270 return (reg < 0) ? reg : 0; 271 } 272 273 static int aqr_read_status(struct phy_device *phydev) 274 { 275 int val; 276 277 if (phydev->autoneg == AUTONEG_ENABLE) { 278 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 279 if (val < 0) 280 return val; 281 282 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 283 phydev->lp_advertising, 284 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL); 285 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 286 phydev->lp_advertising, 287 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF); 288 } 289 290 return genphy_c45_read_status(phydev); 291 } 292 293 static int aqr107_read_downshift_event(struct phy_device *phydev) 294 { 295 int val; 296 297 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS1); 298 if (val < 0) 299 return val; 300 301 return !!(val & MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT); 302 } 303 304 static int aqr107_read_rate(struct phy_device *phydev) 305 { 306 int val; 307 308 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1); 309 if (val < 0) 310 return val; 311 312 switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) { 313 case MDIO_AN_TX_VEND_STATUS1_10BASET: 314 phydev->speed = SPEED_10; 315 break; 316 case MDIO_AN_TX_VEND_STATUS1_100BASETX: 317 phydev->speed = SPEED_100; 318 break; 319 case MDIO_AN_TX_VEND_STATUS1_1000BASET: 320 phydev->speed = SPEED_1000; 321 break; 322 case MDIO_AN_TX_VEND_STATUS1_2500BASET: 323 phydev->speed = SPEED_2500; 324 break; 325 case MDIO_AN_TX_VEND_STATUS1_5000BASET: 326 phydev->speed = SPEED_5000; 327 break; 328 case MDIO_AN_TX_VEND_STATUS1_10GBASET: 329 phydev->speed = SPEED_10000; 330 break; 331 default: 332 phydev->speed = SPEED_UNKNOWN; 333 break; 334 } 335 336 if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX) 337 phydev->duplex = DUPLEX_FULL; 338 else 339 phydev->duplex = DUPLEX_HALF; 340 341 return 0; 342 } 343 344 static int aqr107_read_status(struct phy_device *phydev) 345 { 346 int val, ret; 347 348 ret = aqr_read_status(phydev); 349 if (ret) 350 return ret; 351 352 if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE) 353 return 0; 354 355 val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS); 356 if (val < 0) 357 return val; 358 359 switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) { 360 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR: 361 phydev->interface = PHY_INTERFACE_MODE_10GKR; 362 break; 363 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI: 364 phydev->interface = PHY_INTERFACE_MODE_10GBASER; 365 break; 366 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII: 367 phydev->interface = PHY_INTERFACE_MODE_USXGMII; 368 break; 369 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII: 370 phydev->interface = PHY_INTERFACE_MODE_SGMII; 371 break; 372 case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII: 373 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 374 break; 375 default: 376 phydev->interface = PHY_INTERFACE_MODE_NA; 377 break; 378 } 379 380 val = aqr107_read_downshift_event(phydev); 381 if (val <= 0) 382 return val; 383 384 phydev_warn(phydev, "Downshift occurred! Cabling may be defective.\n"); 385 386 /* Read downshifted rate from vendor register */ 387 return aqr107_read_rate(phydev); 388 } 389 390 static int aqr107_get_downshift(struct phy_device *phydev, u8 *data) 391 { 392 int val, cnt, enable; 393 394 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV); 395 if (val < 0) 396 return val; 397 398 enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val); 399 cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 400 401 *data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE; 402 403 return 0; 404 } 405 406 static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt) 407 { 408 int val = 0; 409 410 if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt)) 411 return -E2BIG; 412 413 if (cnt != DOWNSHIFT_DEV_DISABLE) { 414 val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN; 415 val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt); 416 } 417 418 return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV, 419 MDIO_AN_VEND_PROV_DOWNSHIFT_EN | 420 MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val); 421 } 422 423 static int aqr107_get_tunable(struct phy_device *phydev, 424 struct ethtool_tunable *tuna, void *data) 425 { 426 switch (tuna->id) { 427 case ETHTOOL_PHY_DOWNSHIFT: 428 return aqr107_get_downshift(phydev, data); 429 default: 430 return -EOPNOTSUPP; 431 } 432 } 433 434 static int aqr107_set_tunable(struct phy_device *phydev, 435 struct ethtool_tunable *tuna, const void *data) 436 { 437 switch (tuna->id) { 438 case ETHTOOL_PHY_DOWNSHIFT: 439 return aqr107_set_downshift(phydev, *(const u8 *)data); 440 default: 441 return -EOPNOTSUPP; 442 } 443 } 444 445 /* If we configure settings whilst firmware is still initializing the chip, 446 * then these settings may be overwritten. Therefore make sure chip 447 * initialization has completed. Use presence of the firmware ID as 448 * indicator for initialization having completed. 449 * The chip also provides a "reset completed" bit, but it's cleared after 450 * read. Therefore function would time out if called again. 451 */ 452 static int aqr107_wait_reset_complete(struct phy_device *phydev) 453 { 454 int val, retries = 100; 455 456 do { 457 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 458 if (val < 0) 459 return val; 460 msleep(20); 461 } while (!val && --retries); 462 463 return val ? 0 : -ETIMEDOUT; 464 } 465 466 static void aqr107_chip_info(struct phy_device *phydev) 467 { 468 u8 fw_major, fw_minor, build_id, prov_id; 469 int val; 470 471 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID); 472 if (val < 0) 473 return; 474 475 fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val); 476 fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val); 477 478 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1); 479 if (val < 0) 480 return; 481 482 build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val); 483 prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val); 484 485 phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n", 486 fw_major, fw_minor, build_id, prov_id); 487 } 488 489 static int aqr107_config_init(struct phy_device *phydev) 490 { 491 int ret; 492 493 /* Check that the PHY interface type is compatible */ 494 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 495 phydev->interface != PHY_INTERFACE_MODE_2500BASEX && 496 phydev->interface != PHY_INTERFACE_MODE_XGMII && 497 phydev->interface != PHY_INTERFACE_MODE_USXGMII && 498 phydev->interface != PHY_INTERFACE_MODE_10GKR && 499 phydev->interface != PHY_INTERFACE_MODE_10GBASER) 500 return -ENODEV; 501 502 WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII, 503 "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n"); 504 505 ret = aqr107_wait_reset_complete(phydev); 506 if (!ret) 507 aqr107_chip_info(phydev); 508 509 /* ensure that a latched downshift event is cleared */ 510 aqr107_read_downshift_event(phydev); 511 512 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 513 } 514 515 static int aqcs109_config_init(struct phy_device *phydev) 516 { 517 int ret; 518 519 /* Check that the PHY interface type is compatible */ 520 if (phydev->interface != PHY_INTERFACE_MODE_SGMII && 521 phydev->interface != PHY_INTERFACE_MODE_2500BASEX) 522 return -ENODEV; 523 524 ret = aqr107_wait_reset_complete(phydev); 525 if (!ret) 526 aqr107_chip_info(phydev); 527 528 /* AQCS109 belongs to a chip family partially supporting 10G and 5G. 529 * PMA speed ability bits are the same for all members of the family, 530 * AQCS109 however supports speeds up to 2.5G only. 531 */ 532 ret = phy_set_max_speed(phydev, SPEED_2500); 533 if (ret) 534 return ret; 535 536 /* ensure that a latched downshift event is cleared */ 537 aqr107_read_downshift_event(phydev); 538 539 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT); 540 } 541 542 static void aqr107_link_change_notify(struct phy_device *phydev) 543 { 544 u8 fw_major, fw_minor; 545 bool downshift, short_reach, afr; 546 int mode, val; 547 548 if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE) 549 return; 550 551 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1); 552 /* call failed or link partner is no Aquantia PHY */ 553 if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY)) 554 return; 555 556 short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH; 557 downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT; 558 559 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4); 560 if (val < 0) 561 return; 562 563 fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val); 564 fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val); 565 566 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3); 567 if (val < 0) 568 return; 569 570 afr = val & MDIO_AN_RX_VEND_STAT3_AFR; 571 572 phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n", 573 fw_major, fw_minor, 574 short_reach ? ", short reach mode" : "", 575 downshift ? ", fast-retrain downshift advertised" : "", 576 afr ? ", fast reframe advertised" : ""); 577 578 val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9); 579 if (val < 0) 580 return; 581 582 mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val); 583 if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2) 584 phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n"); 585 } 586 587 static int aqr107_suspend(struct phy_device *phydev) 588 { 589 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 590 MDIO_CTRL1_LPOWER); 591 } 592 593 static int aqr107_resume(struct phy_device *phydev) 594 { 595 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1, 596 MDIO_CTRL1_LPOWER); 597 } 598 599 static int aqr107_probe(struct phy_device *phydev) 600 { 601 phydev->priv = devm_kzalloc(&phydev->mdio.dev, 602 sizeof(struct aqr107_priv), GFP_KERNEL); 603 if (!phydev->priv) 604 return -ENOMEM; 605 606 return aqr_hwmon_probe(phydev); 607 } 608 609 static struct phy_driver aqr_driver[] = { 610 { 611 PHY_ID_MATCH_MODEL(PHY_ID_AQ1202), 612 .name = "Aquantia AQ1202", 613 .config_aneg = aqr_config_aneg, 614 .config_intr = aqr_config_intr, 615 .ack_interrupt = aqr_ack_interrupt, 616 .read_status = aqr_read_status, 617 }, 618 { 619 PHY_ID_MATCH_MODEL(PHY_ID_AQ2104), 620 .name = "Aquantia AQ2104", 621 .config_aneg = aqr_config_aneg, 622 .config_intr = aqr_config_intr, 623 .ack_interrupt = aqr_ack_interrupt, 624 .read_status = aqr_read_status, 625 }, 626 { 627 PHY_ID_MATCH_MODEL(PHY_ID_AQR105), 628 .name = "Aquantia AQR105", 629 .config_aneg = aqr_config_aneg, 630 .config_intr = aqr_config_intr, 631 .ack_interrupt = aqr_ack_interrupt, 632 .read_status = aqr_read_status, 633 .suspend = aqr107_suspend, 634 .resume = aqr107_resume, 635 }, 636 { 637 PHY_ID_MATCH_MODEL(PHY_ID_AQR106), 638 .name = "Aquantia AQR106", 639 .config_aneg = aqr_config_aneg, 640 .config_intr = aqr_config_intr, 641 .ack_interrupt = aqr_ack_interrupt, 642 .read_status = aqr_read_status, 643 }, 644 { 645 PHY_ID_MATCH_MODEL(PHY_ID_AQR107), 646 .name = "Aquantia AQR107", 647 .probe = aqr107_probe, 648 .config_init = aqr107_config_init, 649 .config_aneg = aqr_config_aneg, 650 .config_intr = aqr_config_intr, 651 .ack_interrupt = aqr_ack_interrupt, 652 .read_status = aqr107_read_status, 653 .get_tunable = aqr107_get_tunable, 654 .set_tunable = aqr107_set_tunable, 655 .suspend = aqr107_suspend, 656 .resume = aqr107_resume, 657 .get_sset_count = aqr107_get_sset_count, 658 .get_strings = aqr107_get_strings, 659 .get_stats = aqr107_get_stats, 660 .link_change_notify = aqr107_link_change_notify, 661 }, 662 { 663 PHY_ID_MATCH_MODEL(PHY_ID_AQCS109), 664 .name = "Aquantia AQCS109", 665 .probe = aqr107_probe, 666 .config_init = aqcs109_config_init, 667 .config_aneg = aqr_config_aneg, 668 .config_intr = aqr_config_intr, 669 .ack_interrupt = aqr_ack_interrupt, 670 .read_status = aqr107_read_status, 671 .get_tunable = aqr107_get_tunable, 672 .set_tunable = aqr107_set_tunable, 673 .suspend = aqr107_suspend, 674 .resume = aqr107_resume, 675 .get_sset_count = aqr107_get_sset_count, 676 .get_strings = aqr107_get_strings, 677 .get_stats = aqr107_get_stats, 678 .link_change_notify = aqr107_link_change_notify, 679 }, 680 { 681 PHY_ID_MATCH_MODEL(PHY_ID_AQR405), 682 .name = "Aquantia AQR405", 683 .config_aneg = aqr_config_aneg, 684 .config_intr = aqr_config_intr, 685 .ack_interrupt = aqr_ack_interrupt, 686 .read_status = aqr_read_status, 687 }, 688 }; 689 690 module_phy_driver(aqr_driver); 691 692 static struct mdio_device_id __maybe_unused aqr_tbl[] = { 693 { PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) }, 694 { PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) }, 695 { PHY_ID_MATCH_MODEL(PHY_ID_AQR105) }, 696 { PHY_ID_MATCH_MODEL(PHY_ID_AQR106) }, 697 { PHY_ID_MATCH_MODEL(PHY_ID_AQR107) }, 698 { PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) }, 699 { PHY_ID_MATCH_MODEL(PHY_ID_AQR405) }, 700 { } 701 }; 702 703 MODULE_DEVICE_TABLE(mdio, aqr_tbl); 704 705 MODULE_DESCRIPTION("Aquantia PHY driver"); 706 MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>"); 707 MODULE_LICENSE("GPL v2"); 708