1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel ADC driver for SAMA5D2 devices and compatible. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of_device.h> 17 #include <linux/platform_device.h> 18 #include <linux/sched.h> 19 #include <linux/wait.h> 20 #include <linux/iio/iio.h> 21 #include <linux/iio/sysfs.h> 22 #include <linux/iio/buffer.h> 23 #include <linux/iio/trigger.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/triggered_buffer.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/regulator/consumer.h> 28 29 /* Control Register */ 30 #define AT91_SAMA5D2_CR 0x00 31 /* Software Reset */ 32 #define AT91_SAMA5D2_CR_SWRST BIT(0) 33 /* Start Conversion */ 34 #define AT91_SAMA5D2_CR_START BIT(1) 35 /* Touchscreen Calibration */ 36 #define AT91_SAMA5D2_CR_TSCALIB BIT(2) 37 /* Comparison Restart */ 38 #define AT91_SAMA5D2_CR_CMPRST BIT(4) 39 40 /* Mode Register */ 41 #define AT91_SAMA5D2_MR 0x04 42 /* Trigger Selection */ 43 #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1) 44 /* ADTRG */ 45 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0 46 /* TIOA0 */ 47 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1 48 /* TIOA1 */ 49 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2 50 /* TIOA2 */ 51 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3 52 /* PWM event line 0 */ 53 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4 54 /* PWM event line 1 */ 55 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5 56 /* TIOA3 */ 57 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6 58 /* RTCOUT0 */ 59 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7 60 /* Sleep Mode */ 61 #define AT91_SAMA5D2_MR_SLEEP BIT(5) 62 /* Fast Wake Up */ 63 #define AT91_SAMA5D2_MR_FWUP BIT(6) 64 /* Prescaler Rate Selection */ 65 #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET) 66 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8 67 #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff 68 #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8) 69 /* Startup Time */ 70 #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16) 71 #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16) 72 /* Analog Change */ 73 #define AT91_SAMA5D2_MR_ANACH BIT(23) 74 /* Tracking Time */ 75 #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24) 76 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff 77 /* Transfer Time */ 78 #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28) 79 #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3 80 /* Use Sequence Enable */ 81 #define AT91_SAMA5D2_MR_USEQ BIT(31) 82 83 /* Channel Sequence Register 1 */ 84 #define AT91_SAMA5D2_SEQR1 0x08 85 /* Channel Sequence Register 2 */ 86 #define AT91_SAMA5D2_SEQR2 0x0c 87 /* Channel Enable Register */ 88 #define AT91_SAMA5D2_CHER 0x10 89 /* Channel Disable Register */ 90 #define AT91_SAMA5D2_CHDR 0x14 91 /* Channel Status Register */ 92 #define AT91_SAMA5D2_CHSR 0x18 93 /* Last Converted Data Register */ 94 #define AT91_SAMA5D2_LCDR 0x20 95 /* Interrupt Enable Register */ 96 #define AT91_SAMA5D2_IER 0x24 97 /* Interrupt Enable Register - TS X measurement ready */ 98 #define AT91_SAMA5D2_IER_XRDY BIT(20) 99 /* Interrupt Enable Register - TS Y measurement ready */ 100 #define AT91_SAMA5D2_IER_YRDY BIT(21) 101 /* Interrupt Enable Register - TS pressure measurement ready */ 102 #define AT91_SAMA5D2_IER_PRDY BIT(22) 103 /* Interrupt Enable Register - general overrun error */ 104 #define AT91_SAMA5D2_IER_GOVRE BIT(25) 105 /* Interrupt Enable Register - Pen detect */ 106 #define AT91_SAMA5D2_IER_PEN BIT(29) 107 /* Interrupt Enable Register - No pen detect */ 108 #define AT91_SAMA5D2_IER_NOPEN BIT(30) 109 /* Interrupt Disable Register */ 110 #define AT91_SAMA5D2_IDR 0x28 111 /* Interrupt Mask Register */ 112 #define AT91_SAMA5D2_IMR 0x2c 113 /* Interrupt Status Register */ 114 #define AT91_SAMA5D2_ISR 0x30 115 /* Interrupt Status Register - Pen touching sense status */ 116 #define AT91_SAMA5D2_ISR_PENS BIT(31) 117 /* Last Channel Trigger Mode Register */ 118 #define AT91_SAMA5D2_LCTMR 0x34 119 /* Last Channel Compare Window Register */ 120 #define AT91_SAMA5D2_LCCWR 0x38 121 /* Overrun Status Register */ 122 #define AT91_SAMA5D2_OVER 0x3c 123 /* Extended Mode Register */ 124 #define AT91_SAMA5D2_EMR 0x40 125 /* Extended Mode Register - Oversampling rate */ 126 #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16) 127 #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16) 128 #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0 129 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1 130 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2 131 132 /* Extended Mode Register - Averaging on single trigger event */ 133 #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20) 134 /* Compare Window Register */ 135 #define AT91_SAMA5D2_CWR 0x44 136 /* Channel Gain Register */ 137 #define AT91_SAMA5D2_CGR 0x48 138 139 /* Channel Offset Register */ 140 #define AT91_SAMA5D2_COR 0x4c 141 #define AT91_SAMA5D2_COR_DIFF_OFFSET 16 142 143 /* Channel Data Register 0 */ 144 #define AT91_SAMA5D2_CDR0 0x50 145 /* Analog Control Register */ 146 #define AT91_SAMA5D2_ACR 0x94 147 /* Analog Control Register - Pen detect sensitivity mask */ 148 #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0) 149 150 /* Touchscreen Mode Register */ 151 #define AT91_SAMA5D2_TSMR 0xb0 152 /* Touchscreen Mode Register - No touch mode */ 153 #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0 154 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */ 155 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1 156 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */ 157 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2 158 /* Touchscreen Mode Register - 5 wire screen */ 159 #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3 160 /* Touchscreen Mode Register - Average samples mask */ 161 #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4) 162 /* Touchscreen Mode Register - Average samples */ 163 #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4) 164 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */ 165 #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8) 166 /* Touchscreen Mode Register - Touch/trigger frequency ratio */ 167 #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8) 168 /* Touchscreen Mode Register - Pen Debounce Time mask */ 169 #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28) 170 /* Touchscreen Mode Register - Pen Debounce Time */ 171 #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28) 172 /* Touchscreen Mode Register - No DMA for touch measurements */ 173 #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22) 174 /* Touchscreen Mode Register - Disable pen detection */ 175 #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24) 176 /* Touchscreen Mode Register - Enable pen detection */ 177 #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24) 178 179 /* Touchscreen X Position Register */ 180 #define AT91_SAMA5D2_XPOSR 0xb4 181 /* Touchscreen Y Position Register */ 182 #define AT91_SAMA5D2_YPOSR 0xb8 183 /* Touchscreen Pressure Register */ 184 #define AT91_SAMA5D2_PRESSR 0xbc 185 /* Trigger Register */ 186 #define AT91_SAMA5D2_TRGR 0xc0 187 /* Mask for TRGMOD field of TRGR register */ 188 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0) 189 /* No trigger, only software trigger can start conversions */ 190 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0 191 /* Trigger Mode external trigger rising edge */ 192 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1 193 /* Trigger Mode external trigger falling edge */ 194 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2 195 /* Trigger Mode external trigger any edge */ 196 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3 197 /* Trigger Mode internal periodic */ 198 #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5 199 /* Trigger Mode - trigger period mask */ 200 #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16) 201 /* Trigger Mode - trigger period */ 202 #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16) 203 204 /* Correction Select Register */ 205 #define AT91_SAMA5D2_COSR 0xd0 206 /* Correction Value Register */ 207 #define AT91_SAMA5D2_CVR 0xd4 208 /* Channel Error Correction Register */ 209 #define AT91_SAMA5D2_CECR 0xd8 210 /* Write Protection Mode Register */ 211 #define AT91_SAMA5D2_WPMR 0xe4 212 /* Write Protection Status Register */ 213 #define AT91_SAMA5D2_WPSR 0xe8 214 /* Version Register */ 215 #define AT91_SAMA5D2_VERSION 0xfc 216 217 #define AT91_SAMA5D2_HW_TRIG_CNT 3 218 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12 219 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6 220 221 #define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 222 AT91_SAMA5D2_DIFF_CHAN_CNT + 1) 223 224 #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 225 AT91_SAMA5D2_DIFF_CHAN_CNT * 2) 226 #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1) 227 #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1) 228 #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX 229 230 #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ 231 #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200 232 233 #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0) 234 235 #define AT91_SAMA5D2_MAX_POS_BITS 12 236 237 /* 238 * Maximum number of bytes to hold conversion from all channels 239 * without the timestamp. 240 */ 241 #define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 242 AT91_SAMA5D2_DIFF_CHAN_CNT) * 2) 243 244 /* This total must also include the timestamp */ 245 #define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8) 246 247 #define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2) 248 249 #define AT91_HWFIFO_MAX_SIZE_STR "128" 250 #define AT91_HWFIFO_MAX_SIZE 128 251 252 /* Possible values for oversampling ratio */ 253 #define AT91_OSR_1SAMPLES 1 254 #define AT91_OSR_4SAMPLES 4 255 #define AT91_OSR_16SAMPLES 16 256 257 #define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \ 258 { \ 259 .type = IIO_VOLTAGE, \ 260 .channel = num, \ 261 .address = addr, \ 262 .scan_index = num, \ 263 .scan_type = { \ 264 .sign = 'u', \ 265 .realbits = 14, \ 266 .storagebits = 16, \ 267 }, \ 268 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 269 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 270 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 271 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 272 .datasheet_name = "CH"#num, \ 273 .indexed = 1, \ 274 } 275 276 #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \ 277 { \ 278 .type = IIO_VOLTAGE, \ 279 .differential = 1, \ 280 .channel = num, \ 281 .channel2 = num2, \ 282 .address = addr, \ 283 .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \ 284 .scan_type = { \ 285 .sign = 's', \ 286 .realbits = 14, \ 287 .storagebits = 16, \ 288 }, \ 289 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 290 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 291 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 292 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 293 .datasheet_name = "CH"#num"-CH"#num2, \ 294 .indexed = 1, \ 295 } 296 297 #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \ 298 { \ 299 .type = IIO_POSITIONRELATIVE, \ 300 .modified = 1, \ 301 .channel = num, \ 302 .channel2 = mod, \ 303 .scan_index = num, \ 304 .scan_type = { \ 305 .sign = 'u', \ 306 .realbits = 12, \ 307 .storagebits = 16, \ 308 }, \ 309 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 310 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 311 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 312 .datasheet_name = name, \ 313 } 314 #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \ 315 { \ 316 .type = IIO_PRESSURE, \ 317 .channel = num, \ 318 .scan_index = num, \ 319 .scan_type = { \ 320 .sign = 'u', \ 321 .realbits = 12, \ 322 .storagebits = 16, \ 323 }, \ 324 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 325 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 326 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 327 .datasheet_name = name, \ 328 } 329 330 #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg) 331 #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg) 332 333 struct at91_adc_soc_info { 334 unsigned startup_time; 335 unsigned min_sample_rate; 336 unsigned max_sample_rate; 337 }; 338 339 struct at91_adc_trigger { 340 char *name; 341 unsigned int trgmod_value; 342 unsigned int edge_type; 343 bool hw_trig; 344 }; 345 346 /** 347 * at91_adc_dma - at91-sama5d2 dma information struct 348 * @dma_chan: the dma channel acquired 349 * @rx_buf: dma coherent allocated area 350 * @rx_dma_buf: dma handler for the buffer 351 * @phys_addr: physical address of the ADC base register 352 * @buf_idx: index inside the dma buffer where reading was last done 353 * @rx_buf_sz: size of buffer used by DMA operation 354 * @watermark: number of conversions to copy before DMA triggers irq 355 * @dma_ts: hold the start timestamp of dma operation 356 */ 357 struct at91_adc_dma { 358 struct dma_chan *dma_chan; 359 u8 *rx_buf; 360 dma_addr_t rx_dma_buf; 361 phys_addr_t phys_addr; 362 int buf_idx; 363 int rx_buf_sz; 364 int watermark; 365 s64 dma_ts; 366 }; 367 368 /** 369 * at91_adc_touch - at91-sama5d2 touchscreen information struct 370 * @sample_period_val: the value for periodic trigger interval 371 * @touching: is the pen touching the screen or not 372 * @x_pos: temporary placeholder for pressure computation 373 * @channels_bitmask: bitmask with the touchscreen channels enabled 374 * @workq: workqueue for buffer data pushing 375 */ 376 struct at91_adc_touch { 377 u16 sample_period_val; 378 bool touching; 379 u16 x_pos; 380 unsigned long channels_bitmask; 381 struct work_struct workq; 382 }; 383 384 struct at91_adc_state { 385 void __iomem *base; 386 int irq; 387 struct clk *per_clk; 388 struct regulator *reg; 389 struct regulator *vref; 390 int vref_uv; 391 unsigned int current_sample_rate; 392 struct iio_trigger *trig; 393 const struct at91_adc_trigger *selected_trig; 394 const struct iio_chan_spec *chan; 395 bool conversion_done; 396 u32 conversion_value; 397 unsigned int oversampling_ratio; 398 struct at91_adc_soc_info soc_info; 399 wait_queue_head_t wq_data_available; 400 struct at91_adc_dma dma_st; 401 struct at91_adc_touch touch_st; 402 u16 buffer[AT91_BUFFER_MAX_HWORDS]; 403 /* 404 * lock to prevent concurrent 'single conversion' requests through 405 * sysfs. 406 */ 407 struct mutex lock; 408 }; 409 410 static const struct at91_adc_trigger at91_adc_trigger_list[] = { 411 { 412 .name = "external_rising", 413 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE, 414 .edge_type = IRQ_TYPE_EDGE_RISING, 415 .hw_trig = true, 416 }, 417 { 418 .name = "external_falling", 419 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL, 420 .edge_type = IRQ_TYPE_EDGE_FALLING, 421 .hw_trig = true, 422 }, 423 { 424 .name = "external_any", 425 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY, 426 .edge_type = IRQ_TYPE_EDGE_BOTH, 427 .hw_trig = true, 428 }, 429 { 430 .name = "software", 431 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER, 432 .edge_type = IRQ_TYPE_NONE, 433 .hw_trig = false, 434 }, 435 }; 436 437 static const struct iio_chan_spec at91_adc_channels[] = { 438 AT91_SAMA5D2_CHAN_SINGLE(0, 0x50), 439 AT91_SAMA5D2_CHAN_SINGLE(1, 0x54), 440 AT91_SAMA5D2_CHAN_SINGLE(2, 0x58), 441 AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c), 442 AT91_SAMA5D2_CHAN_SINGLE(4, 0x60), 443 AT91_SAMA5D2_CHAN_SINGLE(5, 0x64), 444 AT91_SAMA5D2_CHAN_SINGLE(6, 0x68), 445 AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c), 446 AT91_SAMA5D2_CHAN_SINGLE(8, 0x70), 447 AT91_SAMA5D2_CHAN_SINGLE(9, 0x74), 448 AT91_SAMA5D2_CHAN_SINGLE(10, 0x78), 449 AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c), 450 AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50), 451 AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58), 452 AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60), 453 AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68), 454 AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70), 455 AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78), 456 IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_TIMESTAMP_CHAN_IDX), 457 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_X_CHAN_IDX, "x", IIO_MOD_X), 458 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, "y", IIO_MOD_Y), 459 AT91_SAMA5D2_CHAN_PRESSURE(AT91_SAMA5D2_TOUCH_P_CHAN_IDX, "pressure"), 460 }; 461 462 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) 463 { 464 int i; 465 466 for (i = 0; i < indio_dev->num_channels; i++) { 467 if (indio_dev->channels[i].scan_index == chan) 468 return i; 469 } 470 return -EINVAL; 471 } 472 473 static inline struct iio_chan_spec const * 474 at91_adc_chan_get(struct iio_dev *indio_dev, int chan) 475 { 476 int index = at91_adc_chan_xlate(indio_dev, chan); 477 478 if (index < 0) 479 return NULL; 480 return indio_dev->channels + index; 481 } 482 483 static inline int at91_adc_of_xlate(struct iio_dev *indio_dev, 484 const struct of_phandle_args *iiospec) 485 { 486 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]); 487 } 488 489 static void at91_adc_config_emr(struct at91_adc_state *st) 490 { 491 /* configure the extended mode register */ 492 unsigned int emr = at91_adc_readl(st, AT91_SAMA5D2_EMR); 493 494 /* select oversampling per single trigger event */ 495 emr |= AT91_SAMA5D2_EMR_ASTE(1); 496 497 /* delete leftover content if it's the case */ 498 emr &= ~AT91_SAMA5D2_EMR_OSR_MASK; 499 500 /* select oversampling ratio from configuration */ 501 switch (st->oversampling_ratio) { 502 case AT91_OSR_1SAMPLES: 503 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) & 504 AT91_SAMA5D2_EMR_OSR_MASK; 505 break; 506 case AT91_OSR_4SAMPLES: 507 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) & 508 AT91_SAMA5D2_EMR_OSR_MASK; 509 break; 510 case AT91_OSR_16SAMPLES: 511 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) & 512 AT91_SAMA5D2_EMR_OSR_MASK; 513 break; 514 } 515 516 at91_adc_writel(st, AT91_SAMA5D2_EMR, emr); 517 } 518 519 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) 520 { 521 if (st->oversampling_ratio == AT91_OSR_1SAMPLES) { 522 /* 523 * in this case we only have 12 bits of real data, but channel 524 * is registered as 14 bits, so shift left two bits 525 */ 526 *val <<= 2; 527 } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) { 528 /* 529 * in this case we have 13 bits of real data, but channel 530 * is registered as 14 bits, so left shift one bit 531 */ 532 *val <<= 1; 533 } 534 535 return IIO_VAL_INT; 536 } 537 538 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf, 539 int len) 540 { 541 int i = 0, val; 542 u16 *buf_u16 = (u16 *) buf; 543 544 /* 545 * We are converting each two bytes (each sample). 546 * First convert the byte based array to u16, and convert each sample 547 * separately. 548 * Each value is two bytes in an array of chars, so to not shift 549 * more than we need, save the value separately. 550 * len is in bytes, so divide by two to get number of samples. 551 */ 552 while (i < len / 2) { 553 val = buf_u16[i]; 554 at91_adc_adjust_val_osr(st, &val); 555 buf_u16[i] = val; 556 i++; 557 } 558 } 559 560 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state) 561 { 562 u32 clk_khz = st->current_sample_rate / 1000; 563 int i = 0; 564 u16 pendbc; 565 u32 tsmr, acr; 566 567 if (!state) { 568 /* disabling touch IRQs and setting mode to no touch enabled */ 569 at91_adc_writel(st, AT91_SAMA5D2_IDR, 570 AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN); 571 at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0); 572 return 0; 573 } 574 /* 575 * debounce time is in microseconds, we need it in milliseconds to 576 * multiply with kilohertz, so, divide by 1000, but after the multiply. 577 * round up to make sure pendbc is at least 1 578 */ 579 pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US * 580 clk_khz / 1000, 1); 581 582 /* get the required exponent */ 583 while (pendbc >> i++) 584 ; 585 586 pendbc = i; 587 588 tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS; 589 590 tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK; 591 tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) & 592 AT91_SAMA5D2_TSMR_PENDBC_MASK; 593 tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA; 594 tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA; 595 tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK; 596 597 at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr); 598 599 acr = at91_adc_readl(st, AT91_SAMA5D2_ACR); 600 acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK; 601 acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK; 602 at91_adc_writel(st, AT91_SAMA5D2_ACR, acr); 603 604 /* Sample Period Time = (TRGPER + 1) / ADCClock */ 605 st->touch_st.sample_period_val = 606 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US * 607 clk_khz / 1000) - 1, 1); 608 /* enable pen detect IRQ */ 609 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN); 610 611 return 0; 612 } 613 614 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg) 615 { 616 u32 val; 617 u32 scale, result, pos; 618 619 /* 620 * to obtain the actual position we must divide by scale 621 * and multiply with max, where 622 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1 623 */ 624 /* first half of register is the x or y, second half is the scale */ 625 val = at91_adc_readl(st, reg); 626 if (!val) 627 dev_dbg(&iio_priv_to_dev(st)->dev, "pos is 0\n"); 628 629 pos = val & AT91_SAMA5D2_XYZ_MASK; 630 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos; 631 scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; 632 if (scale == 0) { 633 dev_err(&iio_priv_to_dev(st)->dev, "scale is 0\n"); 634 return 0; 635 } 636 result /= scale; 637 638 return result; 639 } 640 641 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st) 642 { 643 st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR); 644 return st->touch_st.x_pos; 645 } 646 647 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st) 648 { 649 return at91_adc_touch_pos(st, AT91_SAMA5D2_YPOSR); 650 } 651 652 static u16 at91_adc_touch_pressure(struct at91_adc_state *st) 653 { 654 u32 val; 655 u32 z1, z2; 656 u32 pres; 657 u32 rxp = 1; 658 u32 factor = 1000; 659 660 /* calculate the pressure */ 661 val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); 662 z1 = val & AT91_SAMA5D2_XYZ_MASK; 663 z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; 664 665 if (z1 != 0) 666 pres = rxp * (st->touch_st.x_pos * factor / 1024) * 667 (z2 * factor / z1 - factor) / 668 factor; 669 else 670 pres = 0xFFFF; /* no pen contact */ 671 672 /* 673 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0. 674 * We compute it this way, but let's return it in the expected way, 675 * growing from 0 to 0xFFFF. 676 */ 677 return 0xFFFF - pres; 678 } 679 680 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val) 681 { 682 *val = 0; 683 if (!st->touch_st.touching) 684 return -ENODATA; 685 if (chan == AT91_SAMA5D2_TOUCH_X_CHAN_IDX) 686 *val = at91_adc_touch_x_pos(st); 687 else if (chan == AT91_SAMA5D2_TOUCH_Y_CHAN_IDX) 688 *val = at91_adc_touch_y_pos(st); 689 else 690 return -ENODATA; 691 692 return IIO_VAL_INT; 693 } 694 695 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val) 696 { 697 *val = 0; 698 if (!st->touch_st.touching) 699 return -ENODATA; 700 if (chan == AT91_SAMA5D2_TOUCH_P_CHAN_IDX) 701 *val = at91_adc_touch_pressure(st); 702 else 703 return -ENODATA; 704 705 return IIO_VAL_INT; 706 } 707 708 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) 709 { 710 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 711 struct at91_adc_state *st = iio_priv(indio); 712 u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR); 713 u8 bit; 714 715 /* clear TRGMOD */ 716 status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK; 717 718 if (state) 719 status |= st->selected_trig->trgmod_value; 720 721 /* set/unset hw trigger */ 722 at91_adc_writel(st, AT91_SAMA5D2_TRGR, status); 723 724 for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) { 725 struct iio_chan_spec const *chan = at91_adc_chan_get(indio, bit); 726 u32 cor; 727 728 if (!chan) 729 continue; 730 /* these channel types cannot be handled by this trigger */ 731 if (chan->type == IIO_POSITIONRELATIVE || 732 chan->type == IIO_PRESSURE) 733 continue; 734 735 if (state) { 736 cor = at91_adc_readl(st, AT91_SAMA5D2_COR); 737 738 if (chan->differential) 739 cor |= (BIT(chan->channel) | 740 BIT(chan->channel2)) << 741 AT91_SAMA5D2_COR_DIFF_OFFSET; 742 else 743 cor &= ~(BIT(chan->channel) << 744 AT91_SAMA5D2_COR_DIFF_OFFSET); 745 746 at91_adc_writel(st, AT91_SAMA5D2_COR, cor); 747 } 748 749 if (state) { 750 at91_adc_writel(st, AT91_SAMA5D2_CHER, 751 BIT(chan->channel)); 752 /* enable irq only if not using DMA */ 753 if (!st->dma_st.dma_chan) { 754 at91_adc_writel(st, AT91_SAMA5D2_IER, 755 BIT(chan->channel)); 756 } 757 } else { 758 /* disable irq only if not using DMA */ 759 if (!st->dma_st.dma_chan) { 760 at91_adc_writel(st, AT91_SAMA5D2_IDR, 761 BIT(chan->channel)); 762 } 763 at91_adc_writel(st, AT91_SAMA5D2_CHDR, 764 BIT(chan->channel)); 765 } 766 } 767 768 return 0; 769 } 770 771 static int at91_adc_reenable_trigger(struct iio_trigger *trig) 772 { 773 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 774 struct at91_adc_state *st = iio_priv(indio); 775 776 /* if we are using DMA, we must not reenable irq after each trigger */ 777 if (st->dma_st.dma_chan) 778 return 0; 779 780 enable_irq(st->irq); 781 782 /* Needed to ACK the DRDY interruption */ 783 at91_adc_readl(st, AT91_SAMA5D2_LCDR); 784 return 0; 785 } 786 787 static const struct iio_trigger_ops at91_adc_trigger_ops = { 788 .set_trigger_state = &at91_adc_configure_trigger, 789 .try_reenable = &at91_adc_reenable_trigger, 790 .validate_device = iio_trigger_validate_own_device, 791 }; 792 793 static int at91_adc_dma_size_done(struct at91_adc_state *st) 794 { 795 struct dma_tx_state state; 796 enum dma_status status; 797 int i, size; 798 799 status = dmaengine_tx_status(st->dma_st.dma_chan, 800 st->dma_st.dma_chan->cookie, 801 &state); 802 if (status != DMA_IN_PROGRESS) 803 return 0; 804 805 /* Transferred length is size in bytes from end of buffer */ 806 i = st->dma_st.rx_buf_sz - state.residue; 807 808 /* Return available bytes */ 809 if (i >= st->dma_st.buf_idx) 810 size = i - st->dma_st.buf_idx; 811 else 812 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx; 813 return size; 814 } 815 816 static void at91_dma_buffer_done(void *data) 817 { 818 struct iio_dev *indio_dev = data; 819 820 iio_trigger_poll_chained(indio_dev->trig); 821 } 822 823 static int at91_adc_dma_start(struct iio_dev *indio_dev) 824 { 825 struct at91_adc_state *st = iio_priv(indio_dev); 826 struct dma_async_tx_descriptor *desc; 827 dma_cookie_t cookie; 828 int ret; 829 u8 bit; 830 831 if (!st->dma_st.dma_chan) 832 return 0; 833 834 /* we start a new DMA, so set buffer index to start */ 835 st->dma_st.buf_idx = 0; 836 837 /* 838 * compute buffer size w.r.t. watermark and enabled channels. 839 * scan_bytes is aligned so we need an exact size for DMA 840 */ 841 st->dma_st.rx_buf_sz = 0; 842 843 for_each_set_bit(bit, indio_dev->active_scan_mask, 844 indio_dev->num_channels) { 845 struct iio_chan_spec const *chan = 846 at91_adc_chan_get(indio_dev, bit); 847 848 if (!chan) 849 continue; 850 851 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8; 852 } 853 st->dma_st.rx_buf_sz *= st->dma_st.watermark; 854 855 /* Prepare a DMA cyclic transaction */ 856 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan, 857 st->dma_st.rx_dma_buf, 858 st->dma_st.rx_buf_sz, 859 st->dma_st.rx_buf_sz / 2, 860 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 861 862 if (!desc) { 863 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n"); 864 return -EBUSY; 865 } 866 867 desc->callback = at91_dma_buffer_done; 868 desc->callback_param = indio_dev; 869 870 cookie = dmaengine_submit(desc); 871 ret = dma_submit_error(cookie); 872 if (ret) { 873 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n"); 874 dmaengine_terminate_async(st->dma_st.dma_chan); 875 return ret; 876 } 877 878 /* enable general overrun error signaling */ 879 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE); 880 /* Issue pending DMA requests */ 881 dma_async_issue_pending(st->dma_st.dma_chan); 882 883 /* consider current time as DMA start time for timestamps */ 884 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); 885 886 dev_dbg(&indio_dev->dev, "DMA cyclic started\n"); 887 888 return 0; 889 } 890 891 static int at91_adc_buffer_postenable(struct iio_dev *indio_dev) 892 { 893 int ret; 894 struct at91_adc_state *st = iio_priv(indio_dev); 895 896 /* check if we are enabling triggered buffer or the touchscreen */ 897 if (bitmap_subset(indio_dev->active_scan_mask, 898 &st->touch_st.channels_bitmask, 899 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) { 900 /* touchscreen enabling */ 901 return at91_adc_configure_touch(st, true); 902 } 903 /* if we are not in triggered mode, we cannot enable the buffer. */ 904 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES)) 905 return -EINVAL; 906 907 /* we continue with the triggered buffer */ 908 ret = at91_adc_dma_start(indio_dev); 909 if (ret) { 910 dev_err(&indio_dev->dev, "buffer postenable failed\n"); 911 return ret; 912 } 913 914 return iio_triggered_buffer_postenable(indio_dev); 915 } 916 917 static int at91_adc_buffer_predisable(struct iio_dev *indio_dev) 918 { 919 struct at91_adc_state *st = iio_priv(indio_dev); 920 int ret; 921 u8 bit; 922 923 /* check if we are disabling triggered buffer or the touchscreen */ 924 if (bitmap_subset(indio_dev->active_scan_mask, 925 &st->touch_st.channels_bitmask, 926 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) { 927 /* touchscreen disable */ 928 return at91_adc_configure_touch(st, false); 929 } 930 /* if we are not in triggered mode, nothing to do here */ 931 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES)) 932 return -EINVAL; 933 934 /* continue with the triggered buffer */ 935 ret = iio_triggered_buffer_predisable(indio_dev); 936 if (ret < 0) 937 dev_err(&indio_dev->dev, "buffer predisable failed\n"); 938 939 if (!st->dma_st.dma_chan) 940 return ret; 941 942 /* if we are using DMA we must clear registers and end DMA */ 943 dmaengine_terminate_sync(st->dma_st.dma_chan); 944 945 /* 946 * For each enabled channel we must read the last converted value 947 * to clear EOC status and not get a possible interrupt later. 948 * This value is being read by DMA from LCDR anyway 949 */ 950 for_each_set_bit(bit, indio_dev->active_scan_mask, 951 indio_dev->num_channels) { 952 struct iio_chan_spec const *chan = 953 at91_adc_chan_get(indio_dev, bit); 954 955 if (!chan) 956 continue; 957 /* these channel types are virtual, no need to do anything */ 958 if (chan->type == IIO_POSITIONRELATIVE || 959 chan->type == IIO_PRESSURE) 960 continue; 961 if (st->dma_st.dma_chan) 962 at91_adc_readl(st, chan->address); 963 } 964 965 /* read overflow register to clear possible overflow status */ 966 at91_adc_readl(st, AT91_SAMA5D2_OVER); 967 return ret; 968 } 969 970 static const struct iio_buffer_setup_ops at91_buffer_setup_ops = { 971 .postenable = &at91_adc_buffer_postenable, 972 .predisable = &at91_adc_buffer_predisable, 973 }; 974 975 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio, 976 char *trigger_name) 977 { 978 struct iio_trigger *trig; 979 int ret; 980 981 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name, 982 indio->id, trigger_name); 983 if (!trig) 984 return NULL; 985 986 trig->dev.parent = indio->dev.parent; 987 iio_trigger_set_drvdata(trig, indio); 988 trig->ops = &at91_adc_trigger_ops; 989 990 ret = devm_iio_trigger_register(&indio->dev, trig); 991 if (ret) 992 return ERR_PTR(ret); 993 994 return trig; 995 } 996 997 static int at91_adc_trigger_init(struct iio_dev *indio) 998 { 999 struct at91_adc_state *st = iio_priv(indio); 1000 1001 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name); 1002 if (IS_ERR(st->trig)) { 1003 dev_err(&indio->dev, 1004 "could not allocate trigger\n"); 1005 return PTR_ERR(st->trig); 1006 } 1007 1008 return 0; 1009 } 1010 1011 static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, 1012 struct iio_poll_func *pf) 1013 { 1014 struct at91_adc_state *st = iio_priv(indio_dev); 1015 int i = 0; 1016 int val; 1017 u8 bit; 1018 1019 for_each_set_bit(bit, indio_dev->active_scan_mask, 1020 indio_dev->num_channels) { 1021 struct iio_chan_spec const *chan = 1022 at91_adc_chan_get(indio_dev, bit); 1023 1024 if (!chan) 1025 continue; 1026 /* 1027 * Our external trigger only supports the voltage channels. 1028 * In case someone requested a different type of channel 1029 * just put zeroes to buffer. 1030 * This should not happen because we check the scan mode 1031 * and scan mask when we enable the buffer, and we don't allow 1032 * the buffer to start with a mixed mask (voltage and something 1033 * else). 1034 * Thus, emit a warning. 1035 */ 1036 if (chan->type == IIO_VOLTAGE) { 1037 val = at91_adc_readl(st, chan->address); 1038 at91_adc_adjust_val_osr(st, &val); 1039 st->buffer[i] = val; 1040 } else { 1041 st->buffer[i] = 0; 1042 WARN(true, "This trigger cannot handle this type of channel"); 1043 } 1044 i++; 1045 } 1046 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer, 1047 pf->timestamp); 1048 } 1049 1050 static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev) 1051 { 1052 struct at91_adc_state *st = iio_priv(indio_dev); 1053 int transferred_len = at91_adc_dma_size_done(st); 1054 s64 ns = iio_get_time_ns(indio_dev); 1055 s64 interval; 1056 int sample_index = 0, sample_count, sample_size; 1057 1058 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR); 1059 /* if we reached this point, we cannot sample faster */ 1060 if (status & AT91_SAMA5D2_IER_GOVRE) 1061 pr_info_ratelimited("%s: conversion overrun detected\n", 1062 indio_dev->name); 1063 1064 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark); 1065 1066 sample_count = div_s64(transferred_len, sample_size); 1067 1068 /* 1069 * interval between samples is total time since last transfer handling 1070 * divided by the number of samples (total size divided by sample size) 1071 */ 1072 interval = div_s64((ns - st->dma_st.dma_ts), sample_count); 1073 1074 while (transferred_len >= sample_size) { 1075 /* 1076 * for all the values in the current sample, 1077 * adjust the values inside the buffer for oversampling 1078 */ 1079 at91_adc_adjust_val_osr_array(st, 1080 &st->dma_st.rx_buf[st->dma_st.buf_idx], 1081 sample_size); 1082 1083 iio_push_to_buffers_with_timestamp(indio_dev, 1084 (st->dma_st.rx_buf + st->dma_st.buf_idx), 1085 (st->dma_st.dma_ts + interval * sample_index)); 1086 /* adjust remaining length */ 1087 transferred_len -= sample_size; 1088 /* adjust buffer index */ 1089 st->dma_st.buf_idx += sample_size; 1090 /* in case of reaching end of buffer, reset index */ 1091 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz) 1092 st->dma_st.buf_idx = 0; 1093 sample_index++; 1094 } 1095 /* adjust saved time for next transfer handling */ 1096 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); 1097 } 1098 1099 static irqreturn_t at91_adc_trigger_handler(int irq, void *p) 1100 { 1101 struct iio_poll_func *pf = p; 1102 struct iio_dev *indio_dev = pf->indio_dev; 1103 struct at91_adc_state *st = iio_priv(indio_dev); 1104 1105 if (st->dma_st.dma_chan) 1106 at91_adc_trigger_handler_dma(indio_dev); 1107 else 1108 at91_adc_trigger_handler_nodma(indio_dev, pf); 1109 1110 iio_trigger_notify_done(indio_dev->trig); 1111 1112 return IRQ_HANDLED; 1113 } 1114 1115 static int at91_adc_buffer_init(struct iio_dev *indio) 1116 { 1117 struct at91_adc_state *st = iio_priv(indio); 1118 1119 if (st->selected_trig->hw_trig) { 1120 return devm_iio_triggered_buffer_setup(&indio->dev, indio, 1121 &iio_pollfunc_store_time, 1122 &at91_adc_trigger_handler, &at91_buffer_setup_ops); 1123 } 1124 /* 1125 * we need to prepare the buffer ops in case we will get 1126 * another buffer attached (like a callback buffer for the touchscreen) 1127 */ 1128 indio->setup_ops = &at91_buffer_setup_ops; 1129 1130 return 0; 1131 } 1132 1133 static unsigned at91_adc_startup_time(unsigned startup_time_min, 1134 unsigned adc_clk_khz) 1135 { 1136 static const unsigned int startup_lookup[] = { 1137 0, 8, 16, 24, 1138 64, 80, 96, 112, 1139 512, 576, 640, 704, 1140 768, 832, 896, 960 1141 }; 1142 unsigned ticks_min, i; 1143 1144 /* 1145 * Since the adc frequency is checked before, there is no reason 1146 * to not meet the startup time constraint. 1147 */ 1148 1149 ticks_min = startup_time_min * adc_clk_khz / 1000; 1150 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++) 1151 if (startup_lookup[i] > ticks_min) 1152 break; 1153 1154 return i; 1155 } 1156 1157 static void at91_adc_setup_samp_freq(struct at91_adc_state *st, unsigned freq) 1158 { 1159 struct iio_dev *indio_dev = iio_priv_to_dev(st); 1160 unsigned f_per, prescal, startup, mr; 1161 1162 f_per = clk_get_rate(st->per_clk); 1163 prescal = (f_per / (2 * freq)) - 1; 1164 1165 startup = at91_adc_startup_time(st->soc_info.startup_time, 1166 freq / 1000); 1167 1168 mr = at91_adc_readl(st, AT91_SAMA5D2_MR); 1169 mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK); 1170 mr |= AT91_SAMA5D2_MR_STARTUP(startup); 1171 mr |= AT91_SAMA5D2_MR_PRESCAL(prescal); 1172 at91_adc_writel(st, AT91_SAMA5D2_MR, mr); 1173 1174 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n", 1175 freq, startup, prescal); 1176 st->current_sample_rate = freq; 1177 } 1178 1179 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st) 1180 { 1181 return st->current_sample_rate; 1182 } 1183 1184 static void at91_adc_touch_data_handler(struct iio_dev *indio_dev) 1185 { 1186 struct at91_adc_state *st = iio_priv(indio_dev); 1187 u8 bit; 1188 u16 val; 1189 int i = 0; 1190 1191 for_each_set_bit(bit, indio_dev->active_scan_mask, 1192 AT91_SAMA5D2_MAX_CHAN_IDX + 1) { 1193 struct iio_chan_spec const *chan = 1194 at91_adc_chan_get(indio_dev, bit); 1195 1196 if (chan->type == IIO_POSITIONRELATIVE) 1197 at91_adc_read_position(st, chan->channel, &val); 1198 else if (chan->type == IIO_PRESSURE) 1199 at91_adc_read_pressure(st, chan->channel, &val); 1200 else 1201 continue; 1202 st->buffer[i] = val; 1203 i++; 1204 } 1205 /* 1206 * Schedule work to push to buffers. 1207 * This is intended to push to the callback buffer that another driver 1208 * registered. We are still in a handler from our IRQ. If we push 1209 * directly, it means the other driver has it's callback called 1210 * from our IRQ context. Which is something we better avoid. 1211 * Let's schedule it after our IRQ is completed. 1212 */ 1213 schedule_work(&st->touch_st.workq); 1214 } 1215 1216 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st) 1217 { 1218 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN); 1219 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN | 1220 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1221 AT91_SAMA5D2_IER_PRDY); 1222 at91_adc_writel(st, AT91_SAMA5D2_TRGR, 1223 AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC | 1224 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val)); 1225 st->touch_st.touching = true; 1226 } 1227 1228 static void at91_adc_no_pen_detect_interrupt(struct at91_adc_state *st) 1229 { 1230 struct iio_dev *indio_dev = iio_priv_to_dev(st); 1231 1232 at91_adc_writel(st, AT91_SAMA5D2_TRGR, 1233 AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER); 1234 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN | 1235 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1236 AT91_SAMA5D2_IER_PRDY); 1237 st->touch_st.touching = false; 1238 1239 at91_adc_touch_data_handler(indio_dev); 1240 1241 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN); 1242 } 1243 1244 static void at91_adc_workq_handler(struct work_struct *workq) 1245 { 1246 struct at91_adc_touch *touch_st = container_of(workq, 1247 struct at91_adc_touch, workq); 1248 struct at91_adc_state *st = container_of(touch_st, 1249 struct at91_adc_state, touch_st); 1250 struct iio_dev *indio_dev = iio_priv_to_dev(st); 1251 1252 iio_push_to_buffers(indio_dev, st->buffer); 1253 } 1254 1255 static irqreturn_t at91_adc_interrupt(int irq, void *private) 1256 { 1257 struct iio_dev *indio = private; 1258 struct at91_adc_state *st = iio_priv(indio); 1259 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR); 1260 u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR); 1261 u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1262 AT91_SAMA5D2_IER_PRDY; 1263 1264 if (!(status & imr)) 1265 return IRQ_NONE; 1266 if (status & AT91_SAMA5D2_IER_PEN) { 1267 /* pen detected IRQ */ 1268 at91_adc_pen_detect_interrupt(st); 1269 } else if ((status & AT91_SAMA5D2_IER_NOPEN)) { 1270 /* nopen detected IRQ */ 1271 at91_adc_no_pen_detect_interrupt(st); 1272 } else if ((status & AT91_SAMA5D2_ISR_PENS) && 1273 ((status & rdy_mask) == rdy_mask)) { 1274 /* periodic trigger IRQ - during pen sense */ 1275 at91_adc_touch_data_handler(indio); 1276 } else if (status & AT91_SAMA5D2_ISR_PENS) { 1277 /* 1278 * touching, but the measurements are not ready yet. 1279 * read and ignore. 1280 */ 1281 status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR); 1282 status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR); 1283 status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); 1284 } else if (iio_buffer_enabled(indio) && !st->dma_st.dma_chan) { 1285 /* triggered buffer without DMA */ 1286 disable_irq_nosync(irq); 1287 iio_trigger_poll(indio->trig); 1288 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) { 1289 /* triggered buffer with DMA - should not happen */ 1290 disable_irq_nosync(irq); 1291 WARN(true, "Unexpected irq occurred\n"); 1292 } else if (!iio_buffer_enabled(indio)) { 1293 /* software requested conversion */ 1294 st->conversion_value = at91_adc_readl(st, st->chan->address); 1295 st->conversion_done = true; 1296 wake_up_interruptible(&st->wq_data_available); 1297 } 1298 return IRQ_HANDLED; 1299 } 1300 1301 static int at91_adc_read_info_raw(struct iio_dev *indio_dev, 1302 struct iio_chan_spec const *chan, int *val) 1303 { 1304 struct at91_adc_state *st = iio_priv(indio_dev); 1305 u32 cor = 0; 1306 u16 tmp_val; 1307 int ret; 1308 1309 /* 1310 * Keep in mind that we cannot use software trigger or touchscreen 1311 * if external trigger is enabled 1312 */ 1313 if (chan->type == IIO_POSITIONRELATIVE) { 1314 ret = iio_device_claim_direct_mode(indio_dev); 1315 if (ret) 1316 return ret; 1317 mutex_lock(&st->lock); 1318 1319 ret = at91_adc_read_position(st, chan->channel, 1320 &tmp_val); 1321 *val = tmp_val; 1322 mutex_unlock(&st->lock); 1323 iio_device_release_direct_mode(indio_dev); 1324 1325 return at91_adc_adjust_val_osr(st, val); 1326 } 1327 if (chan->type == IIO_PRESSURE) { 1328 ret = iio_device_claim_direct_mode(indio_dev); 1329 if (ret) 1330 return ret; 1331 mutex_lock(&st->lock); 1332 1333 ret = at91_adc_read_pressure(st, chan->channel, 1334 &tmp_val); 1335 *val = tmp_val; 1336 mutex_unlock(&st->lock); 1337 iio_device_release_direct_mode(indio_dev); 1338 1339 return at91_adc_adjust_val_osr(st, val); 1340 } 1341 1342 /* in this case we have a voltage channel */ 1343 1344 ret = iio_device_claim_direct_mode(indio_dev); 1345 if (ret) 1346 return ret; 1347 mutex_lock(&st->lock); 1348 1349 st->chan = chan; 1350 1351 if (chan->differential) 1352 cor = (BIT(chan->channel) | BIT(chan->channel2)) << 1353 AT91_SAMA5D2_COR_DIFF_OFFSET; 1354 1355 at91_adc_writel(st, AT91_SAMA5D2_COR, cor); 1356 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); 1357 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel)); 1358 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START); 1359 1360 ret = wait_event_interruptible_timeout(st->wq_data_available, 1361 st->conversion_done, 1362 msecs_to_jiffies(1000)); 1363 if (ret == 0) 1364 ret = -ETIMEDOUT; 1365 1366 if (ret > 0) { 1367 *val = st->conversion_value; 1368 ret = at91_adc_adjust_val_osr(st, val); 1369 if (chan->scan_type.sign == 's') 1370 *val = sign_extend32(*val, 11); 1371 st->conversion_done = false; 1372 } 1373 1374 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel)); 1375 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); 1376 1377 /* Needed to ACK the DRDY interruption */ 1378 at91_adc_readl(st, AT91_SAMA5D2_LCDR); 1379 1380 mutex_unlock(&st->lock); 1381 1382 iio_device_release_direct_mode(indio_dev); 1383 return ret; 1384 } 1385 1386 static int at91_adc_read_raw(struct iio_dev *indio_dev, 1387 struct iio_chan_spec const *chan, 1388 int *val, int *val2, long mask) 1389 { 1390 struct at91_adc_state *st = iio_priv(indio_dev); 1391 1392 switch (mask) { 1393 case IIO_CHAN_INFO_RAW: 1394 return at91_adc_read_info_raw(indio_dev, chan, val); 1395 case IIO_CHAN_INFO_SCALE: 1396 *val = st->vref_uv / 1000; 1397 if (chan->differential) 1398 *val *= 2; 1399 *val2 = chan->scan_type.realbits; 1400 return IIO_VAL_FRACTIONAL_LOG2; 1401 1402 case IIO_CHAN_INFO_SAMP_FREQ: 1403 *val = at91_adc_get_sample_freq(st); 1404 return IIO_VAL_INT; 1405 1406 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1407 *val = st->oversampling_ratio; 1408 return IIO_VAL_INT; 1409 1410 default: 1411 return -EINVAL; 1412 } 1413 } 1414 1415 static int at91_adc_write_raw(struct iio_dev *indio_dev, 1416 struct iio_chan_spec const *chan, 1417 int val, int val2, long mask) 1418 { 1419 struct at91_adc_state *st = iio_priv(indio_dev); 1420 1421 switch (mask) { 1422 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1423 if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) && 1424 (val != AT91_OSR_16SAMPLES)) 1425 return -EINVAL; 1426 /* if no change, optimize out */ 1427 if (val == st->oversampling_ratio) 1428 return 0; 1429 st->oversampling_ratio = val; 1430 /* update ratio */ 1431 at91_adc_config_emr(st); 1432 return 0; 1433 case IIO_CHAN_INFO_SAMP_FREQ: 1434 if (val < st->soc_info.min_sample_rate || 1435 val > st->soc_info.max_sample_rate) 1436 return -EINVAL; 1437 1438 at91_adc_setup_samp_freq(st, val); 1439 return 0; 1440 default: 1441 return -EINVAL; 1442 }; 1443 } 1444 1445 static void at91_adc_dma_init(struct platform_device *pdev) 1446 { 1447 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1448 struct at91_adc_state *st = iio_priv(indio_dev); 1449 struct dma_slave_config config = {0}; 1450 /* 1451 * We make the buffer double the size of the fifo, 1452 * such that DMA uses one half of the buffer (full fifo size) 1453 * and the software uses the other half to read/write. 1454 */ 1455 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * 1456 AT91_BUFFER_MAX_CONVERSION_BYTES * 2, 1457 PAGE_SIZE); 1458 1459 if (st->dma_st.dma_chan) 1460 return; 1461 1462 st->dma_st.dma_chan = dma_request_chan(&pdev->dev, "rx"); 1463 if (IS_ERR(st->dma_st.dma_chan)) { 1464 dev_info(&pdev->dev, "can't get DMA channel\n"); 1465 st->dma_st.dma_chan = NULL; 1466 goto dma_exit; 1467 } 1468 1469 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev, 1470 pages * PAGE_SIZE, 1471 &st->dma_st.rx_dma_buf, 1472 GFP_KERNEL); 1473 if (!st->dma_st.rx_buf) { 1474 dev_info(&pdev->dev, "can't allocate coherent DMA area\n"); 1475 goto dma_chan_disable; 1476 } 1477 1478 /* Configure DMA channel to read data register */ 1479 config.direction = DMA_DEV_TO_MEM; 1480 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr 1481 + AT91_SAMA5D2_LCDR); 1482 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1483 config.src_maxburst = 1; 1484 config.dst_maxburst = 1; 1485 1486 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) { 1487 dev_info(&pdev->dev, "can't configure DMA slave\n"); 1488 goto dma_free_area; 1489 } 1490 1491 dev_info(&pdev->dev, "using %s for rx DMA transfers\n", 1492 dma_chan_name(st->dma_st.dma_chan)); 1493 1494 return; 1495 1496 dma_free_area: 1497 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, 1498 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); 1499 dma_chan_disable: 1500 dma_release_channel(st->dma_st.dma_chan); 1501 st->dma_st.dma_chan = NULL; 1502 dma_exit: 1503 dev_info(&pdev->dev, "continuing without DMA support\n"); 1504 } 1505 1506 static void at91_adc_dma_disable(struct platform_device *pdev) 1507 { 1508 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1509 struct at91_adc_state *st = iio_priv(indio_dev); 1510 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * 1511 AT91_BUFFER_MAX_CONVERSION_BYTES * 2, 1512 PAGE_SIZE); 1513 1514 /* if we are not using DMA, just return */ 1515 if (!st->dma_st.dma_chan) 1516 return; 1517 1518 /* wait for all transactions to be terminated first*/ 1519 dmaengine_terminate_sync(st->dma_st.dma_chan); 1520 1521 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, 1522 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); 1523 dma_release_channel(st->dma_st.dma_chan); 1524 st->dma_st.dma_chan = NULL; 1525 1526 dev_info(&pdev->dev, "continuing without DMA support\n"); 1527 } 1528 1529 static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1530 { 1531 struct at91_adc_state *st = iio_priv(indio_dev); 1532 1533 if (val > AT91_HWFIFO_MAX_SIZE) 1534 return -EINVAL; 1535 1536 if (!st->selected_trig->hw_trig) { 1537 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n"); 1538 return 0; 1539 } 1540 1541 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val); 1542 st->dma_st.watermark = val; 1543 1544 /* 1545 * The logic here is: if we have watermark 1, it means we do 1546 * each conversion with it's own IRQ, thus we don't need DMA. 1547 * If the watermark is higher, we do DMA to do all the transfers in bulk 1548 */ 1549 1550 if (val == 1) 1551 at91_adc_dma_disable(to_platform_device(&indio_dev->dev)); 1552 else if (val > 1) 1553 at91_adc_dma_init(to_platform_device(&indio_dev->dev)); 1554 1555 return 0; 1556 } 1557 1558 static int at91_adc_update_scan_mode(struct iio_dev *indio_dev, 1559 const unsigned long *scan_mask) 1560 { 1561 struct at91_adc_state *st = iio_priv(indio_dev); 1562 1563 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask, 1564 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) 1565 return 0; 1566 /* 1567 * if the new bitmap is a combination of touchscreen and regular 1568 * channels, then we are not fine 1569 */ 1570 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask, 1571 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) 1572 return -EINVAL; 1573 return 0; 1574 } 1575 1576 static void at91_adc_hw_init(struct at91_adc_state *st) 1577 { 1578 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST); 1579 at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff); 1580 /* 1581 * Transfer field must be set to 2 according to the datasheet and 1582 * allows different analog settings for each channel. 1583 */ 1584 at91_adc_writel(st, AT91_SAMA5D2_MR, 1585 AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH); 1586 1587 at91_adc_setup_samp_freq(st, st->soc_info.min_sample_rate); 1588 1589 /* configure extended mode register */ 1590 at91_adc_config_emr(st); 1591 } 1592 1593 static ssize_t at91_adc_get_fifo_state(struct device *dev, 1594 struct device_attribute *attr, char *buf) 1595 { 1596 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1597 struct at91_adc_state *st = iio_priv(indio_dev); 1598 1599 return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan); 1600 } 1601 1602 static ssize_t at91_adc_get_watermark(struct device *dev, 1603 struct device_attribute *attr, char *buf) 1604 { 1605 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1606 struct at91_adc_state *st = iio_priv(indio_dev); 1607 1608 return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark); 1609 } 1610 1611 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 1612 at91_adc_get_fifo_state, NULL, 0); 1613 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 1614 at91_adc_get_watermark, NULL, 0); 1615 1616 static IIO_CONST_ATTR(hwfifo_watermark_min, "2"); 1617 static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR); 1618 1619 static IIO_CONST_ATTR(oversampling_ratio_available, 1620 __stringify(AT91_OSR_1SAMPLES) " " 1621 __stringify(AT91_OSR_4SAMPLES) " " 1622 __stringify(AT91_OSR_16SAMPLES)); 1623 1624 static struct attribute *at91_adc_attributes[] = { 1625 &iio_const_attr_oversampling_ratio_available.dev_attr.attr, 1626 NULL, 1627 }; 1628 1629 static const struct attribute_group at91_adc_attribute_group = { 1630 .attrs = at91_adc_attributes, 1631 }; 1632 1633 static const struct attribute *at91_adc_fifo_attributes[] = { 1634 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 1635 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 1636 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 1637 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 1638 NULL, 1639 }; 1640 1641 static const struct iio_info at91_adc_info = { 1642 .attrs = &at91_adc_attribute_group, 1643 .read_raw = &at91_adc_read_raw, 1644 .write_raw = &at91_adc_write_raw, 1645 .update_scan_mode = &at91_adc_update_scan_mode, 1646 .of_xlate = &at91_adc_of_xlate, 1647 .hwfifo_set_watermark = &at91_adc_set_watermark, 1648 }; 1649 1650 static int at91_adc_probe(struct platform_device *pdev) 1651 { 1652 struct iio_dev *indio_dev; 1653 struct at91_adc_state *st; 1654 struct resource *res; 1655 int ret, i; 1656 u32 edge_type = IRQ_TYPE_NONE; 1657 1658 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); 1659 if (!indio_dev) 1660 return -ENOMEM; 1661 1662 indio_dev->dev.parent = &pdev->dev; 1663 indio_dev->name = dev_name(&pdev->dev); 1664 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 1665 indio_dev->info = &at91_adc_info; 1666 indio_dev->channels = at91_adc_channels; 1667 indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels); 1668 1669 st = iio_priv(indio_dev); 1670 1671 bitmap_set(&st->touch_st.channels_bitmask, 1672 AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 1); 1673 bitmap_set(&st->touch_st.channels_bitmask, 1674 AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 1); 1675 bitmap_set(&st->touch_st.channels_bitmask, 1676 AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 1); 1677 1678 st->oversampling_ratio = AT91_OSR_1SAMPLES; 1679 1680 ret = of_property_read_u32(pdev->dev.of_node, 1681 "atmel,min-sample-rate-hz", 1682 &st->soc_info.min_sample_rate); 1683 if (ret) { 1684 dev_err(&pdev->dev, 1685 "invalid or missing value for atmel,min-sample-rate-hz\n"); 1686 return ret; 1687 } 1688 1689 ret = of_property_read_u32(pdev->dev.of_node, 1690 "atmel,max-sample-rate-hz", 1691 &st->soc_info.max_sample_rate); 1692 if (ret) { 1693 dev_err(&pdev->dev, 1694 "invalid or missing value for atmel,max-sample-rate-hz\n"); 1695 return ret; 1696 } 1697 1698 ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms", 1699 &st->soc_info.startup_time); 1700 if (ret) { 1701 dev_err(&pdev->dev, 1702 "invalid or missing value for atmel,startup-time-ms\n"); 1703 return ret; 1704 } 1705 1706 ret = of_property_read_u32(pdev->dev.of_node, 1707 "atmel,trigger-edge-type", &edge_type); 1708 if (ret) { 1709 dev_dbg(&pdev->dev, 1710 "atmel,trigger-edge-type not specified, only software trigger available\n"); 1711 } 1712 1713 st->selected_trig = NULL; 1714 1715 /* find the right trigger, or no trigger at all */ 1716 for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++) 1717 if (at91_adc_trigger_list[i].edge_type == edge_type) { 1718 st->selected_trig = &at91_adc_trigger_list[i]; 1719 break; 1720 } 1721 1722 if (!st->selected_trig) { 1723 dev_err(&pdev->dev, "invalid external trigger edge value\n"); 1724 return -EINVAL; 1725 } 1726 1727 init_waitqueue_head(&st->wq_data_available); 1728 mutex_init(&st->lock); 1729 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler); 1730 1731 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1732 if (!res) 1733 return -EINVAL; 1734 1735 /* if we plan to use DMA, we need the physical address of the regs */ 1736 st->dma_st.phys_addr = res->start; 1737 1738 st->base = devm_ioremap_resource(&pdev->dev, res); 1739 if (IS_ERR(st->base)) 1740 return PTR_ERR(st->base); 1741 1742 st->irq = platform_get_irq(pdev, 0); 1743 if (st->irq <= 0) { 1744 if (!st->irq) 1745 st->irq = -ENXIO; 1746 1747 return st->irq; 1748 } 1749 1750 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk"); 1751 if (IS_ERR(st->per_clk)) 1752 return PTR_ERR(st->per_clk); 1753 1754 st->reg = devm_regulator_get(&pdev->dev, "vddana"); 1755 if (IS_ERR(st->reg)) 1756 return PTR_ERR(st->reg); 1757 1758 st->vref = devm_regulator_get(&pdev->dev, "vref"); 1759 if (IS_ERR(st->vref)) 1760 return PTR_ERR(st->vref); 1761 1762 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0, 1763 pdev->dev.driver->name, indio_dev); 1764 if (ret) 1765 return ret; 1766 1767 ret = regulator_enable(st->reg); 1768 if (ret) 1769 return ret; 1770 1771 ret = regulator_enable(st->vref); 1772 if (ret) 1773 goto reg_disable; 1774 1775 st->vref_uv = regulator_get_voltage(st->vref); 1776 if (st->vref_uv <= 0) { 1777 ret = -EINVAL; 1778 goto vref_disable; 1779 } 1780 1781 at91_adc_hw_init(st); 1782 1783 ret = clk_prepare_enable(st->per_clk); 1784 if (ret) 1785 goto vref_disable; 1786 1787 platform_set_drvdata(pdev, indio_dev); 1788 1789 ret = at91_adc_buffer_init(indio_dev); 1790 if (ret < 0) { 1791 dev_err(&pdev->dev, "couldn't initialize the buffer.\n"); 1792 goto per_clk_disable_unprepare; 1793 } 1794 1795 if (st->selected_trig->hw_trig) { 1796 ret = at91_adc_trigger_init(indio_dev); 1797 if (ret < 0) { 1798 dev_err(&pdev->dev, "couldn't setup the triggers.\n"); 1799 goto per_clk_disable_unprepare; 1800 } 1801 /* 1802 * Initially the iio buffer has a length of 2 and 1803 * a watermark of 1 1804 */ 1805 st->dma_st.watermark = 1; 1806 1807 iio_buffer_set_attrs(indio_dev->buffer, 1808 at91_adc_fifo_attributes); 1809 } 1810 1811 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32))) 1812 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n"); 1813 1814 ret = iio_device_register(indio_dev); 1815 if (ret < 0) 1816 goto dma_disable; 1817 1818 if (st->selected_trig->hw_trig) 1819 dev_info(&pdev->dev, "setting up trigger as %s\n", 1820 st->selected_trig->name); 1821 1822 dev_info(&pdev->dev, "version: %x\n", 1823 readl_relaxed(st->base + AT91_SAMA5D2_VERSION)); 1824 1825 return 0; 1826 1827 dma_disable: 1828 at91_adc_dma_disable(pdev); 1829 per_clk_disable_unprepare: 1830 clk_disable_unprepare(st->per_clk); 1831 vref_disable: 1832 regulator_disable(st->vref); 1833 reg_disable: 1834 regulator_disable(st->reg); 1835 return ret; 1836 } 1837 1838 static int at91_adc_remove(struct platform_device *pdev) 1839 { 1840 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1841 struct at91_adc_state *st = iio_priv(indio_dev); 1842 1843 iio_device_unregister(indio_dev); 1844 1845 at91_adc_dma_disable(pdev); 1846 1847 clk_disable_unprepare(st->per_clk); 1848 1849 regulator_disable(st->vref); 1850 regulator_disable(st->reg); 1851 1852 return 0; 1853 } 1854 1855 static __maybe_unused int at91_adc_suspend(struct device *dev) 1856 { 1857 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1858 struct at91_adc_state *st = iio_priv(indio_dev); 1859 1860 /* 1861 * Do a sofware reset of the ADC before we go to suspend. 1862 * this will ensure that all pins are free from being muxed by the ADC 1863 * and can be used by for other devices. 1864 * Otherwise, ADC will hog them and we can't go to suspend mode. 1865 */ 1866 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST); 1867 1868 clk_disable_unprepare(st->per_clk); 1869 regulator_disable(st->vref); 1870 regulator_disable(st->reg); 1871 1872 return pinctrl_pm_select_sleep_state(dev); 1873 } 1874 1875 static __maybe_unused int at91_adc_resume(struct device *dev) 1876 { 1877 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1878 struct at91_adc_state *st = iio_priv(indio_dev); 1879 int ret; 1880 1881 ret = pinctrl_pm_select_default_state(dev); 1882 if (ret) 1883 goto resume_failed; 1884 1885 ret = regulator_enable(st->reg); 1886 if (ret) 1887 goto resume_failed; 1888 1889 ret = regulator_enable(st->vref); 1890 if (ret) 1891 goto reg_disable_resume; 1892 1893 ret = clk_prepare_enable(st->per_clk); 1894 if (ret) 1895 goto vref_disable_resume; 1896 1897 at91_adc_hw_init(st); 1898 1899 /* reconfiguring trigger hardware state */ 1900 if (!iio_buffer_enabled(indio_dev)) 1901 return 0; 1902 1903 /* check if we are enabling triggered buffer or the touchscreen */ 1904 if (bitmap_subset(indio_dev->active_scan_mask, 1905 &st->touch_st.channels_bitmask, 1906 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) { 1907 /* touchscreen enabling */ 1908 return at91_adc_configure_touch(st, true); 1909 } else { 1910 return at91_adc_configure_trigger(st->trig, true); 1911 } 1912 1913 /* not needed but more explicit */ 1914 return 0; 1915 1916 vref_disable_resume: 1917 regulator_disable(st->vref); 1918 reg_disable_resume: 1919 regulator_disable(st->reg); 1920 resume_failed: 1921 dev_err(&indio_dev->dev, "failed to resume\n"); 1922 return ret; 1923 } 1924 1925 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume); 1926 1927 static const struct of_device_id at91_adc_dt_match[] = { 1928 { 1929 .compatible = "atmel,sama5d2-adc", 1930 }, { 1931 /* sentinel */ 1932 } 1933 }; 1934 MODULE_DEVICE_TABLE(of, at91_adc_dt_match); 1935 1936 static struct platform_driver at91_adc_driver = { 1937 .probe = at91_adc_probe, 1938 .remove = at91_adc_remove, 1939 .driver = { 1940 .name = "at91-sama5d2_adc", 1941 .of_match_table = at91_adc_dt_match, 1942 .pm = &at91_adc_pm_ops, 1943 }, 1944 }; 1945 module_platform_driver(at91_adc_driver) 1946 1947 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 1948 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC"); 1949 MODULE_LICENSE("GPL v2"); 1950