1 /* 2 * Broadcom NetXtreme-E RoCE driver. 3 * 4 * Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term 5 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 6 * 7 * This software is available to you under a choice of one of two 8 * licenses. You may choose to be licensed under the terms of the GNU 9 * General Public License (GPL) Version 2, available from the file 10 * COPYING in the main directory of this source tree, or the 11 * BSD license below: 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 17 * 1. Redistributions of source code must retain the above copyright 18 * notice, this list of conditions and the following disclaimer. 19 * 2. Redistributions in binary form must reproduce the above copyright 20 * notice, this list of conditions and the following disclaimer in 21 * the documentation and/or other materials provided with the 22 * distribution. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 28 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 31 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 33 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 34 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 * 36 * Description: IB Verbs interpreter 37 */ 38 39 #include <linux/interrupt.h> 40 #include <linux/types.h> 41 #include <linux/pci.h> 42 #include <linux/netdevice.h> 43 #include <linux/if_ether.h> 44 45 #include <rdma/ib_verbs.h> 46 #include <rdma/ib_user_verbs.h> 47 #include <rdma/ib_umem.h> 48 #include <rdma/ib_addr.h> 49 #include <rdma/ib_mad.h> 50 #include <rdma/ib_cache.h> 51 #include <rdma/uverbs_ioctl.h> 52 53 #include "bnxt_ulp.h" 54 55 #include "roce_hsi.h" 56 #include "qplib_res.h" 57 #include "qplib_sp.h" 58 #include "qplib_fp.h" 59 #include "qplib_rcfw.h" 60 61 #include "bnxt_re.h" 62 #include "ib_verbs.h" 63 #include <rdma/bnxt_re-abi.h> 64 65 static int __from_ib_access_flags(int iflags) 66 { 67 int qflags = 0; 68 69 if (iflags & IB_ACCESS_LOCAL_WRITE) 70 qflags |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 71 if (iflags & IB_ACCESS_REMOTE_READ) 72 qflags |= BNXT_QPLIB_ACCESS_REMOTE_READ; 73 if (iflags & IB_ACCESS_REMOTE_WRITE) 74 qflags |= BNXT_QPLIB_ACCESS_REMOTE_WRITE; 75 if (iflags & IB_ACCESS_REMOTE_ATOMIC) 76 qflags |= BNXT_QPLIB_ACCESS_REMOTE_ATOMIC; 77 if (iflags & IB_ACCESS_MW_BIND) 78 qflags |= BNXT_QPLIB_ACCESS_MW_BIND; 79 if (iflags & IB_ZERO_BASED) 80 qflags |= BNXT_QPLIB_ACCESS_ZERO_BASED; 81 if (iflags & IB_ACCESS_ON_DEMAND) 82 qflags |= BNXT_QPLIB_ACCESS_ON_DEMAND; 83 return qflags; 84 }; 85 86 static enum ib_access_flags __to_ib_access_flags(int qflags) 87 { 88 enum ib_access_flags iflags = 0; 89 90 if (qflags & BNXT_QPLIB_ACCESS_LOCAL_WRITE) 91 iflags |= IB_ACCESS_LOCAL_WRITE; 92 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_WRITE) 93 iflags |= IB_ACCESS_REMOTE_WRITE; 94 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_READ) 95 iflags |= IB_ACCESS_REMOTE_READ; 96 if (qflags & BNXT_QPLIB_ACCESS_REMOTE_ATOMIC) 97 iflags |= IB_ACCESS_REMOTE_ATOMIC; 98 if (qflags & BNXT_QPLIB_ACCESS_MW_BIND) 99 iflags |= IB_ACCESS_MW_BIND; 100 if (qflags & BNXT_QPLIB_ACCESS_ZERO_BASED) 101 iflags |= IB_ZERO_BASED; 102 if (qflags & BNXT_QPLIB_ACCESS_ON_DEMAND) 103 iflags |= IB_ACCESS_ON_DEMAND; 104 return iflags; 105 }; 106 107 static int bnxt_re_build_sgl(struct ib_sge *ib_sg_list, 108 struct bnxt_qplib_sge *sg_list, int num) 109 { 110 int i, total = 0; 111 112 for (i = 0; i < num; i++) { 113 sg_list[i].addr = ib_sg_list[i].addr; 114 sg_list[i].lkey = ib_sg_list[i].lkey; 115 sg_list[i].size = ib_sg_list[i].length; 116 total += sg_list[i].size; 117 } 118 return total; 119 } 120 121 /* Device */ 122 int bnxt_re_query_device(struct ib_device *ibdev, 123 struct ib_device_attr *ib_attr, 124 struct ib_udata *udata) 125 { 126 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 127 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 128 129 memset(ib_attr, 0, sizeof(*ib_attr)); 130 memcpy(&ib_attr->fw_ver, dev_attr->fw_ver, 131 min(sizeof(dev_attr->fw_ver), 132 sizeof(ib_attr->fw_ver))); 133 bnxt_qplib_get_guid(rdev->netdev->dev_addr, 134 (u8 *)&ib_attr->sys_image_guid); 135 ib_attr->max_mr_size = BNXT_RE_MAX_MR_SIZE; 136 ib_attr->page_size_cap = BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M; 137 138 ib_attr->vendor_id = rdev->en_dev->pdev->vendor; 139 ib_attr->vendor_part_id = rdev->en_dev->pdev->device; 140 ib_attr->hw_ver = rdev->en_dev->pdev->subsystem_device; 141 ib_attr->max_qp = dev_attr->max_qp; 142 ib_attr->max_qp_wr = dev_attr->max_qp_wqes; 143 ib_attr->device_cap_flags = 144 IB_DEVICE_CURR_QP_STATE_MOD 145 | IB_DEVICE_RC_RNR_NAK_GEN 146 | IB_DEVICE_SHUTDOWN_PORT 147 | IB_DEVICE_SYS_IMAGE_GUID 148 | IB_DEVICE_LOCAL_DMA_LKEY 149 | IB_DEVICE_RESIZE_MAX_WR 150 | IB_DEVICE_PORT_ACTIVE_EVENT 151 | IB_DEVICE_N_NOTIFY_CQ 152 | IB_DEVICE_MEM_WINDOW 153 | IB_DEVICE_MEM_WINDOW_TYPE_2B 154 | IB_DEVICE_MEM_MGT_EXTENSIONS; 155 ib_attr->max_send_sge = dev_attr->max_qp_sges; 156 ib_attr->max_recv_sge = dev_attr->max_qp_sges; 157 ib_attr->max_sge_rd = dev_attr->max_qp_sges; 158 ib_attr->max_cq = dev_attr->max_cq; 159 ib_attr->max_cqe = dev_attr->max_cq_wqes; 160 ib_attr->max_mr = dev_attr->max_mr; 161 ib_attr->max_pd = dev_attr->max_pd; 162 ib_attr->max_qp_rd_atom = dev_attr->max_qp_rd_atom; 163 ib_attr->max_qp_init_rd_atom = dev_attr->max_qp_init_rd_atom; 164 ib_attr->atomic_cap = IB_ATOMIC_NONE; 165 ib_attr->masked_atomic_cap = IB_ATOMIC_NONE; 166 167 ib_attr->max_ee_rd_atom = 0; 168 ib_attr->max_res_rd_atom = 0; 169 ib_attr->max_ee_init_rd_atom = 0; 170 ib_attr->max_ee = 0; 171 ib_attr->max_rdd = 0; 172 ib_attr->max_mw = dev_attr->max_mw; 173 ib_attr->max_raw_ipv6_qp = 0; 174 ib_attr->max_raw_ethy_qp = dev_attr->max_raw_ethy_qp; 175 ib_attr->max_mcast_grp = 0; 176 ib_attr->max_mcast_qp_attach = 0; 177 ib_attr->max_total_mcast_qp_attach = 0; 178 ib_attr->max_ah = dev_attr->max_ah; 179 180 ib_attr->max_fmr = 0; 181 ib_attr->max_map_per_fmr = 0; 182 183 ib_attr->max_srq = dev_attr->max_srq; 184 ib_attr->max_srq_wr = dev_attr->max_srq_wqes; 185 ib_attr->max_srq_sge = dev_attr->max_srq_sges; 186 187 ib_attr->max_fast_reg_page_list_len = MAX_PBL_LVL_1_PGS; 188 189 ib_attr->max_pkeys = 1; 190 ib_attr->local_ca_ack_delay = BNXT_RE_DEFAULT_ACK_DELAY; 191 return 0; 192 } 193 194 /* Port */ 195 int bnxt_re_query_port(struct ib_device *ibdev, u8 port_num, 196 struct ib_port_attr *port_attr) 197 { 198 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 199 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 200 201 memset(port_attr, 0, sizeof(*port_attr)); 202 203 if (netif_running(rdev->netdev) && netif_carrier_ok(rdev->netdev)) { 204 port_attr->state = IB_PORT_ACTIVE; 205 port_attr->phys_state = IB_PORT_PHYS_STATE_LINK_UP; 206 } else { 207 port_attr->state = IB_PORT_DOWN; 208 port_attr->phys_state = IB_PORT_PHYS_STATE_DISABLED; 209 } 210 port_attr->max_mtu = IB_MTU_4096; 211 port_attr->active_mtu = iboe_get_mtu(rdev->netdev->mtu); 212 port_attr->gid_tbl_len = dev_attr->max_sgid; 213 port_attr->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP | 214 IB_PORT_DEVICE_MGMT_SUP | 215 IB_PORT_VENDOR_CLASS_SUP; 216 port_attr->ip_gids = true; 217 218 port_attr->max_msg_sz = (u32)BNXT_RE_MAX_MR_SIZE_LOW; 219 port_attr->bad_pkey_cntr = 0; 220 port_attr->qkey_viol_cntr = 0; 221 port_attr->pkey_tbl_len = dev_attr->max_pkey; 222 port_attr->lid = 0; 223 port_attr->sm_lid = 0; 224 port_attr->lmc = 0; 225 port_attr->max_vl_num = 4; 226 port_attr->sm_sl = 0; 227 port_attr->subnet_timeout = 0; 228 port_attr->init_type_reply = 0; 229 port_attr->active_speed = rdev->active_speed; 230 port_attr->active_width = rdev->active_width; 231 232 return 0; 233 } 234 235 int bnxt_re_get_port_immutable(struct ib_device *ibdev, u8 port_num, 236 struct ib_port_immutable *immutable) 237 { 238 struct ib_port_attr port_attr; 239 240 if (bnxt_re_query_port(ibdev, port_num, &port_attr)) 241 return -EINVAL; 242 243 immutable->pkey_tbl_len = port_attr.pkey_tbl_len; 244 immutable->gid_tbl_len = port_attr.gid_tbl_len; 245 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE; 246 immutable->core_cap_flags |= RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP; 247 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 248 return 0; 249 } 250 251 void bnxt_re_query_fw_str(struct ib_device *ibdev, char *str) 252 { 253 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 254 255 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%d.%d", 256 rdev->dev_attr.fw_ver[0], rdev->dev_attr.fw_ver[1], 257 rdev->dev_attr.fw_ver[2], rdev->dev_attr.fw_ver[3]); 258 } 259 260 int bnxt_re_query_pkey(struct ib_device *ibdev, u8 port_num, 261 u16 index, u16 *pkey) 262 { 263 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 264 265 /* Ignore port_num */ 266 267 memset(pkey, 0, sizeof(*pkey)); 268 return bnxt_qplib_get_pkey(&rdev->qplib_res, 269 &rdev->qplib_res.pkey_tbl, index, pkey); 270 } 271 272 int bnxt_re_query_gid(struct ib_device *ibdev, u8 port_num, 273 int index, union ib_gid *gid) 274 { 275 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 276 int rc = 0; 277 278 /* Ignore port_num */ 279 memset(gid, 0, sizeof(*gid)); 280 rc = bnxt_qplib_get_sgid(&rdev->qplib_res, 281 &rdev->qplib_res.sgid_tbl, index, 282 (struct bnxt_qplib_gid *)gid); 283 return rc; 284 } 285 286 int bnxt_re_del_gid(const struct ib_gid_attr *attr, void **context) 287 { 288 int rc = 0; 289 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 290 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 291 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 292 struct bnxt_qplib_gid *gid_to_del; 293 u16 vlan_id = 0xFFFF; 294 295 /* Delete the entry from the hardware */ 296 ctx = *context; 297 if (!ctx) 298 return -EINVAL; 299 300 if (sgid_tbl && sgid_tbl->active) { 301 if (ctx->idx >= sgid_tbl->max) 302 return -EINVAL; 303 gid_to_del = &sgid_tbl->tbl[ctx->idx].gid; 304 vlan_id = sgid_tbl->tbl[ctx->idx].vlan_id; 305 /* DEL_GID is called in WQ context(netdevice_event_work_handler) 306 * or via the ib_unregister_device path. In the former case QP1 307 * may not be destroyed yet, in which case just return as FW 308 * needs that entry to be present and will fail it's deletion. 309 * We could get invoked again after QP1 is destroyed OR get an 310 * ADD_GID call with a different GID value for the same index 311 * where we issue MODIFY_GID cmd to update the GID entry -- TBD 312 */ 313 if (ctx->idx == 0 && 314 rdma_link_local_addr((struct in6_addr *)gid_to_del) && 315 ctx->refcnt == 1 && rdev->qp1_sqp) { 316 dev_dbg(rdev_to_dev(rdev), 317 "Trying to delete GID0 while QP1 is alive\n"); 318 return -EFAULT; 319 } 320 ctx->refcnt--; 321 if (!ctx->refcnt) { 322 rc = bnxt_qplib_del_sgid(sgid_tbl, gid_to_del, 323 vlan_id, true); 324 if (rc) { 325 dev_err(rdev_to_dev(rdev), 326 "Failed to remove GID: %#x", rc); 327 } else { 328 ctx_tbl = sgid_tbl->ctx; 329 ctx_tbl[ctx->idx] = NULL; 330 kfree(ctx); 331 } 332 } 333 } else { 334 return -EINVAL; 335 } 336 return rc; 337 } 338 339 int bnxt_re_add_gid(const struct ib_gid_attr *attr, void **context) 340 { 341 int rc; 342 u32 tbl_idx = 0; 343 u16 vlan_id = 0xFFFF; 344 struct bnxt_re_gid_ctx *ctx, **ctx_tbl; 345 struct bnxt_re_dev *rdev = to_bnxt_re_dev(attr->device, ibdev); 346 struct bnxt_qplib_sgid_tbl *sgid_tbl = &rdev->qplib_res.sgid_tbl; 347 348 rc = rdma_read_gid_l2_fields(attr, &vlan_id, NULL); 349 if (rc) 350 return rc; 351 352 rc = bnxt_qplib_add_sgid(sgid_tbl, (struct bnxt_qplib_gid *)&attr->gid, 353 rdev->qplib_res.netdev->dev_addr, 354 vlan_id, true, &tbl_idx); 355 if (rc == -EALREADY) { 356 ctx_tbl = sgid_tbl->ctx; 357 ctx_tbl[tbl_idx]->refcnt++; 358 *context = ctx_tbl[tbl_idx]; 359 return 0; 360 } 361 362 if (rc < 0) { 363 dev_err(rdev_to_dev(rdev), "Failed to add GID: %#x", rc); 364 return rc; 365 } 366 367 ctx = kmalloc(sizeof(*ctx), GFP_KERNEL); 368 if (!ctx) 369 return -ENOMEM; 370 ctx_tbl = sgid_tbl->ctx; 371 ctx->idx = tbl_idx; 372 ctx->refcnt = 1; 373 ctx_tbl[tbl_idx] = ctx; 374 *context = ctx; 375 376 return rc; 377 } 378 379 enum rdma_link_layer bnxt_re_get_link_layer(struct ib_device *ibdev, 380 u8 port_num) 381 { 382 return IB_LINK_LAYER_ETHERNET; 383 } 384 385 #define BNXT_RE_FENCE_PBL_SIZE DIV_ROUND_UP(BNXT_RE_FENCE_BYTES, PAGE_SIZE) 386 387 static void bnxt_re_create_fence_wqe(struct bnxt_re_pd *pd) 388 { 389 struct bnxt_re_fence_data *fence = &pd->fence; 390 struct ib_mr *ib_mr = &fence->mr->ib_mr; 391 struct bnxt_qplib_swqe *wqe = &fence->bind_wqe; 392 393 memset(wqe, 0, sizeof(*wqe)); 394 wqe->type = BNXT_QPLIB_SWQE_TYPE_BIND_MW; 395 wqe->wr_id = BNXT_QPLIB_FENCE_WRID; 396 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 397 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 398 wqe->bind.zero_based = false; 399 wqe->bind.parent_l_key = ib_mr->lkey; 400 wqe->bind.va = (u64)(unsigned long)fence->va; 401 wqe->bind.length = fence->size; 402 wqe->bind.access_cntl = __from_ib_access_flags(IB_ACCESS_REMOTE_READ); 403 wqe->bind.mw_type = SQ_BIND_MW_TYPE_TYPE1; 404 405 /* Save the initial rkey in fence structure for now; 406 * wqe->bind.r_key will be set at (re)bind time. 407 */ 408 fence->bind_rkey = ib_inc_rkey(fence->mw->rkey); 409 } 410 411 static int bnxt_re_bind_fence_mw(struct bnxt_qplib_qp *qplib_qp) 412 { 413 struct bnxt_re_qp *qp = container_of(qplib_qp, struct bnxt_re_qp, 414 qplib_qp); 415 struct ib_pd *ib_pd = qp->ib_qp.pd; 416 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 417 struct bnxt_re_fence_data *fence = &pd->fence; 418 struct bnxt_qplib_swqe *fence_wqe = &fence->bind_wqe; 419 struct bnxt_qplib_swqe wqe; 420 int rc; 421 422 memcpy(&wqe, fence_wqe, sizeof(wqe)); 423 wqe.bind.r_key = fence->bind_rkey; 424 fence->bind_rkey = ib_inc_rkey(fence->bind_rkey); 425 426 dev_dbg(rdev_to_dev(qp->rdev), 427 "Posting bind fence-WQE: rkey: %#x QP: %d PD: %p\n", 428 wqe.bind.r_key, qp->qplib_qp.id, pd); 429 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 430 if (rc) { 431 dev_err(rdev_to_dev(qp->rdev), "Failed to bind fence-WQE\n"); 432 return rc; 433 } 434 bnxt_qplib_post_send_db(&qp->qplib_qp); 435 436 return rc; 437 } 438 439 static void bnxt_re_destroy_fence_mr(struct bnxt_re_pd *pd) 440 { 441 struct bnxt_re_fence_data *fence = &pd->fence; 442 struct bnxt_re_dev *rdev = pd->rdev; 443 struct device *dev = &rdev->en_dev->pdev->dev; 444 struct bnxt_re_mr *mr = fence->mr; 445 446 if (fence->mw) { 447 bnxt_re_dealloc_mw(fence->mw); 448 fence->mw = NULL; 449 } 450 if (mr) { 451 if (mr->ib_mr.rkey) 452 bnxt_qplib_dereg_mrw(&rdev->qplib_res, &mr->qplib_mr, 453 true); 454 if (mr->ib_mr.lkey) 455 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 456 kfree(mr); 457 fence->mr = NULL; 458 } 459 if (fence->dma_addr) { 460 dma_unmap_single(dev, fence->dma_addr, BNXT_RE_FENCE_BYTES, 461 DMA_BIDIRECTIONAL); 462 fence->dma_addr = 0; 463 } 464 } 465 466 static int bnxt_re_create_fence_mr(struct bnxt_re_pd *pd) 467 { 468 int mr_access_flags = IB_ACCESS_LOCAL_WRITE | IB_ACCESS_MW_BIND; 469 struct bnxt_re_fence_data *fence = &pd->fence; 470 struct bnxt_re_dev *rdev = pd->rdev; 471 struct device *dev = &rdev->en_dev->pdev->dev; 472 struct bnxt_re_mr *mr = NULL; 473 dma_addr_t dma_addr = 0; 474 struct ib_mw *mw; 475 u64 pbl_tbl; 476 int rc; 477 478 dma_addr = dma_map_single(dev, fence->va, BNXT_RE_FENCE_BYTES, 479 DMA_BIDIRECTIONAL); 480 rc = dma_mapping_error(dev, dma_addr); 481 if (rc) { 482 dev_err(rdev_to_dev(rdev), "Failed to dma-map fence-MR-mem\n"); 483 rc = -EIO; 484 fence->dma_addr = 0; 485 goto fail; 486 } 487 fence->dma_addr = dma_addr; 488 489 /* Allocate a MR */ 490 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 491 if (!mr) { 492 rc = -ENOMEM; 493 goto fail; 494 } 495 fence->mr = mr; 496 mr->rdev = rdev; 497 mr->qplib_mr.pd = &pd->qplib_pd; 498 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 499 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 500 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 501 if (rc) { 502 dev_err(rdev_to_dev(rdev), "Failed to alloc fence-HW-MR\n"); 503 goto fail; 504 } 505 506 /* Register MR */ 507 mr->ib_mr.lkey = mr->qplib_mr.lkey; 508 mr->qplib_mr.va = (u64)(unsigned long)fence->va; 509 mr->qplib_mr.total_size = BNXT_RE_FENCE_BYTES; 510 pbl_tbl = dma_addr; 511 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl_tbl, 512 BNXT_RE_FENCE_PBL_SIZE, false, PAGE_SIZE); 513 if (rc) { 514 dev_err(rdev_to_dev(rdev), "Failed to register fence-MR\n"); 515 goto fail; 516 } 517 mr->ib_mr.rkey = mr->qplib_mr.rkey; 518 519 /* Create a fence MW only for kernel consumers */ 520 mw = bnxt_re_alloc_mw(&pd->ib_pd, IB_MW_TYPE_1, NULL); 521 if (IS_ERR(mw)) { 522 dev_err(rdev_to_dev(rdev), 523 "Failed to create fence-MW for PD: %p\n", pd); 524 rc = PTR_ERR(mw); 525 goto fail; 526 } 527 fence->mw = mw; 528 529 bnxt_re_create_fence_wqe(pd); 530 return 0; 531 532 fail: 533 bnxt_re_destroy_fence_mr(pd); 534 return rc; 535 } 536 537 /* Protection Domains */ 538 void bnxt_re_dealloc_pd(struct ib_pd *ib_pd, struct ib_udata *udata) 539 { 540 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 541 struct bnxt_re_dev *rdev = pd->rdev; 542 543 bnxt_re_destroy_fence_mr(pd); 544 545 if (pd->qplib_pd.id) 546 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 547 &pd->qplib_pd); 548 } 549 550 int bnxt_re_alloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) 551 { 552 struct ib_device *ibdev = ibpd->device; 553 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 554 struct bnxt_re_ucontext *ucntx = rdma_udata_to_drv_context( 555 udata, struct bnxt_re_ucontext, ib_uctx); 556 struct bnxt_re_pd *pd = container_of(ibpd, struct bnxt_re_pd, ib_pd); 557 int rc; 558 559 pd->rdev = rdev; 560 if (bnxt_qplib_alloc_pd(&rdev->qplib_res.pd_tbl, &pd->qplib_pd)) { 561 dev_err(rdev_to_dev(rdev), "Failed to allocate HW PD"); 562 rc = -ENOMEM; 563 goto fail; 564 } 565 566 if (udata) { 567 struct bnxt_re_pd_resp resp; 568 569 if (!ucntx->dpi.dbr) { 570 /* Allocate DPI in alloc_pd to avoid failing of 571 * ibv_devinfo and family of application when DPIs 572 * are depleted. 573 */ 574 if (bnxt_qplib_alloc_dpi(&rdev->qplib_res.dpi_tbl, 575 &ucntx->dpi, ucntx)) { 576 rc = -ENOMEM; 577 goto dbfail; 578 } 579 } 580 581 resp.pdid = pd->qplib_pd.id; 582 /* Still allow mapping this DBR to the new user PD. */ 583 resp.dpi = ucntx->dpi.dpi; 584 resp.dbr = (u64)ucntx->dpi.umdbr; 585 586 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 587 if (rc) { 588 dev_err(rdev_to_dev(rdev), 589 "Failed to copy user response\n"); 590 goto dbfail; 591 } 592 } 593 594 if (!udata) 595 if (bnxt_re_create_fence_mr(pd)) 596 dev_warn(rdev_to_dev(rdev), 597 "Failed to create Fence-MR\n"); 598 return 0; 599 dbfail: 600 bnxt_qplib_dealloc_pd(&rdev->qplib_res, &rdev->qplib_res.pd_tbl, 601 &pd->qplib_pd); 602 fail: 603 return rc; 604 } 605 606 /* Address Handles */ 607 void bnxt_re_destroy_ah(struct ib_ah *ib_ah, u32 flags) 608 { 609 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 610 struct bnxt_re_dev *rdev = ah->rdev; 611 612 bnxt_qplib_destroy_ah(&rdev->qplib_res, &ah->qplib_ah, 613 !(flags & RDMA_DESTROY_AH_SLEEPABLE)); 614 } 615 616 static u8 bnxt_re_stack_to_dev_nw_type(enum rdma_network_type ntype) 617 { 618 u8 nw_type; 619 620 switch (ntype) { 621 case RDMA_NETWORK_IPV4: 622 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV4; 623 break; 624 case RDMA_NETWORK_IPV6: 625 nw_type = CMDQ_CREATE_AH_TYPE_V2IPV6; 626 break; 627 default: 628 nw_type = CMDQ_CREATE_AH_TYPE_V1; 629 break; 630 } 631 return nw_type; 632 } 633 634 int bnxt_re_create_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr, 635 u32 flags, struct ib_udata *udata) 636 { 637 struct ib_pd *ib_pd = ib_ah->pd; 638 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 639 const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr); 640 struct bnxt_re_dev *rdev = pd->rdev; 641 const struct ib_gid_attr *sgid_attr; 642 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 643 u8 nw_type; 644 int rc; 645 646 if (!(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH)) { 647 dev_err(rdev_to_dev(rdev), "Failed to alloc AH: GRH not set"); 648 return -EINVAL; 649 } 650 651 ah->rdev = rdev; 652 ah->qplib_ah.pd = &pd->qplib_pd; 653 654 /* Supply the configuration for the HW */ 655 memcpy(ah->qplib_ah.dgid.data, grh->dgid.raw, 656 sizeof(union ib_gid)); 657 /* 658 * If RoCE V2 is enabled, stack will have two entries for 659 * each GID entry. Avoiding this duplicte entry in HW. Dividing 660 * the GID index by 2 for RoCE V2 661 */ 662 ah->qplib_ah.sgid_index = grh->sgid_index / 2; 663 ah->qplib_ah.host_sgid_index = grh->sgid_index; 664 ah->qplib_ah.traffic_class = grh->traffic_class; 665 ah->qplib_ah.flow_label = grh->flow_label; 666 ah->qplib_ah.hop_limit = grh->hop_limit; 667 ah->qplib_ah.sl = rdma_ah_get_sl(ah_attr); 668 669 sgid_attr = grh->sgid_attr; 670 /* Get network header type for this GID */ 671 nw_type = rdma_gid_attr_network_type(sgid_attr); 672 ah->qplib_ah.nw_type = bnxt_re_stack_to_dev_nw_type(nw_type); 673 674 memcpy(ah->qplib_ah.dmac, ah_attr->roce.dmac, ETH_ALEN); 675 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, 676 !(flags & RDMA_CREATE_AH_SLEEPABLE)); 677 if (rc) { 678 dev_err(rdev_to_dev(rdev), "Failed to allocate HW AH"); 679 return rc; 680 } 681 682 /* Write AVID to shared page. */ 683 if (udata) { 684 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 685 udata, struct bnxt_re_ucontext, ib_uctx); 686 unsigned long flag; 687 u32 *wrptr; 688 689 spin_lock_irqsave(&uctx->sh_lock, flag); 690 wrptr = (u32 *)(uctx->shpg + BNXT_RE_AVID_OFFT); 691 *wrptr = ah->qplib_ah.id; 692 wmb(); /* make sure cache is updated. */ 693 spin_unlock_irqrestore(&uctx->sh_lock, flag); 694 } 695 696 return 0; 697 } 698 699 int bnxt_re_modify_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 700 { 701 return 0; 702 } 703 704 int bnxt_re_query_ah(struct ib_ah *ib_ah, struct rdma_ah_attr *ah_attr) 705 { 706 struct bnxt_re_ah *ah = container_of(ib_ah, struct bnxt_re_ah, ib_ah); 707 708 ah_attr->type = ib_ah->type; 709 rdma_ah_set_sl(ah_attr, ah->qplib_ah.sl); 710 memcpy(ah_attr->roce.dmac, ah->qplib_ah.dmac, ETH_ALEN); 711 rdma_ah_set_grh(ah_attr, NULL, 0, 712 ah->qplib_ah.host_sgid_index, 713 0, ah->qplib_ah.traffic_class); 714 rdma_ah_set_dgid_raw(ah_attr, ah->qplib_ah.dgid.data); 715 rdma_ah_set_port_num(ah_attr, 1); 716 rdma_ah_set_static_rate(ah_attr, 0); 717 return 0; 718 } 719 720 unsigned long bnxt_re_lock_cqs(struct bnxt_re_qp *qp) 721 __acquires(&qp->scq->cq_lock) __acquires(&qp->rcq->cq_lock) 722 { 723 unsigned long flags; 724 725 spin_lock_irqsave(&qp->scq->cq_lock, flags); 726 if (qp->rcq != qp->scq) 727 spin_lock(&qp->rcq->cq_lock); 728 else 729 __acquire(&qp->rcq->cq_lock); 730 731 return flags; 732 } 733 734 void bnxt_re_unlock_cqs(struct bnxt_re_qp *qp, 735 unsigned long flags) 736 __releases(&qp->scq->cq_lock) __releases(&qp->rcq->cq_lock) 737 { 738 if (qp->rcq != qp->scq) 739 spin_unlock(&qp->rcq->cq_lock); 740 else 741 __release(&qp->rcq->cq_lock); 742 spin_unlock_irqrestore(&qp->scq->cq_lock, flags); 743 } 744 745 /* Queue Pairs */ 746 int bnxt_re_destroy_qp(struct ib_qp *ib_qp, struct ib_udata *udata) 747 { 748 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 749 struct bnxt_re_dev *rdev = qp->rdev; 750 unsigned int flags; 751 int rc; 752 753 bnxt_qplib_flush_cqn_wq(&qp->qplib_qp); 754 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 755 if (rc) { 756 dev_err(rdev_to_dev(rdev), "Failed to destroy HW QP"); 757 return rc; 758 } 759 760 if (rdma_is_kernel_res(&qp->ib_qp.res)) { 761 flags = bnxt_re_lock_cqs(qp); 762 bnxt_qplib_clean_qp(&qp->qplib_qp); 763 bnxt_re_unlock_cqs(qp, flags); 764 } 765 766 bnxt_qplib_free_qp_res(&rdev->qplib_res, &qp->qplib_qp); 767 768 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) { 769 bnxt_qplib_destroy_ah(&rdev->qplib_res, &rdev->sqp_ah->qplib_ah, 770 false); 771 772 bnxt_qplib_clean_qp(&qp->qplib_qp); 773 rc = bnxt_qplib_destroy_qp(&rdev->qplib_res, 774 &rdev->qp1_sqp->qplib_qp); 775 if (rc) { 776 dev_err(rdev_to_dev(rdev), 777 "Failed to destroy Shadow QP"); 778 return rc; 779 } 780 bnxt_qplib_free_qp_res(&rdev->qplib_res, 781 &rdev->qp1_sqp->qplib_qp); 782 mutex_lock(&rdev->qp_lock); 783 list_del(&rdev->qp1_sqp->list); 784 atomic_dec(&rdev->qp_count); 785 mutex_unlock(&rdev->qp_lock); 786 787 kfree(rdev->sqp_ah); 788 kfree(rdev->qp1_sqp); 789 rdev->qp1_sqp = NULL; 790 rdev->sqp_ah = NULL; 791 } 792 793 ib_umem_release(qp->rumem); 794 ib_umem_release(qp->sumem); 795 796 mutex_lock(&rdev->qp_lock); 797 list_del(&qp->list); 798 atomic_dec(&rdev->qp_count); 799 mutex_unlock(&rdev->qp_lock); 800 kfree(qp); 801 return 0; 802 } 803 804 static u8 __from_ib_qp_type(enum ib_qp_type type) 805 { 806 switch (type) { 807 case IB_QPT_GSI: 808 return CMDQ_CREATE_QP1_TYPE_GSI; 809 case IB_QPT_RC: 810 return CMDQ_CREATE_QP_TYPE_RC; 811 case IB_QPT_UD: 812 return CMDQ_CREATE_QP_TYPE_UD; 813 default: 814 return IB_QPT_MAX; 815 } 816 } 817 818 static int bnxt_re_init_user_qp(struct bnxt_re_dev *rdev, struct bnxt_re_pd *pd, 819 struct bnxt_re_qp *qp, struct ib_udata *udata) 820 { 821 struct bnxt_re_qp_req ureq; 822 struct bnxt_qplib_qp *qplib_qp = &qp->qplib_qp; 823 struct ib_umem *umem; 824 int bytes = 0, psn_sz; 825 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 826 udata, struct bnxt_re_ucontext, ib_uctx); 827 828 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 829 return -EFAULT; 830 831 bytes = (qplib_qp->sq.max_wqe * BNXT_QPLIB_MAX_SQE_ENTRY_SIZE); 832 /* Consider mapping PSN search memory only for RC QPs. */ 833 if (qplib_qp->type == CMDQ_CREATE_QP_TYPE_RC) { 834 psn_sz = bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx) ? 835 sizeof(struct sq_psn_search_ext) : 836 sizeof(struct sq_psn_search); 837 bytes += (qplib_qp->sq.max_wqe * psn_sz); 838 } 839 bytes = PAGE_ALIGN(bytes); 840 umem = ib_umem_get(&rdev->ibdev, ureq.qpsva, bytes, 841 IB_ACCESS_LOCAL_WRITE); 842 if (IS_ERR(umem)) 843 return PTR_ERR(umem); 844 845 qp->sumem = umem; 846 qplib_qp->sq.sg_info.sglist = umem->sg_head.sgl; 847 qplib_qp->sq.sg_info.npages = ib_umem_num_pages(umem); 848 qplib_qp->sq.sg_info.nmap = umem->nmap; 849 qplib_qp->qp_handle = ureq.qp_handle; 850 851 if (!qp->qplib_qp.srq) { 852 bytes = (qplib_qp->rq.max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE); 853 bytes = PAGE_ALIGN(bytes); 854 umem = ib_umem_get(&rdev->ibdev, ureq.qprva, bytes, 855 IB_ACCESS_LOCAL_WRITE); 856 if (IS_ERR(umem)) 857 goto rqfail; 858 qp->rumem = umem; 859 qplib_qp->rq.sg_info.sglist = umem->sg_head.sgl; 860 qplib_qp->rq.sg_info.npages = ib_umem_num_pages(umem); 861 qplib_qp->rq.sg_info.nmap = umem->nmap; 862 } 863 864 qplib_qp->dpi = &cntx->dpi; 865 return 0; 866 rqfail: 867 ib_umem_release(qp->sumem); 868 qp->sumem = NULL; 869 memset(&qplib_qp->sq.sg_info, 0, sizeof(qplib_qp->sq.sg_info)); 870 871 return PTR_ERR(umem); 872 } 873 874 static struct bnxt_re_ah *bnxt_re_create_shadow_qp_ah 875 (struct bnxt_re_pd *pd, 876 struct bnxt_qplib_res *qp1_res, 877 struct bnxt_qplib_qp *qp1_qp) 878 { 879 struct bnxt_re_dev *rdev = pd->rdev; 880 struct bnxt_re_ah *ah; 881 union ib_gid sgid; 882 int rc; 883 884 ah = kzalloc(sizeof(*ah), GFP_KERNEL); 885 if (!ah) 886 return NULL; 887 888 ah->rdev = rdev; 889 ah->qplib_ah.pd = &pd->qplib_pd; 890 891 rc = bnxt_re_query_gid(&rdev->ibdev, 1, 0, &sgid); 892 if (rc) 893 goto fail; 894 895 /* supply the dgid data same as sgid */ 896 memcpy(ah->qplib_ah.dgid.data, &sgid.raw, 897 sizeof(union ib_gid)); 898 ah->qplib_ah.sgid_index = 0; 899 900 ah->qplib_ah.traffic_class = 0; 901 ah->qplib_ah.flow_label = 0; 902 ah->qplib_ah.hop_limit = 1; 903 ah->qplib_ah.sl = 0; 904 /* Have DMAC same as SMAC */ 905 ether_addr_copy(ah->qplib_ah.dmac, rdev->netdev->dev_addr); 906 907 rc = bnxt_qplib_create_ah(&rdev->qplib_res, &ah->qplib_ah, false); 908 if (rc) { 909 dev_err(rdev_to_dev(rdev), 910 "Failed to allocate HW AH for Shadow QP"); 911 goto fail; 912 } 913 914 return ah; 915 916 fail: 917 kfree(ah); 918 return NULL; 919 } 920 921 static struct bnxt_re_qp *bnxt_re_create_shadow_qp 922 (struct bnxt_re_pd *pd, 923 struct bnxt_qplib_res *qp1_res, 924 struct bnxt_qplib_qp *qp1_qp) 925 { 926 struct bnxt_re_dev *rdev = pd->rdev; 927 struct bnxt_re_qp *qp; 928 int rc; 929 930 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 931 if (!qp) 932 return NULL; 933 934 qp->rdev = rdev; 935 936 /* Initialize the shadow QP structure from the QP1 values */ 937 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 938 939 qp->qplib_qp.pd = &pd->qplib_pd; 940 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 941 qp->qplib_qp.type = IB_QPT_UD; 942 943 qp->qplib_qp.max_inline_data = 0; 944 qp->qplib_qp.sig_type = true; 945 946 /* Shadow QP SQ depth should be same as QP1 RQ depth */ 947 qp->qplib_qp.sq.max_wqe = qp1_qp->rq.max_wqe; 948 qp->qplib_qp.sq.max_sge = 2; 949 /* Q full delta can be 1 since it is internal QP */ 950 qp->qplib_qp.sq.q_full_delta = 1; 951 952 qp->qplib_qp.scq = qp1_qp->scq; 953 qp->qplib_qp.rcq = qp1_qp->rcq; 954 955 qp->qplib_qp.rq.max_wqe = qp1_qp->rq.max_wqe; 956 qp->qplib_qp.rq.max_sge = qp1_qp->rq.max_sge; 957 /* Q full delta can be 1 since it is internal QP */ 958 qp->qplib_qp.rq.q_full_delta = 1; 959 960 qp->qplib_qp.mtu = qp1_qp->mtu; 961 962 qp->qplib_qp.sq_hdr_buf_size = 0; 963 qp->qplib_qp.rq_hdr_buf_size = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 964 qp->qplib_qp.dpi = &rdev->dpi_privileged; 965 966 rc = bnxt_qplib_create_qp(qp1_res, &qp->qplib_qp); 967 if (rc) 968 goto fail; 969 970 rdev->sqp_id = qp->qplib_qp.id; 971 972 spin_lock_init(&qp->sq_lock); 973 INIT_LIST_HEAD(&qp->list); 974 mutex_lock(&rdev->qp_lock); 975 list_add_tail(&qp->list, &rdev->qp_list); 976 atomic_inc(&rdev->qp_count); 977 mutex_unlock(&rdev->qp_lock); 978 return qp; 979 fail: 980 kfree(qp); 981 return NULL; 982 } 983 984 struct ib_qp *bnxt_re_create_qp(struct ib_pd *ib_pd, 985 struct ib_qp_init_attr *qp_init_attr, 986 struct ib_udata *udata) 987 { 988 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 989 struct bnxt_re_dev *rdev = pd->rdev; 990 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 991 struct bnxt_re_qp *qp; 992 struct bnxt_re_cq *cq; 993 struct bnxt_re_srq *srq; 994 int rc, entries; 995 996 if ((qp_init_attr->cap.max_send_wr > dev_attr->max_qp_wqes) || 997 (qp_init_attr->cap.max_recv_wr > dev_attr->max_qp_wqes) || 998 (qp_init_attr->cap.max_send_sge > dev_attr->max_qp_sges) || 999 (qp_init_attr->cap.max_recv_sge > dev_attr->max_qp_sges) || 1000 (qp_init_attr->cap.max_inline_data > dev_attr->max_inline_data)) 1001 return ERR_PTR(-EINVAL); 1002 1003 qp = kzalloc(sizeof(*qp), GFP_KERNEL); 1004 if (!qp) 1005 return ERR_PTR(-ENOMEM); 1006 1007 qp->rdev = rdev; 1008 ether_addr_copy(qp->qplib_qp.smac, rdev->netdev->dev_addr); 1009 qp->qplib_qp.pd = &pd->qplib_pd; 1010 qp->qplib_qp.qp_handle = (u64)(unsigned long)(&qp->qplib_qp); 1011 qp->qplib_qp.type = __from_ib_qp_type(qp_init_attr->qp_type); 1012 1013 if (qp_init_attr->qp_type == IB_QPT_GSI && 1014 bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx)) 1015 qp->qplib_qp.type = CMDQ_CREATE_QP_TYPE_GSI; 1016 if (qp->qplib_qp.type == IB_QPT_MAX) { 1017 dev_err(rdev_to_dev(rdev), "QP type 0x%x not supported", 1018 qp->qplib_qp.type); 1019 rc = -EINVAL; 1020 goto fail; 1021 } 1022 1023 qp->qplib_qp.max_inline_data = qp_init_attr->cap.max_inline_data; 1024 qp->qplib_qp.sig_type = ((qp_init_attr->sq_sig_type == 1025 IB_SIGNAL_ALL_WR) ? true : false); 1026 1027 qp->qplib_qp.sq.max_sge = qp_init_attr->cap.max_send_sge; 1028 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges) 1029 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges; 1030 1031 if (qp_init_attr->send_cq) { 1032 cq = container_of(qp_init_attr->send_cq, struct bnxt_re_cq, 1033 ib_cq); 1034 if (!cq) { 1035 dev_err(rdev_to_dev(rdev), "Send CQ not found"); 1036 rc = -EINVAL; 1037 goto fail; 1038 } 1039 qp->qplib_qp.scq = &cq->qplib_cq; 1040 qp->scq = cq; 1041 } 1042 1043 if (qp_init_attr->recv_cq) { 1044 cq = container_of(qp_init_attr->recv_cq, struct bnxt_re_cq, 1045 ib_cq); 1046 if (!cq) { 1047 dev_err(rdev_to_dev(rdev), "Receive CQ not found"); 1048 rc = -EINVAL; 1049 goto fail; 1050 } 1051 qp->qplib_qp.rcq = &cq->qplib_cq; 1052 qp->rcq = cq; 1053 } 1054 1055 if (qp_init_attr->srq) { 1056 srq = container_of(qp_init_attr->srq, struct bnxt_re_srq, 1057 ib_srq); 1058 if (!srq) { 1059 dev_err(rdev_to_dev(rdev), "SRQ not found"); 1060 rc = -EINVAL; 1061 goto fail; 1062 } 1063 qp->qplib_qp.srq = &srq->qplib_srq; 1064 qp->qplib_qp.rq.max_wqe = 0; 1065 } else { 1066 /* Allocate 1 more than what's provided so posting max doesn't 1067 * mean empty 1068 */ 1069 entries = roundup_pow_of_two(qp_init_attr->cap.max_recv_wr + 1); 1070 qp->qplib_qp.rq.max_wqe = min_t(u32, entries, 1071 dev_attr->max_qp_wqes + 1); 1072 1073 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 1074 qp_init_attr->cap.max_recv_wr; 1075 1076 qp->qplib_qp.rq.max_sge = qp_init_attr->cap.max_recv_sge; 1077 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges) 1078 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1079 } 1080 1081 qp->qplib_qp.mtu = ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1082 1083 if (qp_init_attr->qp_type == IB_QPT_GSI && 1084 !(bnxt_qplib_is_chip_gen_p5(&rdev->chip_ctx))) { 1085 /* Allocate 1 more than what's provided */ 1086 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1); 1087 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1088 dev_attr->max_qp_wqes + 1); 1089 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 1090 qp_init_attr->cap.max_send_wr; 1091 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1092 if (qp->qplib_qp.rq.max_sge > dev_attr->max_qp_sges) 1093 qp->qplib_qp.rq.max_sge = dev_attr->max_qp_sges; 1094 qp->qplib_qp.sq.max_sge++; 1095 if (qp->qplib_qp.sq.max_sge > dev_attr->max_qp_sges) 1096 qp->qplib_qp.sq.max_sge = dev_attr->max_qp_sges; 1097 1098 qp->qplib_qp.rq_hdr_buf_size = 1099 BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 1100 1101 qp->qplib_qp.sq_hdr_buf_size = 1102 BNXT_QPLIB_MAX_QP1_SQ_HDR_SIZE_V2; 1103 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1104 rc = bnxt_qplib_create_qp1(&rdev->qplib_res, &qp->qplib_qp); 1105 if (rc) { 1106 dev_err(rdev_to_dev(rdev), "Failed to create HW QP1"); 1107 goto fail; 1108 } 1109 /* Create a shadow QP to handle the QP1 traffic */ 1110 rdev->qp1_sqp = bnxt_re_create_shadow_qp(pd, &rdev->qplib_res, 1111 &qp->qplib_qp); 1112 if (!rdev->qp1_sqp) { 1113 rc = -EINVAL; 1114 dev_err(rdev_to_dev(rdev), 1115 "Failed to create Shadow QP for QP1"); 1116 goto qp_destroy; 1117 } 1118 rdev->sqp_ah = bnxt_re_create_shadow_qp_ah(pd, &rdev->qplib_res, 1119 &qp->qplib_qp); 1120 if (!rdev->sqp_ah) { 1121 bnxt_qplib_destroy_qp(&rdev->qplib_res, 1122 &rdev->qp1_sqp->qplib_qp); 1123 rc = -EINVAL; 1124 dev_err(rdev_to_dev(rdev), 1125 "Failed to create AH entry for ShadowQP"); 1126 goto qp_destroy; 1127 } 1128 1129 } else { 1130 /* Allocate 128 + 1 more than what's provided */ 1131 entries = roundup_pow_of_two(qp_init_attr->cap.max_send_wr + 1132 BNXT_QPLIB_RESERVED_QP_WRS + 1); 1133 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1134 dev_attr->max_qp_wqes + 1135 BNXT_QPLIB_RESERVED_QP_WRS + 1); 1136 qp->qplib_qp.sq.q_full_delta = BNXT_QPLIB_RESERVED_QP_WRS + 1; 1137 1138 /* 1139 * Reserving one slot for Phantom WQE. Application can 1140 * post one extra entry in this case. But allowing this to avoid 1141 * unexpected Queue full condition 1142 */ 1143 1144 qp->qplib_qp.sq.q_full_delta -= 1; 1145 1146 qp->qplib_qp.max_rd_atomic = dev_attr->max_qp_rd_atom; 1147 qp->qplib_qp.max_dest_rd_atomic = dev_attr->max_qp_init_rd_atom; 1148 if (udata) { 1149 rc = bnxt_re_init_user_qp(rdev, pd, qp, udata); 1150 if (rc) 1151 goto fail; 1152 } else { 1153 qp->qplib_qp.dpi = &rdev->dpi_privileged; 1154 } 1155 1156 rc = bnxt_qplib_create_qp(&rdev->qplib_res, &qp->qplib_qp); 1157 if (rc) { 1158 dev_err(rdev_to_dev(rdev), "Failed to create HW QP"); 1159 goto free_umem; 1160 } 1161 } 1162 1163 qp->ib_qp.qp_num = qp->qplib_qp.id; 1164 spin_lock_init(&qp->sq_lock); 1165 spin_lock_init(&qp->rq_lock); 1166 1167 if (udata) { 1168 struct bnxt_re_qp_resp resp; 1169 1170 resp.qpid = qp->ib_qp.qp_num; 1171 resp.rsvd = 0; 1172 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1173 if (rc) { 1174 dev_err(rdev_to_dev(rdev), "Failed to copy QP udata"); 1175 goto qp_destroy; 1176 } 1177 } 1178 INIT_LIST_HEAD(&qp->list); 1179 mutex_lock(&rdev->qp_lock); 1180 list_add_tail(&qp->list, &rdev->qp_list); 1181 atomic_inc(&rdev->qp_count); 1182 mutex_unlock(&rdev->qp_lock); 1183 1184 return &qp->ib_qp; 1185 qp_destroy: 1186 bnxt_qplib_destroy_qp(&rdev->qplib_res, &qp->qplib_qp); 1187 free_umem: 1188 ib_umem_release(qp->rumem); 1189 ib_umem_release(qp->sumem); 1190 fail: 1191 kfree(qp); 1192 return ERR_PTR(rc); 1193 } 1194 1195 static u8 __from_ib_qp_state(enum ib_qp_state state) 1196 { 1197 switch (state) { 1198 case IB_QPS_RESET: 1199 return CMDQ_MODIFY_QP_NEW_STATE_RESET; 1200 case IB_QPS_INIT: 1201 return CMDQ_MODIFY_QP_NEW_STATE_INIT; 1202 case IB_QPS_RTR: 1203 return CMDQ_MODIFY_QP_NEW_STATE_RTR; 1204 case IB_QPS_RTS: 1205 return CMDQ_MODIFY_QP_NEW_STATE_RTS; 1206 case IB_QPS_SQD: 1207 return CMDQ_MODIFY_QP_NEW_STATE_SQD; 1208 case IB_QPS_SQE: 1209 return CMDQ_MODIFY_QP_NEW_STATE_SQE; 1210 case IB_QPS_ERR: 1211 default: 1212 return CMDQ_MODIFY_QP_NEW_STATE_ERR; 1213 } 1214 } 1215 1216 static enum ib_qp_state __to_ib_qp_state(u8 state) 1217 { 1218 switch (state) { 1219 case CMDQ_MODIFY_QP_NEW_STATE_RESET: 1220 return IB_QPS_RESET; 1221 case CMDQ_MODIFY_QP_NEW_STATE_INIT: 1222 return IB_QPS_INIT; 1223 case CMDQ_MODIFY_QP_NEW_STATE_RTR: 1224 return IB_QPS_RTR; 1225 case CMDQ_MODIFY_QP_NEW_STATE_RTS: 1226 return IB_QPS_RTS; 1227 case CMDQ_MODIFY_QP_NEW_STATE_SQD: 1228 return IB_QPS_SQD; 1229 case CMDQ_MODIFY_QP_NEW_STATE_SQE: 1230 return IB_QPS_SQE; 1231 case CMDQ_MODIFY_QP_NEW_STATE_ERR: 1232 default: 1233 return IB_QPS_ERR; 1234 } 1235 } 1236 1237 static u32 __from_ib_mtu(enum ib_mtu mtu) 1238 { 1239 switch (mtu) { 1240 case IB_MTU_256: 1241 return CMDQ_MODIFY_QP_PATH_MTU_MTU_256; 1242 case IB_MTU_512: 1243 return CMDQ_MODIFY_QP_PATH_MTU_MTU_512; 1244 case IB_MTU_1024: 1245 return CMDQ_MODIFY_QP_PATH_MTU_MTU_1024; 1246 case IB_MTU_2048: 1247 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1248 case IB_MTU_4096: 1249 return CMDQ_MODIFY_QP_PATH_MTU_MTU_4096; 1250 default: 1251 return CMDQ_MODIFY_QP_PATH_MTU_MTU_2048; 1252 } 1253 } 1254 1255 static enum ib_mtu __to_ib_mtu(u32 mtu) 1256 { 1257 switch (mtu & CREQ_QUERY_QP_RESP_SB_PATH_MTU_MASK) { 1258 case CMDQ_MODIFY_QP_PATH_MTU_MTU_256: 1259 return IB_MTU_256; 1260 case CMDQ_MODIFY_QP_PATH_MTU_MTU_512: 1261 return IB_MTU_512; 1262 case CMDQ_MODIFY_QP_PATH_MTU_MTU_1024: 1263 return IB_MTU_1024; 1264 case CMDQ_MODIFY_QP_PATH_MTU_MTU_2048: 1265 return IB_MTU_2048; 1266 case CMDQ_MODIFY_QP_PATH_MTU_MTU_4096: 1267 return IB_MTU_4096; 1268 default: 1269 return IB_MTU_2048; 1270 } 1271 } 1272 1273 /* Shared Receive Queues */ 1274 void bnxt_re_destroy_srq(struct ib_srq *ib_srq, struct ib_udata *udata) 1275 { 1276 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1277 ib_srq); 1278 struct bnxt_re_dev *rdev = srq->rdev; 1279 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1280 struct bnxt_qplib_nq *nq = NULL; 1281 1282 if (qplib_srq->cq) 1283 nq = qplib_srq->cq->nq; 1284 bnxt_qplib_destroy_srq(&rdev->qplib_res, qplib_srq); 1285 ib_umem_release(srq->umem); 1286 atomic_dec(&rdev->srq_count); 1287 if (nq) 1288 nq->budget--; 1289 } 1290 1291 static int bnxt_re_init_user_srq(struct bnxt_re_dev *rdev, 1292 struct bnxt_re_pd *pd, 1293 struct bnxt_re_srq *srq, 1294 struct ib_udata *udata) 1295 { 1296 struct bnxt_re_srq_req ureq; 1297 struct bnxt_qplib_srq *qplib_srq = &srq->qplib_srq; 1298 struct ib_umem *umem; 1299 int bytes = 0; 1300 struct bnxt_re_ucontext *cntx = rdma_udata_to_drv_context( 1301 udata, struct bnxt_re_ucontext, ib_uctx); 1302 1303 if (ib_copy_from_udata(&ureq, udata, sizeof(ureq))) 1304 return -EFAULT; 1305 1306 bytes = (qplib_srq->max_wqe * BNXT_QPLIB_MAX_RQE_ENTRY_SIZE); 1307 bytes = PAGE_ALIGN(bytes); 1308 umem = ib_umem_get(&rdev->ibdev, ureq.srqva, bytes, 1309 IB_ACCESS_LOCAL_WRITE); 1310 if (IS_ERR(umem)) 1311 return PTR_ERR(umem); 1312 1313 srq->umem = umem; 1314 qplib_srq->sg_info.sglist = umem->sg_head.sgl; 1315 qplib_srq->sg_info.npages = ib_umem_num_pages(umem); 1316 qplib_srq->sg_info.nmap = umem->nmap; 1317 qplib_srq->srq_handle = ureq.srq_handle; 1318 qplib_srq->dpi = &cntx->dpi; 1319 1320 return 0; 1321 } 1322 1323 int bnxt_re_create_srq(struct ib_srq *ib_srq, 1324 struct ib_srq_init_attr *srq_init_attr, 1325 struct ib_udata *udata) 1326 { 1327 struct ib_pd *ib_pd = ib_srq->pd; 1328 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 1329 struct bnxt_re_dev *rdev = pd->rdev; 1330 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1331 struct bnxt_re_srq *srq = 1332 container_of(ib_srq, struct bnxt_re_srq, ib_srq); 1333 struct bnxt_qplib_nq *nq = NULL; 1334 int rc, entries; 1335 1336 if (srq_init_attr->attr.max_wr >= dev_attr->max_srq_wqes) { 1337 dev_err(rdev_to_dev(rdev), "Create CQ failed - max exceeded"); 1338 rc = -EINVAL; 1339 goto exit; 1340 } 1341 1342 if (srq_init_attr->srq_type != IB_SRQT_BASIC) { 1343 rc = -EOPNOTSUPP; 1344 goto exit; 1345 } 1346 1347 srq->rdev = rdev; 1348 srq->qplib_srq.pd = &pd->qplib_pd; 1349 srq->qplib_srq.dpi = &rdev->dpi_privileged; 1350 /* Allocate 1 more than what's provided so posting max doesn't 1351 * mean empty 1352 */ 1353 entries = roundup_pow_of_two(srq_init_attr->attr.max_wr + 1); 1354 if (entries > dev_attr->max_srq_wqes + 1) 1355 entries = dev_attr->max_srq_wqes + 1; 1356 1357 srq->qplib_srq.max_wqe = entries; 1358 srq->qplib_srq.max_sge = srq_init_attr->attr.max_sge; 1359 srq->qplib_srq.threshold = srq_init_attr->attr.srq_limit; 1360 srq->srq_limit = srq_init_attr->attr.srq_limit; 1361 srq->qplib_srq.eventq_hw_ring_id = rdev->nq[0].ring_id; 1362 nq = &rdev->nq[0]; 1363 1364 if (udata) { 1365 rc = bnxt_re_init_user_srq(rdev, pd, srq, udata); 1366 if (rc) 1367 goto fail; 1368 } 1369 1370 rc = bnxt_qplib_create_srq(&rdev->qplib_res, &srq->qplib_srq); 1371 if (rc) { 1372 dev_err(rdev_to_dev(rdev), "Create HW SRQ failed!"); 1373 goto fail; 1374 } 1375 1376 if (udata) { 1377 struct bnxt_re_srq_resp resp; 1378 1379 resp.srqid = srq->qplib_srq.id; 1380 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 1381 if (rc) { 1382 dev_err(rdev_to_dev(rdev), "SRQ copy to udata failed!"); 1383 bnxt_qplib_destroy_srq(&rdev->qplib_res, 1384 &srq->qplib_srq); 1385 goto fail; 1386 } 1387 } 1388 if (nq) 1389 nq->budget++; 1390 atomic_inc(&rdev->srq_count); 1391 1392 return 0; 1393 1394 fail: 1395 ib_umem_release(srq->umem); 1396 exit: 1397 return rc; 1398 } 1399 1400 int bnxt_re_modify_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr, 1401 enum ib_srq_attr_mask srq_attr_mask, 1402 struct ib_udata *udata) 1403 { 1404 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1405 ib_srq); 1406 struct bnxt_re_dev *rdev = srq->rdev; 1407 int rc; 1408 1409 switch (srq_attr_mask) { 1410 case IB_SRQ_MAX_WR: 1411 /* SRQ resize is not supported */ 1412 break; 1413 case IB_SRQ_LIMIT: 1414 /* Change the SRQ threshold */ 1415 if (srq_attr->srq_limit > srq->qplib_srq.max_wqe) 1416 return -EINVAL; 1417 1418 srq->qplib_srq.threshold = srq_attr->srq_limit; 1419 rc = bnxt_qplib_modify_srq(&rdev->qplib_res, &srq->qplib_srq); 1420 if (rc) { 1421 dev_err(rdev_to_dev(rdev), "Modify HW SRQ failed!"); 1422 return rc; 1423 } 1424 /* On success, update the shadow */ 1425 srq->srq_limit = srq_attr->srq_limit; 1426 /* No need to Build and send response back to udata */ 1427 break; 1428 default: 1429 dev_err(rdev_to_dev(rdev), 1430 "Unsupported srq_attr_mask 0x%x", srq_attr_mask); 1431 return -EINVAL; 1432 } 1433 return 0; 1434 } 1435 1436 int bnxt_re_query_srq(struct ib_srq *ib_srq, struct ib_srq_attr *srq_attr) 1437 { 1438 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1439 ib_srq); 1440 struct bnxt_re_srq tsrq; 1441 struct bnxt_re_dev *rdev = srq->rdev; 1442 int rc; 1443 1444 /* Get live SRQ attr */ 1445 tsrq.qplib_srq.id = srq->qplib_srq.id; 1446 rc = bnxt_qplib_query_srq(&rdev->qplib_res, &tsrq.qplib_srq); 1447 if (rc) { 1448 dev_err(rdev_to_dev(rdev), "Query HW SRQ failed!"); 1449 return rc; 1450 } 1451 srq_attr->max_wr = srq->qplib_srq.max_wqe; 1452 srq_attr->max_sge = srq->qplib_srq.max_sge; 1453 srq_attr->srq_limit = tsrq.qplib_srq.threshold; 1454 1455 return 0; 1456 } 1457 1458 int bnxt_re_post_srq_recv(struct ib_srq *ib_srq, const struct ib_recv_wr *wr, 1459 const struct ib_recv_wr **bad_wr) 1460 { 1461 struct bnxt_re_srq *srq = container_of(ib_srq, struct bnxt_re_srq, 1462 ib_srq); 1463 struct bnxt_qplib_swqe wqe; 1464 unsigned long flags; 1465 int rc = 0; 1466 1467 spin_lock_irqsave(&srq->lock, flags); 1468 while (wr) { 1469 /* Transcribe each ib_recv_wr to qplib_swqe */ 1470 wqe.num_sge = wr->num_sge; 1471 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 1472 wqe.wr_id = wr->wr_id; 1473 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 1474 1475 rc = bnxt_qplib_post_srq_recv(&srq->qplib_srq, &wqe); 1476 if (rc) { 1477 *bad_wr = wr; 1478 break; 1479 } 1480 wr = wr->next; 1481 } 1482 spin_unlock_irqrestore(&srq->lock, flags); 1483 1484 return rc; 1485 } 1486 static int bnxt_re_modify_shadow_qp(struct bnxt_re_dev *rdev, 1487 struct bnxt_re_qp *qp1_qp, 1488 int qp_attr_mask) 1489 { 1490 struct bnxt_re_qp *qp = rdev->qp1_sqp; 1491 int rc = 0; 1492 1493 if (qp_attr_mask & IB_QP_STATE) { 1494 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1495 qp->qplib_qp.state = qp1_qp->qplib_qp.state; 1496 } 1497 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1498 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1499 qp->qplib_qp.pkey_index = qp1_qp->qplib_qp.pkey_index; 1500 } 1501 1502 if (qp_attr_mask & IB_QP_QKEY) { 1503 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1504 /* Using a Random QKEY */ 1505 qp->qplib_qp.qkey = 0x81818181; 1506 } 1507 if (qp_attr_mask & IB_QP_SQ_PSN) { 1508 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1509 qp->qplib_qp.sq.psn = qp1_qp->qplib_qp.sq.psn; 1510 } 1511 1512 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1513 if (rc) 1514 dev_err(rdev_to_dev(rdev), 1515 "Failed to modify Shadow QP for QP1"); 1516 return rc; 1517 } 1518 1519 int bnxt_re_modify_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1520 int qp_attr_mask, struct ib_udata *udata) 1521 { 1522 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1523 struct bnxt_re_dev *rdev = qp->rdev; 1524 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 1525 enum ib_qp_state curr_qp_state, new_qp_state; 1526 int rc, entries; 1527 unsigned int flags; 1528 u8 nw_type; 1529 1530 qp->qplib_qp.modify_flags = 0; 1531 if (qp_attr_mask & IB_QP_STATE) { 1532 curr_qp_state = __to_ib_qp_state(qp->qplib_qp.cur_qp_state); 1533 new_qp_state = qp_attr->qp_state; 1534 if (!ib_modify_qp_is_ok(curr_qp_state, new_qp_state, 1535 ib_qp->qp_type, qp_attr_mask)) { 1536 dev_err(rdev_to_dev(rdev), 1537 "Invalid attribute mask: %#x specified ", 1538 qp_attr_mask); 1539 dev_err(rdev_to_dev(rdev), 1540 "for qpn: %#x type: %#x", 1541 ib_qp->qp_num, ib_qp->qp_type); 1542 dev_err(rdev_to_dev(rdev), 1543 "curr_qp_state=0x%x, new_qp_state=0x%x\n", 1544 curr_qp_state, new_qp_state); 1545 return -EINVAL; 1546 } 1547 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_STATE; 1548 qp->qplib_qp.state = __from_ib_qp_state(qp_attr->qp_state); 1549 1550 if (!qp->sumem && 1551 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_ERR) { 1552 dev_dbg(rdev_to_dev(rdev), 1553 "Move QP = %p to flush list\n", 1554 qp); 1555 flags = bnxt_re_lock_cqs(qp); 1556 bnxt_qplib_add_flush_qp(&qp->qplib_qp); 1557 bnxt_re_unlock_cqs(qp, flags); 1558 } 1559 if (!qp->sumem && 1560 qp->qplib_qp.state == CMDQ_MODIFY_QP_NEW_STATE_RESET) { 1561 dev_dbg(rdev_to_dev(rdev), 1562 "Move QP = %p out of flush list\n", 1563 qp); 1564 flags = bnxt_re_lock_cqs(qp); 1565 bnxt_qplib_clean_qp(&qp->qplib_qp); 1566 bnxt_re_unlock_cqs(qp, flags); 1567 } 1568 } 1569 if (qp_attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) { 1570 qp->qplib_qp.modify_flags |= 1571 CMDQ_MODIFY_QP_MODIFY_MASK_EN_SQD_ASYNC_NOTIFY; 1572 qp->qplib_qp.en_sqd_async_notify = true; 1573 } 1574 if (qp_attr_mask & IB_QP_ACCESS_FLAGS) { 1575 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_ACCESS; 1576 qp->qplib_qp.access = 1577 __from_ib_access_flags(qp_attr->qp_access_flags); 1578 /* LOCAL_WRITE access must be set to allow RC receive */ 1579 qp->qplib_qp.access |= BNXT_QPLIB_ACCESS_LOCAL_WRITE; 1580 /* Temp: Set all params on QP as of now */ 1581 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_WRITE; 1582 qp->qplib_qp.access |= CMDQ_MODIFY_QP_ACCESS_REMOTE_READ; 1583 } 1584 if (qp_attr_mask & IB_QP_PKEY_INDEX) { 1585 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_PKEY; 1586 qp->qplib_qp.pkey_index = qp_attr->pkey_index; 1587 } 1588 if (qp_attr_mask & IB_QP_QKEY) { 1589 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_QKEY; 1590 qp->qplib_qp.qkey = qp_attr->qkey; 1591 } 1592 if (qp_attr_mask & IB_QP_AV) { 1593 const struct ib_global_route *grh = 1594 rdma_ah_read_grh(&qp_attr->ah_attr); 1595 const struct ib_gid_attr *sgid_attr; 1596 1597 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_DGID | 1598 CMDQ_MODIFY_QP_MODIFY_MASK_FLOW_LABEL | 1599 CMDQ_MODIFY_QP_MODIFY_MASK_SGID_INDEX | 1600 CMDQ_MODIFY_QP_MODIFY_MASK_HOP_LIMIT | 1601 CMDQ_MODIFY_QP_MODIFY_MASK_TRAFFIC_CLASS | 1602 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_MAC | 1603 CMDQ_MODIFY_QP_MODIFY_MASK_VLAN_ID; 1604 memcpy(qp->qplib_qp.ah.dgid.data, grh->dgid.raw, 1605 sizeof(qp->qplib_qp.ah.dgid.data)); 1606 qp->qplib_qp.ah.flow_label = grh->flow_label; 1607 /* If RoCE V2 is enabled, stack will have two entries for 1608 * each GID entry. Avoiding this duplicte entry in HW. Dividing 1609 * the GID index by 2 for RoCE V2 1610 */ 1611 qp->qplib_qp.ah.sgid_index = grh->sgid_index / 2; 1612 qp->qplib_qp.ah.host_sgid_index = grh->sgid_index; 1613 qp->qplib_qp.ah.hop_limit = grh->hop_limit; 1614 qp->qplib_qp.ah.traffic_class = grh->traffic_class; 1615 qp->qplib_qp.ah.sl = rdma_ah_get_sl(&qp_attr->ah_attr); 1616 ether_addr_copy(qp->qplib_qp.ah.dmac, 1617 qp_attr->ah_attr.roce.dmac); 1618 1619 sgid_attr = qp_attr->ah_attr.grh.sgid_attr; 1620 rc = rdma_read_gid_l2_fields(sgid_attr, NULL, 1621 &qp->qplib_qp.smac[0]); 1622 if (rc) 1623 return rc; 1624 1625 nw_type = rdma_gid_attr_network_type(sgid_attr); 1626 switch (nw_type) { 1627 case RDMA_NETWORK_IPV4: 1628 qp->qplib_qp.nw_type = 1629 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV4; 1630 break; 1631 case RDMA_NETWORK_IPV6: 1632 qp->qplib_qp.nw_type = 1633 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV2_IPV6; 1634 break; 1635 default: 1636 qp->qplib_qp.nw_type = 1637 CMDQ_MODIFY_QP_NETWORK_TYPE_ROCEV1; 1638 break; 1639 } 1640 } 1641 1642 if (qp_attr_mask & IB_QP_PATH_MTU) { 1643 qp->qplib_qp.modify_flags |= 1644 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1645 qp->qplib_qp.path_mtu = __from_ib_mtu(qp_attr->path_mtu); 1646 qp->qplib_qp.mtu = ib_mtu_enum_to_int(qp_attr->path_mtu); 1647 } else if (qp_attr->qp_state == IB_QPS_RTR) { 1648 qp->qplib_qp.modify_flags |= 1649 CMDQ_MODIFY_QP_MODIFY_MASK_PATH_MTU; 1650 qp->qplib_qp.path_mtu = 1651 __from_ib_mtu(iboe_get_mtu(rdev->netdev->mtu)); 1652 qp->qplib_qp.mtu = 1653 ib_mtu_enum_to_int(iboe_get_mtu(rdev->netdev->mtu)); 1654 } 1655 1656 if (qp_attr_mask & IB_QP_TIMEOUT) { 1657 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_TIMEOUT; 1658 qp->qplib_qp.timeout = qp_attr->timeout; 1659 } 1660 if (qp_attr_mask & IB_QP_RETRY_CNT) { 1661 qp->qplib_qp.modify_flags |= 1662 CMDQ_MODIFY_QP_MODIFY_MASK_RETRY_CNT; 1663 qp->qplib_qp.retry_cnt = qp_attr->retry_cnt; 1664 } 1665 if (qp_attr_mask & IB_QP_RNR_RETRY) { 1666 qp->qplib_qp.modify_flags |= 1667 CMDQ_MODIFY_QP_MODIFY_MASK_RNR_RETRY; 1668 qp->qplib_qp.rnr_retry = qp_attr->rnr_retry; 1669 } 1670 if (qp_attr_mask & IB_QP_MIN_RNR_TIMER) { 1671 qp->qplib_qp.modify_flags |= 1672 CMDQ_MODIFY_QP_MODIFY_MASK_MIN_RNR_TIMER; 1673 qp->qplib_qp.min_rnr_timer = qp_attr->min_rnr_timer; 1674 } 1675 if (qp_attr_mask & IB_QP_RQ_PSN) { 1676 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_RQ_PSN; 1677 qp->qplib_qp.rq.psn = qp_attr->rq_psn; 1678 } 1679 if (qp_attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { 1680 qp->qplib_qp.modify_flags |= 1681 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_RD_ATOMIC; 1682 /* Cap the max_rd_atomic to device max */ 1683 qp->qplib_qp.max_rd_atomic = min_t(u32, qp_attr->max_rd_atomic, 1684 dev_attr->max_qp_rd_atom); 1685 } 1686 if (qp_attr_mask & IB_QP_SQ_PSN) { 1687 qp->qplib_qp.modify_flags |= CMDQ_MODIFY_QP_MODIFY_MASK_SQ_PSN; 1688 qp->qplib_qp.sq.psn = qp_attr->sq_psn; 1689 } 1690 if (qp_attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { 1691 if (qp_attr->max_dest_rd_atomic > 1692 dev_attr->max_qp_init_rd_atom) { 1693 dev_err(rdev_to_dev(rdev), 1694 "max_dest_rd_atomic requested%d is > dev_max%d", 1695 qp_attr->max_dest_rd_atomic, 1696 dev_attr->max_qp_init_rd_atom); 1697 return -EINVAL; 1698 } 1699 1700 qp->qplib_qp.modify_flags |= 1701 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_DEST_RD_ATOMIC; 1702 qp->qplib_qp.max_dest_rd_atomic = qp_attr->max_dest_rd_atomic; 1703 } 1704 if (qp_attr_mask & IB_QP_CAP) { 1705 qp->qplib_qp.modify_flags |= 1706 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SIZE | 1707 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SIZE | 1708 CMDQ_MODIFY_QP_MODIFY_MASK_SQ_SGE | 1709 CMDQ_MODIFY_QP_MODIFY_MASK_RQ_SGE | 1710 CMDQ_MODIFY_QP_MODIFY_MASK_MAX_INLINE_DATA; 1711 if ((qp_attr->cap.max_send_wr >= dev_attr->max_qp_wqes) || 1712 (qp_attr->cap.max_recv_wr >= dev_attr->max_qp_wqes) || 1713 (qp_attr->cap.max_send_sge >= dev_attr->max_qp_sges) || 1714 (qp_attr->cap.max_recv_sge >= dev_attr->max_qp_sges) || 1715 (qp_attr->cap.max_inline_data >= 1716 dev_attr->max_inline_data)) { 1717 dev_err(rdev_to_dev(rdev), 1718 "Create QP failed - max exceeded"); 1719 return -EINVAL; 1720 } 1721 entries = roundup_pow_of_two(qp_attr->cap.max_send_wr); 1722 qp->qplib_qp.sq.max_wqe = min_t(u32, entries, 1723 dev_attr->max_qp_wqes + 1); 1724 qp->qplib_qp.sq.q_full_delta = qp->qplib_qp.sq.max_wqe - 1725 qp_attr->cap.max_send_wr; 1726 /* 1727 * Reserving one slot for Phantom WQE. Some application can 1728 * post one extra entry in this case. Allowing this to avoid 1729 * unexpected Queue full condition 1730 */ 1731 qp->qplib_qp.sq.q_full_delta -= 1; 1732 qp->qplib_qp.sq.max_sge = qp_attr->cap.max_send_sge; 1733 if (qp->qplib_qp.rq.max_wqe) { 1734 entries = roundup_pow_of_two(qp_attr->cap.max_recv_wr); 1735 qp->qplib_qp.rq.max_wqe = 1736 min_t(u32, entries, dev_attr->max_qp_wqes + 1); 1737 qp->qplib_qp.rq.q_full_delta = qp->qplib_qp.rq.max_wqe - 1738 qp_attr->cap.max_recv_wr; 1739 qp->qplib_qp.rq.max_sge = qp_attr->cap.max_recv_sge; 1740 } else { 1741 /* SRQ was used prior, just ignore the RQ caps */ 1742 } 1743 } 1744 if (qp_attr_mask & IB_QP_DEST_QPN) { 1745 qp->qplib_qp.modify_flags |= 1746 CMDQ_MODIFY_QP_MODIFY_MASK_DEST_QP_ID; 1747 qp->qplib_qp.dest_qpn = qp_attr->dest_qp_num; 1748 } 1749 rc = bnxt_qplib_modify_qp(&rdev->qplib_res, &qp->qplib_qp); 1750 if (rc) { 1751 dev_err(rdev_to_dev(rdev), "Failed to modify HW QP"); 1752 return rc; 1753 } 1754 if (ib_qp->qp_type == IB_QPT_GSI && rdev->qp1_sqp) 1755 rc = bnxt_re_modify_shadow_qp(rdev, qp, qp_attr_mask); 1756 return rc; 1757 } 1758 1759 int bnxt_re_query_qp(struct ib_qp *ib_qp, struct ib_qp_attr *qp_attr, 1760 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr) 1761 { 1762 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 1763 struct bnxt_re_dev *rdev = qp->rdev; 1764 struct bnxt_qplib_qp *qplib_qp; 1765 int rc; 1766 1767 qplib_qp = kzalloc(sizeof(*qplib_qp), GFP_KERNEL); 1768 if (!qplib_qp) 1769 return -ENOMEM; 1770 1771 qplib_qp->id = qp->qplib_qp.id; 1772 qplib_qp->ah.host_sgid_index = qp->qplib_qp.ah.host_sgid_index; 1773 1774 rc = bnxt_qplib_query_qp(&rdev->qplib_res, qplib_qp); 1775 if (rc) { 1776 dev_err(rdev_to_dev(rdev), "Failed to query HW QP"); 1777 goto out; 1778 } 1779 qp_attr->qp_state = __to_ib_qp_state(qplib_qp->state); 1780 qp_attr->en_sqd_async_notify = qplib_qp->en_sqd_async_notify ? 1 : 0; 1781 qp_attr->qp_access_flags = __to_ib_access_flags(qplib_qp->access); 1782 qp_attr->pkey_index = qplib_qp->pkey_index; 1783 qp_attr->qkey = qplib_qp->qkey; 1784 qp_attr->ah_attr.type = RDMA_AH_ATTR_TYPE_ROCE; 1785 rdma_ah_set_grh(&qp_attr->ah_attr, NULL, qplib_qp->ah.flow_label, 1786 qplib_qp->ah.host_sgid_index, 1787 qplib_qp->ah.hop_limit, 1788 qplib_qp->ah.traffic_class); 1789 rdma_ah_set_dgid_raw(&qp_attr->ah_attr, qplib_qp->ah.dgid.data); 1790 rdma_ah_set_sl(&qp_attr->ah_attr, qplib_qp->ah.sl); 1791 ether_addr_copy(qp_attr->ah_attr.roce.dmac, qplib_qp->ah.dmac); 1792 qp_attr->path_mtu = __to_ib_mtu(qplib_qp->path_mtu); 1793 qp_attr->timeout = qplib_qp->timeout; 1794 qp_attr->retry_cnt = qplib_qp->retry_cnt; 1795 qp_attr->rnr_retry = qplib_qp->rnr_retry; 1796 qp_attr->min_rnr_timer = qplib_qp->min_rnr_timer; 1797 qp_attr->rq_psn = qplib_qp->rq.psn; 1798 qp_attr->max_rd_atomic = qplib_qp->max_rd_atomic; 1799 qp_attr->sq_psn = qplib_qp->sq.psn; 1800 qp_attr->max_dest_rd_atomic = qplib_qp->max_dest_rd_atomic; 1801 qp_init_attr->sq_sig_type = qplib_qp->sig_type ? IB_SIGNAL_ALL_WR : 1802 IB_SIGNAL_REQ_WR; 1803 qp_attr->dest_qp_num = qplib_qp->dest_qpn; 1804 1805 qp_attr->cap.max_send_wr = qp->qplib_qp.sq.max_wqe; 1806 qp_attr->cap.max_send_sge = qp->qplib_qp.sq.max_sge; 1807 qp_attr->cap.max_recv_wr = qp->qplib_qp.rq.max_wqe; 1808 qp_attr->cap.max_recv_sge = qp->qplib_qp.rq.max_sge; 1809 qp_attr->cap.max_inline_data = qp->qplib_qp.max_inline_data; 1810 qp_init_attr->cap = qp_attr->cap; 1811 1812 out: 1813 kfree(qplib_qp); 1814 return rc; 1815 } 1816 1817 /* Routine for sending QP1 packets for RoCE V1 an V2 1818 */ 1819 static int bnxt_re_build_qp1_send_v2(struct bnxt_re_qp *qp, 1820 const struct ib_send_wr *wr, 1821 struct bnxt_qplib_swqe *wqe, 1822 int payload_size) 1823 { 1824 struct bnxt_re_ah *ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, 1825 ib_ah); 1826 struct bnxt_qplib_ah *qplib_ah = &ah->qplib_ah; 1827 const struct ib_gid_attr *sgid_attr = ah->ib_ah.sgid_attr; 1828 struct bnxt_qplib_sge sge; 1829 u8 nw_type; 1830 u16 ether_type; 1831 union ib_gid dgid; 1832 bool is_eth = false; 1833 bool is_vlan = false; 1834 bool is_grh = false; 1835 bool is_udp = false; 1836 u8 ip_version = 0; 1837 u16 vlan_id = 0xFFFF; 1838 void *buf; 1839 int i, rc = 0; 1840 1841 memset(&qp->qp1_hdr, 0, sizeof(qp->qp1_hdr)); 1842 1843 rc = rdma_read_gid_l2_fields(sgid_attr, &vlan_id, NULL); 1844 if (rc) 1845 return rc; 1846 1847 /* Get network header type for this GID */ 1848 nw_type = rdma_gid_attr_network_type(sgid_attr); 1849 switch (nw_type) { 1850 case RDMA_NETWORK_IPV4: 1851 nw_type = BNXT_RE_ROCEV2_IPV4_PACKET; 1852 break; 1853 case RDMA_NETWORK_IPV6: 1854 nw_type = BNXT_RE_ROCEV2_IPV6_PACKET; 1855 break; 1856 default: 1857 nw_type = BNXT_RE_ROCE_V1_PACKET; 1858 break; 1859 } 1860 memcpy(&dgid.raw, &qplib_ah->dgid, 16); 1861 is_udp = sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP; 1862 if (is_udp) { 1863 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid_attr->gid)) { 1864 ip_version = 4; 1865 ether_type = ETH_P_IP; 1866 } else { 1867 ip_version = 6; 1868 ether_type = ETH_P_IPV6; 1869 } 1870 is_grh = false; 1871 } else { 1872 ether_type = ETH_P_IBOE; 1873 is_grh = true; 1874 } 1875 1876 is_eth = true; 1877 is_vlan = (vlan_id && (vlan_id < 0x1000)) ? true : false; 1878 1879 ib_ud_header_init(payload_size, !is_eth, is_eth, is_vlan, is_grh, 1880 ip_version, is_udp, 0, &qp->qp1_hdr); 1881 1882 /* ETH */ 1883 ether_addr_copy(qp->qp1_hdr.eth.dmac_h, ah->qplib_ah.dmac); 1884 ether_addr_copy(qp->qp1_hdr.eth.smac_h, qp->qplib_qp.smac); 1885 1886 /* For vlan, check the sgid for vlan existence */ 1887 1888 if (!is_vlan) { 1889 qp->qp1_hdr.eth.type = cpu_to_be16(ether_type); 1890 } else { 1891 qp->qp1_hdr.vlan.type = cpu_to_be16(ether_type); 1892 qp->qp1_hdr.vlan.tag = cpu_to_be16(vlan_id); 1893 } 1894 1895 if (is_grh || (ip_version == 6)) { 1896 memcpy(qp->qp1_hdr.grh.source_gid.raw, sgid_attr->gid.raw, 1897 sizeof(sgid_attr->gid)); 1898 memcpy(qp->qp1_hdr.grh.destination_gid.raw, qplib_ah->dgid.data, 1899 sizeof(sgid_attr->gid)); 1900 qp->qp1_hdr.grh.hop_limit = qplib_ah->hop_limit; 1901 } 1902 1903 if (ip_version == 4) { 1904 qp->qp1_hdr.ip4.tos = 0; 1905 qp->qp1_hdr.ip4.id = 0; 1906 qp->qp1_hdr.ip4.frag_off = htons(IP_DF); 1907 qp->qp1_hdr.ip4.ttl = qplib_ah->hop_limit; 1908 1909 memcpy(&qp->qp1_hdr.ip4.saddr, sgid_attr->gid.raw + 12, 4); 1910 memcpy(&qp->qp1_hdr.ip4.daddr, qplib_ah->dgid.data + 12, 4); 1911 qp->qp1_hdr.ip4.check = ib_ud_ip4_csum(&qp->qp1_hdr); 1912 } 1913 1914 if (is_udp) { 1915 qp->qp1_hdr.udp.dport = htons(ROCE_V2_UDP_DPORT); 1916 qp->qp1_hdr.udp.sport = htons(0x8CD1); 1917 qp->qp1_hdr.udp.csum = 0; 1918 } 1919 1920 /* BTH */ 1921 if (wr->opcode == IB_WR_SEND_WITH_IMM) { 1922 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE; 1923 qp->qp1_hdr.immediate_present = 1; 1924 } else { 1925 qp->qp1_hdr.bth.opcode = IB_OPCODE_UD_SEND_ONLY; 1926 } 1927 if (wr->send_flags & IB_SEND_SOLICITED) 1928 qp->qp1_hdr.bth.solicited_event = 1; 1929 /* pad_count */ 1930 qp->qp1_hdr.bth.pad_count = (4 - payload_size) & 3; 1931 1932 /* P_key for QP1 is for all members */ 1933 qp->qp1_hdr.bth.pkey = cpu_to_be16(0xFFFF); 1934 qp->qp1_hdr.bth.destination_qpn = IB_QP1; 1935 qp->qp1_hdr.bth.ack_req = 0; 1936 qp->send_psn++; 1937 qp->send_psn &= BTH_PSN_MASK; 1938 qp->qp1_hdr.bth.psn = cpu_to_be32(qp->send_psn); 1939 /* DETH */ 1940 /* Use the priviledged Q_Key for QP1 */ 1941 qp->qp1_hdr.deth.qkey = cpu_to_be32(IB_QP1_QKEY); 1942 qp->qp1_hdr.deth.source_qpn = IB_QP1; 1943 1944 /* Pack the QP1 to the transmit buffer */ 1945 buf = bnxt_qplib_get_qp1_sq_buf(&qp->qplib_qp, &sge); 1946 if (buf) { 1947 ib_ud_header_pack(&qp->qp1_hdr, buf); 1948 for (i = wqe->num_sge; i; i--) { 1949 wqe->sg_list[i].addr = wqe->sg_list[i - 1].addr; 1950 wqe->sg_list[i].lkey = wqe->sg_list[i - 1].lkey; 1951 wqe->sg_list[i].size = wqe->sg_list[i - 1].size; 1952 } 1953 1954 /* 1955 * Max Header buf size for IPV6 RoCE V2 is 86, 1956 * which is same as the QP1 SQ header buffer. 1957 * Header buf size for IPV4 RoCE V2 can be 66. 1958 * ETH(14) + VLAN(4)+ IP(20) + UDP (8) + BTH(20). 1959 * Subtract 20 bytes from QP1 SQ header buf size 1960 */ 1961 if (is_udp && ip_version == 4) 1962 sge.size -= 20; 1963 /* 1964 * Max Header buf size for RoCE V1 is 78. 1965 * ETH(14) + VLAN(4) + GRH(40) + BTH(20). 1966 * Subtract 8 bytes from QP1 SQ header buf size 1967 */ 1968 if (!is_udp) 1969 sge.size -= 8; 1970 1971 /* Subtract 4 bytes for non vlan packets */ 1972 if (!is_vlan) 1973 sge.size -= 4; 1974 1975 wqe->sg_list[0].addr = sge.addr; 1976 wqe->sg_list[0].lkey = sge.lkey; 1977 wqe->sg_list[0].size = sge.size; 1978 wqe->num_sge++; 1979 1980 } else { 1981 dev_err(rdev_to_dev(qp->rdev), "QP1 buffer is empty!"); 1982 rc = -ENOMEM; 1983 } 1984 return rc; 1985 } 1986 1987 /* For the MAD layer, it only provides the recv SGE the size of 1988 * ib_grh + MAD datagram. No Ethernet headers, Ethertype, BTH, DETH, 1989 * nor RoCE iCRC. The Cu+ solution must provide buffer for the entire 1990 * receive packet (334 bytes) with no VLAN and then copy the GRH 1991 * and the MAD datagram out to the provided SGE. 1992 */ 1993 static int bnxt_re_build_qp1_shadow_qp_recv(struct bnxt_re_qp *qp, 1994 const struct ib_recv_wr *wr, 1995 struct bnxt_qplib_swqe *wqe, 1996 int payload_size) 1997 { 1998 struct bnxt_qplib_sge ref, sge; 1999 u32 rq_prod_index; 2000 struct bnxt_re_sqp_entries *sqp_entry; 2001 2002 rq_prod_index = bnxt_qplib_get_rq_prod_index(&qp->qplib_qp); 2003 2004 if (!bnxt_qplib_get_qp1_rq_buf(&qp->qplib_qp, &sge)) 2005 return -ENOMEM; 2006 2007 /* Create 1 SGE to receive the entire 2008 * ethernet packet 2009 */ 2010 /* Save the reference from ULP */ 2011 ref.addr = wqe->sg_list[0].addr; 2012 ref.lkey = wqe->sg_list[0].lkey; 2013 ref.size = wqe->sg_list[0].size; 2014 2015 sqp_entry = &qp->rdev->sqp_tbl[rq_prod_index]; 2016 2017 /* SGE 1 */ 2018 wqe->sg_list[0].addr = sge.addr; 2019 wqe->sg_list[0].lkey = sge.lkey; 2020 wqe->sg_list[0].size = BNXT_QPLIB_MAX_QP1_RQ_HDR_SIZE_V2; 2021 sge.size -= wqe->sg_list[0].size; 2022 2023 sqp_entry->sge.addr = ref.addr; 2024 sqp_entry->sge.lkey = ref.lkey; 2025 sqp_entry->sge.size = ref.size; 2026 /* Store the wrid for reporting completion */ 2027 sqp_entry->wrid = wqe->wr_id; 2028 /* change the wqe->wrid to table index */ 2029 wqe->wr_id = rq_prod_index; 2030 return 0; 2031 } 2032 2033 static int is_ud_qp(struct bnxt_re_qp *qp) 2034 { 2035 return (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_UD || 2036 qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI); 2037 } 2038 2039 static int bnxt_re_build_send_wqe(struct bnxt_re_qp *qp, 2040 const struct ib_send_wr *wr, 2041 struct bnxt_qplib_swqe *wqe) 2042 { 2043 struct bnxt_re_ah *ah = NULL; 2044 2045 if (is_ud_qp(qp)) { 2046 ah = container_of(ud_wr(wr)->ah, struct bnxt_re_ah, ib_ah); 2047 wqe->send.q_key = ud_wr(wr)->remote_qkey; 2048 wqe->send.dst_qp = ud_wr(wr)->remote_qpn; 2049 wqe->send.avid = ah->qplib_ah.id; 2050 } 2051 switch (wr->opcode) { 2052 case IB_WR_SEND: 2053 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND; 2054 break; 2055 case IB_WR_SEND_WITH_IMM: 2056 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM; 2057 wqe->send.imm_data = wr->ex.imm_data; 2058 break; 2059 case IB_WR_SEND_WITH_INV: 2060 wqe->type = BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV; 2061 wqe->send.inv_key = wr->ex.invalidate_rkey; 2062 break; 2063 default: 2064 return -EINVAL; 2065 } 2066 if (wr->send_flags & IB_SEND_SIGNALED) 2067 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2068 if (wr->send_flags & IB_SEND_FENCE) 2069 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2070 if (wr->send_flags & IB_SEND_SOLICITED) 2071 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2072 if (wr->send_flags & IB_SEND_INLINE) 2073 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2074 2075 return 0; 2076 } 2077 2078 static int bnxt_re_build_rdma_wqe(const struct ib_send_wr *wr, 2079 struct bnxt_qplib_swqe *wqe) 2080 { 2081 switch (wr->opcode) { 2082 case IB_WR_RDMA_WRITE: 2083 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE; 2084 break; 2085 case IB_WR_RDMA_WRITE_WITH_IMM: 2086 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM; 2087 wqe->rdma.imm_data = wr->ex.imm_data; 2088 break; 2089 case IB_WR_RDMA_READ: 2090 wqe->type = BNXT_QPLIB_SWQE_TYPE_RDMA_READ; 2091 wqe->rdma.inv_key = wr->ex.invalidate_rkey; 2092 break; 2093 default: 2094 return -EINVAL; 2095 } 2096 wqe->rdma.remote_va = rdma_wr(wr)->remote_addr; 2097 wqe->rdma.r_key = rdma_wr(wr)->rkey; 2098 if (wr->send_flags & IB_SEND_SIGNALED) 2099 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2100 if (wr->send_flags & IB_SEND_FENCE) 2101 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2102 if (wr->send_flags & IB_SEND_SOLICITED) 2103 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2104 if (wr->send_flags & IB_SEND_INLINE) 2105 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_INLINE; 2106 2107 return 0; 2108 } 2109 2110 static int bnxt_re_build_atomic_wqe(const struct ib_send_wr *wr, 2111 struct bnxt_qplib_swqe *wqe) 2112 { 2113 switch (wr->opcode) { 2114 case IB_WR_ATOMIC_CMP_AND_SWP: 2115 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP; 2116 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2117 wqe->atomic.swap_data = atomic_wr(wr)->swap; 2118 break; 2119 case IB_WR_ATOMIC_FETCH_AND_ADD: 2120 wqe->type = BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD; 2121 wqe->atomic.cmp_data = atomic_wr(wr)->compare_add; 2122 break; 2123 default: 2124 return -EINVAL; 2125 } 2126 wqe->atomic.remote_va = atomic_wr(wr)->remote_addr; 2127 wqe->atomic.r_key = atomic_wr(wr)->rkey; 2128 if (wr->send_flags & IB_SEND_SIGNALED) 2129 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2130 if (wr->send_flags & IB_SEND_FENCE) 2131 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2132 if (wr->send_flags & IB_SEND_SOLICITED) 2133 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2134 return 0; 2135 } 2136 2137 static int bnxt_re_build_inv_wqe(const struct ib_send_wr *wr, 2138 struct bnxt_qplib_swqe *wqe) 2139 { 2140 wqe->type = BNXT_QPLIB_SWQE_TYPE_LOCAL_INV; 2141 wqe->local_inv.inv_l_key = wr->ex.invalidate_rkey; 2142 2143 /* Need unconditional fence for local invalidate 2144 * opcode to work as expected. 2145 */ 2146 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2147 2148 if (wr->send_flags & IB_SEND_SIGNALED) 2149 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2150 if (wr->send_flags & IB_SEND_SOLICITED) 2151 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SOLICIT_EVENT; 2152 2153 return 0; 2154 } 2155 2156 static int bnxt_re_build_reg_wqe(const struct ib_reg_wr *wr, 2157 struct bnxt_qplib_swqe *wqe) 2158 { 2159 struct bnxt_re_mr *mr = container_of(wr->mr, struct bnxt_re_mr, ib_mr); 2160 struct bnxt_qplib_frpl *qplib_frpl = &mr->qplib_frpl; 2161 int access = wr->access; 2162 2163 wqe->frmr.pbl_ptr = (__le64 *)qplib_frpl->hwq.pbl_ptr[0]; 2164 wqe->frmr.pbl_dma_ptr = qplib_frpl->hwq.pbl_dma_ptr[0]; 2165 wqe->frmr.page_list = mr->pages; 2166 wqe->frmr.page_list_len = mr->npages; 2167 wqe->frmr.levels = qplib_frpl->hwq.level + 1; 2168 wqe->type = BNXT_QPLIB_SWQE_TYPE_REG_MR; 2169 2170 /* Need unconditional fence for reg_mr 2171 * opcode to function as expected. 2172 */ 2173 2174 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_UC_FENCE; 2175 2176 if (wr->wr.send_flags & IB_SEND_SIGNALED) 2177 wqe->flags |= BNXT_QPLIB_SWQE_FLAGS_SIGNAL_COMP; 2178 2179 if (access & IB_ACCESS_LOCAL_WRITE) 2180 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_LOCAL_WRITE; 2181 if (access & IB_ACCESS_REMOTE_READ) 2182 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_READ; 2183 if (access & IB_ACCESS_REMOTE_WRITE) 2184 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_WRITE; 2185 if (access & IB_ACCESS_REMOTE_ATOMIC) 2186 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_REMOTE_ATOMIC; 2187 if (access & IB_ACCESS_MW_BIND) 2188 wqe->frmr.access_cntl |= SQ_FR_PMR_ACCESS_CNTL_WINDOW_BIND; 2189 2190 wqe->frmr.l_key = wr->key; 2191 wqe->frmr.length = wr->mr->length; 2192 wqe->frmr.pbl_pg_sz_log = (wr->mr->page_size >> PAGE_SHIFT_4K) - 1; 2193 wqe->frmr.va = wr->mr->iova; 2194 return 0; 2195 } 2196 2197 static int bnxt_re_copy_inline_data(struct bnxt_re_dev *rdev, 2198 const struct ib_send_wr *wr, 2199 struct bnxt_qplib_swqe *wqe) 2200 { 2201 /* Copy the inline data to the data field */ 2202 u8 *in_data; 2203 u32 i, sge_len; 2204 void *sge_addr; 2205 2206 in_data = wqe->inline_data; 2207 for (i = 0; i < wr->num_sge; i++) { 2208 sge_addr = (void *)(unsigned long) 2209 wr->sg_list[i].addr; 2210 sge_len = wr->sg_list[i].length; 2211 2212 if ((sge_len + wqe->inline_len) > 2213 BNXT_QPLIB_SWQE_MAX_INLINE_LENGTH) { 2214 dev_err(rdev_to_dev(rdev), 2215 "Inline data size requested > supported value"); 2216 return -EINVAL; 2217 } 2218 sge_len = wr->sg_list[i].length; 2219 2220 memcpy(in_data, sge_addr, sge_len); 2221 in_data += wr->sg_list[i].length; 2222 wqe->inline_len += wr->sg_list[i].length; 2223 } 2224 return wqe->inline_len; 2225 } 2226 2227 static int bnxt_re_copy_wr_payload(struct bnxt_re_dev *rdev, 2228 const struct ib_send_wr *wr, 2229 struct bnxt_qplib_swqe *wqe) 2230 { 2231 int payload_sz = 0; 2232 2233 if (wr->send_flags & IB_SEND_INLINE) 2234 payload_sz = bnxt_re_copy_inline_data(rdev, wr, wqe); 2235 else 2236 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe->sg_list, 2237 wqe->num_sge); 2238 2239 return payload_sz; 2240 } 2241 2242 static void bnxt_ud_qp_hw_stall_workaround(struct bnxt_re_qp *qp) 2243 { 2244 if ((qp->ib_qp.qp_type == IB_QPT_UD || 2245 qp->ib_qp.qp_type == IB_QPT_GSI || 2246 qp->ib_qp.qp_type == IB_QPT_RAW_ETHERTYPE) && 2247 qp->qplib_qp.wqe_cnt == BNXT_RE_UD_QP_HW_STALL) { 2248 int qp_attr_mask; 2249 struct ib_qp_attr qp_attr; 2250 2251 qp_attr_mask = IB_QP_STATE; 2252 qp_attr.qp_state = IB_QPS_RTS; 2253 bnxt_re_modify_qp(&qp->ib_qp, &qp_attr, qp_attr_mask, NULL); 2254 qp->qplib_qp.wqe_cnt = 0; 2255 } 2256 } 2257 2258 static int bnxt_re_post_send_shadow_qp(struct bnxt_re_dev *rdev, 2259 struct bnxt_re_qp *qp, 2260 const struct ib_send_wr *wr) 2261 { 2262 struct bnxt_qplib_swqe wqe; 2263 int rc = 0, payload_sz = 0; 2264 unsigned long flags; 2265 2266 spin_lock_irqsave(&qp->sq_lock, flags); 2267 memset(&wqe, 0, sizeof(wqe)); 2268 while (wr) { 2269 /* House keeping */ 2270 memset(&wqe, 0, sizeof(wqe)); 2271 2272 /* Common */ 2273 wqe.num_sge = wr->num_sge; 2274 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2275 dev_err(rdev_to_dev(rdev), 2276 "Limit exceeded for Send SGEs"); 2277 rc = -EINVAL; 2278 goto bad; 2279 } 2280 2281 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2282 if (payload_sz < 0) { 2283 rc = -EINVAL; 2284 goto bad; 2285 } 2286 wqe.wr_id = wr->wr_id; 2287 2288 wqe.type = BNXT_QPLIB_SWQE_TYPE_SEND; 2289 2290 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2291 if (!rc) 2292 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2293 bad: 2294 if (rc) { 2295 dev_err(rdev_to_dev(rdev), 2296 "Post send failed opcode = %#x rc = %d", 2297 wr->opcode, rc); 2298 break; 2299 } 2300 wr = wr->next; 2301 } 2302 bnxt_qplib_post_send_db(&qp->qplib_qp); 2303 bnxt_ud_qp_hw_stall_workaround(qp); 2304 spin_unlock_irqrestore(&qp->sq_lock, flags); 2305 return rc; 2306 } 2307 2308 int bnxt_re_post_send(struct ib_qp *ib_qp, const struct ib_send_wr *wr, 2309 const struct ib_send_wr **bad_wr) 2310 { 2311 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2312 struct bnxt_qplib_swqe wqe; 2313 int rc = 0, payload_sz = 0; 2314 unsigned long flags; 2315 2316 spin_lock_irqsave(&qp->sq_lock, flags); 2317 while (wr) { 2318 /* House keeping */ 2319 memset(&wqe, 0, sizeof(wqe)); 2320 2321 /* Common */ 2322 wqe.num_sge = wr->num_sge; 2323 if (wr->num_sge > qp->qplib_qp.sq.max_sge) { 2324 dev_err(rdev_to_dev(qp->rdev), 2325 "Limit exceeded for Send SGEs"); 2326 rc = -EINVAL; 2327 goto bad; 2328 } 2329 2330 payload_sz = bnxt_re_copy_wr_payload(qp->rdev, wr, &wqe); 2331 if (payload_sz < 0) { 2332 rc = -EINVAL; 2333 goto bad; 2334 } 2335 wqe.wr_id = wr->wr_id; 2336 2337 switch (wr->opcode) { 2338 case IB_WR_SEND: 2339 case IB_WR_SEND_WITH_IMM: 2340 if (qp->qplib_qp.type == CMDQ_CREATE_QP1_TYPE_GSI) { 2341 rc = bnxt_re_build_qp1_send_v2(qp, wr, &wqe, 2342 payload_sz); 2343 if (rc) 2344 goto bad; 2345 wqe.rawqp1.lflags |= 2346 SQ_SEND_RAWETH_QP1_LFLAGS_ROCE_CRC; 2347 } 2348 switch (wr->send_flags) { 2349 case IB_SEND_IP_CSUM: 2350 wqe.rawqp1.lflags |= 2351 SQ_SEND_RAWETH_QP1_LFLAGS_IP_CHKSUM; 2352 break; 2353 default: 2354 break; 2355 } 2356 /* fall through */ 2357 case IB_WR_SEND_WITH_INV: 2358 rc = bnxt_re_build_send_wqe(qp, wr, &wqe); 2359 break; 2360 case IB_WR_RDMA_WRITE: 2361 case IB_WR_RDMA_WRITE_WITH_IMM: 2362 case IB_WR_RDMA_READ: 2363 rc = bnxt_re_build_rdma_wqe(wr, &wqe); 2364 break; 2365 case IB_WR_ATOMIC_CMP_AND_SWP: 2366 case IB_WR_ATOMIC_FETCH_AND_ADD: 2367 rc = bnxt_re_build_atomic_wqe(wr, &wqe); 2368 break; 2369 case IB_WR_RDMA_READ_WITH_INV: 2370 dev_err(rdev_to_dev(qp->rdev), 2371 "RDMA Read with Invalidate is not supported"); 2372 rc = -EINVAL; 2373 goto bad; 2374 case IB_WR_LOCAL_INV: 2375 rc = bnxt_re_build_inv_wqe(wr, &wqe); 2376 break; 2377 case IB_WR_REG_MR: 2378 rc = bnxt_re_build_reg_wqe(reg_wr(wr), &wqe); 2379 break; 2380 default: 2381 /* Unsupported WRs */ 2382 dev_err(rdev_to_dev(qp->rdev), 2383 "WR (%#x) is not supported", wr->opcode); 2384 rc = -EINVAL; 2385 goto bad; 2386 } 2387 if (!rc) 2388 rc = bnxt_qplib_post_send(&qp->qplib_qp, &wqe); 2389 bad: 2390 if (rc) { 2391 dev_err(rdev_to_dev(qp->rdev), 2392 "post_send failed op:%#x qps = %#x rc = %d\n", 2393 wr->opcode, qp->qplib_qp.state, rc); 2394 *bad_wr = wr; 2395 break; 2396 } 2397 wr = wr->next; 2398 } 2399 bnxt_qplib_post_send_db(&qp->qplib_qp); 2400 bnxt_ud_qp_hw_stall_workaround(qp); 2401 spin_unlock_irqrestore(&qp->sq_lock, flags); 2402 2403 return rc; 2404 } 2405 2406 static int bnxt_re_post_recv_shadow_qp(struct bnxt_re_dev *rdev, 2407 struct bnxt_re_qp *qp, 2408 const struct ib_recv_wr *wr) 2409 { 2410 struct bnxt_qplib_swqe wqe; 2411 int rc = 0; 2412 2413 memset(&wqe, 0, sizeof(wqe)); 2414 while (wr) { 2415 /* House keeping */ 2416 memset(&wqe, 0, sizeof(wqe)); 2417 2418 /* Common */ 2419 wqe.num_sge = wr->num_sge; 2420 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2421 dev_err(rdev_to_dev(rdev), 2422 "Limit exceeded for Receive SGEs"); 2423 rc = -EINVAL; 2424 break; 2425 } 2426 bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, wr->num_sge); 2427 wqe.wr_id = wr->wr_id; 2428 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2429 2430 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2431 if (rc) 2432 break; 2433 2434 wr = wr->next; 2435 } 2436 if (!rc) 2437 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2438 return rc; 2439 } 2440 2441 int bnxt_re_post_recv(struct ib_qp *ib_qp, const struct ib_recv_wr *wr, 2442 const struct ib_recv_wr **bad_wr) 2443 { 2444 struct bnxt_re_qp *qp = container_of(ib_qp, struct bnxt_re_qp, ib_qp); 2445 struct bnxt_qplib_swqe wqe; 2446 int rc = 0, payload_sz = 0; 2447 unsigned long flags; 2448 u32 count = 0; 2449 2450 spin_lock_irqsave(&qp->rq_lock, flags); 2451 while (wr) { 2452 /* House keeping */ 2453 memset(&wqe, 0, sizeof(wqe)); 2454 2455 /* Common */ 2456 wqe.num_sge = wr->num_sge; 2457 if (wr->num_sge > qp->qplib_qp.rq.max_sge) { 2458 dev_err(rdev_to_dev(qp->rdev), 2459 "Limit exceeded for Receive SGEs"); 2460 rc = -EINVAL; 2461 *bad_wr = wr; 2462 break; 2463 } 2464 2465 payload_sz = bnxt_re_build_sgl(wr->sg_list, wqe.sg_list, 2466 wr->num_sge); 2467 wqe.wr_id = wr->wr_id; 2468 wqe.type = BNXT_QPLIB_SWQE_TYPE_RECV; 2469 2470 if (ib_qp->qp_type == IB_QPT_GSI && 2471 qp->qplib_qp.type != CMDQ_CREATE_QP_TYPE_GSI) 2472 rc = bnxt_re_build_qp1_shadow_qp_recv(qp, wr, &wqe, 2473 payload_sz); 2474 if (!rc) 2475 rc = bnxt_qplib_post_recv(&qp->qplib_qp, &wqe); 2476 if (rc) { 2477 *bad_wr = wr; 2478 break; 2479 } 2480 2481 /* Ring DB if the RQEs posted reaches a threshold value */ 2482 if (++count >= BNXT_RE_RQ_WQE_THRESHOLD) { 2483 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2484 count = 0; 2485 } 2486 2487 wr = wr->next; 2488 } 2489 2490 if (count) 2491 bnxt_qplib_post_recv_db(&qp->qplib_qp); 2492 2493 spin_unlock_irqrestore(&qp->rq_lock, flags); 2494 2495 return rc; 2496 } 2497 2498 /* Completion Queues */ 2499 void bnxt_re_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) 2500 { 2501 struct bnxt_re_cq *cq; 2502 struct bnxt_qplib_nq *nq; 2503 struct bnxt_re_dev *rdev; 2504 2505 cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 2506 rdev = cq->rdev; 2507 nq = cq->qplib_cq.nq; 2508 2509 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2510 ib_umem_release(cq->umem); 2511 2512 atomic_dec(&rdev->cq_count); 2513 nq->budget--; 2514 kfree(cq->cql); 2515 } 2516 2517 int bnxt_re_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 2518 struct ib_udata *udata) 2519 { 2520 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibcq->device, ibdev); 2521 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 2522 struct bnxt_re_cq *cq = container_of(ibcq, struct bnxt_re_cq, ib_cq); 2523 int rc, entries; 2524 int cqe = attr->cqe; 2525 struct bnxt_qplib_nq *nq = NULL; 2526 unsigned int nq_alloc_cnt; 2527 2528 /* Validate CQ fields */ 2529 if (cqe < 1 || cqe > dev_attr->max_cq_wqes) { 2530 dev_err(rdev_to_dev(rdev), "Failed to create CQ -max exceeded"); 2531 return -EINVAL; 2532 } 2533 2534 cq->rdev = rdev; 2535 cq->qplib_cq.cq_handle = (u64)(unsigned long)(&cq->qplib_cq); 2536 2537 entries = roundup_pow_of_two(cqe + 1); 2538 if (entries > dev_attr->max_cq_wqes + 1) 2539 entries = dev_attr->max_cq_wqes + 1; 2540 2541 if (udata) { 2542 struct bnxt_re_cq_req req; 2543 struct bnxt_re_ucontext *uctx = rdma_udata_to_drv_context( 2544 udata, struct bnxt_re_ucontext, ib_uctx); 2545 if (ib_copy_from_udata(&req, udata, sizeof(req))) { 2546 rc = -EFAULT; 2547 goto fail; 2548 } 2549 2550 cq->umem = ib_umem_get(&rdev->ibdev, req.cq_va, 2551 entries * sizeof(struct cq_base), 2552 IB_ACCESS_LOCAL_WRITE); 2553 if (IS_ERR(cq->umem)) { 2554 rc = PTR_ERR(cq->umem); 2555 goto fail; 2556 } 2557 cq->qplib_cq.sg_info.sglist = cq->umem->sg_head.sgl; 2558 cq->qplib_cq.sg_info.npages = ib_umem_num_pages(cq->umem); 2559 cq->qplib_cq.sg_info.nmap = cq->umem->nmap; 2560 cq->qplib_cq.dpi = &uctx->dpi; 2561 } else { 2562 cq->max_cql = min_t(u32, entries, MAX_CQL_PER_POLL); 2563 cq->cql = kcalloc(cq->max_cql, sizeof(struct bnxt_qplib_cqe), 2564 GFP_KERNEL); 2565 if (!cq->cql) { 2566 rc = -ENOMEM; 2567 goto fail; 2568 } 2569 2570 cq->qplib_cq.dpi = &rdev->dpi_privileged; 2571 } 2572 /* 2573 * Allocating the NQ in a round robin fashion. nq_alloc_cnt is a 2574 * used for getting the NQ index. 2575 */ 2576 nq_alloc_cnt = atomic_inc_return(&rdev->nq_alloc_cnt); 2577 nq = &rdev->nq[nq_alloc_cnt % (rdev->num_msix - 1)]; 2578 cq->qplib_cq.max_wqe = entries; 2579 cq->qplib_cq.cnq_hw_ring_id = nq->ring_id; 2580 cq->qplib_cq.nq = nq; 2581 2582 rc = bnxt_qplib_create_cq(&rdev->qplib_res, &cq->qplib_cq); 2583 if (rc) { 2584 dev_err(rdev_to_dev(rdev), "Failed to create HW CQ"); 2585 goto fail; 2586 } 2587 2588 cq->ib_cq.cqe = entries; 2589 cq->cq_period = cq->qplib_cq.period; 2590 nq->budget++; 2591 2592 atomic_inc(&rdev->cq_count); 2593 spin_lock_init(&cq->cq_lock); 2594 2595 if (udata) { 2596 struct bnxt_re_cq_resp resp; 2597 2598 resp.cqid = cq->qplib_cq.id; 2599 resp.tail = cq->qplib_cq.hwq.cons; 2600 resp.phase = cq->qplib_cq.period; 2601 resp.rsvd = 0; 2602 rc = ib_copy_to_udata(udata, &resp, sizeof(resp)); 2603 if (rc) { 2604 dev_err(rdev_to_dev(rdev), "Failed to copy CQ udata"); 2605 bnxt_qplib_destroy_cq(&rdev->qplib_res, &cq->qplib_cq); 2606 goto c2fail; 2607 } 2608 } 2609 2610 return 0; 2611 2612 c2fail: 2613 ib_umem_release(cq->umem); 2614 fail: 2615 kfree(cq->cql); 2616 return rc; 2617 } 2618 2619 static u8 __req_to_ib_wc_status(u8 qstatus) 2620 { 2621 switch (qstatus) { 2622 case CQ_REQ_STATUS_OK: 2623 return IB_WC_SUCCESS; 2624 case CQ_REQ_STATUS_BAD_RESPONSE_ERR: 2625 return IB_WC_BAD_RESP_ERR; 2626 case CQ_REQ_STATUS_LOCAL_LENGTH_ERR: 2627 return IB_WC_LOC_LEN_ERR; 2628 case CQ_REQ_STATUS_LOCAL_QP_OPERATION_ERR: 2629 return IB_WC_LOC_QP_OP_ERR; 2630 case CQ_REQ_STATUS_LOCAL_PROTECTION_ERR: 2631 return IB_WC_LOC_PROT_ERR; 2632 case CQ_REQ_STATUS_MEMORY_MGT_OPERATION_ERR: 2633 return IB_WC_GENERAL_ERR; 2634 case CQ_REQ_STATUS_REMOTE_INVALID_REQUEST_ERR: 2635 return IB_WC_REM_INV_REQ_ERR; 2636 case CQ_REQ_STATUS_REMOTE_ACCESS_ERR: 2637 return IB_WC_REM_ACCESS_ERR; 2638 case CQ_REQ_STATUS_REMOTE_OPERATION_ERR: 2639 return IB_WC_REM_OP_ERR; 2640 case CQ_REQ_STATUS_RNR_NAK_RETRY_CNT_ERR: 2641 return IB_WC_RNR_RETRY_EXC_ERR; 2642 case CQ_REQ_STATUS_TRANSPORT_RETRY_CNT_ERR: 2643 return IB_WC_RETRY_EXC_ERR; 2644 case CQ_REQ_STATUS_WORK_REQUEST_FLUSHED_ERR: 2645 return IB_WC_WR_FLUSH_ERR; 2646 default: 2647 return IB_WC_GENERAL_ERR; 2648 } 2649 return 0; 2650 } 2651 2652 static u8 __rawqp1_to_ib_wc_status(u8 qstatus) 2653 { 2654 switch (qstatus) { 2655 case CQ_RES_RAWETH_QP1_STATUS_OK: 2656 return IB_WC_SUCCESS; 2657 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_ACCESS_ERROR: 2658 return IB_WC_LOC_ACCESS_ERR; 2659 case CQ_RES_RAWETH_QP1_STATUS_HW_LOCAL_LENGTH_ERR: 2660 return IB_WC_LOC_LEN_ERR; 2661 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_PROTECTION_ERR: 2662 return IB_WC_LOC_PROT_ERR; 2663 case CQ_RES_RAWETH_QP1_STATUS_LOCAL_QP_OPERATION_ERR: 2664 return IB_WC_LOC_QP_OP_ERR; 2665 case CQ_RES_RAWETH_QP1_STATUS_MEMORY_MGT_OPERATION_ERR: 2666 return IB_WC_GENERAL_ERR; 2667 case CQ_RES_RAWETH_QP1_STATUS_WORK_REQUEST_FLUSHED_ERR: 2668 return IB_WC_WR_FLUSH_ERR; 2669 case CQ_RES_RAWETH_QP1_STATUS_HW_FLUSH_ERR: 2670 return IB_WC_WR_FLUSH_ERR; 2671 default: 2672 return IB_WC_GENERAL_ERR; 2673 } 2674 } 2675 2676 static u8 __rc_to_ib_wc_status(u8 qstatus) 2677 { 2678 switch (qstatus) { 2679 case CQ_RES_RC_STATUS_OK: 2680 return IB_WC_SUCCESS; 2681 case CQ_RES_RC_STATUS_LOCAL_ACCESS_ERROR: 2682 return IB_WC_LOC_ACCESS_ERR; 2683 case CQ_RES_RC_STATUS_LOCAL_LENGTH_ERR: 2684 return IB_WC_LOC_LEN_ERR; 2685 case CQ_RES_RC_STATUS_LOCAL_PROTECTION_ERR: 2686 return IB_WC_LOC_PROT_ERR; 2687 case CQ_RES_RC_STATUS_LOCAL_QP_OPERATION_ERR: 2688 return IB_WC_LOC_QP_OP_ERR; 2689 case CQ_RES_RC_STATUS_MEMORY_MGT_OPERATION_ERR: 2690 return IB_WC_GENERAL_ERR; 2691 case CQ_RES_RC_STATUS_REMOTE_INVALID_REQUEST_ERR: 2692 return IB_WC_REM_INV_REQ_ERR; 2693 case CQ_RES_RC_STATUS_WORK_REQUEST_FLUSHED_ERR: 2694 return IB_WC_WR_FLUSH_ERR; 2695 case CQ_RES_RC_STATUS_HW_FLUSH_ERR: 2696 return IB_WC_WR_FLUSH_ERR; 2697 default: 2698 return IB_WC_GENERAL_ERR; 2699 } 2700 } 2701 2702 static void bnxt_re_process_req_wc(struct ib_wc *wc, struct bnxt_qplib_cqe *cqe) 2703 { 2704 switch (cqe->type) { 2705 case BNXT_QPLIB_SWQE_TYPE_SEND: 2706 wc->opcode = IB_WC_SEND; 2707 break; 2708 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_IMM: 2709 wc->opcode = IB_WC_SEND; 2710 wc->wc_flags |= IB_WC_WITH_IMM; 2711 break; 2712 case BNXT_QPLIB_SWQE_TYPE_SEND_WITH_INV: 2713 wc->opcode = IB_WC_SEND; 2714 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2715 break; 2716 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE: 2717 wc->opcode = IB_WC_RDMA_WRITE; 2718 break; 2719 case BNXT_QPLIB_SWQE_TYPE_RDMA_WRITE_WITH_IMM: 2720 wc->opcode = IB_WC_RDMA_WRITE; 2721 wc->wc_flags |= IB_WC_WITH_IMM; 2722 break; 2723 case BNXT_QPLIB_SWQE_TYPE_RDMA_READ: 2724 wc->opcode = IB_WC_RDMA_READ; 2725 break; 2726 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_CMP_AND_SWP: 2727 wc->opcode = IB_WC_COMP_SWAP; 2728 break; 2729 case BNXT_QPLIB_SWQE_TYPE_ATOMIC_FETCH_AND_ADD: 2730 wc->opcode = IB_WC_FETCH_ADD; 2731 break; 2732 case BNXT_QPLIB_SWQE_TYPE_LOCAL_INV: 2733 wc->opcode = IB_WC_LOCAL_INV; 2734 break; 2735 case BNXT_QPLIB_SWQE_TYPE_REG_MR: 2736 wc->opcode = IB_WC_REG_MR; 2737 break; 2738 default: 2739 wc->opcode = IB_WC_SEND; 2740 break; 2741 } 2742 2743 wc->status = __req_to_ib_wc_status(cqe->status); 2744 } 2745 2746 static int bnxt_re_check_packet_type(u16 raweth_qp1_flags, 2747 u16 raweth_qp1_flags2) 2748 { 2749 bool is_ipv6 = false, is_ipv4 = false; 2750 2751 /* raweth_qp1_flags Bit 9-6 indicates itype */ 2752 if ((raweth_qp1_flags & CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2753 != CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS_ITYPE_ROCE) 2754 return -1; 2755 2756 if (raweth_qp1_flags2 & 2757 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_CS_CALC && 2758 raweth_qp1_flags2 & 2759 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_L4_CS_CALC) { 2760 /* raweth_qp1_flags2 Bit 8 indicates ip_type. 0-v4 1 - v6 */ 2761 (raweth_qp1_flags2 & 2762 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_IP_TYPE) ? 2763 (is_ipv6 = true) : (is_ipv4 = true); 2764 return ((is_ipv6) ? 2765 BNXT_RE_ROCEV2_IPV6_PACKET : 2766 BNXT_RE_ROCEV2_IPV4_PACKET); 2767 } else { 2768 return BNXT_RE_ROCE_V1_PACKET; 2769 } 2770 } 2771 2772 static int bnxt_re_to_ib_nw_type(int nw_type) 2773 { 2774 u8 nw_hdr_type = 0xFF; 2775 2776 switch (nw_type) { 2777 case BNXT_RE_ROCE_V1_PACKET: 2778 nw_hdr_type = RDMA_NETWORK_ROCE_V1; 2779 break; 2780 case BNXT_RE_ROCEV2_IPV4_PACKET: 2781 nw_hdr_type = RDMA_NETWORK_IPV4; 2782 break; 2783 case BNXT_RE_ROCEV2_IPV6_PACKET: 2784 nw_hdr_type = RDMA_NETWORK_IPV6; 2785 break; 2786 } 2787 return nw_hdr_type; 2788 } 2789 2790 static bool bnxt_re_is_loopback_packet(struct bnxt_re_dev *rdev, 2791 void *rq_hdr_buf) 2792 { 2793 u8 *tmp_buf = NULL; 2794 struct ethhdr *eth_hdr; 2795 u16 eth_type; 2796 bool rc = false; 2797 2798 tmp_buf = (u8 *)rq_hdr_buf; 2799 /* 2800 * If dest mac is not same as I/F mac, this could be a 2801 * loopback address or multicast address, check whether 2802 * it is a loopback packet 2803 */ 2804 if (!ether_addr_equal(tmp_buf, rdev->netdev->dev_addr)) { 2805 tmp_buf += 4; 2806 /* Check the ether type */ 2807 eth_hdr = (struct ethhdr *)tmp_buf; 2808 eth_type = ntohs(eth_hdr->h_proto); 2809 switch (eth_type) { 2810 case ETH_P_IBOE: 2811 rc = true; 2812 break; 2813 case ETH_P_IP: 2814 case ETH_P_IPV6: { 2815 u32 len; 2816 struct udphdr *udp_hdr; 2817 2818 len = (eth_type == ETH_P_IP ? sizeof(struct iphdr) : 2819 sizeof(struct ipv6hdr)); 2820 tmp_buf += sizeof(struct ethhdr) + len; 2821 udp_hdr = (struct udphdr *)tmp_buf; 2822 if (ntohs(udp_hdr->dest) == 2823 ROCE_V2_UDP_DPORT) 2824 rc = true; 2825 break; 2826 } 2827 default: 2828 break; 2829 } 2830 } 2831 2832 return rc; 2833 } 2834 2835 static int bnxt_re_process_raw_qp_pkt_rx(struct bnxt_re_qp *qp1_qp, 2836 struct bnxt_qplib_cqe *cqe) 2837 { 2838 struct bnxt_re_dev *rdev = qp1_qp->rdev; 2839 struct bnxt_re_sqp_entries *sqp_entry = NULL; 2840 struct bnxt_re_qp *qp = rdev->qp1_sqp; 2841 struct ib_send_wr *swr; 2842 struct ib_ud_wr udwr; 2843 struct ib_recv_wr rwr; 2844 int pkt_type = 0; 2845 u32 tbl_idx; 2846 void *rq_hdr_buf; 2847 dma_addr_t rq_hdr_buf_map; 2848 dma_addr_t shrq_hdr_buf_map; 2849 u32 offset = 0; 2850 u32 skip_bytes = 0; 2851 struct ib_sge s_sge[2]; 2852 struct ib_sge r_sge[2]; 2853 int rc; 2854 2855 memset(&udwr, 0, sizeof(udwr)); 2856 memset(&rwr, 0, sizeof(rwr)); 2857 memset(&s_sge, 0, sizeof(s_sge)); 2858 memset(&r_sge, 0, sizeof(r_sge)); 2859 2860 swr = &udwr.wr; 2861 tbl_idx = cqe->wr_id; 2862 2863 rq_hdr_buf = qp1_qp->qplib_qp.rq_hdr_buf + 2864 (tbl_idx * qp1_qp->qplib_qp.rq_hdr_buf_size); 2865 rq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp1_qp->qplib_qp, 2866 tbl_idx); 2867 2868 /* Shadow QP header buffer */ 2869 shrq_hdr_buf_map = bnxt_qplib_get_qp_buf_from_index(&qp->qplib_qp, 2870 tbl_idx); 2871 sqp_entry = &rdev->sqp_tbl[tbl_idx]; 2872 2873 /* Store this cqe */ 2874 memcpy(&sqp_entry->cqe, cqe, sizeof(struct bnxt_qplib_cqe)); 2875 sqp_entry->qp1_qp = qp1_qp; 2876 2877 /* Find packet type from the cqe */ 2878 2879 pkt_type = bnxt_re_check_packet_type(cqe->raweth_qp1_flags, 2880 cqe->raweth_qp1_flags2); 2881 if (pkt_type < 0) { 2882 dev_err(rdev_to_dev(rdev), "Invalid packet\n"); 2883 return -EINVAL; 2884 } 2885 2886 /* Adjust the offset for the user buffer and post in the rq */ 2887 2888 if (pkt_type == BNXT_RE_ROCEV2_IPV4_PACKET) 2889 offset = 20; 2890 2891 /* 2892 * QP1 loopback packet has 4 bytes of internal header before 2893 * ether header. Skip these four bytes. 2894 */ 2895 if (bnxt_re_is_loopback_packet(rdev, rq_hdr_buf)) 2896 skip_bytes = 4; 2897 2898 /* First send SGE . Skip the ether header*/ 2899 s_sge[0].addr = rq_hdr_buf_map + BNXT_QPLIB_MAX_QP1_RQ_ETH_HDR_SIZE 2900 + skip_bytes; 2901 s_sge[0].lkey = 0xFFFFFFFF; 2902 s_sge[0].length = offset ? BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV4 : 2903 BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6; 2904 2905 /* Second Send SGE */ 2906 s_sge[1].addr = s_sge[0].addr + s_sge[0].length + 2907 BNXT_QPLIB_MAX_QP1_RQ_BDETH_HDR_SIZE; 2908 if (pkt_type != BNXT_RE_ROCE_V1_PACKET) 2909 s_sge[1].addr += 8; 2910 s_sge[1].lkey = 0xFFFFFFFF; 2911 s_sge[1].length = 256; 2912 2913 /* First recv SGE */ 2914 2915 r_sge[0].addr = shrq_hdr_buf_map; 2916 r_sge[0].lkey = 0xFFFFFFFF; 2917 r_sge[0].length = 40; 2918 2919 r_sge[1].addr = sqp_entry->sge.addr + offset; 2920 r_sge[1].lkey = sqp_entry->sge.lkey; 2921 r_sge[1].length = BNXT_QPLIB_MAX_GRH_HDR_SIZE_IPV6 + 256 - offset; 2922 2923 /* Create receive work request */ 2924 rwr.num_sge = 2; 2925 rwr.sg_list = r_sge; 2926 rwr.wr_id = tbl_idx; 2927 rwr.next = NULL; 2928 2929 rc = bnxt_re_post_recv_shadow_qp(rdev, qp, &rwr); 2930 if (rc) { 2931 dev_err(rdev_to_dev(rdev), 2932 "Failed to post Rx buffers to shadow QP"); 2933 return -ENOMEM; 2934 } 2935 2936 swr->num_sge = 2; 2937 swr->sg_list = s_sge; 2938 swr->wr_id = tbl_idx; 2939 swr->opcode = IB_WR_SEND; 2940 swr->next = NULL; 2941 2942 udwr.ah = &rdev->sqp_ah->ib_ah; 2943 udwr.remote_qpn = rdev->qp1_sqp->qplib_qp.id; 2944 udwr.remote_qkey = rdev->qp1_sqp->qplib_qp.qkey; 2945 2946 /* post data received in the send queue */ 2947 rc = bnxt_re_post_send_shadow_qp(rdev, qp, swr); 2948 2949 return 0; 2950 } 2951 2952 static void bnxt_re_process_res_rawqp1_wc(struct ib_wc *wc, 2953 struct bnxt_qplib_cqe *cqe) 2954 { 2955 wc->opcode = IB_WC_RECV; 2956 wc->status = __rawqp1_to_ib_wc_status(cqe->status); 2957 wc->wc_flags |= IB_WC_GRH; 2958 } 2959 2960 static bool bnxt_re_is_vlan_pkt(struct bnxt_qplib_cqe *orig_cqe, 2961 u16 *vid, u8 *sl) 2962 { 2963 bool ret = false; 2964 u32 metadata; 2965 u16 tpid; 2966 2967 metadata = orig_cqe->raweth_qp1_metadata; 2968 if (orig_cqe->raweth_qp1_flags2 & 2969 CQ_RES_RAWETH_QP1_RAWETH_QP1_FLAGS2_META_FORMAT_VLAN) { 2970 tpid = ((metadata & 2971 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_MASK) >> 2972 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_TPID_SFT); 2973 if (tpid == ETH_P_8021Q) { 2974 *vid = metadata & 2975 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_VID_MASK; 2976 *sl = (metadata & 2977 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_MASK) >> 2978 CQ_RES_RAWETH_QP1_RAWETH_QP1_METADATA_PRI_SFT; 2979 ret = true; 2980 } 2981 } 2982 2983 return ret; 2984 } 2985 2986 static void bnxt_re_process_res_rc_wc(struct ib_wc *wc, 2987 struct bnxt_qplib_cqe *cqe) 2988 { 2989 wc->opcode = IB_WC_RECV; 2990 wc->status = __rc_to_ib_wc_status(cqe->status); 2991 2992 if (cqe->flags & CQ_RES_RC_FLAGS_IMM) 2993 wc->wc_flags |= IB_WC_WITH_IMM; 2994 if (cqe->flags & CQ_RES_RC_FLAGS_INV) 2995 wc->wc_flags |= IB_WC_WITH_INVALIDATE; 2996 if ((cqe->flags & (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) == 2997 (CQ_RES_RC_FLAGS_RDMA | CQ_RES_RC_FLAGS_IMM)) 2998 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM; 2999 } 3000 3001 static void bnxt_re_process_res_shadow_qp_wc(struct bnxt_re_qp *qp, 3002 struct ib_wc *wc, 3003 struct bnxt_qplib_cqe *cqe) 3004 { 3005 struct bnxt_re_dev *rdev = qp->rdev; 3006 struct bnxt_re_qp *qp1_qp = NULL; 3007 struct bnxt_qplib_cqe *orig_cqe = NULL; 3008 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3009 int nw_type; 3010 u32 tbl_idx; 3011 u16 vlan_id; 3012 u8 sl; 3013 3014 tbl_idx = cqe->wr_id; 3015 3016 sqp_entry = &rdev->sqp_tbl[tbl_idx]; 3017 qp1_qp = sqp_entry->qp1_qp; 3018 orig_cqe = &sqp_entry->cqe; 3019 3020 wc->wr_id = sqp_entry->wrid; 3021 wc->byte_len = orig_cqe->length; 3022 wc->qp = &qp1_qp->ib_qp; 3023 3024 wc->ex.imm_data = orig_cqe->immdata; 3025 wc->src_qp = orig_cqe->src_qp; 3026 memcpy(wc->smac, orig_cqe->smac, ETH_ALEN); 3027 if (bnxt_re_is_vlan_pkt(orig_cqe, &vlan_id, &sl)) { 3028 wc->vlan_id = vlan_id; 3029 wc->sl = sl; 3030 wc->wc_flags |= IB_WC_WITH_VLAN; 3031 } 3032 wc->port_num = 1; 3033 wc->vendor_err = orig_cqe->status; 3034 3035 wc->opcode = IB_WC_RECV; 3036 wc->status = __rawqp1_to_ib_wc_status(orig_cqe->status); 3037 wc->wc_flags |= IB_WC_GRH; 3038 3039 nw_type = bnxt_re_check_packet_type(orig_cqe->raweth_qp1_flags, 3040 orig_cqe->raweth_qp1_flags2); 3041 if (nw_type >= 0) { 3042 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3043 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3044 } 3045 } 3046 3047 static void bnxt_re_process_res_ud_wc(struct bnxt_re_qp *qp, 3048 struct ib_wc *wc, 3049 struct bnxt_qplib_cqe *cqe) 3050 { 3051 u8 nw_type; 3052 3053 wc->opcode = IB_WC_RECV; 3054 wc->status = __rc_to_ib_wc_status(cqe->status); 3055 3056 if (cqe->flags & CQ_RES_UD_FLAGS_IMM) 3057 wc->wc_flags |= IB_WC_WITH_IMM; 3058 /* report only on GSI QP for Thor */ 3059 if (qp->qplib_qp.type == CMDQ_CREATE_QP_TYPE_GSI) { 3060 wc->wc_flags |= IB_WC_GRH; 3061 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3062 wc->wc_flags |= IB_WC_WITH_SMAC; 3063 if (cqe->flags & CQ_RES_UD_FLAGS_META_FORMAT_VLAN) { 3064 wc->vlan_id = (cqe->cfa_meta & 0xFFF); 3065 if (wc->vlan_id < 0x1000) 3066 wc->wc_flags |= IB_WC_WITH_VLAN; 3067 } 3068 nw_type = (cqe->flags & CQ_RES_UD_FLAGS_ROCE_IP_VER_MASK) >> 3069 CQ_RES_UD_FLAGS_ROCE_IP_VER_SFT; 3070 wc->network_hdr_type = bnxt_re_to_ib_nw_type(nw_type); 3071 wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE; 3072 } 3073 3074 } 3075 3076 static int send_phantom_wqe(struct bnxt_re_qp *qp) 3077 { 3078 struct bnxt_qplib_qp *lib_qp = &qp->qplib_qp; 3079 unsigned long flags; 3080 int rc = 0; 3081 3082 spin_lock_irqsave(&qp->sq_lock, flags); 3083 3084 rc = bnxt_re_bind_fence_mw(lib_qp); 3085 if (!rc) { 3086 lib_qp->sq.phantom_wqe_cnt++; 3087 dev_dbg(&lib_qp->sq.hwq.pdev->dev, 3088 "qp %#x sq->prod %#x sw_prod %#x phantom_wqe_cnt %d\n", 3089 lib_qp->id, lib_qp->sq.hwq.prod, 3090 HWQ_CMP(lib_qp->sq.hwq.prod, &lib_qp->sq.hwq), 3091 lib_qp->sq.phantom_wqe_cnt); 3092 } 3093 3094 spin_unlock_irqrestore(&qp->sq_lock, flags); 3095 return rc; 3096 } 3097 3098 int bnxt_re_poll_cq(struct ib_cq *ib_cq, int num_entries, struct ib_wc *wc) 3099 { 3100 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3101 struct bnxt_re_qp *qp; 3102 struct bnxt_qplib_cqe *cqe; 3103 int i, ncqe, budget; 3104 struct bnxt_qplib_q *sq; 3105 struct bnxt_qplib_qp *lib_qp; 3106 u32 tbl_idx; 3107 struct bnxt_re_sqp_entries *sqp_entry = NULL; 3108 unsigned long flags; 3109 3110 spin_lock_irqsave(&cq->cq_lock, flags); 3111 budget = min_t(u32, num_entries, cq->max_cql); 3112 num_entries = budget; 3113 if (!cq->cql) { 3114 dev_err(rdev_to_dev(cq->rdev), "POLL CQ : no CQL to use"); 3115 goto exit; 3116 } 3117 cqe = &cq->cql[0]; 3118 while (budget) { 3119 lib_qp = NULL; 3120 ncqe = bnxt_qplib_poll_cq(&cq->qplib_cq, cqe, budget, &lib_qp); 3121 if (lib_qp) { 3122 sq = &lib_qp->sq; 3123 if (sq->send_phantom) { 3124 qp = container_of(lib_qp, 3125 struct bnxt_re_qp, qplib_qp); 3126 if (send_phantom_wqe(qp) == -ENOMEM) 3127 dev_err(rdev_to_dev(cq->rdev), 3128 "Phantom failed! Scheduled to send again\n"); 3129 else 3130 sq->send_phantom = false; 3131 } 3132 } 3133 if (ncqe < budget) 3134 ncqe += bnxt_qplib_process_flush_list(&cq->qplib_cq, 3135 cqe + ncqe, 3136 budget - ncqe); 3137 3138 if (!ncqe) 3139 break; 3140 3141 for (i = 0; i < ncqe; i++, cqe++) { 3142 /* Transcribe each qplib_wqe back to ib_wc */ 3143 memset(wc, 0, sizeof(*wc)); 3144 3145 wc->wr_id = cqe->wr_id; 3146 wc->byte_len = cqe->length; 3147 qp = container_of 3148 ((struct bnxt_qplib_qp *) 3149 (unsigned long)(cqe->qp_handle), 3150 struct bnxt_re_qp, qplib_qp); 3151 if (!qp) { 3152 dev_err(rdev_to_dev(cq->rdev), 3153 "POLL CQ : bad QP handle"); 3154 continue; 3155 } 3156 wc->qp = &qp->ib_qp; 3157 wc->ex.imm_data = cqe->immdata; 3158 wc->src_qp = cqe->src_qp; 3159 memcpy(wc->smac, cqe->smac, ETH_ALEN); 3160 wc->port_num = 1; 3161 wc->vendor_err = cqe->status; 3162 3163 switch (cqe->opcode) { 3164 case CQ_BASE_CQE_TYPE_REQ: 3165 if (qp->rdev->qp1_sqp && qp->qplib_qp.id == 3166 qp->rdev->qp1_sqp->qplib_qp.id) { 3167 /* Handle this completion with 3168 * the stored completion 3169 */ 3170 memset(wc, 0, sizeof(*wc)); 3171 continue; 3172 } 3173 bnxt_re_process_req_wc(wc, cqe); 3174 break; 3175 case CQ_BASE_CQE_TYPE_RES_RAWETH_QP1: 3176 if (!cqe->status) { 3177 int rc = 0; 3178 3179 rc = bnxt_re_process_raw_qp_pkt_rx 3180 (qp, cqe); 3181 if (!rc) { 3182 memset(wc, 0, sizeof(*wc)); 3183 continue; 3184 } 3185 cqe->status = -1; 3186 } 3187 /* Errors need not be looped back. 3188 * But change the wr_id to the one 3189 * stored in the table 3190 */ 3191 tbl_idx = cqe->wr_id; 3192 sqp_entry = &cq->rdev->sqp_tbl[tbl_idx]; 3193 wc->wr_id = sqp_entry->wrid; 3194 bnxt_re_process_res_rawqp1_wc(wc, cqe); 3195 break; 3196 case CQ_BASE_CQE_TYPE_RES_RC: 3197 bnxt_re_process_res_rc_wc(wc, cqe); 3198 break; 3199 case CQ_BASE_CQE_TYPE_RES_UD: 3200 if (qp->rdev->qp1_sqp && qp->qplib_qp.id == 3201 qp->rdev->qp1_sqp->qplib_qp.id) { 3202 /* Handle this completion with 3203 * the stored completion 3204 */ 3205 if (cqe->status) { 3206 continue; 3207 } else { 3208 bnxt_re_process_res_shadow_qp_wc 3209 (qp, wc, cqe); 3210 break; 3211 } 3212 } 3213 bnxt_re_process_res_ud_wc(qp, wc, cqe); 3214 break; 3215 default: 3216 dev_err(rdev_to_dev(cq->rdev), 3217 "POLL CQ : type 0x%x not handled", 3218 cqe->opcode); 3219 continue; 3220 } 3221 wc++; 3222 budget--; 3223 } 3224 } 3225 exit: 3226 spin_unlock_irqrestore(&cq->cq_lock, flags); 3227 return num_entries - budget; 3228 } 3229 3230 int bnxt_re_req_notify_cq(struct ib_cq *ib_cq, 3231 enum ib_cq_notify_flags ib_cqn_flags) 3232 { 3233 struct bnxt_re_cq *cq = container_of(ib_cq, struct bnxt_re_cq, ib_cq); 3234 int type = 0, rc = 0; 3235 unsigned long flags; 3236 3237 spin_lock_irqsave(&cq->cq_lock, flags); 3238 /* Trigger on the very next completion */ 3239 if (ib_cqn_flags & IB_CQ_NEXT_COMP) 3240 type = DBC_DBC_TYPE_CQ_ARMALL; 3241 /* Trigger on the next solicited completion */ 3242 else if (ib_cqn_flags & IB_CQ_SOLICITED) 3243 type = DBC_DBC_TYPE_CQ_ARMSE; 3244 3245 /* Poll to see if there are missed events */ 3246 if ((ib_cqn_flags & IB_CQ_REPORT_MISSED_EVENTS) && 3247 !(bnxt_qplib_is_cq_empty(&cq->qplib_cq))) { 3248 rc = 1; 3249 goto exit; 3250 } 3251 bnxt_qplib_req_notify_cq(&cq->qplib_cq, type); 3252 3253 exit: 3254 spin_unlock_irqrestore(&cq->cq_lock, flags); 3255 return rc; 3256 } 3257 3258 /* Memory Regions */ 3259 struct ib_mr *bnxt_re_get_dma_mr(struct ib_pd *ib_pd, int mr_access_flags) 3260 { 3261 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3262 struct bnxt_re_dev *rdev = pd->rdev; 3263 struct bnxt_re_mr *mr; 3264 u64 pbl = 0; 3265 int rc; 3266 3267 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3268 if (!mr) 3269 return ERR_PTR(-ENOMEM); 3270 3271 mr->rdev = rdev; 3272 mr->qplib_mr.pd = &pd->qplib_pd; 3273 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3274 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3275 3276 /* Allocate and register 0 as the address */ 3277 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3278 if (rc) 3279 goto fail; 3280 3281 mr->qplib_mr.hwq.level = PBL_LVL_MAX; 3282 mr->qplib_mr.total_size = -1; /* Infinte length */ 3283 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, &pbl, 0, false, 3284 PAGE_SIZE); 3285 if (rc) 3286 goto fail_mr; 3287 3288 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3289 if (mr_access_flags & (IB_ACCESS_REMOTE_WRITE | IB_ACCESS_REMOTE_READ | 3290 IB_ACCESS_REMOTE_ATOMIC)) 3291 mr->ib_mr.rkey = mr->ib_mr.lkey; 3292 atomic_inc(&rdev->mr_count); 3293 3294 return &mr->ib_mr; 3295 3296 fail_mr: 3297 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3298 fail: 3299 kfree(mr); 3300 return ERR_PTR(rc); 3301 } 3302 3303 int bnxt_re_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) 3304 { 3305 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3306 struct bnxt_re_dev *rdev = mr->rdev; 3307 int rc; 3308 3309 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3310 if (rc) { 3311 dev_err(rdev_to_dev(rdev), "Dereg MR failed: %#x\n", rc); 3312 return rc; 3313 } 3314 3315 if (mr->pages) { 3316 rc = bnxt_qplib_free_fast_reg_page_list(&rdev->qplib_res, 3317 &mr->qplib_frpl); 3318 kfree(mr->pages); 3319 mr->npages = 0; 3320 mr->pages = NULL; 3321 } 3322 ib_umem_release(mr->ib_umem); 3323 3324 kfree(mr); 3325 atomic_dec(&rdev->mr_count); 3326 return rc; 3327 } 3328 3329 static int bnxt_re_set_page(struct ib_mr *ib_mr, u64 addr) 3330 { 3331 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3332 3333 if (unlikely(mr->npages == mr->qplib_frpl.max_pg_ptrs)) 3334 return -ENOMEM; 3335 3336 mr->pages[mr->npages++] = addr; 3337 return 0; 3338 } 3339 3340 int bnxt_re_map_mr_sg(struct ib_mr *ib_mr, struct scatterlist *sg, int sg_nents, 3341 unsigned int *sg_offset) 3342 { 3343 struct bnxt_re_mr *mr = container_of(ib_mr, struct bnxt_re_mr, ib_mr); 3344 3345 mr->npages = 0; 3346 return ib_sg_to_pages(ib_mr, sg, sg_nents, sg_offset, bnxt_re_set_page); 3347 } 3348 3349 struct ib_mr *bnxt_re_alloc_mr(struct ib_pd *ib_pd, enum ib_mr_type type, 3350 u32 max_num_sg, struct ib_udata *udata) 3351 { 3352 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3353 struct bnxt_re_dev *rdev = pd->rdev; 3354 struct bnxt_re_mr *mr = NULL; 3355 int rc; 3356 3357 if (type != IB_MR_TYPE_MEM_REG) { 3358 dev_dbg(rdev_to_dev(rdev), "MR type 0x%x not supported", type); 3359 return ERR_PTR(-EINVAL); 3360 } 3361 if (max_num_sg > MAX_PBL_LVL_1_PGS) 3362 return ERR_PTR(-EINVAL); 3363 3364 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3365 if (!mr) 3366 return ERR_PTR(-ENOMEM); 3367 3368 mr->rdev = rdev; 3369 mr->qplib_mr.pd = &pd->qplib_pd; 3370 mr->qplib_mr.flags = BNXT_QPLIB_FR_PMR; 3371 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_PMR; 3372 3373 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3374 if (rc) 3375 goto bail; 3376 3377 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3378 mr->ib_mr.rkey = mr->ib_mr.lkey; 3379 3380 mr->pages = kcalloc(max_num_sg, sizeof(u64), GFP_KERNEL); 3381 if (!mr->pages) { 3382 rc = -ENOMEM; 3383 goto fail; 3384 } 3385 rc = bnxt_qplib_alloc_fast_reg_page_list(&rdev->qplib_res, 3386 &mr->qplib_frpl, max_num_sg); 3387 if (rc) { 3388 dev_err(rdev_to_dev(rdev), 3389 "Failed to allocate HW FR page list"); 3390 goto fail_mr; 3391 } 3392 3393 atomic_inc(&rdev->mr_count); 3394 return &mr->ib_mr; 3395 3396 fail_mr: 3397 kfree(mr->pages); 3398 fail: 3399 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3400 bail: 3401 kfree(mr); 3402 return ERR_PTR(rc); 3403 } 3404 3405 struct ib_mw *bnxt_re_alloc_mw(struct ib_pd *ib_pd, enum ib_mw_type type, 3406 struct ib_udata *udata) 3407 { 3408 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3409 struct bnxt_re_dev *rdev = pd->rdev; 3410 struct bnxt_re_mw *mw; 3411 int rc; 3412 3413 mw = kzalloc(sizeof(*mw), GFP_KERNEL); 3414 if (!mw) 3415 return ERR_PTR(-ENOMEM); 3416 mw->rdev = rdev; 3417 mw->qplib_mw.pd = &pd->qplib_pd; 3418 3419 mw->qplib_mw.type = (type == IB_MW_TYPE_1 ? 3420 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE1 : 3421 CMDQ_ALLOCATE_MRW_MRW_FLAGS_MW_TYPE2B); 3422 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mw->qplib_mw); 3423 if (rc) { 3424 dev_err(rdev_to_dev(rdev), "Allocate MW failed!"); 3425 goto fail; 3426 } 3427 mw->ib_mw.rkey = mw->qplib_mw.rkey; 3428 3429 atomic_inc(&rdev->mw_count); 3430 return &mw->ib_mw; 3431 3432 fail: 3433 kfree(mw); 3434 return ERR_PTR(rc); 3435 } 3436 3437 int bnxt_re_dealloc_mw(struct ib_mw *ib_mw) 3438 { 3439 struct bnxt_re_mw *mw = container_of(ib_mw, struct bnxt_re_mw, ib_mw); 3440 struct bnxt_re_dev *rdev = mw->rdev; 3441 int rc; 3442 3443 rc = bnxt_qplib_free_mrw(&rdev->qplib_res, &mw->qplib_mw); 3444 if (rc) { 3445 dev_err(rdev_to_dev(rdev), "Free MW failed: %#x\n", rc); 3446 return rc; 3447 } 3448 3449 kfree(mw); 3450 atomic_dec(&rdev->mw_count); 3451 return rc; 3452 } 3453 3454 static int bnxt_re_page_size_ok(int page_shift) 3455 { 3456 switch (page_shift) { 3457 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4K: 3458 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_8K: 3459 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_64K: 3460 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_2M: 3461 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_256K: 3462 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1M: 3463 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_4M: 3464 case CMDQ_REGISTER_MR_LOG2_PBL_PG_SIZE_PG_1G: 3465 return 1; 3466 default: 3467 return 0; 3468 } 3469 } 3470 3471 static int fill_umem_pbl_tbl(struct ib_umem *umem, u64 *pbl_tbl_orig, 3472 int page_shift) 3473 { 3474 u64 *pbl_tbl = pbl_tbl_orig; 3475 u64 page_size = BIT_ULL(page_shift); 3476 struct ib_block_iter biter; 3477 3478 rdma_for_each_block(umem->sg_head.sgl, &biter, umem->nmap, page_size) 3479 *pbl_tbl++ = rdma_block_iter_dma_address(&biter); 3480 3481 return pbl_tbl - pbl_tbl_orig; 3482 } 3483 3484 /* uverbs */ 3485 struct ib_mr *bnxt_re_reg_user_mr(struct ib_pd *ib_pd, u64 start, u64 length, 3486 u64 virt_addr, int mr_access_flags, 3487 struct ib_udata *udata) 3488 { 3489 struct bnxt_re_pd *pd = container_of(ib_pd, struct bnxt_re_pd, ib_pd); 3490 struct bnxt_re_dev *rdev = pd->rdev; 3491 struct bnxt_re_mr *mr; 3492 struct ib_umem *umem; 3493 u64 *pbl_tbl = NULL; 3494 int umem_pgs, page_shift, rc; 3495 3496 if (length > BNXT_RE_MAX_MR_SIZE) { 3497 dev_err(rdev_to_dev(rdev), "MR Size: %lld > Max supported:%lld\n", 3498 length, BNXT_RE_MAX_MR_SIZE); 3499 return ERR_PTR(-ENOMEM); 3500 } 3501 3502 mr = kzalloc(sizeof(*mr), GFP_KERNEL); 3503 if (!mr) 3504 return ERR_PTR(-ENOMEM); 3505 3506 mr->rdev = rdev; 3507 mr->qplib_mr.pd = &pd->qplib_pd; 3508 mr->qplib_mr.flags = __from_ib_access_flags(mr_access_flags); 3509 mr->qplib_mr.type = CMDQ_ALLOCATE_MRW_MRW_FLAGS_MR; 3510 3511 rc = bnxt_qplib_alloc_mrw(&rdev->qplib_res, &mr->qplib_mr); 3512 if (rc) { 3513 dev_err(rdev_to_dev(rdev), "Failed to allocate MR"); 3514 goto free_mr; 3515 } 3516 /* The fixed portion of the rkey is the same as the lkey */ 3517 mr->ib_mr.rkey = mr->qplib_mr.rkey; 3518 3519 umem = ib_umem_get(&rdev->ibdev, start, length, mr_access_flags); 3520 if (IS_ERR(umem)) { 3521 dev_err(rdev_to_dev(rdev), "Failed to get umem"); 3522 rc = -EFAULT; 3523 goto free_mrw; 3524 } 3525 mr->ib_umem = umem; 3526 3527 mr->qplib_mr.va = virt_addr; 3528 umem_pgs = ib_umem_page_count(umem); 3529 if (!umem_pgs) { 3530 dev_err(rdev_to_dev(rdev), "umem is invalid!"); 3531 rc = -EINVAL; 3532 goto free_umem; 3533 } 3534 mr->qplib_mr.total_size = length; 3535 3536 pbl_tbl = kcalloc(umem_pgs, sizeof(u64 *), GFP_KERNEL); 3537 if (!pbl_tbl) { 3538 rc = -ENOMEM; 3539 goto free_umem; 3540 } 3541 3542 page_shift = __ffs(ib_umem_find_best_pgsz(umem, 3543 BNXT_RE_PAGE_SIZE_4K | BNXT_RE_PAGE_SIZE_2M, 3544 virt_addr)); 3545 3546 if (!bnxt_re_page_size_ok(page_shift)) { 3547 dev_err(rdev_to_dev(rdev), "umem page size unsupported!"); 3548 rc = -EFAULT; 3549 goto fail; 3550 } 3551 3552 if (page_shift == BNXT_RE_PAGE_SHIFT_4K && 3553 length > BNXT_RE_MAX_MR_SIZE_LOW) { 3554 dev_err(rdev_to_dev(rdev), "Requested MR Sz:%llu Max sup:%llu", 3555 length, (u64)BNXT_RE_MAX_MR_SIZE_LOW); 3556 rc = -EINVAL; 3557 goto fail; 3558 } 3559 3560 /* Map umem buf ptrs to the PBL */ 3561 umem_pgs = fill_umem_pbl_tbl(umem, pbl_tbl, page_shift); 3562 rc = bnxt_qplib_reg_mr(&rdev->qplib_res, &mr->qplib_mr, pbl_tbl, 3563 umem_pgs, false, 1 << page_shift); 3564 if (rc) { 3565 dev_err(rdev_to_dev(rdev), "Failed to register user MR"); 3566 goto fail; 3567 } 3568 3569 kfree(pbl_tbl); 3570 3571 mr->ib_mr.lkey = mr->qplib_mr.lkey; 3572 mr->ib_mr.rkey = mr->qplib_mr.lkey; 3573 atomic_inc(&rdev->mr_count); 3574 3575 return &mr->ib_mr; 3576 fail: 3577 kfree(pbl_tbl); 3578 free_umem: 3579 ib_umem_release(umem); 3580 free_mrw: 3581 bnxt_qplib_free_mrw(&rdev->qplib_res, &mr->qplib_mr); 3582 free_mr: 3583 kfree(mr); 3584 return ERR_PTR(rc); 3585 } 3586 3587 int bnxt_re_alloc_ucontext(struct ib_ucontext *ctx, struct ib_udata *udata) 3588 { 3589 struct ib_device *ibdev = ctx->device; 3590 struct bnxt_re_ucontext *uctx = 3591 container_of(ctx, struct bnxt_re_ucontext, ib_uctx); 3592 struct bnxt_re_dev *rdev = to_bnxt_re_dev(ibdev, ibdev); 3593 struct bnxt_qplib_dev_attr *dev_attr = &rdev->dev_attr; 3594 struct bnxt_re_uctx_resp resp; 3595 u32 chip_met_rev_num = 0; 3596 int rc; 3597 3598 dev_dbg(rdev_to_dev(rdev), "ABI version requested %u", 3599 ibdev->ops.uverbs_abi_ver); 3600 3601 if (ibdev->ops.uverbs_abi_ver != BNXT_RE_ABI_VERSION) { 3602 dev_dbg(rdev_to_dev(rdev), " is different from the device %d ", 3603 BNXT_RE_ABI_VERSION); 3604 return -EPERM; 3605 } 3606 3607 uctx->rdev = rdev; 3608 3609 uctx->shpg = (void *)__get_free_page(GFP_KERNEL); 3610 if (!uctx->shpg) { 3611 rc = -ENOMEM; 3612 goto fail; 3613 } 3614 spin_lock_init(&uctx->sh_lock); 3615 3616 resp.comp_mask = BNXT_RE_UCNTX_CMASK_HAVE_CCTX; 3617 chip_met_rev_num = rdev->chip_ctx.chip_num; 3618 chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_rev & 0xFF) << 3619 BNXT_RE_CHIP_ID0_CHIP_REV_SFT; 3620 chip_met_rev_num |= ((u32)rdev->chip_ctx.chip_metal & 0xFF) << 3621 BNXT_RE_CHIP_ID0_CHIP_MET_SFT; 3622 resp.chip_id0 = chip_met_rev_num; 3623 /* Future extension of chip info */ 3624 resp.chip_id1 = 0; 3625 /*Temp, Use xa_alloc instead */ 3626 resp.dev_id = rdev->en_dev->pdev->devfn; 3627 resp.max_qp = rdev->qplib_ctx.qpc_count; 3628 resp.pg_size = PAGE_SIZE; 3629 resp.cqe_sz = sizeof(struct cq_base); 3630 resp.max_cqd = dev_attr->max_cq_wqes; 3631 resp.rsvd = 0; 3632 3633 rc = ib_copy_to_udata(udata, &resp, min(udata->outlen, sizeof(resp))); 3634 if (rc) { 3635 dev_err(rdev_to_dev(rdev), "Failed to copy user context"); 3636 rc = -EFAULT; 3637 goto cfail; 3638 } 3639 3640 return 0; 3641 cfail: 3642 free_page((unsigned long)uctx->shpg); 3643 uctx->shpg = NULL; 3644 fail: 3645 return rc; 3646 } 3647 3648 void bnxt_re_dealloc_ucontext(struct ib_ucontext *ib_uctx) 3649 { 3650 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3651 struct bnxt_re_ucontext, 3652 ib_uctx); 3653 3654 struct bnxt_re_dev *rdev = uctx->rdev; 3655 3656 if (uctx->shpg) 3657 free_page((unsigned long)uctx->shpg); 3658 3659 if (uctx->dpi.dbr) { 3660 /* Free DPI only if this is the first PD allocated by the 3661 * application and mark the context dpi as NULL 3662 */ 3663 bnxt_qplib_dealloc_dpi(&rdev->qplib_res, 3664 &rdev->qplib_res.dpi_tbl, &uctx->dpi); 3665 uctx->dpi.dbr = NULL; 3666 } 3667 } 3668 3669 /* Helper function to mmap the virtual memory from user app */ 3670 int bnxt_re_mmap(struct ib_ucontext *ib_uctx, struct vm_area_struct *vma) 3671 { 3672 struct bnxt_re_ucontext *uctx = container_of(ib_uctx, 3673 struct bnxt_re_ucontext, 3674 ib_uctx); 3675 struct bnxt_re_dev *rdev = uctx->rdev; 3676 u64 pfn; 3677 3678 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 3679 return -EINVAL; 3680 3681 if (vma->vm_pgoff) { 3682 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 3683 if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff, 3684 PAGE_SIZE, vma->vm_page_prot)) { 3685 dev_err(rdev_to_dev(rdev), "Failed to map DPI"); 3686 return -EAGAIN; 3687 } 3688 } else { 3689 pfn = virt_to_phys(uctx->shpg) >> PAGE_SHIFT; 3690 if (remap_pfn_range(vma, vma->vm_start, 3691 pfn, PAGE_SIZE, vma->vm_page_prot)) { 3692 dev_err(rdev_to_dev(rdev), 3693 "Failed to map shared page"); 3694 return -EAGAIN; 3695 } 3696 } 3697 3698 return 0; 3699 } 3700