1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * 4 * hda_intel.c - Implementation of primary alsa driver code base 5 * for Intel HD Audio. 6 * 7 * Copyright(c) 2004 Intel Corporation. All rights reserved. 8 * 9 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> 10 * PeiSen Hou <pshou@realtek.com.tw> 11 * 12 * CONTACTS: 13 * 14 * Matt Jared matt.jared@intel.com 15 * Andy Kopp andy.kopp@intel.com 16 * Dan Kogan dan.d.kogan@intel.com 17 * 18 * CHANGES: 19 * 20 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou 21 */ 22 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/moduleparam.h> 29 #include <linux/init.h> 30 #include <linux/slab.h> 31 #include <linux/pci.h> 32 #include <linux/mutex.h> 33 #include <linux/io.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/clocksource.h> 36 #include <linux/time.h> 37 #include <linux/completion.h> 38 #include <linux/acpi.h> 39 #include <linux/pgtable.h> 40 41 #ifdef CONFIG_X86 42 /* for snoop control */ 43 #include <asm/set_memory.h> 44 #include <asm/cpufeature.h> 45 #endif 46 #include <sound/core.h> 47 #include <sound/initval.h> 48 #include <sound/hdaudio.h> 49 #include <sound/hda_i915.h> 50 #include <sound/intel-dsp-config.h> 51 #include <linux/vgaarb.h> 52 #include <linux/vga_switcheroo.h> 53 #include <linux/firmware.h> 54 #include <sound/hda_codec.h> 55 #include "hda_controller.h" 56 #include "hda_intel.h" 57 58 #define CREATE_TRACE_POINTS 59 #include "hda_intel_trace.h" 60 61 /* position fix mode */ 62 enum { 63 POS_FIX_AUTO, 64 POS_FIX_LPIB, 65 POS_FIX_POSBUF, 66 POS_FIX_VIACOMBO, 67 POS_FIX_COMBO, 68 POS_FIX_SKL, 69 POS_FIX_FIFO, 70 }; 71 72 /* Defines for ATI HD Audio support in SB450 south bridge */ 73 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42 74 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02 75 76 /* Defines for Nvidia HDA support */ 77 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e 78 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f 79 #define NVIDIA_HDA_ISTRM_COH 0x4d 80 #define NVIDIA_HDA_OSTRM_COH 0x4c 81 #define NVIDIA_HDA_ENABLE_COHBIT 0x01 82 83 /* Defines for Intel SCH HDA snoop control */ 84 #define INTEL_HDA_CGCTL 0x48 85 #define INTEL_HDA_CGCTL_MISCBDCGE (0x1 << 6) 86 #define INTEL_SCH_HDA_DEVC 0x78 87 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11) 88 89 /* Define VIA HD Audio Device ID*/ 90 #define VIA_HDAC_DEVICE_ID 0x3288 91 92 /* max number of SDs */ 93 /* ICH, ATI and VIA have 4 playback and 4 capture */ 94 #define ICH6_NUM_CAPTURE 4 95 #define ICH6_NUM_PLAYBACK 4 96 97 /* ULI has 6 playback and 5 capture */ 98 #define ULI_NUM_CAPTURE 5 99 #define ULI_NUM_PLAYBACK 6 100 101 /* ATI HDMI may have up to 8 playbacks and 0 capture */ 102 #define ATIHDMI_NUM_CAPTURE 0 103 #define ATIHDMI_NUM_PLAYBACK 8 104 105 /* TERA has 4 playback and 3 capture */ 106 #define TERA_NUM_CAPTURE 3 107 #define TERA_NUM_PLAYBACK 4 108 109 110 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; 111 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; 112 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; 113 static char *model[SNDRV_CARDS]; 114 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 115 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 116 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1}; 117 static int probe_only[SNDRV_CARDS]; 118 static int jackpoll_ms[SNDRV_CARDS]; 119 static int single_cmd = -1; 120 static int enable_msi = -1; 121 #ifdef CONFIG_SND_HDA_PATCH_LOADER 122 static char *patch[SNDRV_CARDS]; 123 #endif 124 #ifdef CONFIG_SND_HDA_INPUT_BEEP 125 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 126 CONFIG_SND_HDA_INPUT_BEEP_MODE}; 127 #endif 128 static bool dmic_detect = 1; 129 130 module_param_array(index, int, NULL, 0444); 131 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface."); 132 module_param_array(id, charp, NULL, 0444); 133 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface."); 134 module_param_array(enable, bool, NULL, 0444); 135 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface."); 136 module_param_array(model, charp, NULL, 0444); 137 MODULE_PARM_DESC(model, "Use the given board model."); 138 module_param_array(position_fix, int, NULL, 0444); 139 MODULE_PARM_DESC(position_fix, "DMA pointer read method." 140 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO, 5 = SKL+, 6 = FIFO)."); 141 module_param_array(bdl_pos_adj, int, NULL, 0644); 142 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset."); 143 module_param_array(probe_mask, int, NULL, 0444); 144 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1)."); 145 module_param_array(probe_only, int, NULL, 0444); 146 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization."); 147 module_param_array(jackpoll_ms, int, NULL, 0444); 148 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)"); 149 module_param(single_cmd, bint, 0444); 150 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs " 151 "(for debugging only)."); 152 module_param(enable_msi, bint, 0444); 153 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)"); 154 #ifdef CONFIG_SND_HDA_PATCH_LOADER 155 module_param_array(patch, charp, NULL, 0444); 156 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface."); 157 #endif 158 #ifdef CONFIG_SND_HDA_INPUT_BEEP 159 module_param_array(beep_mode, bool, NULL, 0444); 160 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode " 161 "(0=off, 1=on) (default=1)."); 162 #endif 163 module_param(dmic_detect, bool, 0444); 164 MODULE_PARM_DESC(dmic_detect, "Allow DSP driver selection (bypass this driver) " 165 "(0=off, 1=on) (default=1); " 166 "deprecated, use snd-intel-dspcfg.dsp_driver option instead"); 167 168 #ifdef CONFIG_PM 169 static int param_set_xint(const char *val, const struct kernel_param *kp); 170 static const struct kernel_param_ops param_ops_xint = { 171 .set = param_set_xint, 172 .get = param_get_int, 173 }; 174 #define param_check_xint param_check_int 175 176 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT; 177 module_param(power_save, xint, 0644); 178 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout " 179 "(in second, 0 = disable)."); 180 181 static bool pm_blacklist = true; 182 module_param(pm_blacklist, bool, 0644); 183 MODULE_PARM_DESC(pm_blacklist, "Enable power-management denylist"); 184 185 /* reset the HD-audio controller in power save mode. 186 * this may give more power-saving, but will take longer time to 187 * wake up. 188 */ 189 static bool power_save_controller = 1; 190 module_param(power_save_controller, bool, 0644); 191 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode."); 192 #else 193 #define power_save 0 194 #endif /* CONFIG_PM */ 195 196 static int align_buffer_size = -1; 197 module_param(align_buffer_size, bint, 0644); 198 MODULE_PARM_DESC(align_buffer_size, 199 "Force buffer and period sizes to be multiple of 128 bytes."); 200 201 #ifdef CONFIG_X86 202 static int hda_snoop = -1; 203 module_param_named(snoop, hda_snoop, bint, 0444); 204 MODULE_PARM_DESC(snoop, "Enable/disable snooping"); 205 #else 206 #define hda_snoop true 207 #endif 208 209 210 MODULE_LICENSE("GPL"); 211 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6}," 212 "{Intel, ICH6M}," 213 "{Intel, ICH7}," 214 "{Intel, ESB2}," 215 "{Intel, ICH8}," 216 "{Intel, ICH9}," 217 "{Intel, ICH10}," 218 "{Intel, PCH}," 219 "{Intel, CPT}," 220 "{Intel, PPT}," 221 "{Intel, LPT}," 222 "{Intel, LPT_LP}," 223 "{Intel, WPT_LP}," 224 "{Intel, SPT}," 225 "{Intel, SPT_LP}," 226 "{Intel, HPT}," 227 "{Intel, PBG}," 228 "{Intel, SCH}," 229 "{ATI, SB450}," 230 "{ATI, SB600}," 231 "{ATI, RS600}," 232 "{ATI, RS690}," 233 "{ATI, RS780}," 234 "{ATI, R600}," 235 "{ATI, RV630}," 236 "{ATI, RV610}," 237 "{ATI, RV670}," 238 "{ATI, RV635}," 239 "{ATI, RV620}," 240 "{ATI, RV770}," 241 "{VIA, VT8251}," 242 "{VIA, VT8237A}," 243 "{SiS, SIS966}," 244 "{ULI, M5461}}"); 245 MODULE_DESCRIPTION("Intel HDA driver"); 246 247 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) 248 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI) 249 #define SUPPORT_VGA_SWITCHEROO 250 #endif 251 #endif 252 253 254 /* 255 */ 256 257 /* driver types */ 258 enum { 259 AZX_DRIVER_ICH, 260 AZX_DRIVER_PCH, 261 AZX_DRIVER_SCH, 262 AZX_DRIVER_SKL, 263 AZX_DRIVER_HDMI, 264 AZX_DRIVER_ATI, 265 AZX_DRIVER_ATIHDMI, 266 AZX_DRIVER_ATIHDMI_NS, 267 AZX_DRIVER_VIA, 268 AZX_DRIVER_SIS, 269 AZX_DRIVER_ULI, 270 AZX_DRIVER_NVIDIA, 271 AZX_DRIVER_TERA, 272 AZX_DRIVER_CTX, 273 AZX_DRIVER_CTHDA, 274 AZX_DRIVER_CMEDIA, 275 AZX_DRIVER_ZHAOXIN, 276 AZX_DRIVER_GENERIC, 277 AZX_NUM_DRIVERS, /* keep this as last entry */ 278 }; 279 280 #define azx_get_snoop_type(chip) \ 281 (((chip)->driver_caps & AZX_DCAPS_SNOOP_MASK) >> 10) 282 #define AZX_DCAPS_SNOOP_TYPE(type) ((AZX_SNOOP_TYPE_ ## type) << 10) 283 284 /* quirks for old Intel chipsets */ 285 #define AZX_DCAPS_INTEL_ICH \ 286 (AZX_DCAPS_OLD_SSYNC | AZX_DCAPS_NO_ALIGN_BUFSIZE) 287 288 /* quirks for Intel PCH */ 289 #define AZX_DCAPS_INTEL_PCH_BASE \ 290 (AZX_DCAPS_NO_ALIGN_BUFSIZE | AZX_DCAPS_COUNT_LPIB_DELAY |\ 291 AZX_DCAPS_SNOOP_TYPE(SCH)) 292 293 /* PCH up to IVB; no runtime PM; bind with i915 gfx */ 294 #define AZX_DCAPS_INTEL_PCH_NOPM \ 295 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 296 297 /* PCH for HSW/BDW; with runtime PM */ 298 /* no i915 binding for this as HSW/BDW has another controller for HDMI */ 299 #define AZX_DCAPS_INTEL_PCH \ 300 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 301 AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP) 302 303 /* HSW HDMI */ 304 #define AZX_DCAPS_INTEL_HASWELL \ 305 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_COUNT_LPIB_DELAY |\ 306 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 307 AZX_DCAPS_SNOOP_TYPE(SCH)) 308 309 /* Broadwell HDMI can't use position buffer reliably, force to use LPIB */ 310 #define AZX_DCAPS_INTEL_BROADWELL \ 311 (/*AZX_DCAPS_ALIGN_BUFSIZE |*/ AZX_DCAPS_POSFIX_LPIB |\ 312 AZX_DCAPS_PM_RUNTIME | AZX_DCAPS_I915_COMPONENT |\ 313 AZX_DCAPS_SNOOP_TYPE(SCH)) 314 315 #define AZX_DCAPS_INTEL_BAYTRAIL \ 316 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_I915_COMPONENT) 317 318 #define AZX_DCAPS_INTEL_BRASWELL \ 319 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 320 AZX_DCAPS_I915_COMPONENT) 321 322 #define AZX_DCAPS_INTEL_SKYLAKE \ 323 (AZX_DCAPS_INTEL_PCH_BASE | AZX_DCAPS_PM_RUNTIME |\ 324 AZX_DCAPS_SEPARATE_STREAM_TAG | AZX_DCAPS_I915_COMPONENT) 325 326 #define AZX_DCAPS_INTEL_BROXTON AZX_DCAPS_INTEL_SKYLAKE 327 328 /* quirks for ATI SB / AMD Hudson */ 329 #define AZX_DCAPS_PRESET_ATI_SB \ 330 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB |\ 331 AZX_DCAPS_SNOOP_TYPE(ATI)) 332 333 /* quirks for ATI/AMD HDMI */ 334 #define AZX_DCAPS_PRESET_ATI_HDMI \ 335 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_POSFIX_LPIB|\ 336 AZX_DCAPS_NO_MSI64) 337 338 /* quirks for ATI HDMI with snoop off */ 339 #define AZX_DCAPS_PRESET_ATI_HDMI_NS \ 340 (AZX_DCAPS_PRESET_ATI_HDMI | AZX_DCAPS_SNOOP_OFF) 341 342 /* quirks for AMD SB */ 343 #define AZX_DCAPS_PRESET_AMD_SB \ 344 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_AMD_WORKAROUND |\ 345 AZX_DCAPS_SNOOP_TYPE(ATI) | AZX_DCAPS_PM_RUNTIME) 346 347 /* quirks for Nvidia */ 348 #define AZX_DCAPS_PRESET_NVIDIA \ 349 (AZX_DCAPS_NO_MSI | AZX_DCAPS_CORBRP_SELF_CLEAR |\ 350 AZX_DCAPS_SNOOP_TYPE(NVIDIA)) 351 352 #define AZX_DCAPS_PRESET_CTHDA \ 353 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB |\ 354 AZX_DCAPS_NO_64BIT |\ 355 AZX_DCAPS_4K_BDLE_BOUNDARY | AZX_DCAPS_SNOOP_OFF) 356 357 /* 358 * vga_switcheroo support 359 */ 360 #ifdef SUPPORT_VGA_SWITCHEROO 361 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo) 362 #define needs_eld_notify_link(chip) ((chip)->bus.keep_power) 363 #else 364 #define use_vga_switcheroo(chip) 0 365 #define needs_eld_notify_link(chip) false 366 #endif 367 368 #define CONTROLLER_IN_GPU(pci) (((pci)->device == 0x0a0c) || \ 369 ((pci)->device == 0x0c0c) || \ 370 ((pci)->device == 0x0d0c) || \ 371 ((pci)->device == 0x160c)) 372 373 #define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) 374 375 static const char * const driver_short_names[] = { 376 [AZX_DRIVER_ICH] = "HDA Intel", 377 [AZX_DRIVER_PCH] = "HDA Intel PCH", 378 [AZX_DRIVER_SCH] = "HDA Intel MID", 379 [AZX_DRIVER_SKL] = "HDA Intel PCH", /* kept old name for compatibility */ 380 [AZX_DRIVER_HDMI] = "HDA Intel HDMI", 381 [AZX_DRIVER_ATI] = "HDA ATI SB", 382 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI", 383 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI", 384 [AZX_DRIVER_VIA] = "HDA VIA VT82xx", 385 [AZX_DRIVER_SIS] = "HDA SIS966", 386 [AZX_DRIVER_ULI] = "HDA ULI M5461", 387 [AZX_DRIVER_NVIDIA] = "HDA NVidia", 388 [AZX_DRIVER_TERA] = "HDA Teradici", 389 [AZX_DRIVER_CTX] = "HDA Creative", 390 [AZX_DRIVER_CTHDA] = "HDA Creative", 391 [AZX_DRIVER_CMEDIA] = "HDA C-Media", 392 [AZX_DRIVER_ZHAOXIN] = "HDA Zhaoxin", 393 [AZX_DRIVER_GENERIC] = "HD-Audio Generic", 394 }; 395 396 static int azx_acquire_irq(struct azx *chip, int do_disconnect); 397 static void set_default_power_save(struct azx *chip); 398 399 /* 400 * initialize the PCI registers 401 */ 402 /* update bits in a PCI register byte */ 403 static void update_pci_byte(struct pci_dev *pci, unsigned int reg, 404 unsigned char mask, unsigned char val) 405 { 406 unsigned char data; 407 408 pci_read_config_byte(pci, reg, &data); 409 data &= ~mask; 410 data |= (val & mask); 411 pci_write_config_byte(pci, reg, data); 412 } 413 414 static void azx_init_pci(struct azx *chip) 415 { 416 int snoop_type = azx_get_snoop_type(chip); 417 418 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44) 419 * TCSEL == Traffic Class Select Register, which sets PCI express QOS 420 * Ensuring these bits are 0 clears playback static on some HD Audio 421 * codecs. 422 * The PCI register TCSEL is defined in the Intel manuals. 423 */ 424 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) { 425 dev_dbg(chip->card->dev, "Clearing TCSEL\n"); 426 update_pci_byte(chip->pci, AZX_PCIREG_TCSEL, 0x07, 0); 427 } 428 429 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio, 430 * we need to enable snoop. 431 */ 432 if (snoop_type == AZX_SNOOP_TYPE_ATI) { 433 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n", 434 azx_snoop(chip)); 435 update_pci_byte(chip->pci, 436 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07, 437 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0); 438 } 439 440 /* For NVIDIA HDA, enable snoop */ 441 if (snoop_type == AZX_SNOOP_TYPE_NVIDIA) { 442 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n", 443 azx_snoop(chip)); 444 update_pci_byte(chip->pci, 445 NVIDIA_HDA_TRANSREG_ADDR, 446 0x0f, NVIDIA_HDA_ENABLE_COHBITS); 447 update_pci_byte(chip->pci, 448 NVIDIA_HDA_ISTRM_COH, 449 0x01, NVIDIA_HDA_ENABLE_COHBIT); 450 update_pci_byte(chip->pci, 451 NVIDIA_HDA_OSTRM_COH, 452 0x01, NVIDIA_HDA_ENABLE_COHBIT); 453 } 454 455 /* Enable SCH/PCH snoop if needed */ 456 if (snoop_type == AZX_SNOOP_TYPE_SCH) { 457 unsigned short snoop; 458 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop); 459 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) || 460 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) { 461 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP; 462 if (!azx_snoop(chip)) 463 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP; 464 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop); 465 pci_read_config_word(chip->pci, 466 INTEL_SCH_HDA_DEVC, &snoop); 467 } 468 dev_dbg(chip->card->dev, "SCH snoop: %s\n", 469 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ? 470 "Disabled" : "Enabled"); 471 } 472 } 473 474 /* 475 * In BXT-P A0, HD-Audio DMA requests is later than expected, 476 * and makes an audio stream sensitive to system latencies when 477 * 24/32 bits are playing. 478 * Adjusting threshold of DMA fifo to force the DMA request 479 * sooner to improve latency tolerance at the expense of power. 480 */ 481 static void bxt_reduce_dma_latency(struct azx *chip) 482 { 483 u32 val; 484 485 val = azx_readl(chip, VS_EM4L); 486 val &= (0x3 << 20); 487 azx_writel(chip, VS_EM4L, val); 488 } 489 490 /* 491 * ML_LCAP bits: 492 * bit 0: 6 MHz Supported 493 * bit 1: 12 MHz Supported 494 * bit 2: 24 MHz Supported 495 * bit 3: 48 MHz Supported 496 * bit 4: 96 MHz Supported 497 * bit 5: 192 MHz Supported 498 */ 499 static int intel_get_lctl_scf(struct azx *chip) 500 { 501 struct hdac_bus *bus = azx_bus(chip); 502 static const int preferred_bits[] = { 2, 3, 1, 4, 5 }; 503 u32 val, t; 504 int i; 505 506 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCAP); 507 508 for (i = 0; i < ARRAY_SIZE(preferred_bits); i++) { 509 t = preferred_bits[i]; 510 if (val & (1 << t)) 511 return t; 512 } 513 514 dev_warn(chip->card->dev, "set audio clock frequency to 6MHz"); 515 return 0; 516 } 517 518 static int intel_ml_lctl_set_power(struct azx *chip, int state) 519 { 520 struct hdac_bus *bus = azx_bus(chip); 521 u32 val; 522 int timeout; 523 524 /* 525 * the codecs are sharing the first link setting by default 526 * If other links are enabled for stream, they need similar fix 527 */ 528 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 529 val &= ~AZX_MLCTL_SPA; 530 val |= state << AZX_MLCTL_SPA_SHIFT; 531 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 532 /* wait for CPA */ 533 timeout = 50; 534 while (timeout) { 535 if (((readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL)) & 536 AZX_MLCTL_CPA) == (state << AZX_MLCTL_CPA_SHIFT)) 537 return 0; 538 timeout--; 539 udelay(10); 540 } 541 542 return -1; 543 } 544 545 static void intel_init_lctl(struct azx *chip) 546 { 547 struct hdac_bus *bus = azx_bus(chip); 548 u32 val; 549 int ret; 550 551 /* 0. check lctl register value is correct or not */ 552 val = readl(bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 553 /* if SCF is already set, let's use it */ 554 if ((val & ML_LCTL_SCF_MASK) != 0) 555 return; 556 557 /* 558 * Before operating on SPA, CPA must match SPA. 559 * Any deviation may result in undefined behavior. 560 */ 561 if (((val & AZX_MLCTL_SPA) >> AZX_MLCTL_SPA_SHIFT) != 562 ((val & AZX_MLCTL_CPA) >> AZX_MLCTL_CPA_SHIFT)) 563 return; 564 565 /* 1. turn link down: set SPA to 0 and wait CPA to 0 */ 566 ret = intel_ml_lctl_set_power(chip, 0); 567 udelay(100); 568 if (ret) 569 goto set_spa; 570 571 /* 2. update SCF to select a properly audio clock*/ 572 val &= ~ML_LCTL_SCF_MASK; 573 val |= intel_get_lctl_scf(chip); 574 writel(val, bus->mlcap + AZX_ML_BASE + AZX_REG_ML_LCTL); 575 576 set_spa: 577 /* 4. turn link up: set SPA to 1 and wait CPA to 1 */ 578 intel_ml_lctl_set_power(chip, 1); 579 udelay(100); 580 } 581 582 static void hda_intel_init_chip(struct azx *chip, bool full_reset) 583 { 584 struct hdac_bus *bus = azx_bus(chip); 585 struct pci_dev *pci = chip->pci; 586 u32 val; 587 588 snd_hdac_set_codec_wakeup(bus, true); 589 if (chip->driver_type == AZX_DRIVER_SKL) { 590 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 591 val = val & ~INTEL_HDA_CGCTL_MISCBDCGE; 592 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 593 } 594 azx_init_chip(chip, full_reset); 595 if (chip->driver_type == AZX_DRIVER_SKL) { 596 pci_read_config_dword(pci, INTEL_HDA_CGCTL, &val); 597 val = val | INTEL_HDA_CGCTL_MISCBDCGE; 598 pci_write_config_dword(pci, INTEL_HDA_CGCTL, val); 599 } 600 601 snd_hdac_set_codec_wakeup(bus, false); 602 603 /* reduce dma latency to avoid noise */ 604 if (IS_BXT(pci)) 605 bxt_reduce_dma_latency(chip); 606 607 if (bus->mlcap != NULL) 608 intel_init_lctl(chip); 609 } 610 611 /* calculate runtime delay from LPIB */ 612 static int azx_get_delay_from_lpib(struct azx *chip, struct azx_dev *azx_dev, 613 unsigned int pos) 614 { 615 struct snd_pcm_substream *substream = azx_dev->core.substream; 616 int stream = substream->stream; 617 unsigned int lpib_pos = azx_get_pos_lpib(chip, azx_dev); 618 int delay; 619 620 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 621 delay = pos - lpib_pos; 622 else 623 delay = lpib_pos - pos; 624 if (delay < 0) { 625 if (delay >= azx_dev->core.delay_negative_threshold) 626 delay = 0; 627 else 628 delay += azx_dev->core.bufsize; 629 } 630 631 if (delay >= azx_dev->core.period_bytes) { 632 dev_info(chip->card->dev, 633 "Unstable LPIB (%d >= %d); disabling LPIB delay counting\n", 634 delay, azx_dev->core.period_bytes); 635 delay = 0; 636 chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY; 637 chip->get_delay[stream] = NULL; 638 } 639 640 return bytes_to_frames(substream->runtime, delay); 641 } 642 643 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev); 644 645 /* called from IRQ */ 646 static int azx_position_check(struct azx *chip, struct azx_dev *azx_dev) 647 { 648 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 649 int ok; 650 651 ok = azx_position_ok(chip, azx_dev); 652 if (ok == 1) { 653 azx_dev->irq_pending = 0; 654 return ok; 655 } else if (ok == 0) { 656 /* bogus IRQ, process it later */ 657 azx_dev->irq_pending = 1; 658 schedule_work(&hda->irq_pending_work); 659 } 660 return 0; 661 } 662 663 #define display_power(chip, enable) \ 664 snd_hdac_display_power(azx_bus(chip), HDA_CODEC_IDX_CONTROLLER, enable) 665 666 /* 667 * Check whether the current DMA position is acceptable for updating 668 * periods. Returns non-zero if it's OK. 669 * 670 * Many HD-audio controllers appear pretty inaccurate about 671 * the update-IRQ timing. The IRQ is issued before actually the 672 * data is processed. So, we need to process it afterwords in a 673 * workqueue. 674 */ 675 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev) 676 { 677 struct snd_pcm_substream *substream = azx_dev->core.substream; 678 int stream = substream->stream; 679 u32 wallclk; 680 unsigned int pos; 681 682 wallclk = azx_readl(chip, WALLCLK) - azx_dev->core.start_wallclk; 683 if (wallclk < (azx_dev->core.period_wallclk * 2) / 3) 684 return -1; /* bogus (too early) interrupt */ 685 686 if (chip->get_position[stream]) 687 pos = chip->get_position[stream](chip, azx_dev); 688 else { /* use the position buffer as default */ 689 pos = azx_get_pos_posbuf(chip, azx_dev); 690 if (!pos || pos == (u32)-1) { 691 dev_info(chip->card->dev, 692 "Invalid position buffer, using LPIB read method instead.\n"); 693 chip->get_position[stream] = azx_get_pos_lpib; 694 if (chip->get_position[0] == azx_get_pos_lpib && 695 chip->get_position[1] == azx_get_pos_lpib) 696 azx_bus(chip)->use_posbuf = false; 697 pos = azx_get_pos_lpib(chip, azx_dev); 698 chip->get_delay[stream] = NULL; 699 } else { 700 chip->get_position[stream] = azx_get_pos_posbuf; 701 if (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY) 702 chip->get_delay[stream] = azx_get_delay_from_lpib; 703 } 704 } 705 706 if (pos >= azx_dev->core.bufsize) 707 pos = 0; 708 709 if (WARN_ONCE(!azx_dev->core.period_bytes, 710 "hda-intel: zero azx_dev->period_bytes")) 711 return -1; /* this shouldn't happen! */ 712 if (wallclk < (azx_dev->core.period_wallclk * 5) / 4 && 713 pos % azx_dev->core.period_bytes > azx_dev->core.period_bytes / 2) 714 /* NG - it's below the first next period boundary */ 715 return chip->bdl_pos_adj ? 0 : -1; 716 azx_dev->core.start_wallclk += wallclk; 717 return 1; /* OK, it's fine */ 718 } 719 720 /* 721 * The work for pending PCM period updates. 722 */ 723 static void azx_irq_pending_work(struct work_struct *work) 724 { 725 struct hda_intel *hda = container_of(work, struct hda_intel, irq_pending_work); 726 struct azx *chip = &hda->chip; 727 struct hdac_bus *bus = azx_bus(chip); 728 struct hdac_stream *s; 729 int pending, ok; 730 731 if (!hda->irq_pending_warned) { 732 dev_info(chip->card->dev, 733 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n", 734 chip->card->number); 735 hda->irq_pending_warned = 1; 736 } 737 738 for (;;) { 739 pending = 0; 740 spin_lock_irq(&bus->reg_lock); 741 list_for_each_entry(s, &bus->stream_list, list) { 742 struct azx_dev *azx_dev = stream_to_azx_dev(s); 743 if (!azx_dev->irq_pending || 744 !s->substream || 745 !s->running) 746 continue; 747 ok = azx_position_ok(chip, azx_dev); 748 if (ok > 0) { 749 azx_dev->irq_pending = 0; 750 spin_unlock(&bus->reg_lock); 751 snd_pcm_period_elapsed(s->substream); 752 spin_lock(&bus->reg_lock); 753 } else if (ok < 0) { 754 pending = 0; /* too early */ 755 } else 756 pending++; 757 } 758 spin_unlock_irq(&bus->reg_lock); 759 if (!pending) 760 return; 761 msleep(1); 762 } 763 } 764 765 /* clear irq_pending flags and assure no on-going workq */ 766 static void azx_clear_irq_pending(struct azx *chip) 767 { 768 struct hdac_bus *bus = azx_bus(chip); 769 struct hdac_stream *s; 770 771 spin_lock_irq(&bus->reg_lock); 772 list_for_each_entry(s, &bus->stream_list, list) { 773 struct azx_dev *azx_dev = stream_to_azx_dev(s); 774 azx_dev->irq_pending = 0; 775 } 776 spin_unlock_irq(&bus->reg_lock); 777 } 778 779 static int azx_acquire_irq(struct azx *chip, int do_disconnect) 780 { 781 struct hdac_bus *bus = azx_bus(chip); 782 783 if (request_irq(chip->pci->irq, azx_interrupt, 784 chip->msi ? 0 : IRQF_SHARED, 785 chip->card->irq_descr, chip)) { 786 dev_err(chip->card->dev, 787 "unable to grab IRQ %d, disabling device\n", 788 chip->pci->irq); 789 if (do_disconnect) 790 snd_card_disconnect(chip->card); 791 return -1; 792 } 793 bus->irq = chip->pci->irq; 794 chip->card->sync_irq = bus->irq; 795 pci_intx(chip->pci, !chip->msi); 796 return 0; 797 } 798 799 /* get the current DMA position with correction on VIA chips */ 800 static unsigned int azx_via_get_position(struct azx *chip, 801 struct azx_dev *azx_dev) 802 { 803 unsigned int link_pos, mini_pos, bound_pos; 804 unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos; 805 unsigned int fifo_size; 806 807 link_pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 808 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 809 /* Playback, no problem using link position */ 810 return link_pos; 811 } 812 813 /* Capture */ 814 /* For new chipset, 815 * use mod to get the DMA position just like old chipset 816 */ 817 mod_dma_pos = le32_to_cpu(*azx_dev->core.posbuf); 818 mod_dma_pos %= azx_dev->core.period_bytes; 819 820 fifo_size = azx_stream(azx_dev)->fifo_size - 1; 821 822 if (azx_dev->insufficient) { 823 /* Link position never gather than FIFO size */ 824 if (link_pos <= fifo_size) 825 return 0; 826 827 azx_dev->insufficient = 0; 828 } 829 830 if (link_pos <= fifo_size) 831 mini_pos = azx_dev->core.bufsize + link_pos - fifo_size; 832 else 833 mini_pos = link_pos - fifo_size; 834 835 /* Find nearest previous boudary */ 836 mod_mini_pos = mini_pos % azx_dev->core.period_bytes; 837 mod_link_pos = link_pos % azx_dev->core.period_bytes; 838 if (mod_link_pos >= fifo_size) 839 bound_pos = link_pos - mod_link_pos; 840 else if (mod_dma_pos >= mod_mini_pos) 841 bound_pos = mini_pos - mod_mini_pos; 842 else { 843 bound_pos = mini_pos - mod_mini_pos + azx_dev->core.period_bytes; 844 if (bound_pos >= azx_dev->core.bufsize) 845 bound_pos = 0; 846 } 847 848 /* Calculate real DMA position we want */ 849 return bound_pos + mod_dma_pos; 850 } 851 852 #define AMD_FIFO_SIZE 32 853 854 /* get the current DMA position with FIFO size correction */ 855 static unsigned int azx_get_pos_fifo(struct azx *chip, struct azx_dev *azx_dev) 856 { 857 struct snd_pcm_substream *substream = azx_dev->core.substream; 858 struct snd_pcm_runtime *runtime = substream->runtime; 859 unsigned int pos, delay; 860 861 pos = snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev)); 862 if (!runtime) 863 return pos; 864 865 runtime->delay = AMD_FIFO_SIZE; 866 delay = frames_to_bytes(runtime, AMD_FIFO_SIZE); 867 if (azx_dev->insufficient) { 868 if (pos < delay) { 869 delay = pos; 870 runtime->delay = bytes_to_frames(runtime, pos); 871 } else { 872 azx_dev->insufficient = 0; 873 } 874 } 875 876 /* correct the DMA position for capture stream */ 877 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 878 if (pos < delay) 879 pos += azx_dev->core.bufsize; 880 pos -= delay; 881 } 882 883 return pos; 884 } 885 886 static int azx_get_delay_from_fifo(struct azx *chip, struct azx_dev *azx_dev, 887 unsigned int pos) 888 { 889 struct snd_pcm_substream *substream = azx_dev->core.substream; 890 891 /* just read back the calculated value in the above */ 892 return substream->runtime->delay; 893 } 894 895 static unsigned int azx_skl_get_dpib_pos(struct azx *chip, 896 struct azx_dev *azx_dev) 897 { 898 return _snd_hdac_chip_readl(azx_bus(chip), 899 AZX_REG_VS_SDXDPIB_XBASE + 900 (AZX_REG_VS_SDXDPIB_XINTERVAL * 901 azx_dev->core.index)); 902 } 903 904 /* get the current DMA position with correction on SKL+ chips */ 905 static unsigned int azx_get_pos_skl(struct azx *chip, struct azx_dev *azx_dev) 906 { 907 /* DPIB register gives a more accurate position for playback */ 908 if (azx_dev->core.substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 909 return azx_skl_get_dpib_pos(chip, azx_dev); 910 911 /* For capture, we need to read posbuf, but it requires a delay 912 * for the possible boundary overlap; the read of DPIB fetches the 913 * actual posbuf 914 */ 915 udelay(20); 916 azx_skl_get_dpib_pos(chip, azx_dev); 917 return azx_get_pos_posbuf(chip, azx_dev); 918 } 919 920 #ifdef CONFIG_PM 921 static DEFINE_MUTEX(card_list_lock); 922 static LIST_HEAD(card_list); 923 924 static void azx_add_card_list(struct azx *chip) 925 { 926 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 927 mutex_lock(&card_list_lock); 928 list_add(&hda->list, &card_list); 929 mutex_unlock(&card_list_lock); 930 } 931 932 static void azx_del_card_list(struct azx *chip) 933 { 934 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 935 mutex_lock(&card_list_lock); 936 list_del_init(&hda->list); 937 mutex_unlock(&card_list_lock); 938 } 939 940 /* trigger power-save check at writing parameter */ 941 static int param_set_xint(const char *val, const struct kernel_param *kp) 942 { 943 struct hda_intel *hda; 944 struct azx *chip; 945 int prev = power_save; 946 int ret = param_set_int(val, kp); 947 948 if (ret || prev == power_save) 949 return ret; 950 951 mutex_lock(&card_list_lock); 952 list_for_each_entry(hda, &card_list, list) { 953 chip = &hda->chip; 954 if (!hda->probe_continued || chip->disabled) 955 continue; 956 snd_hda_set_power_save(&chip->bus, power_save * 1000); 957 } 958 mutex_unlock(&card_list_lock); 959 return 0; 960 } 961 962 /* 963 * power management 964 */ 965 static bool azx_is_pm_ready(struct snd_card *card) 966 { 967 struct azx *chip; 968 struct hda_intel *hda; 969 970 if (!card) 971 return false; 972 chip = card->private_data; 973 hda = container_of(chip, struct hda_intel, chip); 974 if (chip->disabled || hda->init_failed || !chip->running) 975 return false; 976 return true; 977 } 978 979 static void __azx_runtime_suspend(struct azx *chip) 980 { 981 azx_stop_chip(chip); 982 azx_enter_link_reset(chip); 983 azx_clear_irq_pending(chip); 984 display_power(chip, false); 985 } 986 987 static void __azx_runtime_resume(struct azx *chip, bool from_rt) 988 { 989 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 990 struct hdac_bus *bus = azx_bus(chip); 991 struct hda_codec *codec; 992 int status; 993 994 display_power(chip, true); 995 if (hda->need_i915_power) 996 snd_hdac_i915_set_bclk(bus); 997 998 /* Read STATESTS before controller reset */ 999 status = azx_readw(chip, STATESTS); 1000 1001 azx_init_pci(chip); 1002 hda_intel_init_chip(chip, true); 1003 1004 if (status && from_rt) { 1005 list_for_each_codec(codec, &chip->bus) 1006 if (!codec->relaxed_resume && 1007 (status & (1 << codec->addr))) 1008 schedule_delayed_work(&codec->jackpoll_work, 1009 codec->jackpoll_interval); 1010 } 1011 1012 /* power down again for link-controlled chips */ 1013 if (!hda->need_i915_power) 1014 display_power(chip, false); 1015 } 1016 1017 #ifdef CONFIG_PM_SLEEP 1018 static int azx_suspend(struct device *dev) 1019 { 1020 struct snd_card *card = dev_get_drvdata(dev); 1021 struct azx *chip; 1022 struct hdac_bus *bus; 1023 1024 if (!azx_is_pm_ready(card)) 1025 return 0; 1026 1027 chip = card->private_data; 1028 bus = azx_bus(chip); 1029 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot); 1030 /* An ugly workaround: direct call of __azx_runtime_suspend() and 1031 * __azx_runtime_resume() for old Intel platforms that suffer from 1032 * spurious wakeups after S3 suspend 1033 */ 1034 if (chip->driver_caps & AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP) 1035 __azx_runtime_suspend(chip); 1036 else 1037 pm_runtime_force_suspend(dev); 1038 if (bus->irq >= 0) { 1039 free_irq(bus->irq, chip); 1040 bus->irq = -1; 1041 chip->card->sync_irq = -1; 1042 } 1043 1044 if (chip->msi) 1045 pci_disable_msi(chip->pci); 1046 1047 trace_azx_suspend(chip); 1048 return 0; 1049 } 1050 1051 static int azx_resume(struct device *dev) 1052 { 1053 struct snd_card *card = dev_get_drvdata(dev); 1054 struct azx *chip; 1055 1056 if (!azx_is_pm_ready(card)) 1057 return 0; 1058 1059 chip = card->private_data; 1060 if (chip->msi) 1061 if (pci_enable_msi(chip->pci) < 0) 1062 chip->msi = 0; 1063 if (azx_acquire_irq(chip, 1) < 0) 1064 return -EIO; 1065 1066 if (chip->driver_caps & AZX_DCAPS_SUSPEND_SPURIOUS_WAKEUP) 1067 __azx_runtime_resume(chip, false); 1068 else 1069 pm_runtime_force_resume(dev); 1070 snd_power_change_state(card, SNDRV_CTL_POWER_D0); 1071 1072 trace_azx_resume(chip); 1073 return 0; 1074 } 1075 1076 /* put codec down to D3 at hibernation for Intel SKL+; 1077 * otherwise BIOS may still access the codec and screw up the driver 1078 */ 1079 static int azx_freeze_noirq(struct device *dev) 1080 { 1081 struct snd_card *card = dev_get_drvdata(dev); 1082 struct azx *chip = card->private_data; 1083 struct pci_dev *pci = to_pci_dev(dev); 1084 1085 if (!azx_is_pm_ready(card)) 1086 return 0; 1087 if (chip->driver_type == AZX_DRIVER_SKL) 1088 pci_set_power_state(pci, PCI_D3hot); 1089 1090 return 0; 1091 } 1092 1093 static int azx_thaw_noirq(struct device *dev) 1094 { 1095 struct snd_card *card = dev_get_drvdata(dev); 1096 struct azx *chip = card->private_data; 1097 struct pci_dev *pci = to_pci_dev(dev); 1098 1099 if (!azx_is_pm_ready(card)) 1100 return 0; 1101 if (chip->driver_type == AZX_DRIVER_SKL) 1102 pci_set_power_state(pci, PCI_D0); 1103 1104 return 0; 1105 } 1106 #endif /* CONFIG_PM_SLEEP */ 1107 1108 static int azx_runtime_suspend(struct device *dev) 1109 { 1110 struct snd_card *card = dev_get_drvdata(dev); 1111 struct azx *chip; 1112 1113 if (!azx_is_pm_ready(card)) 1114 return 0; 1115 chip = card->private_data; 1116 1117 /* enable controller wake up event */ 1118 if (snd_power_get_state(card) == SNDRV_CTL_POWER_D0) { 1119 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) | 1120 STATESTS_INT_MASK); 1121 } 1122 1123 __azx_runtime_suspend(chip); 1124 trace_azx_runtime_suspend(chip); 1125 return 0; 1126 } 1127 1128 static int azx_runtime_resume(struct device *dev) 1129 { 1130 struct snd_card *card = dev_get_drvdata(dev); 1131 struct azx *chip; 1132 bool from_rt = snd_power_get_state(card) == SNDRV_CTL_POWER_D0; 1133 1134 if (!azx_is_pm_ready(card)) 1135 return 0; 1136 chip = card->private_data; 1137 __azx_runtime_resume(chip, from_rt); 1138 1139 /* disable controller Wake Up event*/ 1140 if (from_rt) { 1141 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) & 1142 ~STATESTS_INT_MASK); 1143 } 1144 1145 trace_azx_runtime_resume(chip); 1146 return 0; 1147 } 1148 1149 static int azx_runtime_idle(struct device *dev) 1150 { 1151 struct snd_card *card = dev_get_drvdata(dev); 1152 struct azx *chip; 1153 struct hda_intel *hda; 1154 1155 if (!card) 1156 return 0; 1157 1158 chip = card->private_data; 1159 hda = container_of(chip, struct hda_intel, chip); 1160 if (chip->disabled || hda->init_failed) 1161 return 0; 1162 1163 if (!power_save_controller || !azx_has_pm_runtime(chip) || 1164 azx_bus(chip)->codec_powered || !chip->running) 1165 return -EBUSY; 1166 1167 /* ELD notification gets broken when HD-audio bus is off */ 1168 if (needs_eld_notify_link(chip)) 1169 return -EBUSY; 1170 1171 return 0; 1172 } 1173 1174 static const struct dev_pm_ops azx_pm = { 1175 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume) 1176 #ifdef CONFIG_PM_SLEEP 1177 .freeze_noirq = azx_freeze_noirq, 1178 .thaw_noirq = azx_thaw_noirq, 1179 #endif 1180 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle) 1181 }; 1182 1183 #define AZX_PM_OPS &azx_pm 1184 #else 1185 #define azx_add_card_list(chip) /* NOP */ 1186 #define azx_del_card_list(chip) /* NOP */ 1187 #define AZX_PM_OPS NULL 1188 #endif /* CONFIG_PM */ 1189 1190 1191 static int azx_probe_continue(struct azx *chip); 1192 1193 #ifdef SUPPORT_VGA_SWITCHEROO 1194 static struct pci_dev *get_bound_vga(struct pci_dev *pci); 1195 1196 static void azx_vs_set_state(struct pci_dev *pci, 1197 enum vga_switcheroo_state state) 1198 { 1199 struct snd_card *card = pci_get_drvdata(pci); 1200 struct azx *chip = card->private_data; 1201 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1202 struct hda_codec *codec; 1203 bool disabled; 1204 1205 wait_for_completion(&hda->probe_wait); 1206 if (hda->init_failed) 1207 return; 1208 1209 disabled = (state == VGA_SWITCHEROO_OFF); 1210 if (chip->disabled == disabled) 1211 return; 1212 1213 if (!hda->probe_continued) { 1214 chip->disabled = disabled; 1215 if (!disabled) { 1216 dev_info(chip->card->dev, 1217 "Start delayed initialization\n"); 1218 if (azx_probe_continue(chip) < 0) 1219 dev_err(chip->card->dev, "initialization error\n"); 1220 } 1221 } else { 1222 dev_info(chip->card->dev, "%s via vga_switcheroo\n", 1223 disabled ? "Disabling" : "Enabling"); 1224 if (disabled) { 1225 list_for_each_codec(codec, &chip->bus) { 1226 pm_runtime_suspend(hda_codec_dev(codec)); 1227 pm_runtime_disable(hda_codec_dev(codec)); 1228 } 1229 pm_runtime_suspend(card->dev); 1230 pm_runtime_disable(card->dev); 1231 /* when we get suspended by vga_switcheroo we end up in D3cold, 1232 * however we have no ACPI handle, so pci/acpi can't put us there, 1233 * put ourselves there */ 1234 pci->current_state = PCI_D3cold; 1235 chip->disabled = true; 1236 if (snd_hda_lock_devices(&chip->bus)) 1237 dev_warn(chip->card->dev, 1238 "Cannot lock devices!\n"); 1239 } else { 1240 snd_hda_unlock_devices(&chip->bus); 1241 chip->disabled = false; 1242 pm_runtime_enable(card->dev); 1243 list_for_each_codec(codec, &chip->bus) { 1244 pm_runtime_enable(hda_codec_dev(codec)); 1245 pm_runtime_resume(hda_codec_dev(codec)); 1246 } 1247 } 1248 } 1249 } 1250 1251 static bool azx_vs_can_switch(struct pci_dev *pci) 1252 { 1253 struct snd_card *card = pci_get_drvdata(pci); 1254 struct azx *chip = card->private_data; 1255 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1256 1257 wait_for_completion(&hda->probe_wait); 1258 if (hda->init_failed) 1259 return false; 1260 if (chip->disabled || !hda->probe_continued) 1261 return true; 1262 if (snd_hda_lock_devices(&chip->bus)) 1263 return false; 1264 snd_hda_unlock_devices(&chip->bus); 1265 return true; 1266 } 1267 1268 /* 1269 * The discrete GPU cannot power down unless the HDA controller runtime 1270 * suspends, so activate runtime PM on codecs even if power_save == 0. 1271 */ 1272 static void setup_vga_switcheroo_runtime_pm(struct azx *chip) 1273 { 1274 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1275 struct hda_codec *codec; 1276 1277 if (hda->use_vga_switcheroo && !needs_eld_notify_link(chip)) { 1278 list_for_each_codec(codec, &chip->bus) 1279 codec->auto_runtime_pm = 1; 1280 /* reset the power save setup */ 1281 if (chip->running) 1282 set_default_power_save(chip); 1283 } 1284 } 1285 1286 static void azx_vs_gpu_bound(struct pci_dev *pci, 1287 enum vga_switcheroo_client_id client_id) 1288 { 1289 struct snd_card *card = pci_get_drvdata(pci); 1290 struct azx *chip = card->private_data; 1291 1292 if (client_id == VGA_SWITCHEROO_DIS) 1293 chip->bus.keep_power = 0; 1294 setup_vga_switcheroo_runtime_pm(chip); 1295 } 1296 1297 static void init_vga_switcheroo(struct azx *chip) 1298 { 1299 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1300 struct pci_dev *p = get_bound_vga(chip->pci); 1301 struct pci_dev *parent; 1302 if (p) { 1303 dev_info(chip->card->dev, 1304 "Handle vga_switcheroo audio client\n"); 1305 hda->use_vga_switcheroo = 1; 1306 1307 /* cleared in either gpu_bound op or codec probe, or when its 1308 * upstream port has _PR3 (i.e. dGPU). 1309 */ 1310 parent = pci_upstream_bridge(p); 1311 chip->bus.keep_power = parent ? !pci_pr3_present(parent) : 1; 1312 chip->driver_caps |= AZX_DCAPS_PM_RUNTIME; 1313 pci_dev_put(p); 1314 } 1315 } 1316 1317 static const struct vga_switcheroo_client_ops azx_vs_ops = { 1318 .set_gpu_state = azx_vs_set_state, 1319 .can_switch = azx_vs_can_switch, 1320 .gpu_bound = azx_vs_gpu_bound, 1321 }; 1322 1323 static int register_vga_switcheroo(struct azx *chip) 1324 { 1325 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1326 struct pci_dev *p; 1327 int err; 1328 1329 if (!hda->use_vga_switcheroo) 1330 return 0; 1331 1332 p = get_bound_vga(chip->pci); 1333 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops, p); 1334 pci_dev_put(p); 1335 1336 if (err < 0) 1337 return err; 1338 hda->vga_switcheroo_registered = 1; 1339 1340 return 0; 1341 } 1342 #else 1343 #define init_vga_switcheroo(chip) /* NOP */ 1344 #define register_vga_switcheroo(chip) 0 1345 #define check_hdmi_disabled(pci) false 1346 #define setup_vga_switcheroo_runtime_pm(chip) /* NOP */ 1347 #endif /* SUPPORT_VGA_SWITCHER */ 1348 1349 /* 1350 * destructor 1351 */ 1352 static void azx_free(struct azx *chip) 1353 { 1354 struct pci_dev *pci = chip->pci; 1355 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 1356 struct hdac_bus *bus = azx_bus(chip); 1357 1358 if (hda->freed) 1359 return; 1360 1361 if (azx_has_pm_runtime(chip) && chip->running) 1362 pm_runtime_get_noresume(&pci->dev); 1363 chip->running = 0; 1364 1365 azx_del_card_list(chip); 1366 1367 hda->init_failed = 1; /* to be sure */ 1368 complete_all(&hda->probe_wait); 1369 1370 if (use_vga_switcheroo(hda)) { 1371 if (chip->disabled && hda->probe_continued) 1372 snd_hda_unlock_devices(&chip->bus); 1373 if (hda->vga_switcheroo_registered) 1374 vga_switcheroo_unregister_client(chip->pci); 1375 } 1376 1377 if (bus->chip_init) { 1378 azx_clear_irq_pending(chip); 1379 azx_stop_all_streams(chip); 1380 azx_stop_chip(chip); 1381 } 1382 1383 if (bus->irq >= 0) 1384 free_irq(bus->irq, (void*)chip); 1385 if (chip->msi) 1386 pci_disable_msi(chip->pci); 1387 iounmap(bus->remap_addr); 1388 1389 azx_free_stream_pages(chip); 1390 azx_free_streams(chip); 1391 snd_hdac_bus_exit(bus); 1392 1393 if (chip->region_requested) 1394 pci_release_regions(chip->pci); 1395 1396 pci_disable_device(chip->pci); 1397 #ifdef CONFIG_SND_HDA_PATCH_LOADER 1398 release_firmware(chip->fw); 1399 #endif 1400 display_power(chip, false); 1401 1402 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) 1403 snd_hdac_i915_exit(bus); 1404 1405 hda->freed = 1; 1406 } 1407 1408 static int azx_dev_disconnect(struct snd_device *device) 1409 { 1410 struct azx *chip = device->device_data; 1411 struct hdac_bus *bus = azx_bus(chip); 1412 1413 chip->bus.shutdown = 1; 1414 cancel_work_sync(&bus->unsol_work); 1415 1416 return 0; 1417 } 1418 1419 static int azx_dev_free(struct snd_device *device) 1420 { 1421 azx_free(device->device_data); 1422 return 0; 1423 } 1424 1425 #ifdef SUPPORT_VGA_SWITCHEROO 1426 #ifdef CONFIG_ACPI 1427 /* ATPX is in the integrated GPU's namespace */ 1428 static bool atpx_present(void) 1429 { 1430 struct pci_dev *pdev = NULL; 1431 acpi_handle dhandle, atpx_handle; 1432 acpi_status status; 1433 1434 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { 1435 dhandle = ACPI_HANDLE(&pdev->dev); 1436 if (dhandle) { 1437 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1438 if (!ACPI_FAILURE(status)) { 1439 pci_dev_put(pdev); 1440 return true; 1441 } 1442 } 1443 } 1444 while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_OTHER << 8, pdev)) != NULL) { 1445 dhandle = ACPI_HANDLE(&pdev->dev); 1446 if (dhandle) { 1447 status = acpi_get_handle(dhandle, "ATPX", &atpx_handle); 1448 if (!ACPI_FAILURE(status)) { 1449 pci_dev_put(pdev); 1450 return true; 1451 } 1452 } 1453 } 1454 return false; 1455 } 1456 #else 1457 static bool atpx_present(void) 1458 { 1459 return false; 1460 } 1461 #endif 1462 1463 /* 1464 * Check of disabled HDMI controller by vga_switcheroo 1465 */ 1466 static struct pci_dev *get_bound_vga(struct pci_dev *pci) 1467 { 1468 struct pci_dev *p; 1469 1470 /* check only discrete GPU */ 1471 switch (pci->vendor) { 1472 case PCI_VENDOR_ID_ATI: 1473 case PCI_VENDOR_ID_AMD: 1474 if (pci->devfn == 1) { 1475 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1476 pci->bus->number, 0); 1477 if (p) { 1478 /* ATPX is in the integrated GPU's ACPI namespace 1479 * rather than the dGPU's namespace. However, 1480 * the dGPU is the one who is involved in 1481 * vgaswitcheroo. 1482 */ 1483 if (((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) && 1484 atpx_present()) 1485 return p; 1486 pci_dev_put(p); 1487 } 1488 } 1489 break; 1490 case PCI_VENDOR_ID_NVIDIA: 1491 if (pci->devfn == 1) { 1492 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus), 1493 pci->bus->number, 0); 1494 if (p) { 1495 if ((p->class >> 16) == PCI_BASE_CLASS_DISPLAY) 1496 return p; 1497 pci_dev_put(p); 1498 } 1499 } 1500 break; 1501 } 1502 return NULL; 1503 } 1504 1505 static bool check_hdmi_disabled(struct pci_dev *pci) 1506 { 1507 bool vga_inactive = false; 1508 struct pci_dev *p = get_bound_vga(pci); 1509 1510 if (p) { 1511 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF) 1512 vga_inactive = true; 1513 pci_dev_put(p); 1514 } 1515 return vga_inactive; 1516 } 1517 #endif /* SUPPORT_VGA_SWITCHEROO */ 1518 1519 /* 1520 * allow/deny-listing for position_fix 1521 */ 1522 static const struct snd_pci_quirk position_fix_list[] = { 1523 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB), 1524 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB), 1525 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB), 1526 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB), 1527 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB), 1528 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB), 1529 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB), 1530 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB), 1531 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB), 1532 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB), 1533 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB), 1534 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB), 1535 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB), 1536 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB), 1537 {} 1538 }; 1539 1540 static int check_position_fix(struct azx *chip, int fix) 1541 { 1542 const struct snd_pci_quirk *q; 1543 1544 switch (fix) { 1545 case POS_FIX_AUTO: 1546 case POS_FIX_LPIB: 1547 case POS_FIX_POSBUF: 1548 case POS_FIX_VIACOMBO: 1549 case POS_FIX_COMBO: 1550 case POS_FIX_SKL: 1551 case POS_FIX_FIFO: 1552 return fix; 1553 } 1554 1555 q = snd_pci_quirk_lookup(chip->pci, position_fix_list); 1556 if (q) { 1557 dev_info(chip->card->dev, 1558 "position_fix set to %d for device %04x:%04x\n", 1559 q->value, q->subvendor, q->subdevice); 1560 return q->value; 1561 } 1562 1563 /* Check VIA/ATI HD Audio Controller exist */ 1564 if (chip->driver_type == AZX_DRIVER_VIA) { 1565 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n"); 1566 return POS_FIX_VIACOMBO; 1567 } 1568 if (chip->driver_caps & AZX_DCAPS_AMD_WORKAROUND) { 1569 dev_dbg(chip->card->dev, "Using FIFO position fix\n"); 1570 return POS_FIX_FIFO; 1571 } 1572 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) { 1573 dev_dbg(chip->card->dev, "Using LPIB position fix\n"); 1574 return POS_FIX_LPIB; 1575 } 1576 if (chip->driver_type == AZX_DRIVER_SKL) { 1577 dev_dbg(chip->card->dev, "Using SKL position fix\n"); 1578 return POS_FIX_SKL; 1579 } 1580 return POS_FIX_AUTO; 1581 } 1582 1583 static void assign_position_fix(struct azx *chip, int fix) 1584 { 1585 static const azx_get_pos_callback_t callbacks[] = { 1586 [POS_FIX_AUTO] = NULL, 1587 [POS_FIX_LPIB] = azx_get_pos_lpib, 1588 [POS_FIX_POSBUF] = azx_get_pos_posbuf, 1589 [POS_FIX_VIACOMBO] = azx_via_get_position, 1590 [POS_FIX_COMBO] = azx_get_pos_lpib, 1591 [POS_FIX_SKL] = azx_get_pos_skl, 1592 [POS_FIX_FIFO] = azx_get_pos_fifo, 1593 }; 1594 1595 chip->get_position[0] = chip->get_position[1] = callbacks[fix]; 1596 1597 /* combo mode uses LPIB only for playback */ 1598 if (fix == POS_FIX_COMBO) 1599 chip->get_position[1] = NULL; 1600 1601 if ((fix == POS_FIX_POSBUF || fix == POS_FIX_SKL) && 1602 (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) { 1603 chip->get_delay[0] = chip->get_delay[1] = 1604 azx_get_delay_from_lpib; 1605 } 1606 1607 if (fix == POS_FIX_FIFO) 1608 chip->get_delay[0] = chip->get_delay[1] = 1609 azx_get_delay_from_fifo; 1610 } 1611 1612 /* 1613 * deny-lists for probe_mask 1614 */ 1615 static const struct snd_pci_quirk probe_mask_list[] = { 1616 /* Thinkpad often breaks the controller communication when accessing 1617 * to the non-working (or non-existing) modem codec slot. 1618 */ 1619 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01), 1620 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01), 1621 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01), 1622 /* broken BIOS */ 1623 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01), 1624 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */ 1625 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01), 1626 /* forced codec slots */ 1627 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103), 1628 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103), 1629 /* WinFast VP200 H (Teradici) user reported broken communication */ 1630 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101), 1631 {} 1632 }; 1633 1634 #define AZX_FORCE_CODEC_MASK 0x100 1635 1636 static void check_probe_mask(struct azx *chip, int dev) 1637 { 1638 const struct snd_pci_quirk *q; 1639 1640 chip->codec_probe_mask = probe_mask[dev]; 1641 if (chip->codec_probe_mask == -1) { 1642 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list); 1643 if (q) { 1644 dev_info(chip->card->dev, 1645 "probe_mask set to 0x%x for device %04x:%04x\n", 1646 q->value, q->subvendor, q->subdevice); 1647 chip->codec_probe_mask = q->value; 1648 } 1649 } 1650 1651 /* check forced option */ 1652 if (chip->codec_probe_mask != -1 && 1653 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) { 1654 azx_bus(chip)->codec_mask = chip->codec_probe_mask & 0xff; 1655 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n", 1656 (int)azx_bus(chip)->codec_mask); 1657 } 1658 } 1659 1660 /* 1661 * allow/deny-list for enable_msi 1662 */ 1663 static const struct snd_pci_quirk msi_deny_list[] = { 1664 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */ 1665 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */ 1666 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */ 1667 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */ 1668 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */ 1669 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */ 1670 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */ 1671 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */ 1672 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */ 1673 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */ 1674 {} 1675 }; 1676 1677 static void check_msi(struct azx *chip) 1678 { 1679 const struct snd_pci_quirk *q; 1680 1681 if (enable_msi >= 0) { 1682 chip->msi = !!enable_msi; 1683 return; 1684 } 1685 chip->msi = 1; /* enable MSI as default */ 1686 q = snd_pci_quirk_lookup(chip->pci, msi_deny_list); 1687 if (q) { 1688 dev_info(chip->card->dev, 1689 "msi for device %04x:%04x set to %d\n", 1690 q->subvendor, q->subdevice, q->value); 1691 chip->msi = q->value; 1692 return; 1693 } 1694 1695 /* NVidia chipsets seem to cause troubles with MSI */ 1696 if (chip->driver_caps & AZX_DCAPS_NO_MSI) { 1697 dev_info(chip->card->dev, "Disabling MSI\n"); 1698 chip->msi = 0; 1699 } 1700 } 1701 1702 /* check the snoop mode availability */ 1703 static void azx_check_snoop_available(struct azx *chip) 1704 { 1705 int snoop = hda_snoop; 1706 1707 if (snoop >= 0) { 1708 dev_info(chip->card->dev, "Force to %s mode by module option\n", 1709 snoop ? "snoop" : "non-snoop"); 1710 chip->snoop = snoop; 1711 chip->uc_buffer = !snoop; 1712 return; 1713 } 1714 1715 snoop = true; 1716 if (azx_get_snoop_type(chip) == AZX_SNOOP_TYPE_NONE && 1717 chip->driver_type == AZX_DRIVER_VIA) { 1718 /* force to non-snoop mode for a new VIA controller 1719 * when BIOS is set 1720 */ 1721 u8 val; 1722 pci_read_config_byte(chip->pci, 0x42, &val); 1723 if (!(val & 0x80) && (chip->pci->revision == 0x30 || 1724 chip->pci->revision == 0x20)) 1725 snoop = false; 1726 } 1727 1728 if (chip->driver_caps & AZX_DCAPS_SNOOP_OFF) 1729 snoop = false; 1730 1731 chip->snoop = snoop; 1732 if (!snoop) { 1733 dev_info(chip->card->dev, "Force to non-snoop mode\n"); 1734 /* C-Media requires non-cached pages only for CORB/RIRB */ 1735 if (chip->driver_type != AZX_DRIVER_CMEDIA) 1736 chip->uc_buffer = true; 1737 } 1738 } 1739 1740 static void azx_probe_work(struct work_struct *work) 1741 { 1742 struct hda_intel *hda = container_of(work, struct hda_intel, probe_work); 1743 azx_probe_continue(&hda->chip); 1744 } 1745 1746 static int default_bdl_pos_adj(struct azx *chip) 1747 { 1748 /* some exceptions: Atoms seem problematic with value 1 */ 1749 if (chip->pci->vendor == PCI_VENDOR_ID_INTEL) { 1750 switch (chip->pci->device) { 1751 case 0x0f04: /* Baytrail */ 1752 case 0x2284: /* Braswell */ 1753 return 32; 1754 } 1755 } 1756 1757 switch (chip->driver_type) { 1758 case AZX_DRIVER_ICH: 1759 case AZX_DRIVER_PCH: 1760 return 1; 1761 default: 1762 return 32; 1763 } 1764 } 1765 1766 /* 1767 * constructor 1768 */ 1769 static const struct hda_controller_ops pci_hda_ops; 1770 1771 static int azx_create(struct snd_card *card, struct pci_dev *pci, 1772 int dev, unsigned int driver_caps, 1773 struct azx **rchip) 1774 { 1775 static const struct snd_device_ops ops = { 1776 .dev_disconnect = azx_dev_disconnect, 1777 .dev_free = azx_dev_free, 1778 }; 1779 struct hda_intel *hda; 1780 struct azx *chip; 1781 int err; 1782 1783 *rchip = NULL; 1784 1785 err = pci_enable_device(pci); 1786 if (err < 0) 1787 return err; 1788 1789 hda = devm_kzalloc(&pci->dev, sizeof(*hda), GFP_KERNEL); 1790 if (!hda) { 1791 pci_disable_device(pci); 1792 return -ENOMEM; 1793 } 1794 1795 chip = &hda->chip; 1796 mutex_init(&chip->open_mutex); 1797 chip->card = card; 1798 chip->pci = pci; 1799 chip->ops = &pci_hda_ops; 1800 chip->driver_caps = driver_caps; 1801 chip->driver_type = driver_caps & 0xff; 1802 check_msi(chip); 1803 chip->dev_index = dev; 1804 if (jackpoll_ms[dev] >= 50 && jackpoll_ms[dev] <= 60000) 1805 chip->jackpoll_interval = msecs_to_jiffies(jackpoll_ms[dev]); 1806 INIT_LIST_HEAD(&chip->pcm_list); 1807 INIT_WORK(&hda->irq_pending_work, azx_irq_pending_work); 1808 INIT_LIST_HEAD(&hda->list); 1809 init_vga_switcheroo(chip); 1810 init_completion(&hda->probe_wait); 1811 1812 assign_position_fix(chip, check_position_fix(chip, position_fix[dev])); 1813 1814 check_probe_mask(chip, dev); 1815 1816 if (single_cmd < 0) /* allow fallback to single_cmd at errors */ 1817 chip->fallback_to_single_cmd = 1; 1818 else /* explicitly set to single_cmd or not */ 1819 chip->single_cmd = single_cmd; 1820 1821 azx_check_snoop_available(chip); 1822 1823 if (bdl_pos_adj[dev] < 0) 1824 chip->bdl_pos_adj = default_bdl_pos_adj(chip); 1825 else 1826 chip->bdl_pos_adj = bdl_pos_adj[dev]; 1827 1828 err = azx_bus_init(chip, model[dev]); 1829 if (err < 0) { 1830 pci_disable_device(pci); 1831 return err; 1832 } 1833 1834 /* use the non-cached pages in non-snoop mode */ 1835 if (!azx_snoop(chip)) 1836 azx_bus(chip)->dma_type = SNDRV_DMA_TYPE_DEV_UC; 1837 1838 if (chip->driver_type == AZX_DRIVER_NVIDIA) { 1839 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n"); 1840 chip->bus.core.needs_damn_long_delay = 1; 1841 } 1842 1843 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops); 1844 if (err < 0) { 1845 dev_err(card->dev, "Error creating device [card]!\n"); 1846 azx_free(chip); 1847 return err; 1848 } 1849 1850 /* continue probing in work context as may trigger request module */ 1851 INIT_WORK(&hda->probe_work, azx_probe_work); 1852 1853 *rchip = chip; 1854 1855 return 0; 1856 } 1857 1858 static int azx_first_init(struct azx *chip) 1859 { 1860 int dev = chip->dev_index; 1861 struct pci_dev *pci = chip->pci; 1862 struct snd_card *card = chip->card; 1863 struct hdac_bus *bus = azx_bus(chip); 1864 int err; 1865 unsigned short gcap; 1866 unsigned int dma_bits = 64; 1867 1868 #if BITS_PER_LONG != 64 1869 /* Fix up base address on ULI M5461 */ 1870 if (chip->driver_type == AZX_DRIVER_ULI) { 1871 u16 tmp3; 1872 pci_read_config_word(pci, 0x40, &tmp3); 1873 pci_write_config_word(pci, 0x40, tmp3 | 0x10); 1874 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0); 1875 } 1876 #endif 1877 1878 err = pci_request_regions(pci, "ICH HD audio"); 1879 if (err < 0) 1880 return err; 1881 chip->region_requested = 1; 1882 1883 bus->addr = pci_resource_start(pci, 0); 1884 bus->remap_addr = pci_ioremap_bar(pci, 0); 1885 if (bus->remap_addr == NULL) { 1886 dev_err(card->dev, "ioremap error\n"); 1887 return -ENXIO; 1888 } 1889 1890 if (chip->driver_type == AZX_DRIVER_SKL) 1891 snd_hdac_bus_parse_capabilities(bus); 1892 1893 /* 1894 * Some Intel CPUs has always running timer (ART) feature and 1895 * controller may have Global time sync reporting capability, so 1896 * check both of these before declaring synchronized time reporting 1897 * capability SNDRV_PCM_INFO_HAS_LINK_SYNCHRONIZED_ATIME 1898 */ 1899 chip->gts_present = false; 1900 1901 #ifdef CONFIG_X86 1902 if (bus->ppcap && boot_cpu_has(X86_FEATURE_ART)) 1903 chip->gts_present = true; 1904 #endif 1905 1906 if (chip->msi) { 1907 if (chip->driver_caps & AZX_DCAPS_NO_MSI64) { 1908 dev_dbg(card->dev, "Disabling 64bit MSI\n"); 1909 pci->no_64bit_msi = true; 1910 } 1911 if (pci_enable_msi(pci) < 0) 1912 chip->msi = 0; 1913 } 1914 1915 pci_set_master(pci); 1916 1917 gcap = azx_readw(chip, GCAP); 1918 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap); 1919 1920 /* AMD devices support 40 or 48bit DMA, take the safe one */ 1921 if (chip->pci->vendor == PCI_VENDOR_ID_AMD) 1922 dma_bits = 40; 1923 1924 /* disable SB600 64bit support for safety */ 1925 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) { 1926 struct pci_dev *p_smbus; 1927 dma_bits = 40; 1928 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI, 1929 PCI_DEVICE_ID_ATI_SBX00_SMBUS, 1930 NULL); 1931 if (p_smbus) { 1932 if (p_smbus->revision < 0x30) 1933 gcap &= ~AZX_GCAP_64OK; 1934 pci_dev_put(p_smbus); 1935 } 1936 } 1937 1938 /* NVidia hardware normally only supports up to 40 bits of DMA */ 1939 if (chip->pci->vendor == PCI_VENDOR_ID_NVIDIA) 1940 dma_bits = 40; 1941 1942 /* disable 64bit DMA address on some devices */ 1943 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) { 1944 dev_dbg(card->dev, "Disabling 64bit DMA\n"); 1945 gcap &= ~AZX_GCAP_64OK; 1946 } 1947 1948 /* disable buffer size rounding to 128-byte multiples if supported */ 1949 if (align_buffer_size >= 0) 1950 chip->align_buffer_size = !!align_buffer_size; 1951 else { 1952 if (chip->driver_caps & AZX_DCAPS_NO_ALIGN_BUFSIZE) 1953 chip->align_buffer_size = 0; 1954 else 1955 chip->align_buffer_size = 1; 1956 } 1957 1958 /* allow 64bit DMA address if supported by H/W */ 1959 if (!(gcap & AZX_GCAP_64OK)) 1960 dma_bits = 32; 1961 if (!dma_set_mask(&pci->dev, DMA_BIT_MASK(dma_bits))) { 1962 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(dma_bits)); 1963 } else { 1964 dma_set_mask(&pci->dev, DMA_BIT_MASK(32)); 1965 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(32)); 1966 } 1967 1968 /* read number of streams from GCAP register instead of using 1969 * hardcoded value 1970 */ 1971 chip->capture_streams = (gcap >> 8) & 0x0f; 1972 chip->playback_streams = (gcap >> 12) & 0x0f; 1973 if (!chip->playback_streams && !chip->capture_streams) { 1974 /* gcap didn't give any info, switching to old method */ 1975 1976 switch (chip->driver_type) { 1977 case AZX_DRIVER_ULI: 1978 chip->playback_streams = ULI_NUM_PLAYBACK; 1979 chip->capture_streams = ULI_NUM_CAPTURE; 1980 break; 1981 case AZX_DRIVER_ATIHDMI: 1982 case AZX_DRIVER_ATIHDMI_NS: 1983 chip->playback_streams = ATIHDMI_NUM_PLAYBACK; 1984 chip->capture_streams = ATIHDMI_NUM_CAPTURE; 1985 break; 1986 case AZX_DRIVER_GENERIC: 1987 default: 1988 chip->playback_streams = ICH6_NUM_PLAYBACK; 1989 chip->capture_streams = ICH6_NUM_CAPTURE; 1990 break; 1991 } 1992 } 1993 chip->capture_index_offset = 0; 1994 chip->playback_index_offset = chip->capture_streams; 1995 chip->num_streams = chip->playback_streams + chip->capture_streams; 1996 1997 /* sanity check for the SDxCTL.STRM field overflow */ 1998 if (chip->num_streams > 15 && 1999 (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG) == 0) { 2000 dev_warn(chip->card->dev, "number of I/O streams is %d, " 2001 "forcing separate stream tags", chip->num_streams); 2002 chip->driver_caps |= AZX_DCAPS_SEPARATE_STREAM_TAG; 2003 } 2004 2005 /* initialize streams */ 2006 err = azx_init_streams(chip); 2007 if (err < 0) 2008 return err; 2009 2010 err = azx_alloc_stream_pages(chip); 2011 if (err < 0) 2012 return err; 2013 2014 /* initialize chip */ 2015 azx_init_pci(chip); 2016 2017 snd_hdac_i915_set_bclk(bus); 2018 2019 hda_intel_init_chip(chip, (probe_only[dev] & 2) == 0); 2020 2021 /* codec detection */ 2022 if (!azx_bus(chip)->codec_mask) { 2023 dev_err(card->dev, "no codecs found!\n"); 2024 /* keep running the rest for the runtime PM */ 2025 } 2026 2027 if (azx_acquire_irq(chip, 0) < 0) 2028 return -EBUSY; 2029 2030 strcpy(card->driver, "HDA-Intel"); 2031 strlcpy(card->shortname, driver_short_names[chip->driver_type], 2032 sizeof(card->shortname)); 2033 snprintf(card->longname, sizeof(card->longname), 2034 "%s at 0x%lx irq %i", 2035 card->shortname, bus->addr, bus->irq); 2036 2037 return 0; 2038 } 2039 2040 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2041 /* callback from request_firmware_nowait() */ 2042 static void azx_firmware_cb(const struct firmware *fw, void *context) 2043 { 2044 struct snd_card *card = context; 2045 struct azx *chip = card->private_data; 2046 2047 if (fw) 2048 chip->fw = fw; 2049 else 2050 dev_err(card->dev, "Cannot load firmware, continue without patching\n"); 2051 if (!chip->disabled) { 2052 /* continue probing */ 2053 azx_probe_continue(chip); 2054 } 2055 } 2056 #endif 2057 2058 static int disable_msi_reset_irq(struct azx *chip) 2059 { 2060 struct hdac_bus *bus = azx_bus(chip); 2061 int err; 2062 2063 free_irq(bus->irq, chip); 2064 bus->irq = -1; 2065 chip->card->sync_irq = -1; 2066 pci_disable_msi(chip->pci); 2067 chip->msi = 0; 2068 err = azx_acquire_irq(chip, 1); 2069 if (err < 0) 2070 return err; 2071 2072 return 0; 2073 } 2074 2075 static void pcm_mmap_prepare(struct snd_pcm_substream *substream, 2076 struct vm_area_struct *area) 2077 { 2078 #ifdef CONFIG_X86 2079 struct azx_pcm *apcm = snd_pcm_substream_chip(substream); 2080 struct azx *chip = apcm->chip; 2081 if (chip->uc_buffer) 2082 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot); 2083 #endif 2084 } 2085 2086 /* Denylist for skipping the whole probe: 2087 * some HD-audio PCI entries are exposed without any codecs, and such devices 2088 * should be ignored from the beginning. 2089 */ 2090 static const struct pci_device_id driver_denylist[] = { 2091 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1043, 0x874f) }, /* ASUS ROG Zenith II / Strix */ 2092 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb59) }, /* MSI TRX40 Creator */ 2093 { PCI_DEVICE_SUB(0x1022, 0x1487, 0x1462, 0xcb60) }, /* MSI TRX40 */ 2094 {} 2095 }; 2096 2097 static const struct hda_controller_ops pci_hda_ops = { 2098 .disable_msi_reset_irq = disable_msi_reset_irq, 2099 .pcm_mmap_prepare = pcm_mmap_prepare, 2100 .position_check = azx_position_check, 2101 }; 2102 2103 static int azx_probe(struct pci_dev *pci, 2104 const struct pci_device_id *pci_id) 2105 { 2106 static int dev; 2107 struct snd_card *card; 2108 struct hda_intel *hda; 2109 struct azx *chip; 2110 bool schedule_probe; 2111 int err; 2112 2113 if (pci_match_id(driver_denylist, pci)) { 2114 dev_info(&pci->dev, "Skipping the device on the denylist\n"); 2115 return -ENODEV; 2116 } 2117 2118 if (dev >= SNDRV_CARDS) 2119 return -ENODEV; 2120 if (!enable[dev]) { 2121 dev++; 2122 return -ENOENT; 2123 } 2124 2125 /* 2126 * stop probe if another Intel's DSP driver should be activated 2127 */ 2128 if (dmic_detect) { 2129 err = snd_intel_dsp_driver_probe(pci); 2130 if (err != SND_INTEL_DSP_DRIVER_ANY && 2131 err != SND_INTEL_DSP_DRIVER_LEGACY) 2132 return -ENODEV; 2133 } else { 2134 dev_warn(&pci->dev, "dmic_detect option is deprecated, pass snd-intel-dspcfg.dsp_driver=1 option instead\n"); 2135 } 2136 2137 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE, 2138 0, &card); 2139 if (err < 0) { 2140 dev_err(&pci->dev, "Error creating card!\n"); 2141 return err; 2142 } 2143 2144 err = azx_create(card, pci, dev, pci_id->driver_data, &chip); 2145 if (err < 0) 2146 goto out_free; 2147 card->private_data = chip; 2148 hda = container_of(chip, struct hda_intel, chip); 2149 2150 pci_set_drvdata(pci, card); 2151 2152 err = register_vga_switcheroo(chip); 2153 if (err < 0) { 2154 dev_err(card->dev, "Error registering vga_switcheroo client\n"); 2155 goto out_free; 2156 } 2157 2158 if (check_hdmi_disabled(pci)) { 2159 dev_info(card->dev, "VGA controller is disabled\n"); 2160 dev_info(card->dev, "Delaying initialization\n"); 2161 chip->disabled = true; 2162 } 2163 2164 schedule_probe = !chip->disabled; 2165 2166 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2167 if (patch[dev] && *patch[dev]) { 2168 dev_info(card->dev, "Applying patch firmware '%s'\n", 2169 patch[dev]); 2170 err = request_firmware_nowait(THIS_MODULE, true, patch[dev], 2171 &pci->dev, GFP_KERNEL, card, 2172 azx_firmware_cb); 2173 if (err < 0) 2174 goto out_free; 2175 schedule_probe = false; /* continued in azx_firmware_cb() */ 2176 } 2177 #endif /* CONFIG_SND_HDA_PATCH_LOADER */ 2178 2179 #ifndef CONFIG_SND_HDA_I915 2180 if (CONTROLLER_IN_GPU(pci)) 2181 dev_err(card->dev, "Haswell/Broadwell HDMI/DP must build in CONFIG_SND_HDA_I915\n"); 2182 #endif 2183 2184 if (schedule_probe) 2185 schedule_work(&hda->probe_work); 2186 2187 dev++; 2188 if (chip->disabled) 2189 complete_all(&hda->probe_wait); 2190 return 0; 2191 2192 out_free: 2193 snd_card_free(card); 2194 return err; 2195 } 2196 2197 #ifdef CONFIG_PM 2198 /* On some boards setting power_save to a non 0 value leads to clicking / 2199 * popping sounds when ever we enter/leave powersaving mode. Ideally we would 2200 * figure out how to avoid these sounds, but that is not always feasible. 2201 * So we keep a list of devices where we disable powersaving as its known 2202 * to causes problems on these devices. 2203 */ 2204 static const struct snd_pci_quirk power_save_denylist[] = { 2205 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2206 SND_PCI_QUIRK(0x1849, 0xc892, "Asrock B85M-ITX", 0), 2207 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2208 SND_PCI_QUIRK(0x1849, 0x0397, "Asrock N68C-S UCC", 0), 2209 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2210 SND_PCI_QUIRK(0x1849, 0x7662, "Asrock H81M-HDS", 0), 2211 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2212 SND_PCI_QUIRK(0x1043, 0x8733, "Asus Prime X370-Pro", 0), 2213 /* https://bugzilla.redhat.com/show_bug.cgi?id=1581607 */ 2214 SND_PCI_QUIRK(0x1558, 0x3501, "Clevo W35xSS_370SS", 0), 2215 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2216 SND_PCI_QUIRK(0x1558, 0x6504, "Clevo W65_67SB", 0), 2217 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2218 SND_PCI_QUIRK(0x1028, 0x0497, "Dell Precision T3600", 0), 2219 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2220 /* Note the P55A-UD3 and Z87-D3HP share the subsys id for the HDA dev */ 2221 SND_PCI_QUIRK(0x1458, 0xa002, "Gigabyte P55A-UD3 / Z87-D3HP", 0), 2222 /* https://bugzilla.redhat.com/show_bug.cgi?id=1525104 */ 2223 SND_PCI_QUIRK(0x8086, 0x2040, "Intel DZ77BH-55K", 0), 2224 /* https://bugzilla.kernel.org/show_bug.cgi?id=199607 */ 2225 SND_PCI_QUIRK(0x8086, 0x2057, "Intel NUC5i7RYB", 0), 2226 /* https://bugs.launchpad.net/bugs/1821663 */ 2227 SND_PCI_QUIRK(0x8086, 0x2064, "Intel SDP 8086:2064", 0), 2228 /* https://bugzilla.redhat.com/show_bug.cgi?id=1520902 */ 2229 SND_PCI_QUIRK(0x8086, 0x2068, "Intel NUC7i3BNB", 0), 2230 /* https://bugzilla.kernel.org/show_bug.cgi?id=198611 */ 2231 SND_PCI_QUIRK(0x17aa, 0x2227, "Lenovo X1 Carbon 3rd Gen", 0), 2232 /* https://bugzilla.redhat.com/show_bug.cgi?id=1689623 */ 2233 SND_PCI_QUIRK(0x17aa, 0x367b, "Lenovo IdeaCentre B550", 0), 2234 /* https://bugzilla.redhat.com/show_bug.cgi?id=1572975 */ 2235 SND_PCI_QUIRK(0x17aa, 0x36a7, "Lenovo C50 All in one", 0), 2236 /* https://bugs.launchpad.net/bugs/1821663 */ 2237 SND_PCI_QUIRK(0x1631, 0xe017, "Packard Bell NEC IMEDIA 5204", 0), 2238 {} 2239 }; 2240 #endif /* CONFIG_PM */ 2241 2242 static void set_default_power_save(struct azx *chip) 2243 { 2244 int val = power_save; 2245 2246 #ifdef CONFIG_PM 2247 if (pm_blacklist) { 2248 const struct snd_pci_quirk *q; 2249 2250 q = snd_pci_quirk_lookup(chip->pci, power_save_denylist); 2251 if (q && val) { 2252 dev_info(chip->card->dev, "device %04x:%04x is on the power_save denylist, forcing power_save to 0\n", 2253 q->subvendor, q->subdevice); 2254 val = 0; 2255 } 2256 } 2257 #endif /* CONFIG_PM */ 2258 snd_hda_set_power_save(&chip->bus, val * 1000); 2259 } 2260 2261 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */ 2262 static const unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = { 2263 [AZX_DRIVER_NVIDIA] = 8, 2264 [AZX_DRIVER_TERA] = 1, 2265 }; 2266 2267 static int azx_probe_continue(struct azx *chip) 2268 { 2269 struct hda_intel *hda = container_of(chip, struct hda_intel, chip); 2270 struct hdac_bus *bus = azx_bus(chip); 2271 struct pci_dev *pci = chip->pci; 2272 int dev = chip->dev_index; 2273 int err; 2274 2275 to_hda_bus(bus)->bus_probing = 1; 2276 hda->probe_continued = 1; 2277 2278 /* bind with i915 if needed */ 2279 if (chip->driver_caps & AZX_DCAPS_I915_COMPONENT) { 2280 err = snd_hdac_i915_init(bus); 2281 if (err < 0) { 2282 /* if the controller is bound only with HDMI/DP 2283 * (for HSW and BDW), we need to abort the probe; 2284 * for other chips, still continue probing as other 2285 * codecs can be on the same link. 2286 */ 2287 if (CONTROLLER_IN_GPU(pci)) { 2288 dev_err(chip->card->dev, 2289 "HSW/BDW HD-audio HDMI/DP requires binding with gfx driver\n"); 2290 goto out_free; 2291 } else { 2292 /* don't bother any longer */ 2293 chip->driver_caps &= ~AZX_DCAPS_I915_COMPONENT; 2294 } 2295 } 2296 2297 /* HSW/BDW controllers need this power */ 2298 if (CONTROLLER_IN_GPU(pci)) 2299 hda->need_i915_power = 1; 2300 } 2301 2302 /* Request display power well for the HDA controller or codec. For 2303 * Haswell/Broadwell, both the display HDA controller and codec need 2304 * this power. For other platforms, like Baytrail/Braswell, only the 2305 * display codec needs the power and it can be released after probe. 2306 */ 2307 display_power(chip, true); 2308 2309 err = azx_first_init(chip); 2310 if (err < 0) 2311 goto out_free; 2312 2313 #ifdef CONFIG_SND_HDA_INPUT_BEEP 2314 chip->beep_mode = beep_mode[dev]; 2315 #endif 2316 2317 /* create codec instances */ 2318 if (bus->codec_mask) { 2319 err = azx_probe_codecs(chip, azx_max_codecs[chip->driver_type]); 2320 if (err < 0) 2321 goto out_free; 2322 } 2323 2324 #ifdef CONFIG_SND_HDA_PATCH_LOADER 2325 if (chip->fw) { 2326 err = snd_hda_load_patch(&chip->bus, chip->fw->size, 2327 chip->fw->data); 2328 if (err < 0) 2329 goto out_free; 2330 #ifndef CONFIG_PM 2331 release_firmware(chip->fw); /* no longer needed */ 2332 chip->fw = NULL; 2333 #endif 2334 } 2335 #endif 2336 if (bus->codec_mask && !(probe_only[dev] & 1)) { 2337 err = azx_codec_configure(chip); 2338 if (err < 0) 2339 goto out_free; 2340 } 2341 2342 err = snd_card_register(chip->card); 2343 if (err < 0) 2344 goto out_free; 2345 2346 setup_vga_switcheroo_runtime_pm(chip); 2347 2348 chip->running = 1; 2349 azx_add_card_list(chip); 2350 2351 set_default_power_save(chip); 2352 2353 if (azx_has_pm_runtime(chip)) { 2354 pm_runtime_use_autosuspend(&pci->dev); 2355 pm_runtime_put_autosuspend(&pci->dev); 2356 } 2357 2358 out_free: 2359 if (err < 0) { 2360 azx_free(chip); 2361 return err; 2362 } 2363 2364 if (!hda->need_i915_power) 2365 display_power(chip, false); 2366 complete_all(&hda->probe_wait); 2367 to_hda_bus(bus)->bus_probing = 0; 2368 return 0; 2369 } 2370 2371 static void azx_remove(struct pci_dev *pci) 2372 { 2373 struct snd_card *card = pci_get_drvdata(pci); 2374 struct azx *chip; 2375 struct hda_intel *hda; 2376 2377 if (card) { 2378 /* cancel the pending probing work */ 2379 chip = card->private_data; 2380 hda = container_of(chip, struct hda_intel, chip); 2381 /* FIXME: below is an ugly workaround. 2382 * Both device_release_driver() and driver_probe_device() 2383 * take *both* the device's and its parent's lock before 2384 * calling the remove() and probe() callbacks. The codec 2385 * probe takes the locks of both the codec itself and its 2386 * parent, i.e. the PCI controller dev. Meanwhile, when 2387 * the PCI controller is unbound, it takes its lock, too 2388 * ==> ouch, a deadlock! 2389 * As a workaround, we unlock temporarily here the controller 2390 * device during cancel_work_sync() call. 2391 */ 2392 device_unlock(&pci->dev); 2393 cancel_work_sync(&hda->probe_work); 2394 device_lock(&pci->dev); 2395 2396 snd_card_free(card); 2397 } 2398 } 2399 2400 static void azx_shutdown(struct pci_dev *pci) 2401 { 2402 struct snd_card *card = pci_get_drvdata(pci); 2403 struct azx *chip; 2404 2405 if (!card) 2406 return; 2407 chip = card->private_data; 2408 if (chip && chip->running) 2409 azx_stop_chip(chip); 2410 } 2411 2412 /* PCI IDs */ 2413 static const struct pci_device_id azx_ids[] = { 2414 /* CPT */ 2415 { PCI_DEVICE(0x8086, 0x1c20), 2416 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2417 /* PBG */ 2418 { PCI_DEVICE(0x8086, 0x1d20), 2419 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2420 /* Panther Point */ 2421 { PCI_DEVICE(0x8086, 0x1e20), 2422 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2423 /* Lynx Point */ 2424 { PCI_DEVICE(0x8086, 0x8c20), 2425 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2426 /* 9 Series */ 2427 { PCI_DEVICE(0x8086, 0x8ca0), 2428 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2429 /* Wellsburg */ 2430 { PCI_DEVICE(0x8086, 0x8d20), 2431 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2432 { PCI_DEVICE(0x8086, 0x8d21), 2433 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2434 /* Lewisburg */ 2435 { PCI_DEVICE(0x8086, 0xa1f0), 2436 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2437 { PCI_DEVICE(0x8086, 0xa270), 2438 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_SKYLAKE }, 2439 /* Lynx Point-LP */ 2440 { PCI_DEVICE(0x8086, 0x9c20), 2441 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2442 /* Lynx Point-LP */ 2443 { PCI_DEVICE(0x8086, 0x9c21), 2444 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2445 /* Wildcat Point-LP */ 2446 { PCI_DEVICE(0x8086, 0x9ca0), 2447 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 2448 /* Sunrise Point */ 2449 { PCI_DEVICE(0x8086, 0xa170), 2450 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2451 /* Sunrise Point-LP */ 2452 { PCI_DEVICE(0x8086, 0x9d70), 2453 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2454 /* Kabylake */ 2455 { PCI_DEVICE(0x8086, 0xa171), 2456 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2457 /* Kabylake-LP */ 2458 { PCI_DEVICE(0x8086, 0x9d71), 2459 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2460 /* Kabylake-H */ 2461 { PCI_DEVICE(0x8086, 0xa2f0), 2462 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE }, 2463 /* Coffelake */ 2464 { PCI_DEVICE(0x8086, 0xa348), 2465 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2466 /* Cannonlake */ 2467 { PCI_DEVICE(0x8086, 0x9dc8), 2468 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2469 /* CometLake-LP */ 2470 { PCI_DEVICE(0x8086, 0x02C8), 2471 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2472 /* CometLake-H */ 2473 { PCI_DEVICE(0x8086, 0x06C8), 2474 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2475 /* CometLake-S */ 2476 { PCI_DEVICE(0x8086, 0xa3f0), 2477 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2478 /* Icelake */ 2479 { PCI_DEVICE(0x8086, 0x34c8), 2480 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2481 /* Icelake-H */ 2482 { PCI_DEVICE(0x8086, 0x3dc8), 2483 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2484 /* Jasperlake */ 2485 { PCI_DEVICE(0x8086, 0x38c8), 2486 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2487 { PCI_DEVICE(0x8086, 0x4dc8), 2488 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2489 /* Tigerlake */ 2490 { PCI_DEVICE(0x8086, 0xa0c8), 2491 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2492 /* Tigerlake-H */ 2493 { PCI_DEVICE(0x8086, 0x43c8), 2494 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2495 /* Elkhart Lake */ 2496 { PCI_DEVICE(0x8086, 0x4b55), 2497 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2498 { PCI_DEVICE(0x8086, 0x4b58), 2499 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_SKYLAKE}, 2500 /* Broxton-P(Apollolake) */ 2501 { PCI_DEVICE(0x8086, 0x5a98), 2502 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2503 /* Broxton-T */ 2504 { PCI_DEVICE(0x8086, 0x1a98), 2505 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2506 /* Gemini-Lake */ 2507 { PCI_DEVICE(0x8086, 0x3198), 2508 .driver_data = AZX_DRIVER_SKL | AZX_DCAPS_INTEL_BROXTON }, 2509 /* Haswell */ 2510 { PCI_DEVICE(0x8086, 0x0a0c), 2511 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2512 { PCI_DEVICE(0x8086, 0x0c0c), 2513 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2514 { PCI_DEVICE(0x8086, 0x0d0c), 2515 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL }, 2516 /* Broadwell */ 2517 { PCI_DEVICE(0x8086, 0x160c), 2518 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_BROADWELL }, 2519 /* 5 Series/3400 */ 2520 { PCI_DEVICE(0x8086, 0x3b56), 2521 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM }, 2522 /* Poulsbo */ 2523 { PCI_DEVICE(0x8086, 0x811b), 2524 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2525 /* Oaktrail */ 2526 { PCI_DEVICE(0x8086, 0x080a), 2527 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_BASE }, 2528 /* BayTrail */ 2529 { PCI_DEVICE(0x8086, 0x0f04), 2530 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BAYTRAIL }, 2531 /* Braswell */ 2532 { PCI_DEVICE(0x8086, 0x2284), 2533 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_BRASWELL }, 2534 /* ICH6 */ 2535 { PCI_DEVICE(0x8086, 0x2668), 2536 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2537 /* ICH7 */ 2538 { PCI_DEVICE(0x8086, 0x27d8), 2539 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2540 /* ESB2 */ 2541 { PCI_DEVICE(0x8086, 0x269a), 2542 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2543 /* ICH8 */ 2544 { PCI_DEVICE(0x8086, 0x284b), 2545 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2546 /* ICH9 */ 2547 { PCI_DEVICE(0x8086, 0x293e), 2548 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2549 /* ICH9 */ 2550 { PCI_DEVICE(0x8086, 0x293f), 2551 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2552 /* ICH10 */ 2553 { PCI_DEVICE(0x8086, 0x3a3e), 2554 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2555 /* ICH10 */ 2556 { PCI_DEVICE(0x8086, 0x3a6e), 2557 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_INTEL_ICH }, 2558 /* Generic Intel */ 2559 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID), 2560 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2561 .class_mask = 0xffffff, 2562 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_NO_ALIGN_BUFSIZE }, 2563 /* ATI SB 450/600/700/800/900 */ 2564 { PCI_DEVICE(0x1002, 0x437b), 2565 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2566 { PCI_DEVICE(0x1002, 0x4383), 2567 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB }, 2568 /* AMD Hudson */ 2569 { PCI_DEVICE(0x1022, 0x780d), 2570 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB }, 2571 /* AMD, X370 & co */ 2572 { PCI_DEVICE(0x1022, 0x1457), 2573 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2574 /* AMD, X570 & co */ 2575 { PCI_DEVICE(0x1022, 0x1487), 2576 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2577 /* AMD Stoney */ 2578 { PCI_DEVICE(0x1022, 0x157a), 2579 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB | 2580 AZX_DCAPS_PM_RUNTIME }, 2581 /* AMD Raven */ 2582 { PCI_DEVICE(0x1022, 0x15e3), 2583 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_AMD_SB }, 2584 /* ATI HDMI */ 2585 { PCI_DEVICE(0x1002, 0x0002), 2586 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2587 { PCI_DEVICE(0x1002, 0x1308), 2588 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2589 { PCI_DEVICE(0x1002, 0x157a), 2590 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2591 { PCI_DEVICE(0x1002, 0x15b3), 2592 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2593 { PCI_DEVICE(0x1002, 0x793b), 2594 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2595 { PCI_DEVICE(0x1002, 0x7919), 2596 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2597 { PCI_DEVICE(0x1002, 0x960f), 2598 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2599 { PCI_DEVICE(0x1002, 0x970f), 2600 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2601 { PCI_DEVICE(0x1002, 0x9840), 2602 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2603 { PCI_DEVICE(0x1002, 0xaa00), 2604 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2605 { PCI_DEVICE(0x1002, 0xaa08), 2606 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2607 { PCI_DEVICE(0x1002, 0xaa10), 2608 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2609 { PCI_DEVICE(0x1002, 0xaa18), 2610 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2611 { PCI_DEVICE(0x1002, 0xaa20), 2612 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2613 { PCI_DEVICE(0x1002, 0xaa28), 2614 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2615 { PCI_DEVICE(0x1002, 0xaa30), 2616 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2617 { PCI_DEVICE(0x1002, 0xaa38), 2618 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2619 { PCI_DEVICE(0x1002, 0xaa40), 2620 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2621 { PCI_DEVICE(0x1002, 0xaa48), 2622 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2623 { PCI_DEVICE(0x1002, 0xaa50), 2624 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2625 { PCI_DEVICE(0x1002, 0xaa58), 2626 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2627 { PCI_DEVICE(0x1002, 0xaa60), 2628 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2629 { PCI_DEVICE(0x1002, 0xaa68), 2630 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2631 { PCI_DEVICE(0x1002, 0xaa80), 2632 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2633 { PCI_DEVICE(0x1002, 0xaa88), 2634 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2635 { PCI_DEVICE(0x1002, 0xaa90), 2636 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2637 { PCI_DEVICE(0x1002, 0xaa98), 2638 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI }, 2639 { PCI_DEVICE(0x1002, 0x9902), 2640 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2641 { PCI_DEVICE(0x1002, 0xaaa0), 2642 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2643 { PCI_DEVICE(0x1002, 0xaaa8), 2644 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2645 { PCI_DEVICE(0x1002, 0xaab0), 2646 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2647 { PCI_DEVICE(0x1002, 0xaac0), 2648 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2649 { PCI_DEVICE(0x1002, 0xaac8), 2650 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS }, 2651 { PCI_DEVICE(0x1002, 0xaad8), 2652 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2653 AZX_DCAPS_PM_RUNTIME }, 2654 { PCI_DEVICE(0x1002, 0xaae0), 2655 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2656 AZX_DCAPS_PM_RUNTIME }, 2657 { PCI_DEVICE(0x1002, 0xaae8), 2658 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2659 AZX_DCAPS_PM_RUNTIME }, 2660 { PCI_DEVICE(0x1002, 0xaaf0), 2661 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2662 AZX_DCAPS_PM_RUNTIME }, 2663 { PCI_DEVICE(0x1002, 0xaaf8), 2664 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2665 AZX_DCAPS_PM_RUNTIME }, 2666 { PCI_DEVICE(0x1002, 0xab00), 2667 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2668 AZX_DCAPS_PM_RUNTIME }, 2669 { PCI_DEVICE(0x1002, 0xab08), 2670 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2671 AZX_DCAPS_PM_RUNTIME }, 2672 { PCI_DEVICE(0x1002, 0xab10), 2673 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2674 AZX_DCAPS_PM_RUNTIME }, 2675 { PCI_DEVICE(0x1002, 0xab18), 2676 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2677 AZX_DCAPS_PM_RUNTIME }, 2678 { PCI_DEVICE(0x1002, 0xab20), 2679 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2680 AZX_DCAPS_PM_RUNTIME }, 2681 { PCI_DEVICE(0x1002, 0xab28), 2682 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2683 AZX_DCAPS_PM_RUNTIME }, 2684 { PCI_DEVICE(0x1002, 0xab38), 2685 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI_NS | 2686 AZX_DCAPS_PM_RUNTIME }, 2687 /* VIA VT8251/VT8237A */ 2688 { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA }, 2689 /* VIA GFX VT7122/VX900 */ 2690 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC }, 2691 /* VIA GFX VT6122/VX11 */ 2692 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC }, 2693 /* SIS966 */ 2694 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS }, 2695 /* ULI M5461 */ 2696 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI }, 2697 /* NVIDIA MCP */ 2698 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), 2699 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2700 .class_mask = 0xffffff, 2701 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA }, 2702 /* Teradici */ 2703 { PCI_DEVICE(0x6549, 0x1200), 2704 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2705 { PCI_DEVICE(0x6549, 0x2200), 2706 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT }, 2707 /* Creative X-Fi (CA0110-IBG) */ 2708 /* CTHDA chips */ 2709 { PCI_DEVICE(0x1102, 0x0010), 2710 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2711 { PCI_DEVICE(0x1102, 0x0012), 2712 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA }, 2713 #if !IS_ENABLED(CONFIG_SND_CTXFI) 2714 /* the following entry conflicts with snd-ctxfi driver, 2715 * as ctxfi driver mutates from HD-audio to native mode with 2716 * a special command sequence. 2717 */ 2718 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID), 2719 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2720 .class_mask = 0xffffff, 2721 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2722 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2723 #else 2724 /* this entry seems still valid -- i.e. without emu20kx chip */ 2725 { PCI_DEVICE(0x1102, 0x0009), 2726 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND | 2727 AZX_DCAPS_NO_64BIT | AZX_DCAPS_POSFIX_LPIB }, 2728 #endif 2729 /* CM8888 */ 2730 { PCI_DEVICE(0x13f6, 0x5011), 2731 .driver_data = AZX_DRIVER_CMEDIA | 2732 AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_SNOOP_OFF }, 2733 /* Vortex86MX */ 2734 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC }, 2735 /* VMware HDAudio */ 2736 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC }, 2737 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */ 2738 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID), 2739 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2740 .class_mask = 0xffffff, 2741 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2742 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID), 2743 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8, 2744 .class_mask = 0xffffff, 2745 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI }, 2746 /* Zhaoxin */ 2747 { PCI_DEVICE(0x1d17, 0x3288), .driver_data = AZX_DRIVER_ZHAOXIN }, 2748 /* Loongson */ 2749 { PCI_DEVICE(0x0014, 0x7a07), .driver_data = AZX_DRIVER_GENERIC }, 2750 { 0, } 2751 }; 2752 MODULE_DEVICE_TABLE(pci, azx_ids); 2753 2754 /* pci_driver definition */ 2755 static struct pci_driver azx_driver = { 2756 .name = KBUILD_MODNAME, 2757 .id_table = azx_ids, 2758 .probe = azx_probe, 2759 .remove = azx_remove, 2760 .shutdown = azx_shutdown, 2761 .driver = { 2762 .pm = AZX_PM_OPS, 2763 }, 2764 }; 2765 2766 module_pci_driver(azx_driver); 2767