1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved. 4 5 #include <linux/kernel.h> 6 #include <linux/module.h> 7 #include <linux/init.h> 8 #include <linux/err.h> 9 #include <linux/of.h> 10 #include <linux/of_device.h> 11 #include <linux/regulator/of_regulator.h> 12 #include <linux/platform_device.h> 13 #include <linux/regulator/driver.h> 14 #include <linux/regulator/machine.h> 15 #include <linux/regulator/pfuze100.h> 16 #include <linux/i2c.h> 17 #include <linux/slab.h> 18 #include <linux/regmap.h> 19 20 #define PFUZE_FLAG_DISABLE_SW BIT(1) 21 22 #define PFUZE_NUMREGS 128 23 #define PFUZE100_VOL_OFFSET 0 24 #define PFUZE100_STANDBY_OFFSET 1 25 #define PFUZE100_MODE_OFFSET 3 26 #define PFUZE100_CONF_OFFSET 4 27 28 #define PFUZE100_DEVICEID 0x0 29 #define PFUZE100_REVID 0x3 30 #define PFUZE100_FABID 0x4 31 32 #define PFUZE100_COINVOL 0x1a 33 #define PFUZE100_SW1ABVOL 0x20 34 #define PFUZE100_SW1ABMODE 0x23 35 #define PFUZE100_SW1CVOL 0x2e 36 #define PFUZE100_SW1CMODE 0x31 37 #define PFUZE100_SW2VOL 0x35 38 #define PFUZE100_SW2MODE 0x38 39 #define PFUZE100_SW3AVOL 0x3c 40 #define PFUZE100_SW3AMODE 0x3f 41 #define PFUZE100_SW3BVOL 0x43 42 #define PFUZE100_SW3BMODE 0x46 43 #define PFUZE100_SW4VOL 0x4a 44 #define PFUZE100_SW4MODE 0x4d 45 #define PFUZE100_SWBSTCON1 0x66 46 #define PFUZE100_VREFDDRCON 0x6a 47 #define PFUZE100_VSNVSVOL 0x6b 48 #define PFUZE100_VGEN1VOL 0x6c 49 #define PFUZE100_VGEN2VOL 0x6d 50 #define PFUZE100_VGEN3VOL 0x6e 51 #define PFUZE100_VGEN4VOL 0x6f 52 #define PFUZE100_VGEN5VOL 0x70 53 #define PFUZE100_VGEN6VOL 0x71 54 55 #define PFUZE100_SWxMODE_MASK 0xf 56 #define PFUZE100_SWxMODE_APS_APS 0x8 57 #define PFUZE100_SWxMODE_APS_OFF 0x4 58 59 #define PFUZE100_VGENxLPWR BIT(6) 60 #define PFUZE100_VGENxSTBY BIT(5) 61 62 enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3, PFUZE3001 = 0x31, }; 63 64 struct pfuze_regulator { 65 struct regulator_desc desc; 66 unsigned char stby_reg; 67 unsigned char stby_mask; 68 bool sw_reg; 69 }; 70 71 struct pfuze_chip { 72 int chip_id; 73 int flags; 74 struct regmap *regmap; 75 struct device *dev; 76 struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR]; 77 struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR]; 78 struct pfuze_regulator *pfuze_regulators; 79 }; 80 81 static const int pfuze100_swbst[] = { 82 5000000, 5050000, 5100000, 5150000, 83 }; 84 85 static const int pfuze100_vsnvs[] = { 86 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000, 87 }; 88 89 static const int pfuze100_coin[] = { 90 2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000, 91 }; 92 93 static const int pfuze3000_sw1a[] = { 94 700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000, 95 900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000, 96 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 97 1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000, 98 }; 99 100 static const int pfuze3000_sw2lo[] = { 101 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000, 102 }; 103 104 static const int pfuze3000_sw2hi[] = { 105 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000, 106 }; 107 108 static const struct i2c_device_id pfuze_device_id[] = { 109 {.name = "pfuze100", .driver_data = PFUZE100}, 110 {.name = "pfuze200", .driver_data = PFUZE200}, 111 {.name = "pfuze3000", .driver_data = PFUZE3000}, 112 {.name = "pfuze3001", .driver_data = PFUZE3001}, 113 { } 114 }; 115 MODULE_DEVICE_TABLE(i2c, pfuze_device_id); 116 117 static const struct of_device_id pfuze_dt_ids[] = { 118 { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100}, 119 { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200}, 120 { .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000}, 121 { .compatible = "fsl,pfuze3001", .data = (void *)PFUZE3001}, 122 { } 123 }; 124 MODULE_DEVICE_TABLE(of, pfuze_dt_ids); 125 126 static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay) 127 { 128 struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev); 129 int id = rdev_get_id(rdev); 130 bool reg_has_ramp_delay; 131 unsigned int ramp_bits = 0; 132 int ret; 133 134 switch (pfuze100->chip_id) { 135 case PFUZE3001: 136 /* no dynamic voltage scaling for PF3001 */ 137 reg_has_ramp_delay = false; 138 break; 139 case PFUZE3000: 140 reg_has_ramp_delay = (id < PFUZE3000_SWBST); 141 break; 142 case PFUZE200: 143 reg_has_ramp_delay = (id < PFUZE200_SWBST); 144 break; 145 case PFUZE100: 146 default: 147 reg_has_ramp_delay = (id < PFUZE100_SWBST); 148 break; 149 } 150 151 if (reg_has_ramp_delay) { 152 if (ramp_delay > 0) { 153 ramp_delay = 12500 / ramp_delay; 154 ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3); 155 } 156 157 ret = regmap_update_bits(pfuze100->regmap, 158 rdev->desc->vsel_reg + 4, 159 0xc0, ramp_bits << 6); 160 if (ret < 0) 161 dev_err(pfuze100->dev, "ramp failed, err %d\n", ret); 162 } else { 163 ret = -EACCES; 164 } 165 166 return ret; 167 } 168 169 static const struct regulator_ops pfuze100_ldo_regulator_ops = { 170 .enable = regulator_enable_regmap, 171 .disable = regulator_disable_regmap, 172 .is_enabled = regulator_is_enabled_regmap, 173 .list_voltage = regulator_list_voltage_linear, 174 .set_voltage_sel = regulator_set_voltage_sel_regmap, 175 .get_voltage_sel = regulator_get_voltage_sel_regmap, 176 }; 177 178 static const struct regulator_ops pfuze100_fixed_regulator_ops = { 179 .enable = regulator_enable_regmap, 180 .disable = regulator_disable_regmap, 181 .is_enabled = regulator_is_enabled_regmap, 182 .list_voltage = regulator_list_voltage_linear, 183 }; 184 185 static const struct regulator_ops pfuze100_sw_regulator_ops = { 186 .list_voltage = regulator_list_voltage_linear, 187 .set_voltage_sel = regulator_set_voltage_sel_regmap, 188 .get_voltage_sel = regulator_get_voltage_sel_regmap, 189 .set_voltage_time_sel = regulator_set_voltage_time_sel, 190 .set_ramp_delay = pfuze100_set_ramp_delay, 191 }; 192 193 static const struct regulator_ops pfuze100_sw_disable_regulator_ops = { 194 .enable = regulator_enable_regmap, 195 .disable = regulator_disable_regmap, 196 .is_enabled = regulator_is_enabled_regmap, 197 .list_voltage = regulator_list_voltage_linear, 198 .set_voltage_sel = regulator_set_voltage_sel_regmap, 199 .get_voltage_sel = regulator_get_voltage_sel_regmap, 200 .set_voltage_time_sel = regulator_set_voltage_time_sel, 201 .set_ramp_delay = pfuze100_set_ramp_delay, 202 }; 203 204 static const struct regulator_ops pfuze100_swb_regulator_ops = { 205 .enable = regulator_enable_regmap, 206 .disable = regulator_disable_regmap, 207 .is_enabled = regulator_is_enabled_regmap, 208 .list_voltage = regulator_list_voltage_table, 209 .map_voltage = regulator_map_voltage_ascend, 210 .set_voltage_sel = regulator_set_voltage_sel_regmap, 211 .get_voltage_sel = regulator_get_voltage_sel_regmap, 212 213 }; 214 215 static const struct regulator_ops pfuze3000_sw_regulator_ops = { 216 .enable = regulator_enable_regmap, 217 .disable = regulator_disable_regmap, 218 .is_enabled = regulator_is_enabled_regmap, 219 .list_voltage = regulator_list_voltage_table, 220 .map_voltage = regulator_map_voltage_ascend, 221 .set_voltage_sel = regulator_set_voltage_sel_regmap, 222 .get_voltage_sel = regulator_get_voltage_sel_regmap, 223 .set_voltage_time_sel = regulator_set_voltage_time_sel, 224 .set_ramp_delay = pfuze100_set_ramp_delay, 225 226 }; 227 228 #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \ 229 [_chip ## _ ## _name] = { \ 230 .desc = { \ 231 .name = #_name, \ 232 .n_voltages = 1, \ 233 .ops = &pfuze100_fixed_regulator_ops, \ 234 .type = REGULATOR_VOLTAGE, \ 235 .id = _chip ## _ ## _name, \ 236 .owner = THIS_MODULE, \ 237 .min_uV = (voltage), \ 238 .enable_reg = (base), \ 239 .enable_mask = 0x10, \ 240 }, \ 241 } 242 243 #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \ 244 [_chip ## _ ## _name] = { \ 245 .desc = { \ 246 .name = #_name,\ 247 .n_voltages = ((max) - (min)) / (step) + 1, \ 248 .ops = &pfuze100_sw_regulator_ops, \ 249 .type = REGULATOR_VOLTAGE, \ 250 .id = _chip ## _ ## _name, \ 251 .owner = THIS_MODULE, \ 252 .min_uV = (min), \ 253 .uV_step = (step), \ 254 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ 255 .vsel_mask = 0x3f, \ 256 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \ 257 .enable_mask = 0xf, \ 258 }, \ 259 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \ 260 .stby_mask = 0x3f, \ 261 .sw_reg = true, \ 262 } 263 264 #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \ 265 [_chip ## _ ## _name] = { \ 266 .desc = { \ 267 .name = #_name, \ 268 .n_voltages = ARRAY_SIZE(voltages), \ 269 .ops = &pfuze100_swb_regulator_ops, \ 270 .type = REGULATOR_VOLTAGE, \ 271 .id = _chip ## _ ## _name, \ 272 .owner = THIS_MODULE, \ 273 .volt_table = voltages, \ 274 .vsel_reg = (base), \ 275 .vsel_mask = (mask), \ 276 .enable_reg = (base), \ 277 .enable_mask = 0x48, \ 278 }, \ 279 } 280 281 #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \ 282 [_chip ## _ ## _name] = { \ 283 .desc = { \ 284 .name = #_name, \ 285 .n_voltages = ((max) - (min)) / (step) + 1, \ 286 .ops = &pfuze100_ldo_regulator_ops, \ 287 .type = REGULATOR_VOLTAGE, \ 288 .id = _chip ## _ ## _name, \ 289 .owner = THIS_MODULE, \ 290 .min_uV = (min), \ 291 .uV_step = (step), \ 292 .vsel_reg = (base), \ 293 .vsel_mask = 0xf, \ 294 .enable_reg = (base), \ 295 .enable_mask = 0x10, \ 296 }, \ 297 .stby_reg = (base), \ 298 .stby_mask = 0x20, \ 299 } 300 301 #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \ 302 [_chip ## _ ## _name] = { \ 303 .desc = { \ 304 .name = #_name, \ 305 .n_voltages = ARRAY_SIZE(voltages), \ 306 .ops = &pfuze100_swb_regulator_ops, \ 307 .type = REGULATOR_VOLTAGE, \ 308 .id = _chip ## _ ## _name, \ 309 .owner = THIS_MODULE, \ 310 .volt_table = voltages, \ 311 .vsel_reg = (base), \ 312 .vsel_mask = (mask), \ 313 .enable_reg = (base), \ 314 .enable_mask = 0x8, \ 315 }, \ 316 } 317 318 #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \ 319 .desc = { \ 320 .name = #_name, \ 321 .n_voltages = ((max) - (min)) / (step) + 1, \ 322 .ops = &pfuze100_ldo_regulator_ops, \ 323 .type = REGULATOR_VOLTAGE, \ 324 .id = _chip ## _ ## _name, \ 325 .owner = THIS_MODULE, \ 326 .min_uV = (min), \ 327 .uV_step = (step), \ 328 .vsel_reg = (base), \ 329 .vsel_mask = 0x3, \ 330 .enable_reg = (base), \ 331 .enable_mask = 0x10, \ 332 }, \ 333 .stby_reg = (base), \ 334 .stby_mask = 0x20, \ 335 } 336 337 /* No linar case for the some switches of PFUZE3000 */ 338 #define PFUZE3000_SW_REG(_chip, _name, base, mask, voltages) \ 339 [_chip ## _ ## _name] = { \ 340 .desc = { \ 341 .name = #_name, \ 342 .n_voltages = ARRAY_SIZE(voltages), \ 343 .ops = &pfuze3000_sw_regulator_ops, \ 344 .type = REGULATOR_VOLTAGE, \ 345 .id = _chip ## _ ## _name, \ 346 .owner = THIS_MODULE, \ 347 .volt_table = voltages, \ 348 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ 349 .vsel_mask = (mask), \ 350 .enable_reg = (base) + PFUZE100_MODE_OFFSET, \ 351 .enable_mask = 0xf, \ 352 .enable_val = 0x8, \ 353 .enable_time = 500, \ 354 }, \ 355 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \ 356 .stby_mask = (mask), \ 357 .sw_reg = true, \ 358 } 359 360 #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \ 361 .desc = { \ 362 .name = #_name,\ 363 .n_voltages = ((max) - (min)) / (step) + 1, \ 364 .ops = &pfuze100_sw_regulator_ops, \ 365 .type = REGULATOR_VOLTAGE, \ 366 .id = _chip ## _ ## _name, \ 367 .owner = THIS_MODULE, \ 368 .min_uV = (min), \ 369 .uV_step = (step), \ 370 .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \ 371 .vsel_mask = 0xf, \ 372 }, \ 373 .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \ 374 .stby_mask = 0xf, \ 375 } 376 377 /* PFUZE100 */ 378 static struct pfuze_regulator pfuze100_regulators[] = { 379 PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000), 380 PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000), 381 PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000), 382 PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000), 383 PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000), 384 PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000), 385 PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst), 386 PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), 387 PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000), 388 PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000), 389 PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000), 390 PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000), 391 PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000), 392 PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000), 393 PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000), 394 PFUZE100_COIN_REG(PFUZE100, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin), 395 }; 396 397 static struct pfuze_regulator pfuze200_regulators[] = { 398 PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000), 399 PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000), 400 PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000), 401 PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000), 402 PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst), 403 PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), 404 PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000), 405 PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000), 406 PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000), 407 PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000), 408 PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000), 409 PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000), 410 PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000), 411 PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin), 412 }; 413 414 static struct pfuze_regulator pfuze3000_regulators[] = { 415 PFUZE3000_SW_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a), 416 PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000), 417 PFUZE3000_SW_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo), 418 PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000), 419 PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst), 420 PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), 421 PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000), 422 PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000), 423 PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000), 424 PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000), 425 PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000), 426 PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000), 427 PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000), 428 }; 429 430 static struct pfuze_regulator pfuze3001_regulators[] = { 431 PFUZE3000_SW_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a), 432 PFUZE3000_SW_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo), 433 PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000), 434 PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs), 435 PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000), 436 PFUZE100_VGEN_REG(PFUZE3001, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000), 437 PFUZE3000_VCC_REG(PFUZE3001, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000), 438 PFUZE3000_VCC_REG(PFUZE3001, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000), 439 PFUZE100_VGEN_REG(PFUZE3001, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000), 440 PFUZE100_VGEN_REG(PFUZE3001, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000), 441 }; 442 443 #ifdef CONFIG_OF 444 /* PFUZE100 */ 445 static struct of_regulator_match pfuze100_matches[] = { 446 { .name = "sw1ab", }, 447 { .name = "sw1c", }, 448 { .name = "sw2", }, 449 { .name = "sw3a", }, 450 { .name = "sw3b", }, 451 { .name = "sw4", }, 452 { .name = "swbst", }, 453 { .name = "vsnvs", }, 454 { .name = "vrefddr", }, 455 { .name = "vgen1", }, 456 { .name = "vgen2", }, 457 { .name = "vgen3", }, 458 { .name = "vgen4", }, 459 { .name = "vgen5", }, 460 { .name = "vgen6", }, 461 { .name = "coin", }, 462 }; 463 464 /* PFUZE200 */ 465 static struct of_regulator_match pfuze200_matches[] = { 466 467 { .name = "sw1ab", }, 468 { .name = "sw2", }, 469 { .name = "sw3a", }, 470 { .name = "sw3b", }, 471 { .name = "swbst", }, 472 { .name = "vsnvs", }, 473 { .name = "vrefddr", }, 474 { .name = "vgen1", }, 475 { .name = "vgen2", }, 476 { .name = "vgen3", }, 477 { .name = "vgen4", }, 478 { .name = "vgen5", }, 479 { .name = "vgen6", }, 480 { .name = "coin", }, 481 }; 482 483 /* PFUZE3000 */ 484 static struct of_regulator_match pfuze3000_matches[] = { 485 486 { .name = "sw1a", }, 487 { .name = "sw1b", }, 488 { .name = "sw2", }, 489 { .name = "sw3", }, 490 { .name = "swbst", }, 491 { .name = "vsnvs", }, 492 { .name = "vrefddr", }, 493 { .name = "vldo1", }, 494 { .name = "vldo2", }, 495 { .name = "vccsd", }, 496 { .name = "v33", }, 497 { .name = "vldo3", }, 498 { .name = "vldo4", }, 499 }; 500 501 /* PFUZE3001 */ 502 static struct of_regulator_match pfuze3001_matches[] = { 503 504 { .name = "sw1", }, 505 { .name = "sw2", }, 506 { .name = "sw3", }, 507 { .name = "vsnvs", }, 508 { .name = "vldo1", }, 509 { .name = "vldo2", }, 510 { .name = "vccsd", }, 511 { .name = "v33", }, 512 { .name = "vldo3", }, 513 { .name = "vldo4", }, 514 }; 515 516 static struct of_regulator_match *pfuze_matches; 517 518 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip) 519 { 520 struct device *dev = chip->dev; 521 struct device_node *np, *parent; 522 int ret; 523 524 np = of_node_get(dev->of_node); 525 if (!np) 526 return -EINVAL; 527 528 if (of_property_read_bool(np, "fsl,pfuze-support-disable-sw")) 529 chip->flags |= PFUZE_FLAG_DISABLE_SW; 530 531 parent = of_get_child_by_name(np, "regulators"); 532 if (!parent) { 533 dev_err(dev, "regulators node not found\n"); 534 return -EINVAL; 535 } 536 537 switch (chip->chip_id) { 538 case PFUZE3001: 539 pfuze_matches = pfuze3001_matches; 540 ret = of_regulator_match(dev, parent, pfuze3001_matches, 541 ARRAY_SIZE(pfuze3001_matches)); 542 break; 543 case PFUZE3000: 544 pfuze_matches = pfuze3000_matches; 545 ret = of_regulator_match(dev, parent, pfuze3000_matches, 546 ARRAY_SIZE(pfuze3000_matches)); 547 break; 548 case PFUZE200: 549 pfuze_matches = pfuze200_matches; 550 ret = of_regulator_match(dev, parent, pfuze200_matches, 551 ARRAY_SIZE(pfuze200_matches)); 552 break; 553 554 case PFUZE100: 555 default: 556 pfuze_matches = pfuze100_matches; 557 ret = of_regulator_match(dev, parent, pfuze100_matches, 558 ARRAY_SIZE(pfuze100_matches)); 559 break; 560 } 561 562 of_node_put(parent); 563 if (ret < 0) { 564 dev_err(dev, "Error parsing regulator init data: %d\n", 565 ret); 566 return ret; 567 } 568 569 return 0; 570 } 571 572 static inline struct regulator_init_data *match_init_data(int index) 573 { 574 return pfuze_matches[index].init_data; 575 } 576 577 static inline struct device_node *match_of_node(int index) 578 { 579 return pfuze_matches[index].of_node; 580 } 581 #else 582 static int pfuze_parse_regulators_dt(struct pfuze_chip *chip) 583 { 584 return 0; 585 } 586 587 static inline struct regulator_init_data *match_init_data(int index) 588 { 589 return NULL; 590 } 591 592 static inline struct device_node *match_of_node(int index) 593 { 594 return NULL; 595 } 596 #endif 597 598 static struct pfuze_chip *syspm_pfuze_chip; 599 600 static void pfuze_power_off_prepare(void) 601 { 602 dev_info(syspm_pfuze_chip->dev, "Configure standby mode for power off"); 603 604 /* Switch from default mode: APS/APS to APS/Off */ 605 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1ABMODE, 606 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF); 607 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1CMODE, 608 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF); 609 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW2MODE, 610 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF); 611 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3AMODE, 612 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF); 613 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3BMODE, 614 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF); 615 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW4MODE, 616 PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF); 617 618 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN1VOL, 619 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY, 620 PFUZE100_VGENxSTBY); 621 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN2VOL, 622 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY, 623 PFUZE100_VGENxSTBY); 624 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN3VOL, 625 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY, 626 PFUZE100_VGENxSTBY); 627 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN4VOL, 628 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY, 629 PFUZE100_VGENxSTBY); 630 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN5VOL, 631 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY, 632 PFUZE100_VGENxSTBY); 633 regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN6VOL, 634 PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY, 635 PFUZE100_VGENxSTBY); 636 } 637 638 static int pfuze_power_off_prepare_init(struct pfuze_chip *pfuze_chip) 639 { 640 if (pfuze_chip->chip_id != PFUZE100) { 641 dev_warn(pfuze_chip->dev, "Requested pm_power_off_prepare handler for not supported chip\n"); 642 return -ENODEV; 643 } 644 645 if (pm_power_off_prepare) { 646 dev_warn(pfuze_chip->dev, "pm_power_off_prepare is already registered.\n"); 647 return -EBUSY; 648 } 649 650 if (syspm_pfuze_chip) { 651 dev_warn(pfuze_chip->dev, "syspm_pfuze_chip is already set.\n"); 652 return -EBUSY; 653 } 654 655 syspm_pfuze_chip = pfuze_chip; 656 pm_power_off_prepare = pfuze_power_off_prepare; 657 658 return 0; 659 } 660 661 static int pfuze_identify(struct pfuze_chip *pfuze_chip) 662 { 663 unsigned int value; 664 int ret; 665 666 ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value); 667 if (ret) 668 return ret; 669 670 if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) { 671 /* 672 * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013 673 * as ID=8 in PFUZE100 674 */ 675 dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8"); 676 } else if ((value & 0x0f) != pfuze_chip->chip_id && 677 (value & 0xf0) >> 4 != pfuze_chip->chip_id && 678 (value != pfuze_chip->chip_id)) { 679 /* device id NOT match with your setting */ 680 dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value); 681 return -ENODEV; 682 } 683 684 ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value); 685 if (ret) 686 return ret; 687 dev_info(pfuze_chip->dev, 688 "Full layer: %x, Metal layer: %x\n", 689 (value & 0xf0) >> 4, value & 0x0f); 690 691 ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value); 692 if (ret) 693 return ret; 694 dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n", 695 (value & 0xc) >> 2, value & 0x3); 696 697 return 0; 698 } 699 700 static const struct regmap_config pfuze_regmap_config = { 701 .reg_bits = 8, 702 .val_bits = 8, 703 .max_register = PFUZE_NUMREGS - 1, 704 .cache_type = REGCACHE_RBTREE, 705 }; 706 707 static int pfuze100_regulator_probe(struct i2c_client *client, 708 const struct i2c_device_id *id) 709 { 710 struct pfuze_chip *pfuze_chip; 711 struct pfuze_regulator_platform_data *pdata = 712 dev_get_platdata(&client->dev); 713 struct regulator_config config = { }; 714 int i, ret; 715 const struct of_device_id *match; 716 u32 regulator_num; 717 u32 sw_check_start, sw_check_end, sw_hi = 0x40; 718 719 pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip), 720 GFP_KERNEL); 721 if (!pfuze_chip) 722 return -ENOMEM; 723 724 if (client->dev.of_node) { 725 match = of_match_device(of_match_ptr(pfuze_dt_ids), 726 &client->dev); 727 if (!match) { 728 dev_err(&client->dev, "Error: No device match found\n"); 729 return -ENODEV; 730 } 731 pfuze_chip->chip_id = (int)(long)match->data; 732 } else if (id) { 733 pfuze_chip->chip_id = id->driver_data; 734 } else { 735 dev_err(&client->dev, "No dts match or id table match found\n"); 736 return -ENODEV; 737 } 738 739 i2c_set_clientdata(client, pfuze_chip); 740 pfuze_chip->dev = &client->dev; 741 742 pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config); 743 if (IS_ERR(pfuze_chip->regmap)) { 744 ret = PTR_ERR(pfuze_chip->regmap); 745 dev_err(&client->dev, 746 "regmap allocation failed with err %d\n", ret); 747 return ret; 748 } 749 750 ret = pfuze_identify(pfuze_chip); 751 if (ret) { 752 dev_err(&client->dev, "unrecognized pfuze chip ID!\n"); 753 return ret; 754 } 755 756 /* use the right regulators after identify the right device */ 757 switch (pfuze_chip->chip_id) { 758 case PFUZE3001: 759 pfuze_chip->pfuze_regulators = pfuze3001_regulators; 760 regulator_num = ARRAY_SIZE(pfuze3001_regulators); 761 sw_check_start = PFUZE3001_SW2; 762 sw_check_end = PFUZE3001_SW2; 763 sw_hi = 1 << 3; 764 break; 765 case PFUZE3000: 766 pfuze_chip->pfuze_regulators = pfuze3000_regulators; 767 regulator_num = ARRAY_SIZE(pfuze3000_regulators); 768 sw_check_start = PFUZE3000_SW2; 769 sw_check_end = PFUZE3000_SW2; 770 sw_hi = 1 << 3; 771 break; 772 case PFUZE200: 773 pfuze_chip->pfuze_regulators = pfuze200_regulators; 774 regulator_num = ARRAY_SIZE(pfuze200_regulators); 775 sw_check_start = PFUZE200_SW2; 776 sw_check_end = PFUZE200_SW3B; 777 break; 778 case PFUZE100: 779 default: 780 pfuze_chip->pfuze_regulators = pfuze100_regulators; 781 regulator_num = ARRAY_SIZE(pfuze100_regulators); 782 sw_check_start = PFUZE100_SW2; 783 sw_check_end = PFUZE100_SW4; 784 break; 785 } 786 dev_info(&client->dev, "pfuze%s found.\n", 787 (pfuze_chip->chip_id == PFUZE100) ? "100" : 788 (((pfuze_chip->chip_id == PFUZE200) ? "200" : 789 ((pfuze_chip->chip_id == PFUZE3000) ? "3000" : "3001")))); 790 791 memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators, 792 sizeof(pfuze_chip->regulator_descs)); 793 794 ret = pfuze_parse_regulators_dt(pfuze_chip); 795 if (ret) 796 return ret; 797 798 for (i = 0; i < regulator_num; i++) { 799 struct regulator_init_data *init_data; 800 struct regulator_desc *desc; 801 int val; 802 803 desc = &pfuze_chip->regulator_descs[i].desc; 804 805 if (pdata) 806 init_data = pdata->init_data[i]; 807 else 808 init_data = match_init_data(i); 809 810 /* SW2~SW4 high bit check and modify the voltage value table */ 811 if (i >= sw_check_start && i <= sw_check_end) { 812 ret = regmap_read(pfuze_chip->regmap, 813 desc->vsel_reg, &val); 814 if (ret) { 815 dev_err(&client->dev, "Fails to read from the register.\n"); 816 return ret; 817 } 818 819 if (val & sw_hi) { 820 if (pfuze_chip->chip_id == PFUZE3000 || 821 pfuze_chip->chip_id == PFUZE3001) { 822 desc->volt_table = pfuze3000_sw2hi; 823 desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi); 824 } else { 825 desc->min_uV = 800000; 826 desc->uV_step = 50000; 827 desc->n_voltages = 51; 828 } 829 } 830 } 831 832 /* 833 * Allow SW regulators to turn off. Checking it trough a flag is 834 * a workaround to keep the backward compatibility with existing 835 * old dtb's which may relay on the fact that we didn't disable 836 * the switched regulator till yet. 837 */ 838 if (pfuze_chip->flags & PFUZE_FLAG_DISABLE_SW) { 839 if (pfuze_chip->regulator_descs[i].sw_reg) { 840 desc->ops = &pfuze100_sw_disable_regulator_ops; 841 desc->enable_val = 0x8; 842 desc->disable_val = 0x0; 843 desc->enable_time = 500; 844 } 845 } 846 847 config.dev = &client->dev; 848 config.init_data = init_data; 849 config.driver_data = pfuze_chip; 850 config.of_node = match_of_node(i); 851 852 pfuze_chip->regulators[i] = 853 devm_regulator_register(&client->dev, desc, &config); 854 if (IS_ERR(pfuze_chip->regulators[i])) { 855 dev_err(&client->dev, "register regulator%s failed\n", 856 pfuze_chip->pfuze_regulators[i].desc.name); 857 return PTR_ERR(pfuze_chip->regulators[i]); 858 } 859 } 860 861 if (of_property_read_bool(client->dev.of_node, 862 "fsl,pmic-stby-poweroff")) 863 return pfuze_power_off_prepare_init(pfuze_chip); 864 865 return 0; 866 } 867 868 static int pfuze100_regulator_remove(struct i2c_client *client) 869 { 870 if (syspm_pfuze_chip) { 871 syspm_pfuze_chip = NULL; 872 pm_power_off_prepare = NULL; 873 } 874 875 return 0; 876 } 877 878 static struct i2c_driver pfuze_driver = { 879 .id_table = pfuze_device_id, 880 .driver = { 881 .name = "pfuze100-regulator", 882 .of_match_table = pfuze_dt_ids, 883 }, 884 .probe = pfuze100_regulator_probe, 885 .remove = pfuze100_regulator_remove, 886 }; 887 module_i2c_driver(pfuze_driver); 888 889 MODULE_AUTHOR("Robin Gong <b38343@freescale.com>"); 890 MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000/3001 PMIC"); 891 MODULE_LICENSE("GPL v2"); 892