1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: "http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#" 5$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6 7title: Atmel Timer Counter Block 8 9maintainers: 10 - Alexandre Belloni <alexandre.belloni@bootlin.com> 11 12description: | 13 The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each 14 timer has three channels with two counters each. 15 16properties: 17 compatible: 18 items: 19 - enum: 20 - atmel,at91rm9200-tcb 21 - atmel,at91sam9x5-tcb 22 - atmel,sama5d2-tcb 23 - const: simple-mfd 24 - const: syscon 25 26 reg: 27 maxItems: 1 28 29 interrupts: 30 description: 31 List of interrupts. One interrupt per TCB channel if available or one 32 interrupt for the TC block 33 minItems: 1 34 maxItems: 3 35 36 clock-names: 37 description: 38 List of clock names. Always includes t0_clk and slow clk. Also includes 39 t1_clk and t2_clk if a clock per channel is available. 40 minItems: 2 41 maxItems: 4 42 43 clocks: 44 minItems: 2 45 maxItems: 4 46 47 '#address-cells': 48 const: 1 49 50 '#size-cells': 51 const: 0 52 53patternProperties: 54 "^timer@[0-2]$": 55 description: The timer block channels that are used as timers or counters. 56 type: object 57 properties: 58 compatible: 59 items: 60 - enum: 61 - atmel,tcb-timer 62 - microchip,tcb-capture 63 reg: 64 description: 65 List of channels to use for this particular timer. In Microchip TCB capture 66 mode channels are registered as a counter devices, for the qdec mode TCB0's 67 channel <0> and <1> are required. 68 69 minItems: 1 70 maxItems: 3 71 72 required: 73 - compatible 74 - reg 75 76allOf: 77 - if: 78 properties: 79 compatible: 80 contains: 81 const: atmel,sama5d2-tcb 82 then: 83 properties: 84 clocks: 85 minItems: 3 86 maxItems: 3 87 clock-names: 88 items: 89 - const: t0_clk 90 - const: gclk 91 - const: slow_clk 92 else: 93 properties: 94 clocks: 95 minItems: 2 96 maxItems: 4 97 clock-names: 98 oneOf: 99 - items: 100 - const: t0_clk 101 - const: slow_clk 102 - items: 103 - const: t0_clk 104 - const: t1_clk 105 - const: t2_clk 106 - const: slow_clk 107 108required: 109 - compatible 110 - reg 111 - interrupts 112 - clocks 113 - clock-names 114 - '#address-cells' 115 - '#size-cells' 116 117additionalProperties: false 118 119examples: 120 - | 121 /* One interrupt per TC block: */ 122 tcb0: timer@fff7c000 { 123 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 reg = <0xfff7c000 0x100>; 127 interrupts = <18 4>; 128 clocks = <&tcb0_clk>, <&clk32k>; 129 clock-names = "t0_clk", "slow_clk"; 130 131 timer@0 { 132 compatible = "atmel,tcb-timer"; 133 reg = <0>, <1>; 134 }; 135 136 timer@2 { 137 compatible = "atmel,tcb-timer"; 138 reg = <2>; 139 }; 140 }; 141 142 /* One interrupt per TC channel in a TC block: */ 143 tcb1: timer@fffdc000 { 144 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 145 #address-cells = <1>; 146 #size-cells = <0>; 147 reg = <0xfffdc000 0x100>; 148 interrupts = <26 4>, <27 4>, <28 4>; 149 clocks = <&tcb1_clk>, <&clk32k>; 150 clock-names = "t0_clk", "slow_clk"; 151 152 timer@0 { 153 compatible = "atmel,tcb-timer"; 154 reg = <0>; 155 }; 156 157 timer@1 { 158 compatible = "atmel,tcb-timer"; 159 reg = <1>; 160 }; 161 }; 162 /* TCB0 Capture with QDEC: */ 163 timer@f800c000 { 164 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 reg = <0xfff7c000 0x100>; 168 interrupts = <18 4>; 169 clocks = <&tcb0_clk>, <&clk32k>; 170 clock-names = "t0_clk", "slow_clk"; 171 172 timer@0 { 173 compatible = "microchip,tcb-capture"; 174 reg = <0>, <1>; 175 }; 176 177 timer@2 { 178 compatible = "atmel,tcb-timer"; 179 reg = <2>; 180 }; 181 }; 182