1 // SPDX-License-Identifier: GPL-2.0-only 2 /* uctrl.c: TS102 Microcontroller interface on Tadpole Sparcbook 3 3 * 4 * Copyright 1999 Derrick J Brashear (shadow@dementia.org) 5 * Copyright 2008 David S. Miller (davem@davemloft.net) 6 */ 7 8 #include <linux/module.h> 9 #include <linux/errno.h> 10 #include <linux/delay.h> 11 #include <linux/interrupt.h> 12 #include <linux/slab.h> 13 #include <linux/mutex.h> 14 #include <linux/ioport.h> 15 #include <linux/miscdevice.h> 16 #include <linux/mm.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 20 #include <asm/openprom.h> 21 #include <asm/oplib.h> 22 #include <asm/irq.h> 23 #include <asm/io.h> 24 #include <asm/pgtable.h> 25 26 #define DEBUG 1 27 #ifdef DEBUG 28 #define dprintk(x) printk x 29 #else 30 #define dprintk(x) 31 #endif 32 33 struct uctrl_regs { 34 u32 uctrl_intr; 35 u32 uctrl_data; 36 u32 uctrl_stat; 37 u32 uctrl_xxx[5]; 38 }; 39 40 struct ts102_regs { 41 u32 card_a_intr; 42 u32 card_a_stat; 43 u32 card_a_ctrl; 44 u32 card_a_xxx; 45 u32 card_b_intr; 46 u32 card_b_stat; 47 u32 card_b_ctrl; 48 u32 card_b_xxx; 49 u32 uctrl_intr; 50 u32 uctrl_data; 51 u32 uctrl_stat; 52 u32 uctrl_xxx; 53 u32 ts102_xxx[4]; 54 }; 55 56 /* Bits for uctrl_intr register */ 57 #define UCTRL_INTR_TXE_REQ 0x01 /* transmit FIFO empty int req */ 58 #define UCTRL_INTR_TXNF_REQ 0x02 /* transmit FIFO not full int req */ 59 #define UCTRL_INTR_RXNE_REQ 0x04 /* receive FIFO not empty int req */ 60 #define UCTRL_INTR_RXO_REQ 0x08 /* receive FIFO overflow int req */ 61 #define UCTRL_INTR_TXE_MSK 0x10 /* transmit FIFO empty mask */ 62 #define UCTRL_INTR_TXNF_MSK 0x20 /* transmit FIFO not full mask */ 63 #define UCTRL_INTR_RXNE_MSK 0x40 /* receive FIFO not empty mask */ 64 #define UCTRL_INTR_RXO_MSK 0x80 /* receive FIFO overflow mask */ 65 66 /* Bits for uctrl_stat register */ 67 #define UCTRL_STAT_TXE_STA 0x01 /* transmit FIFO empty status */ 68 #define UCTRL_STAT_TXNF_STA 0x02 /* transmit FIFO not full status */ 69 #define UCTRL_STAT_RXNE_STA 0x04 /* receive FIFO not empty status */ 70 #define UCTRL_STAT_RXO_STA 0x08 /* receive FIFO overflow status */ 71 72 static DEFINE_MUTEX(uctrl_mutex); 73 static const char *uctrl_extstatus[16] = { 74 "main power available", 75 "internal battery attached", 76 "external battery attached", 77 "external VGA attached", 78 "external keyboard attached", 79 "external mouse attached", 80 "lid down", 81 "internal battery currently charging", 82 "external battery currently charging", 83 "internal battery currently discharging", 84 "external battery currently discharging", 85 }; 86 87 /* Everything required for one transaction with the uctrl */ 88 struct uctrl_txn { 89 u8 opcode; 90 u8 inbits; 91 u8 outbits; 92 u8 *inbuf; 93 u8 *outbuf; 94 }; 95 96 struct uctrl_status { 97 u8 current_temp; /* 0x07 */ 98 u8 reset_status; /* 0x0b */ 99 u16 event_status; /* 0x0c */ 100 u16 error_status; /* 0x10 */ 101 u16 external_status; /* 0x11, 0x1b */ 102 u8 internal_charge; /* 0x18 */ 103 u8 external_charge; /* 0x19 */ 104 u16 control_lcd; /* 0x20 */ 105 u8 control_bitport; /* 0x21 */ 106 u8 speaker_volume; /* 0x23 */ 107 u8 control_tft_brightness; /* 0x24 */ 108 u8 control_kbd_repeat_delay; /* 0x28 */ 109 u8 control_kbd_repeat_period; /* 0x29 */ 110 u8 control_screen_contrast; /* 0x2F */ 111 }; 112 113 enum uctrl_opcode { 114 READ_SERIAL_NUMBER=0x1, 115 READ_ETHERNET_ADDRESS=0x2, 116 READ_HARDWARE_VERSION=0x3, 117 READ_MICROCONTROLLER_VERSION=0x4, 118 READ_MAX_TEMPERATURE=0x5, 119 READ_MIN_TEMPERATURE=0x6, 120 READ_CURRENT_TEMPERATURE=0x7, 121 READ_SYSTEM_VARIANT=0x8, 122 READ_POWERON_CYCLES=0x9, 123 READ_POWERON_SECONDS=0xA, 124 READ_RESET_STATUS=0xB, 125 READ_EVENT_STATUS=0xC, 126 READ_REAL_TIME_CLOCK=0xD, 127 READ_EXTERNAL_VGA_PORT=0xE, 128 READ_MICROCONTROLLER_ROM_CHECKSUM=0xF, 129 READ_ERROR_STATUS=0x10, 130 READ_EXTERNAL_STATUS=0x11, 131 READ_USER_CONFIGURATION_AREA=0x12, 132 READ_MICROCONTROLLER_VOLTAGE=0x13, 133 READ_INTERNAL_BATTERY_VOLTAGE=0x14, 134 READ_DCIN_VOLTAGE=0x15, 135 READ_HORIZONTAL_POINTER_VOLTAGE=0x16, 136 READ_VERTICAL_POINTER_VOLTAGE=0x17, 137 READ_INTERNAL_BATTERY_CHARGE_LEVEL=0x18, 138 READ_EXTERNAL_BATTERY_CHARGE_LEVEL=0x19, 139 READ_REAL_TIME_CLOCK_ALARM=0x1A, 140 READ_EVENT_STATUS_NO_RESET=0x1B, 141 READ_INTERNAL_KEYBOARD_LAYOUT=0x1C, 142 READ_EXTERNAL_KEYBOARD_LAYOUT=0x1D, 143 READ_EEPROM_STATUS=0x1E, 144 CONTROL_LCD=0x20, 145 CONTROL_BITPORT=0x21, 146 SPEAKER_VOLUME=0x23, 147 CONTROL_TFT_BRIGHTNESS=0x24, 148 CONTROL_WATCHDOG=0x25, 149 CONTROL_FACTORY_EEPROM_AREA=0x26, 150 CONTROL_KBD_TIME_UNTIL_REPEAT=0x28, 151 CONTROL_KBD_TIME_BETWEEN_REPEATS=0x29, 152 CONTROL_TIMEZONE=0x2A, 153 CONTROL_MARK_SPACE_RATIO=0x2B, 154 CONTROL_DIAGNOSTIC_MODE=0x2E, 155 CONTROL_SCREEN_CONTRAST=0x2F, 156 RING_BELL=0x30, 157 SET_DIAGNOSTIC_STATUS=0x32, 158 CLEAR_KEY_COMBINATION_TABLE=0x33, 159 PERFORM_SOFTWARE_RESET=0x34, 160 SET_REAL_TIME_CLOCK=0x35, 161 RECALIBRATE_POINTING_STICK=0x36, 162 SET_BELL_FREQUENCY=0x37, 163 SET_INTERNAL_BATTERY_CHARGE_RATE=0x39, 164 SET_EXTERNAL_BATTERY_CHARGE_RATE=0x3A, 165 SET_REAL_TIME_CLOCK_ALARM=0x3B, 166 READ_EEPROM=0x40, 167 WRITE_EEPROM=0x41, 168 WRITE_TO_STATUS_DISPLAY=0x42, 169 DEFINE_SPECIAL_CHARACTER=0x43, 170 DEFINE_KEY_COMBINATION_ENTRY=0x50, 171 DEFINE_STRING_TABLE_ENTRY=0x51, 172 DEFINE_STATUS_SCREEN_DISPLAY=0x52, 173 PERFORM_EMU_COMMANDS=0x64, 174 READ_EMU_REGISTER=0x65, 175 WRITE_EMU_REGISTER=0x66, 176 READ_EMU_RAM=0x67, 177 WRITE_EMU_RAM=0x68, 178 READ_BQ_REGISTER=0x69, 179 WRITE_BQ_REGISTER=0x6A, 180 SET_USER_PASSWORD=0x70, 181 VERIFY_USER_PASSWORD=0x71, 182 GET_SYSTEM_PASSWORD_KEY=0x72, 183 VERIFY_SYSTEM_PASSWORD=0x73, 184 POWER_OFF=0x82, 185 POWER_RESTART=0x83, 186 }; 187 188 static struct uctrl_driver { 189 struct uctrl_regs __iomem *regs; 190 int irq; 191 int pending; 192 struct uctrl_status status; 193 } *global_driver; 194 195 static void uctrl_get_event_status(struct uctrl_driver *); 196 static void uctrl_get_external_status(struct uctrl_driver *); 197 198 static long 199 uctrl_ioctl(struct file *file, unsigned int cmd, unsigned long arg) 200 { 201 switch (cmd) { 202 default: 203 return -EINVAL; 204 } 205 return 0; 206 } 207 208 static int 209 uctrl_open(struct inode *inode, struct file *file) 210 { 211 mutex_lock(&uctrl_mutex); 212 uctrl_get_event_status(global_driver); 213 uctrl_get_external_status(global_driver); 214 mutex_unlock(&uctrl_mutex); 215 return 0; 216 } 217 218 static irqreturn_t uctrl_interrupt(int irq, void *dev_id) 219 { 220 return IRQ_HANDLED; 221 } 222 223 static const struct file_operations uctrl_fops = { 224 .owner = THIS_MODULE, 225 .llseek = no_llseek, 226 .unlocked_ioctl = uctrl_ioctl, 227 .open = uctrl_open, 228 }; 229 230 static struct miscdevice uctrl_dev = { 231 UCTRL_MINOR, 232 "uctrl", 233 &uctrl_fops 234 }; 235 236 /* Wait for space to write, then write to it */ 237 #define WRITEUCTLDATA(value) \ 238 { \ 239 unsigned int i; \ 240 for (i = 0; i < 10000; i++) { \ 241 if (UCTRL_STAT_TXNF_STA & sbus_readl(&driver->regs->uctrl_stat)) \ 242 break; \ 243 } \ 244 dprintk(("write data 0x%02x\n", value)); \ 245 sbus_writel(value, &driver->regs->uctrl_data); \ 246 } 247 248 /* Wait for something to read, read it, then clear the bit */ 249 #define READUCTLDATA(value) \ 250 { \ 251 unsigned int i; \ 252 value = 0; \ 253 for (i = 0; i < 10000; i++) { \ 254 if ((UCTRL_STAT_RXNE_STA & sbus_readl(&driver->regs->uctrl_stat)) == 0) \ 255 break; \ 256 udelay(1); \ 257 } \ 258 value = sbus_readl(&driver->regs->uctrl_data); \ 259 dprintk(("read data 0x%02x\n", value)); \ 260 sbus_writel(UCTRL_STAT_RXNE_STA, &driver->regs->uctrl_stat); \ 261 } 262 263 static void uctrl_do_txn(struct uctrl_driver *driver, struct uctrl_txn *txn) 264 { 265 int stat, incnt, outcnt, bytecnt, intr; 266 u32 byte; 267 268 stat = sbus_readl(&driver->regs->uctrl_stat); 269 intr = sbus_readl(&driver->regs->uctrl_intr); 270 sbus_writel(stat, &driver->regs->uctrl_stat); 271 272 dprintk(("interrupt stat 0x%x int 0x%x\n", stat, intr)); 273 274 incnt = txn->inbits; 275 outcnt = txn->outbits; 276 byte = (txn->opcode << 8); 277 WRITEUCTLDATA(byte); 278 279 bytecnt = 0; 280 while (incnt > 0) { 281 byte = (txn->inbuf[bytecnt] << 8); 282 WRITEUCTLDATA(byte); 283 incnt--; 284 bytecnt++; 285 } 286 287 /* Get the ack */ 288 READUCTLDATA(byte); 289 dprintk(("ack was %x\n", (byte >> 8))); 290 291 bytecnt = 0; 292 while (outcnt > 0) { 293 READUCTLDATA(byte); 294 txn->outbuf[bytecnt] = (byte >> 8); 295 dprintk(("set byte to %02x\n", byte)); 296 outcnt--; 297 bytecnt++; 298 } 299 } 300 301 static void uctrl_get_event_status(struct uctrl_driver *driver) 302 { 303 struct uctrl_txn txn; 304 u8 outbits[2]; 305 306 txn.opcode = READ_EVENT_STATUS; 307 txn.inbits = 0; 308 txn.outbits = 2; 309 txn.inbuf = NULL; 310 txn.outbuf = outbits; 311 312 uctrl_do_txn(driver, &txn); 313 314 dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff))); 315 driver->status.event_status = 316 ((outbits[0] & 0xff) << 8) | (outbits[1] & 0xff); 317 dprintk(("ev is %x\n", driver->status.event_status)); 318 } 319 320 static void uctrl_get_external_status(struct uctrl_driver *driver) 321 { 322 struct uctrl_txn txn; 323 u8 outbits[2]; 324 int i, v; 325 326 txn.opcode = READ_EXTERNAL_STATUS; 327 txn.inbits = 0; 328 txn.outbits = 2; 329 txn.inbuf = NULL; 330 txn.outbuf = outbits; 331 332 uctrl_do_txn(driver, &txn); 333 334 dprintk(("bytes %x %x\n", (outbits[0] & 0xff), (outbits[1] & 0xff))); 335 driver->status.external_status = 336 ((outbits[0] * 256) + (outbits[1])); 337 dprintk(("ex is %x\n", driver->status.external_status)); 338 v = driver->status.external_status; 339 for (i = 0; v != 0; i++, v >>= 1) { 340 if (v & 1) { 341 dprintk(("%s%s", " ", uctrl_extstatus[i])); 342 } 343 } 344 dprintk(("\n")); 345 346 } 347 348 static int uctrl_probe(struct platform_device *op) 349 { 350 struct uctrl_driver *p; 351 int err = -ENOMEM; 352 353 p = kzalloc(sizeof(*p), GFP_KERNEL); 354 if (!p) { 355 printk(KERN_ERR "uctrl: Unable to allocate device struct.\n"); 356 goto out; 357 } 358 359 p->regs = of_ioremap(&op->resource[0], 0, 360 resource_size(&op->resource[0]), 361 "uctrl"); 362 if (!p->regs) { 363 printk(KERN_ERR "uctrl: Unable to map registers.\n"); 364 goto out_free; 365 } 366 367 p->irq = op->archdata.irqs[0]; 368 err = request_irq(p->irq, uctrl_interrupt, 0, "uctrl", p); 369 if (err) { 370 printk(KERN_ERR "uctrl: Unable to register irq.\n"); 371 goto out_iounmap; 372 } 373 374 err = misc_register(&uctrl_dev); 375 if (err) { 376 printk(KERN_ERR "uctrl: Unable to register misc device.\n"); 377 goto out_free_irq; 378 } 379 380 sbus_writel(UCTRL_INTR_RXNE_REQ|UCTRL_INTR_RXNE_MSK, &p->regs->uctrl_intr); 381 printk(KERN_INFO "%pOF: uctrl regs[0x%p] (irq %d)\n", 382 op->dev.of_node, p->regs, p->irq); 383 uctrl_get_event_status(p); 384 uctrl_get_external_status(p); 385 386 dev_set_drvdata(&op->dev, p); 387 global_driver = p; 388 389 out: 390 return err; 391 392 out_free_irq: 393 free_irq(p->irq, p); 394 395 out_iounmap: 396 of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0])); 397 398 out_free: 399 kfree(p); 400 goto out; 401 } 402 403 static int uctrl_remove(struct platform_device *op) 404 { 405 struct uctrl_driver *p = dev_get_drvdata(&op->dev); 406 407 if (p) { 408 misc_deregister(&uctrl_dev); 409 free_irq(p->irq, p); 410 of_iounmap(&op->resource[0], p->regs, resource_size(&op->resource[0])); 411 kfree(p); 412 } 413 return 0; 414 } 415 416 static const struct of_device_id uctrl_match[] = { 417 { 418 .name = "uctrl", 419 }, 420 {}, 421 }; 422 MODULE_DEVICE_TABLE(of, uctrl_match); 423 424 static struct platform_driver uctrl_driver = { 425 .driver = { 426 .name = "uctrl", 427 .of_match_table = uctrl_match, 428 }, 429 .probe = uctrl_probe, 430 .remove = uctrl_remove, 431 }; 432 433 434 module_platform_driver(uctrl_driver); 435 436 MODULE_LICENSE("GPL"); 437