1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/imx35-clock.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Clock bindings for Freescale i.MX35
8
9maintainers:
10  - Steffen Trumtrar <s.trumtrar@pengutronix.de>
11
12description: |
13  The clock consumer should specify the desired clock by having the clock
14  ID in its "clocks" phandle cell. The following is a full list of i.MX35
15  clocks and IDs.
16
17        Clock			ID
18        ---------------------------
19        ckih			0
20        mpll			1
21        ppll			2
22        mpll_075		3
23        arm			4
24        hsp			5
25        hsp_div			6
26        hsp_sel			7
27        ahb			8
28        ipg			9
29        arm_per_div		10
30        ahb_per_div		11
31        ipg_per			12
32        uart_sel		13
33        uart_div		14
34        esdhc_sel		15
35        esdhc1_div		16
36        esdhc2_div		17
37        esdhc3_div		18
38        spdif_sel		19
39        spdif_div_pre		20
40        spdif_div_post		21
41        ssi_sel			22
42        ssi1_div_pre		23
43        ssi1_div_post		24
44        ssi2_div_pre		25
45        ssi2_div_post		26
46        usb_sel			27
47        usb_div			28
48        nfc_div			29
49        asrc_gate		30
50        pata_gate		31
51        audmux_gate		32
52        can1_gate		33
53        can2_gate		34
54        cspi1_gate		35
55        cspi2_gate		36
56        ect_gate		37
57        edio_gate		38
58        emi_gate		39
59        epit1_gate		40
60        epit2_gate		41
61        esai_gate		42
62        esdhc1_gate		43
63        esdhc2_gate		44
64        esdhc3_gate		45
65        fec_gate		46
66        gpio1_gate		47
67        gpio2_gate		48
68        gpio3_gate		49
69        gpt_gate		50
70        i2c1_gate		51
71        i2c2_gate		52
72        i2c3_gate		53
73        iomuxc_gate		54
74        ipu_gate		55
75        kpp_gate		56
76        mlb_gate		57
77        mshc_gate		58
78        owire_gate		59
79        pwm_gate		60
80        rngc_gate		61
81        rtc_gate		62
82        rtic_gate		63
83        scc_gate		64
84        sdma_gate		65
85        spba_gate		66
86        spdif_gate		67
87        ssi1_gate		68
88        ssi2_gate		69
89        uart1_gate		70
90        uart2_gate		71
91        uart3_gate		72
92        usbotg_gate		73
93        wdog_gate		74
94        max_gate		75
95        admux_gate		76
96        csi_gate		77
97        csi_div			78
98        csi_sel			79
99        iim_gate		80
100        gpu2d_gate		81
101        ckli_gate		82
102
103properties:
104  compatible:
105    const: fsl,imx35-ccm
106
107  reg:
108    maxItems: 1
109
110  interrupts:
111    maxItems: 1
112
113  '#clock-cells':
114    const: 1
115
116required:
117  - compatible
118  - reg
119  - interrupts
120  - '#clock-cells'
121
122additionalProperties: false
123
124examples:
125  - |
126    clock-controller@53f80000 {
127        compatible = "fsl,imx35-ccm";
128        reg = <0x53f80000 0x4000>;
129        interrupts = <31>;
130        #clock-cells = <1>;
131    };
132
133    esdhc@53fb4000 {
134        compatible = "fsl,imx35-esdhc";
135        reg = <0x53fb4000 0x4000>;
136        interrupts = <7>;
137        clocks = <&clks 9>, <&clks 8>, <&clks 43>;
138        clock-names = "ipg", "ahb", "per";
139    };
140