1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/mmc/mmc-controller.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: MMC Controller Generic Binding 8 9maintainers: 10 - Ulf Hansson <ulf.hansson@linaro.org> 11 12description: | 13 These properties are common to multiple MMC host controllers. Any host 14 that requires the respective functionality should implement them using 15 these definitions. 16 17properties: 18 $nodename: 19 pattern: "^mmc(@.*)?$" 20 21 "#address-cells": 22 const: 1 23 description: | 24 The cell is the slot ID if a function subnode is used. 25 26 "#size-cells": 27 const: 0 28 29 # Card Detection. 30 # If none of these properties are supplied, the host native card 31 # detect will be used. Only one of them should be provided. 32 33 broken-cd: 34 $ref: /schemas/types.yaml#/definitions/flag 35 description: 36 There is no card detection available; polling must be used. 37 38 cd-gpios: 39 description: 40 The card detection will be done using the GPIO provided. 41 42 non-removable: 43 $ref: /schemas/types.yaml#/definitions/flag 44 description: 45 Non-removable slot (like eMMC); assume always present. 46 47 # *NOTE* on CD and WP polarity. To use common for all SD/MMC host 48 # controllers line polarity properties, we have to fix the meaning 49 # of the "normal" and "inverted" line levels. We choose to follow 50 # the SDHCI standard, which specifies both those lines as "active 51 # low." Therefore, using the "cd-inverted" property means, that the 52 # CD line is active high, i.e. it is high, when a card is 53 # inserted. Similar logic applies to the "wp-inverted" property. 54 # 55 # CD and WP lines can be implemented on the hardware in one of two 56 # ways: as GPIOs, specified in cd-gpios and wp-gpios properties, or 57 # as dedicated pins. Polarity of dedicated pins can be specified, 58 # using *-inverted properties. GPIO polarity can also be specified 59 # using the GPIO_ACTIVE_LOW flag. This creates an ambiguity in the 60 # latter case. We choose to use the XOR logic for GPIO CD and WP 61 # lines. This means, the two properties are "superimposed," for 62 # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the 63 # respective *-inverted property property results in a 64 # double-inversion and actually means the "normal" line polarity is 65 # in effect. 66 wp-inverted: 67 $ref: /schemas/types.yaml#/definitions/flag 68 description: 69 The Write Protect line polarity is inverted. 70 71 cd-inverted: 72 $ref: /schemas/types.yaml#/definitions/flag 73 description: 74 The CD line polarity is inverted. 75 76 # Other properties 77 78 bus-width: 79 description: 80 Number of data lines. 81 $ref: /schemas/types.yaml#/definitions/uint32 82 enum: [1, 4, 8] 83 default: 1 84 85 max-frequency: 86 description: 87 Maximum operating frequency of the bus. 88 $ref: /schemas/types.yaml#/definitions/uint32 89 minimum: 400000 90 maximum: 200000000 91 92 disable-wp: 93 $ref: /schemas/types.yaml#/definitions/flag 94 description: 95 When set, no physical write-protect line is present. This 96 property should only be specified when the controller has a 97 dedicated write-protect detection logic. If a GPIO is always used 98 for the write-protect detection logic, it is sufficient to not 99 specify the wp-gpios property in the absence of a write-protect 100 line. Not used in combination with eMMC or SDIO. 101 102 wp-gpios: 103 description: 104 GPIO to use for the write-protect detection. 105 106 cd-debounce-delay-ms: 107 description: 108 Set delay time before detecting card after card insert 109 interrupt. 110 111 no-1-8-v: 112 $ref: /schemas/types.yaml#/definitions/flag 113 description: 114 When specified, denotes that 1.8V card voltage is not supported 115 on this system, even if the controller claims it. 116 117 cap-sd-highspeed: 118 $ref: /schemas/types.yaml#/definitions/flag 119 description: 120 SD high-speed timing is supported. 121 122 cap-mmc-highspeed: 123 $ref: /schemas/types.yaml#/definitions/flag 124 description: 125 MMC high-speed timing is supported. 126 127 sd-uhs-sdr12: 128 $ref: /schemas/types.yaml#/definitions/flag 129 description: 130 SD UHS SDR12 speed is supported. 131 132 sd-uhs-sdr25: 133 $ref: /schemas/types.yaml#/definitions/flag 134 description: 135 SD UHS SDR25 speed is supported. 136 137 sd-uhs-sdr50: 138 $ref: /schemas/types.yaml#/definitions/flag 139 description: 140 SD UHS SDR50 speed is supported. 141 142 sd-uhs-sdr104: 143 $ref: /schemas/types.yaml#/definitions/flag 144 description: 145 SD UHS SDR104 speed is supported. 146 147 sd-uhs-ddr50: 148 $ref: /schemas/types.yaml#/definitions/flag 149 description: 150 SD UHS DDR50 speed is supported. 151 152 cap-power-off-card: 153 $ref: /schemas/types.yaml#/definitions/flag 154 description: 155 Powering off the card is safe. 156 157 cap-mmc-hw-reset: 158 $ref: /schemas/types.yaml#/definitions/flag 159 description: 160 eMMC hardware reset is supported 161 162 cap-sdio-irq: 163 $ref: /schemas/types.yaml#/definitions/flag 164 description: 165 enable SDIO IRQ signalling on this interface 166 167 full-pwr-cycle: 168 $ref: /schemas/types.yaml#/definitions/flag 169 description: 170 Full power cycle of the card is supported. 171 172 full-pwr-cycle-in-suspend: 173 $ref: /schemas/types.yaml#/definitions/flag 174 description: 175 Full power cycle of the card in suspend is supported. 176 177 mmc-ddr-1_2v: 178 $ref: /schemas/types.yaml#/definitions/flag 179 description: 180 eMMC high-speed DDR mode (1.2V I/O) is supported. 181 182 mmc-ddr-1_8v: 183 $ref: /schemas/types.yaml#/definitions/flag 184 description: 185 eMMC high-speed DDR mode (1.8V I/O) is supported. 186 187 mmc-ddr-3_3v: 188 $ref: /schemas/types.yaml#/definitions/flag 189 description: 190 eMMC high-speed DDR mode (3.3V I/O) is supported. 191 192 mmc-hs200-1_2v: 193 $ref: /schemas/types.yaml#/definitions/flag 194 description: 195 eMMC HS200 mode (1.2V I/O) is supported. 196 197 mmc-hs200-1_8v: 198 $ref: /schemas/types.yaml#/definitions/flag 199 description: 200 eMMC HS200 mode (1.8V I/O) is supported. 201 202 mmc-hs400-1_2v: 203 $ref: /schemas/types.yaml#/definitions/flag 204 description: 205 eMMC HS400 mode (1.2V I/O) is supported. 206 207 mmc-hs400-1_8v: 208 $ref: /schemas/types.yaml#/definitions/flag 209 description: 210 eMMC HS400 mode (1.8V I/O) is supported. 211 212 mmc-hs400-enhanced-strobe: 213 $ref: /schemas/types.yaml#/definitions/flag 214 description: 215 eMMC HS400 enhanced strobe mode is supported 216 217 dsr: 218 description: 219 Value the card Driver Stage Register (DSR) should be programmed 220 with. 221 $ref: /schemas/types.yaml#/definitions/uint32 222 minimum: 0 223 maximum: 0xffff 224 225 no-sdio: 226 $ref: /schemas/types.yaml#/definitions/flag 227 description: 228 Controller is limited to send SDIO commands during 229 initialization. 230 231 no-sd: 232 $ref: /schemas/types.yaml#/definitions/flag 233 description: 234 Controller is limited to send SD commands during initialization. 235 236 no-mmc: 237 $ref: /schemas/types.yaml#/definitions/flag 238 description: 239 Controller is limited to send MMC commands during 240 initialization. 241 242 fixed-emmc-driver-type: 243 description: 244 For non-removable eMMC, enforce this driver type. The value is 245 the driver type as specified in the eMMC specification (table 246 206 in spec version 5.1) 247 $ref: /schemas/types.yaml#/definitions/uint32 248 minimum: 0 249 maximum: 4 250 251 post-power-on-delay-ms: 252 description: 253 It was invented for MMC pwrseq-simple which could be referred to 254 mmc-pwrseq-simple.txt. But now it\'s reused as a tunable delay 255 waiting for I/O signalling and card power supply to be stable, 256 regardless of whether pwrseq-simple is used. Default to 10ms if 257 no available. 258 $ref: /schemas/types.yaml#/definitions/uint32 259 default: 10 260 261 supports-cqe: 262 $ref: /schemas/types.yaml#/definitions/flag 263 description: 264 The presence of this property indicates that the corresponding 265 MMC host controller supports HW command queue feature. 266 267 disable-cqe-dcmd: 268 $ref: /schemas/types.yaml#/definitions/flag 269 description: 270 The presence of this property indicates that the MMC 271 controller\'s command queue engine (CQE) does not support direct 272 commands (DCMDs). 273 274 keep-power-in-suspend: 275 $ref: /schemas/types.yaml#/definitions/flag 276 description: 277 SDIO only. Preserves card power during a suspend/resume cycle. 278 279 # Deprecated: enable-sdio-wakeup 280 wakeup-source: 281 $ref: /schemas/types.yaml#/definitions/flag 282 description: 283 SDIO only. Enables wake up of host system on SDIO IRQ assertion. 284 285 vmmc-supply: 286 description: 287 Supply for the card power 288 289 vqmmc-supply: 290 description: 291 Supply for the bus IO line power 292 293 mmc-pwrseq: 294 $ref: /schemas/types.yaml#/definitions/phandle 295 description: 296 System-on-Chip designs may specify a specific MMC power 297 sequence. To successfully detect an (e)MMC/SD/SDIO card, that 298 power sequence must be maintained while initializing the card. 299 300patternProperties: 301 "^.*@[0-9]+$": 302 type: object 303 description: | 304 On embedded systems the cards connected to a host may need 305 additional properties. These can be specified in subnodes to the 306 host controller node. The subnodes are identified by the 307 standard \'reg\' property. Which information exactly can be 308 specified depends on the bindings for the SDIO function driver 309 for the subnode, as specified by the compatible string. 310 311 properties: 312 compatible: 313 description: | 314 Name of SDIO function following generic names recommended 315 practice 316 317 reg: 318 items: 319 - minimum: 0 320 maximum: 7 321 description: 322 Must contain the SDIO function number of the function this 323 subnode describes. A value of 0 denotes the memory SD 324 function, values from 1 to 7 denote the SDIO functions. 325 326 broken-hpi: 327 $ref: /schemas/types.yaml#/definitions/flag 328 description: 329 Use this to indicate that the mmc-card has a broken hpi 330 implementation, and that hpi should not be used. 331 332 required: 333 - reg 334 335 "^clk-phase-(legacy|sd-hs|mmc-(hs|hs[24]00|ddr52)|uhs-(sdr(12|25|50|104)|ddr50))$": 336 $ref: /schemas/types.yaml#/definitions/uint32-array 337 338 minItems: 2 339 maxItems: 2 340 items: 341 minimum: 0 342 maximum: 359 343 description: 344 Set the clock (phase) delays which are to be configured in the 345 controller while switching to particular speed mode. These values 346 are in pair of degrees. 347 348dependencies: 349 cd-debounce-delay-ms: [ cd-gpios ] 350 fixed-emmc-driver-type: [ non-removable ] 351 352examples: 353 - | 354 mmc@ab000000 { 355 compatible = "sdhci"; 356 reg = <0xab000000 0x200>; 357 interrupts = <23>; 358 bus-width = <4>; 359 cd-gpios = <&gpio 69 0>; 360 cd-inverted; 361 wp-gpios = <&gpio 70 0>; 362 max-frequency = <50000000>; 363 keep-power-in-suspend; 364 wakeup-source; 365 mmc-pwrseq = <&sdhci0_pwrseq>; 366 clk-phase-sd-hs = <63>, <72>; 367 }; 368 369 - | 370 mmc3: mmc@1c12000 { 371 #address-cells = <1>; 372 #size-cells = <0>; 373 reg = <0x1c12000 0x200>; 374 pinctrl-names = "default"; 375 pinctrl-0 = <&mmc3_pins_a>; 376 vmmc-supply = <®_vmmc3>; 377 bus-width = <4>; 378 non-removable; 379 mmc-pwrseq = <&sdhci0_pwrseq>; 380 381 brcmf: bcrmf@1 { 382 reg = <1>; 383 compatible = "brcm,bcm43xx-fmac"; 384 interrupt-parent = <&pio>; 385 interrupts = <10 8>; 386 interrupt-names = "host-wake"; 387 }; 388 }; 389