1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Common prep/pmac/chrp boot and setup code. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/string.h> 8 #include <linux/sched.h> 9 #include <linux/init.h> 10 #include <linux/kernel.h> 11 #include <linux/reboot.h> 12 #include <linux/delay.h> 13 #include <linux/initrd.h> 14 #include <linux/tty.h> 15 #include <linux/seq_file.h> 16 #include <linux/root_dev.h> 17 #include <linux/cpu.h> 18 #include <linux/console.h> 19 #include <linux/memblock.h> 20 #include <linux/export.h> 21 #include <linux/nvram.h> 22 #include <linux/pgtable.h> 23 24 #include <asm/io.h> 25 #include <asm/prom.h> 26 #include <asm/processor.h> 27 #include <asm/setup.h> 28 #include <asm/smp.h> 29 #include <asm/elf.h> 30 #include <asm/cputable.h> 31 #include <asm/bootx.h> 32 #include <asm/btext.h> 33 #include <asm/machdep.h> 34 #include <linux/uaccess.h> 35 #include <asm/pmac_feature.h> 36 #include <asm/sections.h> 37 #include <asm/nvram.h> 38 #include <asm/xmon.h> 39 #include <asm/time.h> 40 #include <asm/serial.h> 41 #include <asm/udbg.h> 42 #include <asm/code-patching.h> 43 #include <asm/cpu_has_feature.h> 44 #include <asm/asm-prototypes.h> 45 #include <asm/kdump.h> 46 #include <asm/feature-fixups.h> 47 #include <asm/early_ioremap.h> 48 49 #include "setup.h" 50 51 #define DBG(fmt...) 52 53 extern void bootx_init(unsigned long r4, unsigned long phys); 54 55 int boot_cpuid_phys; 56 EXPORT_SYMBOL_GPL(boot_cpuid_phys); 57 58 int smp_hw_index[NR_CPUS]; 59 EXPORT_SYMBOL(smp_hw_index); 60 61 unsigned int DMA_MODE_READ; 62 unsigned int DMA_MODE_WRITE; 63 64 EXPORT_SYMBOL(DMA_MODE_READ); 65 EXPORT_SYMBOL(DMA_MODE_WRITE); 66 67 /* 68 * This is run before start_kernel(), the kernel has been relocated 69 * and we are running with enough of the MMU enabled to have our 70 * proper kernel virtual addresses 71 * 72 * We do the initial parsing of the flat device-tree and prepares 73 * for the MMU to be fully initialized. 74 */ 75 notrace void __init machine_init(u64 dt_ptr) 76 { 77 struct ppc_inst *addr = (struct ppc_inst *)patch_site_addr(&patch__memset_nocache); 78 struct ppc_inst insn; 79 80 /* Configure static keys first, now that we're relocated. */ 81 setup_feature_keys(); 82 83 early_ioremap_init(); 84 85 /* Enable early debugging if any specified (see udbg.h) */ 86 udbg_early_init(); 87 88 patch_instruction_site(&patch__memcpy_nocache, ppc_inst(PPC_INST_NOP)); 89 90 create_cond_branch(&insn, addr, branch_target(addr), 0x820000); 91 patch_instruction(addr, insn); /* replace b by bne cr0 */ 92 93 /* Do some early initialization based on the flat device tree */ 94 early_init_devtree(__va(dt_ptr)); 95 96 early_init_mmu(); 97 98 setup_kdump_trampoline(); 99 } 100 101 /* Checks "l2cr=xxxx" command-line option */ 102 static int __init ppc_setup_l2cr(char *str) 103 { 104 if (cpu_has_feature(CPU_FTR_L2CR)) { 105 unsigned long val = simple_strtoul(str, NULL, 0); 106 printk(KERN_INFO "l2cr set to %lx\n", val); 107 _set_L2CR(0); /* force invalidate by disable cache */ 108 _set_L2CR(val); /* and enable it */ 109 } 110 return 1; 111 } 112 __setup("l2cr=", ppc_setup_l2cr); 113 114 /* Checks "l3cr=xxxx" command-line option */ 115 static int __init ppc_setup_l3cr(char *str) 116 { 117 if (cpu_has_feature(CPU_FTR_L3CR)) { 118 unsigned long val = simple_strtoul(str, NULL, 0); 119 printk(KERN_INFO "l3cr set to %lx\n", val); 120 _set_L3CR(val); /* and enable it */ 121 } 122 return 1; 123 } 124 __setup("l3cr=", ppc_setup_l3cr); 125 126 static int __init ppc_init(void) 127 { 128 /* clear the progress line */ 129 if (ppc_md.progress) 130 ppc_md.progress(" ", 0xffff); 131 132 /* call platform init */ 133 if (ppc_md.init != NULL) { 134 ppc_md.init(); 135 } 136 return 0; 137 } 138 arch_initcall(ppc_init); 139 140 static void *__init alloc_stack(void) 141 { 142 void *ptr = memblock_alloc(THREAD_SIZE, THREAD_ALIGN); 143 144 if (!ptr) 145 panic("cannot allocate %d bytes for stack at %pS\n", 146 THREAD_SIZE, (void *)_RET_IP_); 147 148 return ptr; 149 } 150 151 void __init irqstack_early_init(void) 152 { 153 unsigned int i; 154 155 if (IS_ENABLED(CONFIG_VMAP_STACK)) 156 return; 157 158 /* interrupt stacks must be in lowmem, we get that for free on ppc32 159 * as the memblock is limited to lowmem by default */ 160 for_each_possible_cpu(i) { 161 softirq_ctx[i] = alloc_stack(); 162 hardirq_ctx[i] = alloc_stack(); 163 } 164 } 165 166 #ifdef CONFIG_VMAP_STACK 167 void *emergency_ctx[NR_CPUS] __ro_after_init; 168 169 void __init emergency_stack_init(void) 170 { 171 unsigned int i; 172 173 for_each_possible_cpu(i) 174 emergency_ctx[i] = alloc_stack(); 175 } 176 #endif 177 178 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 179 void __init exc_lvl_early_init(void) 180 { 181 unsigned int i, hw_cpu; 182 183 /* interrupt stacks must be in lowmem, we get that for free on ppc32 184 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */ 185 for_each_possible_cpu(i) { 186 #ifdef CONFIG_SMP 187 hw_cpu = get_hard_smp_processor_id(i); 188 #else 189 hw_cpu = 0; 190 #endif 191 192 critirq_ctx[hw_cpu] = alloc_stack(); 193 #ifdef CONFIG_BOOKE 194 dbgirq_ctx[hw_cpu] = alloc_stack(); 195 mcheckirq_ctx[hw_cpu] = alloc_stack(); 196 #endif 197 } 198 } 199 #endif 200 201 void __init setup_power_save(void) 202 { 203 #ifdef CONFIG_PPC_BOOK3S_32 204 if (cpu_has_feature(CPU_FTR_CAN_DOZE) || 205 cpu_has_feature(CPU_FTR_CAN_NAP)) 206 ppc_md.power_save = ppc6xx_idle; 207 #endif 208 209 #ifdef CONFIG_E500 210 if (cpu_has_feature(CPU_FTR_CAN_DOZE) || 211 cpu_has_feature(CPU_FTR_CAN_NAP)) 212 ppc_md.power_save = e500_idle; 213 #endif 214 } 215 216 __init void initialize_cache_info(void) 217 { 218 /* 219 * Set cache line size based on type of cpu as a default. 220 * Systems with OF can look in the properties on the cpu node(s) 221 * for a possibly more accurate value. 222 */ 223 dcache_bsize = cur_cpu_spec->dcache_bsize; 224 icache_bsize = cur_cpu_spec->icache_bsize; 225 ucache_bsize = 0; 226 if (IS_ENABLED(CONFIG_PPC_BOOK3S_601) || IS_ENABLED(CONFIG_E200)) 227 ucache_bsize = icache_bsize = dcache_bsize; 228 } 229