1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2005, Intec Automation Inc. 4 * Copyright (C) 2014, Freescale Semiconductor, Inc. 5 */ 6 7 #ifndef __LINUX_MTD_SFDP_H 8 #define __LINUX_MTD_SFDP_H 9 10 /* Basic Flash Parameter Table */ 11 12 /* 13 * JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. 14 * They are indexed from 1 but C arrays are indexed from 0. 15 */ 16 #define BFPT_DWORD(i) ((i) - 1) 17 #define BFPT_DWORD_MAX 16 18 19 struct sfdp_bfpt { 20 u32 dwords[BFPT_DWORD_MAX]; 21 }; 22 23 /* The first version of JESD216 defined only 9 DWORDs. */ 24 #define BFPT_DWORD_MAX_JESD216 9 25 26 /* 1st DWORD. */ 27 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16) 28 #define BFPT_DWORD1_ADDRESS_BYTES_MASK GENMASK(18, 17) 29 #define BFPT_DWORD1_ADDRESS_BYTES_3_ONLY (0x0UL << 17) 30 #define BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 (0x1UL << 17) 31 #define BFPT_DWORD1_ADDRESS_BYTES_4_ONLY (0x2UL << 17) 32 #define BFPT_DWORD1_DTR BIT(19) 33 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20) 34 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21) 35 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22) 36 37 /* 5th DWORD. */ 38 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0) 39 #define BFPT_DWORD5_FAST_READ_4_4_4 BIT(4) 40 41 /* 11th DWORD. */ 42 #define BFPT_DWORD11_PAGE_SIZE_SHIFT 4 43 #define BFPT_DWORD11_PAGE_SIZE_MASK GENMASK(7, 4) 44 45 /* 15th DWORD. */ 46 47 /* 48 * (from JESD216 rev B) 49 * Quad Enable Requirements (QER): 50 * - 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 51 * reads based on instruction. DQ3/HOLD# functions are hold during 52 * instruction phase. 53 * - 001b: QE is bit 1 of status register 2. It is set via Write Status with 54 * two data bytes where bit 1 of the second byte is one. 55 * [...] 56 * Writing only one byte to the status register has the side-effect of 57 * clearing status register 2, including the QE bit. The 100b code is 58 * used if writing one byte to the status register does not modify 59 * status register 2. 60 * - 010b: QE is bit 6 of status register 1. It is set via Write Status with 61 * one data byte where bit 6 is one. 62 * [...] 63 * - 011b: QE is bit 7 of status register 2. It is set via Write status 64 * register 2 instruction 3Eh with one data byte where bit 7 is one. 65 * [...] 66 * The status register 2 is read using instruction 3Fh. 67 * - 100b: QE is bit 1 of status register 2. It is set via Write Status with 68 * two data bytes where bit 1 of the second byte is one. 69 * [...] 70 * In contrast to the 001b code, writing one byte to the status 71 * register does not modify status register 2. 72 * - 101b: QE is bit 1 of status register 2. Status register 1 is read using 73 * Read Status instruction 05h. Status register2 is read using 74 * instruction 35h. QE is set via Write Status instruction 01h with 75 * two data bytes where bit 1 of the second byte is one. 76 * [...] 77 */ 78 #define BFPT_DWORD15_QER_MASK GENMASK(22, 20) 79 #define BFPT_DWORD15_QER_NONE (0x0UL << 20) /* Micron */ 80 #define BFPT_DWORD15_QER_SR2_BIT1_BUGGY (0x1UL << 20) 81 #define BFPT_DWORD15_QER_SR1_BIT6 (0x2UL << 20) /* Macronix */ 82 #define BFPT_DWORD15_QER_SR2_BIT7 (0x3UL << 20) 83 #define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20) 84 #define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20) /* Spansion */ 85 86 struct sfdp_parameter_header { 87 u8 id_lsb; 88 u8 minor; 89 u8 major; 90 u8 length; /* in double words */ 91 u8 parameter_table_pointer[3]; /* byte address */ 92 u8 id_msb; 93 }; 94 95 int spi_nor_parse_sfdp(struct spi_nor *nor, 96 struct spi_nor_flash_parameter *params); 97 98 #endif /* __LINUX_MTD_SFDP_H */ 99