1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family MCU Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ 6 */ 7 8&cbass_mcu { 9 mcu_conf: scm_conf@40f00000 { 10 compatible = "syscon", "simple-mfd"; 11 reg = <0x0 0x40f00000 0x0 0x20000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x0 0x0 0x40f00000 0x20000>; 15 }; 16 17 mcu_uart0: serial@40a00000 { 18 compatible = "ti,am654-uart"; 19 reg = <0x00 0x40a00000 0x00 0x100>; 20 reg-shift = <2>; 21 reg-io-width = <4>; 22 interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>; 23 clock-frequency = <96000000>; 24 current-speed = <115200>; 25 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 26 }; 27 28 mcu_ram: sram@41c00000 { 29 compatible = "mmio-sram"; 30 reg = <0x00 0x41c00000 0x00 0x80000>; 31 ranges = <0x0 0x00 0x41c00000 0x80000>; 32 #address-cells = <1>; 33 #size-cells = <1>; 34 }; 35 36 mcu_i2c0: i2c@40b00000 { 37 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 38 reg = <0x0 0x40b00000 0x0 0x100>; 39 interrupts = <GIC_SPI 564 IRQ_TYPE_LEVEL_HIGH>; 40 #address-cells = <1>; 41 #size-cells = <0>; 42 clock-names = "fck"; 43 clocks = <&k3_clks 114 1>; 44 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>; 45 }; 46 47 mcu_spi0: spi@40300000 { 48 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 49 reg = <0x0 0x40300000 0x0 0x400>; 50 interrupts = <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; 51 clocks = <&k3_clks 142 1>; 52 power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>; 53 #address-cells = <1>; 54 #size-cells = <0>; 55 }; 56 57 mcu_spi1: spi@40310000 { 58 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 59 reg = <0x0 0x40310000 0x0 0x400>; 60 interrupts = <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 61 clocks = <&k3_clks 143 1>; 62 power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>; 63 #address-cells = <1>; 64 #size-cells = <0>; 65 }; 66 67 mcu_spi2: spi@40320000 { 68 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 69 reg = <0x0 0x40320000 0x0 0x400>; 70 interrupts = <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; 71 clocks = <&k3_clks 144 1>; 72 power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>; 73 #address-cells = <1>; 74 #size-cells = <0>; 75 }; 76 77 tscadc0: tscadc@40200000 { 78 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 79 reg = <0x0 0x40200000 0x0 0x1000>; 80 interrupts = <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 81 clocks = <&k3_clks 0 2>; 82 assigned-clocks = <&k3_clks 0 2>; 83 assigned-clock-rates = <60000000>; 84 clock-names = "adc_tsc_fck"; 85 86 adc { 87 #io-channel-cells = <1>; 88 compatible = "ti,am654-adc", "ti,am3359-adc"; 89 }; 90 }; 91 92 tscadc1: tscadc@40210000 { 93 compatible = "ti,am654-tscadc", "ti,am3359-tscadc"; 94 reg = <0x0 0x40210000 0x0 0x1000>; 95 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 96 clocks = <&k3_clks 1 2>; 97 assigned-clocks = <&k3_clks 1 2>; 98 assigned-clock-rates = <60000000>; 99 clock-names = "adc_tsc_fck"; 100 101 adc { 102 #io-channel-cells = <1>; 103 compatible = "ti,am654-adc", "ti,am3359-adc"; 104 }; 105 }; 106 107 mcu_navss { 108 compatible = "simple-mfd"; 109 #address-cells = <2>; 110 #size-cells = <2>; 111 ranges; 112 dma-coherent; 113 dma-ranges; 114 115 ti,sci-dev-id = <119>; 116 117 mcu_ringacc: ringacc@2b800000 { 118 compatible = "ti,am654-navss-ringacc"; 119 reg = <0x0 0x2b800000 0x0 0x400000>, 120 <0x0 0x2b000000 0x0 0x400000>, 121 <0x0 0x28590000 0x0 0x100>, 122 <0x0 0x2a500000 0x0 0x40000>; 123 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 124 ti,num-rings = <286>; 125 ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */ 126 ti,dma-ring-reset-quirk; 127 ti,sci = <&dmsc>; 128 ti,sci-dev-id = <195>; 129 msi-parent = <&inta_main_udmass>; 130 }; 131 132 mcu_udmap: dma-controller@285c0000 { 133 compatible = "ti,am654-navss-mcu-udmap"; 134 reg = <0x0 0x285c0000 0x0 0x100>, 135 <0x0 0x2a800000 0x0 0x40000>, 136 <0x0 0x2aa00000 0x0 0x40000>; 137 reg-names = "gcfg", "rchanrt", "tchanrt"; 138 msi-parent = <&inta_main_udmass>; 139 #dma-cells = <1>; 140 141 ti,sci = <&dmsc>; 142 ti,sci-dev-id = <194>; 143 ti,ringacc = <&mcu_ringacc>; 144 145 ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */ 146 <0x2>; /* TX_CHAN */ 147 ti,sci-rm-range-rchan = <0x3>, /* RX_HCHAN */ 148 <0x4>; /* RX_CHAN */ 149 ti,sci-rm-range-rflow = <0x5>; /* GP RFLOW */ 150 }; 151 }; 152 153 fss: fss@47000000 { 154 compatible = "simple-bus"; 155 #address-cells = <2>; 156 #size-cells = <2>; 157 ranges; 158 159 ospi0: spi@47040000 { 160 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 161 reg = <0x0 0x47040000 0x0 0x100>, 162 <0x5 0x00000000 0x1 0x0000000>; 163 interrupts = <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>; 164 cdns,fifo-depth = <256>; 165 cdns,fifo-width = <4>; 166 cdns,trigger-address = <0x0>; 167 clocks = <&k3_clks 248 0>; 168 assigned-clocks = <&k3_clks 248 0>; 169 assigned-clock-parents = <&k3_clks 248 2>; 170 assigned-clock-rates = <166666666>; 171 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 172 #address-cells = <1>; 173 #size-cells = <0>; 174 }; 175 176 ospi1: spi@47050000 { 177 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 178 reg = <0x0 0x47050000 0x0 0x100>, 179 <0x7 0x00000000 0x1 0x00000000>; 180 interrupts = <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>; 181 cdns,fifo-depth = <256>; 182 cdns,fifo-width = <4>; 183 cdns,trigger-address = <0x0>; 184 clocks = <&k3_clks 249 6>; 185 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 }; 189 }; 190}; 191