1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
4 */
5
6#include <linux/linkage.h>
7
8#include <soc/tegra/flowctrl.h>
9#include <soc/tegra/fuse.h>
10
11#include <asm/asm-offsets.h>
12#include <asm/assembler.h>
13#include <asm/cache.h>
14
15#include "irammap.h"
16#include "sleep.h"
17
18#define EMC_CFG				0xc
19#define EMC_ADR_CFG			0x10
20#define EMC_TIMING_CONTROL		0x28
21#define EMC_NOP				0xdc
22#define EMC_SELF_REF			0xe0
23#define EMC_MRW				0xe8
24#define EMC_FBIO_CFG5			0x104
25#define EMC_AUTO_CAL_CONFIG		0x2a4
26#define EMC_AUTO_CAL_INTERVAL		0x2a8
27#define EMC_AUTO_CAL_STATUS		0x2ac
28#define EMC_REQ_CTRL			0x2b0
29#define EMC_CFG_DIG_DLL			0x2bc
30#define EMC_EMC_STATUS			0x2b4
31#define EMC_ZCAL_INTERVAL		0x2e0
32#define EMC_ZQ_CAL			0x2ec
33#define EMC_XM2VTTGENPADCTRL		0x310
34#define EMC_XM2VTTGENPADCTRL2		0x314
35
36#define PMC_CTRL			0x0
37#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
38
39#define PMC_PLLP_WB0_OVERRIDE		0xf8
40#define PMC_IO_DPD_REQ			0x1b8
41#define PMC_IO_DPD_STATUS		0x1bc
42
43#define CLK_RESET_CCLK_BURST		0x20
44#define CLK_RESET_CCLK_DIVIDER		0x24
45#define CLK_RESET_SCLK_BURST		0x28
46#define CLK_RESET_SCLK_DIVIDER		0x2c
47
48#define CLK_RESET_PLLC_BASE		0x80
49#define CLK_RESET_PLLC_MISC		0x8c
50#define CLK_RESET_PLLM_BASE		0x90
51#define CLK_RESET_PLLM_MISC		0x9c
52#define CLK_RESET_PLLP_BASE		0xa0
53#define CLK_RESET_PLLP_MISC		0xac
54#define CLK_RESET_PLLA_BASE		0xb0
55#define CLK_RESET_PLLA_MISC		0xbc
56#define CLK_RESET_PLLX_BASE		0xe0
57#define CLK_RESET_PLLX_MISC		0xe4
58#define CLK_RESET_PLLX_MISC3		0x518
59#define CLK_RESET_PLLX_MISC3_IDDQ	3
60#define CLK_RESET_PLLM_MISC_IDDQ	5
61#define CLK_RESET_PLLC_MISC_IDDQ	26
62#define CLK_RESET_PLLP_RESHIFT		0x528
63#define CLK_RESET_PLLP_RESHIFT_DEFAULT	0x3b
64#define CLK_RESET_PLLP_RESHIFT_ENABLE	0x3
65
66#define CLK_RESET_CLK_SOURCE_MSELECT	0x3b4
67
68#define MSELECT_CLKM			(0x3 << 30)
69
70#define LOCK_DELAY 50 /* safety delay after lock is detected */
71
72#define TEGRA30_POWER_HOTPLUG_SHUTDOWN	(1 << 27) /* Hotplug shutdown */
73
74.macro emc_device_mask, rd, base
75	ldr	\rd, [\base, #EMC_ADR_CFG]
76	tst	\rd, #0x1
77	moveq	\rd, #(0x1 << 8)		@ just 1 device
78	movne	\rd, #(0x3 << 8)		@ 2 devices
79.endm
80
81.macro emc_timing_update, rd, base
82	mov	\rd, #1
83	str	\rd, [\base, #EMC_TIMING_CONTROL]
841001:
85	ldr	\rd, [\base, #EMC_EMC_STATUS]
86	tst	\rd, #(0x1<<23)	@ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
87	bne	1001b
88.endm
89
90.macro pll_enable, rd, r_car_base, pll_base, pll_misc
91	ldr	\rd, [\r_car_base, #\pll_base]
92	tst	\rd, #(1 << 30)
93	orreq	\rd, \rd, #(1 << 30)
94	streq	\rd, [\r_car_base, #\pll_base]
95	/* Enable lock detector */
96	.if	\pll_misc
97	ldr	\rd, [\r_car_base, #\pll_misc]
98	bic	\rd, \rd, #(1 << 18)
99	str	\rd, [\r_car_base, #\pll_misc]
100	ldr	\rd, [\r_car_base, #\pll_misc]
101	ldr	\rd, [\r_car_base, #\pll_misc]
102	orr	\rd, \rd, #(1 << 18)
103	str	\rd, [\r_car_base, #\pll_misc]
104	.endif
105.endm
106
107.macro pll_locked, rd, r_car_base, pll_base
1081:
109	ldr	\rd, [\r_car_base, #\pll_base]
110	tst	\rd, #(1 << 27)
111	beq	1b
112.endm
113
114.macro pll_iddq_exit, rd, car, iddq, iddq_bit
115	ldr	\rd, [\car, #\iddq]
116	bic	\rd, \rd, #(1<<\iddq_bit)
117	str	\rd, [\car, #\iddq]
118.endm
119
120.macro pll_iddq_entry, rd, car, iddq, iddq_bit
121	ldr	\rd, [\car, #\iddq]
122	orr	\rd, \rd, #(1<<\iddq_bit)
123	str	\rd, [\car, #\iddq]
124.endm
125
126#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
127/*
128 * tegra30_hotplug_shutdown(void)
129 *
130 * Powergates the current CPU.
131 * Should never return.
132 */
133ENTRY(tegra30_hotplug_shutdown)
134	/* Powergate this CPU */
135	mov	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
136	bl	tegra30_cpu_shutdown
137	ret	lr			@ should never get here
138ENDPROC(tegra30_hotplug_shutdown)
139
140/*
141 * tegra30_cpu_shutdown(unsigned long flags)
142 *
143 * Puts the current CPU in wait-for-event mode on the flow controller
144 * and powergates it -- flags (in R0) indicate the request type.
145 *
146 * r10 = SoC ID
147 * corrupts r0-r4, r10-r12
148 */
149ENTRY(tegra30_cpu_shutdown)
150	cpu_id	r3
151	tegra_get_soc_id TEGRA_APB_MISC_VIRT, r10
152	cmp	r10, #TEGRA30
153	bne	_no_cpu0_chk	@ It's not Tegra30
154
155	cmp	r3, #0
156	reteq	lr		@ Must never be called for CPU 0
157_no_cpu0_chk:
158
159	ldr	r12, =TEGRA_FLOW_CTRL_VIRT
160	cpu_to_csr_reg r1, r3
161	add	r1, r1, r12	@ virtual CSR address for this CPU
162	cpu_to_halt_reg r2, r3
163	add	r2, r2, r12	@ virtual HALT_EVENTS address for this CPU
164
165	/*
166	 * Clear this CPU's "event" and "interrupt" flags and power gate
167	 * it when halting but not before it is in the "WFE" state.
168	 */
169	movw	r12, \
170		FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
171		FLOW_CTRL_CSR_ENABLE
172	cmp	r10, #TEGRA30
173	moveq	r4, #(1 << 4)			@ wfe bitmap
174	movne	r4, #(1 << 8)			@ wfi bitmap
175 ARM(	orr	r12, r12, r4, lsl r3	)
176 THUMB(	lsl	r4, r4, r3		)
177 THUMB(	orr	r12, r12, r4		)
178	str	r12, [r1]
179
180	/* Halt this CPU. */
181	mov	r3, #0x400
182delay_1:
183	subs	r3, r3, #1			@ delay as a part of wfe war.
184	bge	delay_1;
185	cpsid	a				@ disable imprecise aborts.
186	ldr	r3, [r1]			@ read CSR
187	str	r3, [r1]			@ clear CSR
188
189	tst	r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
190	beq	flow_ctrl_setting_for_lp2
191
192	/* flow controller set up for hotplug */
193	mov	r3, #FLOW_CTRL_WAITEVENT		@ For hotplug
194	b	flow_ctrl_done
195flow_ctrl_setting_for_lp2:
196	/* flow controller set up for LP2 */
197	cmp	r10, #TEGRA30
198	moveq   r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT	@ For LP2
199	movne	r3, #FLOW_CTRL_WAITEVENT
200	orrne	r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
201	orrne	r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
202flow_ctrl_done:
203	cmp	r10, #TEGRA30
204	str	r3, [r2]
205	ldr	r0, [r2]
206	b	wfe_war
207
208__cpu_reset_again:
209	dsb
210	.align 5
211	wfeeq					@ CPU should be power gated here
212	wfine
213wfe_war:
214	b	__cpu_reset_again
215
216	/*
217	 * 38 nop's, which fills rest of wfe cache line and
218	 * 4 more cachelines with nop
219	 */
220	.rept 38
221	nop
222	.endr
223	b	.				@ should never get here
224
225ENDPROC(tegra30_cpu_shutdown)
226#endif
227
228#ifdef CONFIG_PM_SLEEP
229/*
230 * tegra30_sleep_core_finish(unsigned long v2p)
231 *
232 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
233 * tegra30_tear_down_core in IRAM
234 */
235ENTRY(tegra30_sleep_core_finish)
236	mov	r4, r0
237	/* Flush, disable the L1 data cache and exit SMP */
238	mov	r0, #TEGRA_FLUSH_CACHE_ALL
239	bl	tegra_disable_clean_inv_dcache
240	mov	r0, r4
241
242	/*
243	 * Preload all the address literals that are needed for the
244	 * CPU power-gating process, to avoid loading from SDRAM which
245	 * are not supported once SDRAM is put into self-refresh.
246	 * LP0 / LP1 use physical address, since the MMU needs to be
247	 * disabled before putting SDRAM into self-refresh to avoid
248	 * memory access due to page table walks.
249	 */
250	mov32	r4, TEGRA_PMC_BASE
251	mov32	r5, TEGRA_CLK_RESET_BASE
252	mov32	r6, TEGRA_FLOW_CTRL_BASE
253	mov32	r7, TEGRA_TMRUS_BASE
254
255	mov32	r3, tegra_shut_off_mmu
256	add	r3, r3, r0
257
258	mov32	r0, tegra30_tear_down_core
259	mov32	r1, tegra30_iram_start
260	sub	r0, r0, r1
261	mov32	r1, TEGRA_IRAM_LPx_RESUME_AREA
262	add	r0, r0, r1
263
264	ret	r3
265ENDPROC(tegra30_sleep_core_finish)
266
267/*
268 * tegra30_pm_secondary_cpu_suspend(unsigned long unused_arg)
269 *
270 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
271 */
272ENTRY(tegra30_pm_secondary_cpu_suspend)
273	mov	r7, lr
274
275	/* Flush and disable the L1 data cache */
276	mov 	r0, #TEGRA_FLUSH_CACHE_LOUIS
277	bl	tegra_disable_clean_inv_dcache
278
279	/* Powergate this CPU. */
280	mov	r0, #0                          @ power mode flags (!hotplug)
281	bl	tegra30_cpu_shutdown
282	mov	r0, #1                          @ never return here
283	ret	r7
284ENDPROC(tegra30_pm_secondary_cpu_suspend)
285
286/*
287 * tegra30_tear_down_cpu
288 *
289 * Switches the CPU to enter sleep.
290 */
291ENTRY(tegra30_tear_down_cpu)
292	mov32	r6, TEGRA_FLOW_CTRL_BASE
293
294	b	tegra30_enter_sleep
295ENDPROC(tegra30_tear_down_cpu)
296
297/* START OF ROUTINES COPIED TO IRAM */
298	.align L1_CACHE_SHIFT
299	.globl tegra30_iram_start
300tegra30_iram_start:
301
302/*
303 * tegra30_lp1_reset
304 *
305 * reset vector for LP1 restore; copied into IRAM during suspend.
306 * Brings the system back up to a safe staring point (SDRAM out of
307 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
308 * system clock running on the same PLL that it suspended at), and
309 * jumps to tegra_resume to restore virtual addressing.
310 * The physical address of tegra_resume expected to be stored in
311 * PMC_SCRATCH41.
312 *
313 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_LPx_RESUME_AREA.
314 */
315ENTRY(tegra30_lp1_reset)
316	/*
317	 * The CPU and system bus are running at 32KHz and executing from
318	 * IRAM when this code is executed; immediately switch to CLKM and
319	 * enable PLLP, PLLM, PLLC, PLLA and PLLX.
320	 */
321	mov32	r0, TEGRA_CLK_RESET_BASE
322
323	mov	r1, #(1 << 28)
324	str	r1, [r0, #CLK_RESET_SCLK_BURST]
325	str	r1, [r0, #CLK_RESET_CCLK_BURST]
326	mov	r1, #0
327	str	r1, [r0, #CLK_RESET_CCLK_DIVIDER]
328	str	r1, [r0, #CLK_RESET_SCLK_DIVIDER]
329
330	tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
331	cmp	r10, #TEGRA30
332	beq	_no_pll_iddq_exit
333
334	pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
335	pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
336	pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
337
338	mov32	r7, TEGRA_TMRUS_BASE
339	ldr	r1, [r7]
340	add	r1, r1, #2
341	wait_until r1, r7, r3
342
343	/* enable PLLM via PMC */
344	mov32	r2, TEGRA_PMC_BASE
345	ldr	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
346	orr	r1, r1, #(1 << 12)
347	str	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
348
349	pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
350	pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
351	pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
352
353	b	_pll_m_c_x_done
354
355_no_pll_iddq_exit:
356	/* enable PLLM via PMC */
357	mov32	r2, TEGRA_PMC_BASE
358	ldr	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
359	orr	r1, r1, #(1 << 12)
360	str	r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
361
362	pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
363	pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
364
365_pll_m_c_x_done:
366	pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
367	pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
368
369	pll_locked r1, r0, CLK_RESET_PLLM_BASE
370	pll_locked r1, r0, CLK_RESET_PLLP_BASE
371	pll_locked r1, r0, CLK_RESET_PLLA_BASE
372	pll_locked r1, r0, CLK_RESET_PLLC_BASE
373
374	/*
375	 * CPUFreq driver could select other PLL for CPU. PLLX will be
376	 * enabled by the Tegra30 CLK driver on an as-needed basis, see
377	 * tegra30_cpu_clock_resume().
378	 */
379	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
380	cmp	r1, #TEGRA30
381	beq	1f
382
383	pll_locked r1, r0, CLK_RESET_PLLX_BASE
384
385	ldr	r1, [r0, #CLK_RESET_PLLP_BASE]
386	bic	r1, r1, #(1<<31)	@ disable PllP bypass
387	str	r1, [r0, #CLK_RESET_PLLP_BASE]
388
389	mov	r1, #CLK_RESET_PLLP_RESHIFT_DEFAULT
390	str	r1, [r0, #CLK_RESET_PLLP_RESHIFT]
3911:
392
393	mov32	r7, TEGRA_TMRUS_BASE
394	ldr	r1, [r7]
395	add	r1, r1, #LOCK_DELAY
396	wait_until r1, r7, r3
397
398	adr	r5, tegra_sdram_pad_save
399
400	ldr	r4, [r5, #0x18]		@ restore CLK_SOURCE_MSELECT
401	str	r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
402
403	ldr	r4, [r5, #0x1C]		@ restore SCLK_BURST
404	str	r4, [r0, #CLK_RESET_SCLK_BURST]
405
406	movw	r4, #:lower16:((1 << 28) | (0x4))	@ burst policy is PLLP
407	movt	r4, #:upper16:((1 << 28) | (0x4))
408	str	r4, [r0, #CLK_RESET_CCLK_BURST]
409
410	/* Restore pad power state to normal */
411	ldr	r1, [r5, #0x14]		@ PMC_IO_DPD_STATUS
412	mvn	r1, r1
413	bic	r1, r1, #(1 << 31)
414	orr	r1, r1, #(1 << 30)
415	str	r1, [r2, #PMC_IO_DPD_REQ]	@ DPD_OFF
416
417	cmp	r10, #TEGRA30
418	movweq	r0, #:lower16:TEGRA_EMC_BASE	@ r0 reserved for emc base
419	movteq	r0, #:upper16:TEGRA_EMC_BASE
420	cmp	r10, #TEGRA114
421	movweq	r0, #:lower16:TEGRA_EMC0_BASE
422	movteq	r0, #:upper16:TEGRA_EMC0_BASE
423	cmp	r10, #TEGRA124
424	movweq	r0, #:lower16:TEGRA124_EMC_BASE
425	movteq	r0, #:upper16:TEGRA124_EMC_BASE
426
427exit_self_refresh:
428	ldr	r1, [r5, #0xC]		@ restore EMC_XM2VTTGENPADCTRL
429	str	r1, [r0, #EMC_XM2VTTGENPADCTRL]
430	ldr	r1, [r5, #0x10]		@ restore EMC_XM2VTTGENPADCTRL2
431	str	r1, [r0, #EMC_XM2VTTGENPADCTRL2]
432	ldr	r1, [r5, #0x8]		@ restore EMC_AUTO_CAL_INTERVAL
433	str	r1, [r0, #EMC_AUTO_CAL_INTERVAL]
434
435	/* Relock DLL */
436	ldr	r1, [r0, #EMC_CFG_DIG_DLL]
437	orr	r1, r1, #(1 << 30)	@ set DLL_RESET
438	str	r1, [r0, #EMC_CFG_DIG_DLL]
439
440	emc_timing_update r1, r0
441
442	cmp	r10, #TEGRA114
443	movweq	r1, #:lower16:TEGRA_EMC1_BASE
444	movteq	r1, #:upper16:TEGRA_EMC1_BASE
445	cmpeq	r0, r1
446
447	ldr	r1, [r0, #EMC_AUTO_CAL_CONFIG]
448	orr	r1, r1, #(1 << 31)	@ set AUTO_CAL_ACTIVE
449	orreq	r1, r1, #(1 << 27)	@ set slave mode for channel 1
450	str	r1, [r0, #EMC_AUTO_CAL_CONFIG]
451
452emc_wait_auto_cal_onetime:
453	ldr	r1, [r0, #EMC_AUTO_CAL_STATUS]
454	tst	r1, #(1 << 31)		@ wait until AUTO_CAL_ACTIVE is cleared
455	bne	emc_wait_auto_cal_onetime
456
457	ldr	r1, [r0, #EMC_CFG]
458	bic	r1, r1, #(1 << 31)	@ disable DRAM_CLK_STOP_PD
459	str	r1, [r0, #EMC_CFG]
460
461	mov	r1, #0
462	str	r1, [r0, #EMC_SELF_REF]	@ take DRAM out of self refresh
463	mov	r1, #1
464	cmp	r10, #TEGRA30
465	streq	r1, [r0, #EMC_NOP]
466	streq	r1, [r0, #EMC_NOP]
467
468	emc_device_mask r1, r0
469
470exit_selfrefresh_loop:
471	ldr	r2, [r0, #EMC_EMC_STATUS]
472	ands	r2, r2, r1
473	bne	exit_selfrefresh_loop
474
475	lsr	r1, r1, #8		@ devSel, bit0:dev0, bit1:dev1
476
477	mov32	r7, TEGRA_TMRUS_BASE
478	ldr	r2, [r0, #EMC_FBIO_CFG5]
479
480	and	r2, r2,	#3		@ check DRAM_TYPE
481	cmp	r2, #2
482	beq	emc_lpddr2
483
484	/* Issue a ZQ_CAL for dev0 - DDR3 */
485	mov32	r2, 0x80000011		@ DEV_SELECTION=2, LENGTH=LONG, CMD=1
486	str	r2, [r0, #EMC_ZQ_CAL]
487	ldr	r2, [r7]
488	add	r2, r2, #10
489	wait_until r2, r7, r3
490
491	tst	r1, #2
492	beq	zcal_done
493
494	/* Issue a ZQ_CAL for dev1 - DDR3 */
495	mov32	r2, 0x40000011		@ DEV_SELECTION=1, LENGTH=LONG, CMD=1
496	str	r2, [r0, #EMC_ZQ_CAL]
497	ldr	r2, [r7]
498	add	r2, r2, #10
499	wait_until r2, r7, r3
500	b	zcal_done
501
502emc_lpddr2:
503	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
504	mov32	r2, 0x800A00AB		@ DEV_SELECTION=2, MA=10, OP=0xAB
505	str	r2, [r0, #EMC_MRW]
506	ldr	r2, [r7]
507	add	r2, r2, #1
508	wait_until r2, r7, r3
509
510	tst	r1, #2
511	beq	zcal_done
512
513	/* Issue a ZQ_CAL for dev0 - LPDDR2 */
514	mov32	r2, 0x400A00AB		@ DEV_SELECTION=1, MA=10, OP=0xAB
515	str	r2, [r0, #EMC_MRW]
516	ldr	r2, [r7]
517	add	r2, r2, #1
518	wait_until r2, r7, r3
519
520zcal_done:
521	mov	r1, #0			@ unstall all transactions
522	str	r1, [r0, #EMC_REQ_CTRL]
523	ldr	r1, [r5, #0x4]		@ restore EMC_ZCAL_INTERVAL
524	str	r1, [r0, #EMC_ZCAL_INTERVAL]
525	ldr	r1, [r5, #0x0]		@ restore EMC_CFG
526	str	r1, [r0, #EMC_CFG]
527
528	emc_timing_update r1, r0
529
530	/* Tegra114 had dual EMC channel, now config the other one */
531	cmp	r10, #TEGRA114
532	bne	__no_dual_emc_chanl
533	mov32	r1, TEGRA_EMC1_BASE
534	cmp	r0, r1
535	movne	r0, r1
536	addne	r5, r5, #0x20
537	bne	exit_self_refresh
538__no_dual_emc_chanl:
539
540	mov32	r0, TEGRA_PMC_BASE
541	ldr	r0, [r0, #PMC_SCRATCH41]
542	ret	r0			@ jump to tegra_resume
543ENDPROC(tegra30_lp1_reset)
544
545	.align	L1_CACHE_SHIFT
546tegra30_sdram_pad_address:
547	.word	TEGRA_EMC_BASE + EMC_CFG				@0x0
548	.word	TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL			@0x4
549	.word	TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL			@0x8
550	.word	TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL			@0xc
551	.word	TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2			@0x10
552	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
553	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
554	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
555tegra30_sdram_pad_address_end:
556
557tegra114_sdram_pad_address:
558	.word	TEGRA_EMC0_BASE + EMC_CFG				@0x0
559	.word	TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL			@0x4
560	.word	TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL			@0x8
561	.word	TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL			@0xc
562	.word	TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2			@0x10
563	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
564	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
565	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
566	.word	TEGRA_EMC1_BASE + EMC_CFG				@0x20
567	.word	TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL			@0x24
568	.word	TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL			@0x28
569	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL			@0x2c
570	.word	TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2			@0x30
571tegra114_sdram_pad_adress_end:
572
573tegra124_sdram_pad_address:
574	.word	TEGRA124_EMC_BASE + EMC_CFG				@0x0
575	.word	TEGRA124_EMC_BASE + EMC_ZCAL_INTERVAL			@0x4
576	.word	TEGRA124_EMC_BASE + EMC_AUTO_CAL_INTERVAL		@0x8
577	.word	TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL		@0xc
578	.word	TEGRA124_EMC_BASE + EMC_XM2VTTGENPADCTRL2		@0x10
579	.word	TEGRA_PMC_BASE + PMC_IO_DPD_STATUS			@0x14
580	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT	@0x18
581	.word	TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST		@0x1c
582tegra124_sdram_pad_address_end:
583
584tegra30_sdram_pad_size:
585	.word	tegra30_sdram_pad_address_end - tegra30_sdram_pad_address
586
587tegra114_sdram_pad_size:
588	.word	tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address
589
590	.type	tegra_sdram_pad_save, %object
591tegra_sdram_pad_save:
592	.rept (tegra114_sdram_pad_adress_end - tegra114_sdram_pad_address) / 4
593	.long	0
594	.endr
595
596/*
597 * tegra30_tear_down_core
598 *
599 * copied into and executed from IRAM
600 * puts memory in self-refresh for LP0 and LP1
601 */
602tegra30_tear_down_core:
603	bl	tegra30_sdram_self_refresh
604	bl	tegra30_switch_cpu_to_clk32k
605	b	tegra30_enter_sleep
606
607/*
608 * tegra30_switch_cpu_to_clk32k
609 *
610 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
611 * to the 32KHz clock.
612 * r4 = TEGRA_PMC_BASE
613 * r5 = TEGRA_CLK_RESET_BASE
614 * r6 = TEGRA_FLOW_CTRL_BASE
615 * r7 = TEGRA_TMRUS_BASE
616 * r10= SoC ID
617 */
618tegra30_switch_cpu_to_clk32k:
619	/*
620	 * start by jumping to CLKM to safely disable PLLs, then jump to
621	 * CLKS.
622	 */
623	mov	r0, #(1 << 28)
624	str	r0, [r5, #CLK_RESET_SCLK_BURST]
625	/* 2uS delay delay between changing SCLK and CCLK */
626	ldr	r1, [r7]
627	add	r1, r1, #2
628	wait_until r1, r7, r9
629	str	r0, [r5, #CLK_RESET_CCLK_BURST]
630	mov	r0, #0
631	str	r0, [r5, #CLK_RESET_CCLK_DIVIDER]
632	str	r0, [r5, #CLK_RESET_SCLK_DIVIDER]
633
634	/* switch the clock source of mselect to be CLK_M */
635	ldr	r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
636	orr	r0, r0, #MSELECT_CLKM
637	str	r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
638
639	/* 2uS delay delay between changing SCLK and disabling PLLs */
640	ldr	r1, [r7]
641	add	r1, r1, #2
642	wait_until r1, r7, r9
643
644	/* disable PLLM via PMC in LP1 */
645	ldr	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
646	bic	r0, r0, #(1 << 12)
647	str	r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
648
649	/* disable PLLP, PLLA, PLLC and PLLX */
650	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
651	cmp	r1, #TEGRA30
652	ldr	r0, [r5, #CLK_RESET_PLLP_BASE]
653	orrne	r0, r0, #(1 << 31)	@ enable PllP bypass on fast cluster
654	bic	r0, r0, #(1 << 30)
655	str	r0, [r5, #CLK_RESET_PLLP_BASE]
656	beq	1f
657	mov	r0, #CLK_RESET_PLLP_RESHIFT_ENABLE
658	str	r0, [r5, #CLK_RESET_PLLP_RESHIFT]
6591:
660	ldr	r0, [r5, #CLK_RESET_PLLA_BASE]
661	bic	r0, r0, #(1 << 30)
662	str	r0, [r5, #CLK_RESET_PLLA_BASE]
663	ldr	r0, [r5, #CLK_RESET_PLLC_BASE]
664	bic	r0, r0, #(1 << 30)
665	str	r0, [r5, #CLK_RESET_PLLC_BASE]
666	ldr	r0, [r5, #CLK_RESET_PLLX_BASE]
667	bic	r0, r0, #(1 << 30)
668	str	r0, [r5, #CLK_RESET_PLLX_BASE]
669
670	cmp	r10, #TEGRA30
671	beq	_no_pll_in_iddq
672	pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
673_no_pll_in_iddq:
674
675	/*
676	 * Switch to clk_s (32KHz); bits 28:31=0
677	 * Enable burst on CPU IRQ; bit 24=1
678	 * Set IRQ burst clock source to clk_m; bits 10:8=0
679	 */
680	mov	r0, #(1 << 24)
681	str	r0, [r5, #CLK_RESET_SCLK_BURST]
682
683	ret	lr
684
685/*
686 * tegra30_enter_sleep
687 *
688 * uses flow controller to enter sleep state
689 * executes from IRAM with SDRAM in selfrefresh when target state is LP0 or LP1
690 * executes from SDRAM with target state is LP2
691 * r6 = TEGRA_FLOW_CTRL_BASE
692 */
693tegra30_enter_sleep:
694	cpu_id	r1
695
696	cpu_to_csr_reg	r2, r1
697	ldr	r0, [r6, r2]
698	orr	r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
699	orr	r0, r0, #FLOW_CTRL_CSR_ENABLE
700	str	r0, [r6, r2]
701
702	tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
703	cmp	r10, #TEGRA30
704	mov	r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
705	orreq	r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
706	orrne   r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
707
708	cpu_to_halt_reg r2, r1
709	str	r0, [r6, r2]
710	dsb
711	ldr	r0, [r6, r2] /* memory barrier */
712
713	cmp	r10, #TEGRA30
714halted:
715	isb
716	dsb
717	wfine	/* CPU should be power gated here */
718	wfeeq
719
720	/* !!!FIXME!!! Implement halt failure handler */
721	b	halted
722
723/*
724 * tegra30_sdram_self_refresh
725 *
726 * called with MMU off and caches disabled
727 * must be executed from IRAM
728 * r4 = TEGRA_PMC_BASE
729 * r5 = TEGRA_CLK_RESET_BASE
730 * r6 = TEGRA_FLOW_CTRL_BASE
731 * r7 = TEGRA_TMRUS_BASE
732 * r10= SoC ID
733 */
734tegra30_sdram_self_refresh:
735
736	adr	r8, tegra_sdram_pad_save
737	tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
738	cmp	r10, #TEGRA30
739	adreq	r2, tegra30_sdram_pad_address
740	ldreq	r3, tegra30_sdram_pad_size
741	cmp	r10, #TEGRA114
742	adreq	r2, tegra114_sdram_pad_address
743	ldreq	r3, tegra114_sdram_pad_size
744	cmp	r10, #TEGRA124
745	adreq	r2, tegra124_sdram_pad_address
746	ldreq	r3, tegra30_sdram_pad_size
747
748	mov	r9, #0
749
750padsave:
751	ldr	r0, [r2, r9]		@ r0 is the addr in the pad_address
752
753	ldr	r1, [r0]
754	str	r1, [r8, r9]		@ save the content of the addr
755
756	add	r9, r9, #4
757	cmp	r3, r9
758	bne	padsave
759padsave_done:
760
761	dsb
762
763	cmp	r10, #TEGRA30
764	ldreq	r0, =TEGRA_EMC_BASE	@ r0 reserved for emc base addr
765	cmp	r10, #TEGRA114
766	ldreq	r0, =TEGRA_EMC0_BASE
767	cmp	r10, #TEGRA124
768	ldreq	r0, =TEGRA124_EMC_BASE
769
770enter_self_refresh:
771	cmp	r10, #TEGRA30
772	mov	r1, #0
773	str	r1, [r0, #EMC_ZCAL_INTERVAL]
774	str	r1, [r0, #EMC_AUTO_CAL_INTERVAL]
775	ldr	r1, [r0, #EMC_CFG]
776	bic	r1, r1, #(1 << 28)
777	bicne	r1, r1, #(1 << 29)
778	str	r1, [r0, #EMC_CFG]	@ disable DYN_SELF_REF
779
780	emc_timing_update r1, r0
781
782	ldr	r1, [r7]
783	add	r1, r1, #5
784	wait_until r1, r7, r2
785
786emc_wait_auto_cal:
787	ldr	r1, [r0, #EMC_AUTO_CAL_STATUS]
788	tst	r1, #(1 << 31)		@ wait until AUTO_CAL_ACTIVE is cleared
789	bne	emc_wait_auto_cal
790
791	mov	r1, #3
792	str	r1, [r0, #EMC_REQ_CTRL]	@ stall incoming DRAM requests
793
794emcidle:
795	ldr	r1, [r0, #EMC_EMC_STATUS]
796	tst	r1, #4
797	beq	emcidle
798
799	mov	r1, #1
800	str	r1, [r0, #EMC_SELF_REF]
801
802	emc_device_mask r1, r0
803
804emcself:
805	ldr	r2, [r0, #EMC_EMC_STATUS]
806	and	r2, r2, r1
807	cmp	r2, r1
808	bne	emcself			@ loop until DDR in self-refresh
809
810	/* Put VTTGEN in the lowest power mode */
811	ldr	r1, [r0, #EMC_XM2VTTGENPADCTRL]
812	mov32	r2, 0xF8F8FFFF	@ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
813	and	r1, r1, r2
814	str	r1, [r0, #EMC_XM2VTTGENPADCTRL]
815	ldr	r1, [r0, #EMC_XM2VTTGENPADCTRL2]
816	cmp	r10, #TEGRA30
817	orreq	r1, r1, #7		@ set E_NO_VTTGEN
818	orrne	r1, r1, #0x3f
819	str	r1, [r0, #EMC_XM2VTTGENPADCTRL2]
820
821	emc_timing_update r1, r0
822
823	/* Tegra114 had dual EMC channel, now config the other one */
824	cmp	r10, #TEGRA114
825	bne	no_dual_emc_chanl
826	mov32	r1, TEGRA_EMC1_BASE
827	cmp	r0, r1
828	movne	r0, r1
829	bne	enter_self_refresh
830no_dual_emc_chanl:
831
832	ldr	r1, [r4, #PMC_CTRL]
833	tst	r1, #PMC_CTRL_SIDE_EFFECT_LP0
834	bne	pmc_io_dpd_skip
835	/*
836	 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
837	 * and COMP in the lowest power mode when LP1.
838	 */
839	mov32	r1, 0x8EC00000
840	str	r1, [r4, #PMC_IO_DPD_REQ]
841pmc_io_dpd_skip:
842
843	dsb
844
845	ret	lr
846
847	.ltorg
848/* dummy symbol for end of IRAM */
849	.align L1_CACHE_SHIFT
850	.global tegra30_iram_end
851tegra30_iram_end:
852	b	.
853#endif
854