1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Ingenic JZ4780 I2C bus driver 4 * 5 * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc. 6 * Copyright (C) 2015 Imagination Technologies 7 * Copyright (C) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com> 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/clk.h> 12 #include <linux/completion.h> 13 #include <linux/delay.h> 14 #include <linux/errno.h> 15 #include <linux/i2c.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/of_device.h> 22 #include <linux/platform_device.h> 23 #include <linux/sched.h> 24 #include <linux/slab.h> 25 #include <linux/time.h> 26 27 #define JZ4780_I2C_CTRL 0x00 28 #define JZ4780_I2C_TAR 0x04 29 #define JZ4780_I2C_SAR 0x08 30 #define JZ4780_I2C_DC 0x10 31 #define JZ4780_I2C_SHCNT 0x14 32 #define JZ4780_I2C_SLCNT 0x18 33 #define JZ4780_I2C_FHCNT 0x1C 34 #define JZ4780_I2C_FLCNT 0x20 35 #define JZ4780_I2C_INTST 0x2C 36 #define JZ4780_I2C_INTM 0x30 37 #define JZ4780_I2C_RXTL 0x38 38 #define JZ4780_I2C_TXTL 0x3C 39 #define JZ4780_I2C_CINTR 0x40 40 #define JZ4780_I2C_CRXUF 0x44 41 #define JZ4780_I2C_CRXOF 0x48 42 #define JZ4780_I2C_CTXOF 0x4C 43 #define JZ4780_I2C_CRXREQ 0x50 44 #define JZ4780_I2C_CTXABRT 0x54 45 #define JZ4780_I2C_CRXDONE 0x58 46 #define JZ4780_I2C_CACT 0x5C 47 #define JZ4780_I2C_CSTP 0x60 48 #define JZ4780_I2C_CSTT 0x64 49 #define JZ4780_I2C_CGC 0x68 50 #define JZ4780_I2C_ENB 0x6C 51 #define JZ4780_I2C_STA 0x70 52 #define JZ4780_I2C_TXABRT 0x80 53 #define JZ4780_I2C_DMACR 0x88 54 #define JZ4780_I2C_DMATDLR 0x8C 55 #define JZ4780_I2C_DMARDLR 0x90 56 #define JZ4780_I2C_SDASU 0x94 57 #define JZ4780_I2C_ACKGC 0x98 58 #define JZ4780_I2C_ENSTA 0x9C 59 #define JZ4780_I2C_SDAHD 0xD0 60 #define X1000_I2C_SDAHD 0x7C 61 62 #define JZ4780_I2C_CTRL_STPHLD BIT(7) 63 #define JZ4780_I2C_CTRL_SLVDIS BIT(6) 64 #define JZ4780_I2C_CTRL_REST BIT(5) 65 #define JZ4780_I2C_CTRL_MATP BIT(4) 66 #define JZ4780_I2C_CTRL_SATP BIT(3) 67 #define JZ4780_I2C_CTRL_SPDF BIT(2) 68 #define JZ4780_I2C_CTRL_SPDS BIT(1) 69 #define JZ4780_I2C_CTRL_MD BIT(0) 70 71 #define JZ4780_I2C_STA_SLVACT BIT(6) 72 #define JZ4780_I2C_STA_MSTACT BIT(5) 73 #define JZ4780_I2C_STA_RFF BIT(4) 74 #define JZ4780_I2C_STA_RFNE BIT(3) 75 #define JZ4780_I2C_STA_TFE BIT(2) 76 #define JZ4780_I2C_STA_TFNF BIT(1) 77 #define JZ4780_I2C_STA_ACT BIT(0) 78 79 #define X1000_I2C_DC_STOP BIT(9) 80 81 #define JZ4780_I2C_INTST_IGC BIT(11) 82 #define JZ4780_I2C_INTST_ISTT BIT(10) 83 #define JZ4780_I2C_INTST_ISTP BIT(9) 84 #define JZ4780_I2C_INTST_IACT BIT(8) 85 #define JZ4780_I2C_INTST_RXDN BIT(7) 86 #define JZ4780_I2C_INTST_TXABT BIT(6) 87 #define JZ4780_I2C_INTST_RDREQ BIT(5) 88 #define JZ4780_I2C_INTST_TXEMP BIT(4) 89 #define JZ4780_I2C_INTST_TXOF BIT(3) 90 #define JZ4780_I2C_INTST_RXFL BIT(2) 91 #define JZ4780_I2C_INTST_RXOF BIT(1) 92 #define JZ4780_I2C_INTST_RXUF BIT(0) 93 94 #define JZ4780_I2C_INTM_MIGC BIT(11) 95 #define JZ4780_I2C_INTM_MISTT BIT(10) 96 #define JZ4780_I2C_INTM_MISTP BIT(9) 97 #define JZ4780_I2C_INTM_MIACT BIT(8) 98 #define JZ4780_I2C_INTM_MRXDN BIT(7) 99 #define JZ4780_I2C_INTM_MTXABT BIT(6) 100 #define JZ4780_I2C_INTM_MRDREQ BIT(5) 101 #define JZ4780_I2C_INTM_MTXEMP BIT(4) 102 #define JZ4780_I2C_INTM_MTXOF BIT(3) 103 #define JZ4780_I2C_INTM_MRXFL BIT(2) 104 #define JZ4780_I2C_INTM_MRXOF BIT(1) 105 #define JZ4780_I2C_INTM_MRXUF BIT(0) 106 107 #define JZ4780_I2C_DC_READ BIT(8) 108 109 #define JZ4780_I2C_SDAHD_HDENB BIT(8) 110 111 #define JZ4780_I2C_ENB_I2C BIT(0) 112 113 #define JZ4780_I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8)) 114 #define JZ4780_I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1)) 115 #define JZ4780_I2CFHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8)) 116 #define JZ4780_I2CFLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1)) 117 118 #define JZ4780_I2C_FIFO_LEN 16 119 120 #define X1000_I2C_FIFO_LEN 64 121 122 #define JZ4780_I2C_TIMEOUT 300 123 124 #define BUFSIZE 200 125 126 enum ingenic_i2c_version { 127 ID_JZ4780, 128 ID_X1000, 129 }; 130 131 /* ingenic_i2c_config: SoC specific config data. */ 132 struct ingenic_i2c_config { 133 enum ingenic_i2c_version version; 134 135 int fifosize; 136 int tx_level; 137 int rx_level; 138 }; 139 140 struct jz4780_i2c { 141 void __iomem *iomem; 142 int irq; 143 struct clk *clk; 144 struct i2c_adapter adap; 145 const struct ingenic_i2c_config *cdata; 146 147 /* lock to protect rbuf and wbuf between xfer_rd/wr and irq handler */ 148 spinlock_t lock; 149 150 /* beginning of lock scope */ 151 unsigned char *rbuf; 152 int rd_total_len; 153 int rd_data_xfered; 154 int rd_cmd_xfered; 155 156 unsigned char *wbuf; 157 int wt_len; 158 159 int is_write; 160 int stop_hold; 161 int speed; 162 163 int data_buf[BUFSIZE]; 164 int cmd_buf[BUFSIZE]; 165 int cmd; 166 167 /* end of lock scope */ 168 struct completion trans_waitq; 169 }; 170 171 static inline unsigned short jz4780_i2c_readw(struct jz4780_i2c *i2c, 172 unsigned long offset) 173 { 174 return readw(i2c->iomem + offset); 175 } 176 177 static inline void jz4780_i2c_writew(struct jz4780_i2c *i2c, 178 unsigned long offset, unsigned short val) 179 { 180 writew(val, i2c->iomem + offset); 181 } 182 183 static int jz4780_i2c_disable(struct jz4780_i2c *i2c) 184 { 185 unsigned short regval; 186 unsigned long loops = 5; 187 188 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 0); 189 190 do { 191 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA); 192 if (!(regval & JZ4780_I2C_ENB_I2C)) 193 return 0; 194 195 usleep_range(5000, 15000); 196 } while (--loops); 197 198 dev_err(&i2c->adap.dev, "disable failed: ENSTA=0x%04x\n", regval); 199 return -ETIMEDOUT; 200 } 201 202 static int jz4780_i2c_enable(struct jz4780_i2c *i2c) 203 { 204 unsigned short regval; 205 unsigned long loops = 5; 206 207 jz4780_i2c_writew(i2c, JZ4780_I2C_ENB, 1); 208 209 do { 210 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_ENSTA); 211 if (regval & JZ4780_I2C_ENB_I2C) 212 return 0; 213 214 usleep_range(5000, 15000); 215 } while (--loops); 216 217 dev_err(&i2c->adap.dev, "enable failed: ENSTA=0x%04x\n", regval); 218 return -ETIMEDOUT; 219 } 220 221 static int jz4780_i2c_set_target(struct jz4780_i2c *i2c, unsigned char address) 222 { 223 unsigned short regval; 224 unsigned long loops = 5; 225 226 do { 227 regval = jz4780_i2c_readw(i2c, JZ4780_I2C_STA); 228 if ((regval & JZ4780_I2C_STA_TFE) && 229 !(regval & JZ4780_I2C_STA_MSTACT)) 230 break; 231 232 usleep_range(5000, 15000); 233 } while (--loops); 234 235 if (loops) { 236 jz4780_i2c_writew(i2c, JZ4780_I2C_TAR, address); 237 return 0; 238 } 239 240 dev_err(&i2c->adap.dev, 241 "set device to address 0x%02x failed, STA=0x%04x\n", 242 address, regval); 243 244 return -ENXIO; 245 } 246 247 static int jz4780_i2c_set_speed(struct jz4780_i2c *i2c) 248 { 249 int dev_clk_khz = clk_get_rate(i2c->clk) / 1000; 250 int cnt_high = 0; /* HIGH period count of the SCL clock */ 251 int cnt_low = 0; /* LOW period count of the SCL clock */ 252 int cnt_period = 0; /* period count of the SCL clock */ 253 int setup_time = 0; 254 int hold_time = 0; 255 unsigned short tmp = 0; 256 int i2c_clk = i2c->speed; 257 258 if (jz4780_i2c_disable(i2c)) 259 dev_dbg(&i2c->adap.dev, "i2c not disabled\n"); 260 261 /* 262 * 1 JZ4780_I2C cycle equals to cnt_period PCLK(i2c_clk) 263 * standard mode, min LOW and HIGH period are 4700 ns and 4000 ns 264 * fast mode, min LOW and HIGH period are 1300 ns and 600 ns 265 */ 266 cnt_period = dev_clk_khz / i2c_clk; 267 268 if (i2c_clk <= 100) 269 cnt_high = (cnt_period * 4000) / (4700 + 4000); 270 else 271 cnt_high = (cnt_period * 600) / (1300 + 600); 272 273 cnt_low = cnt_period - cnt_high; 274 275 /* 276 * NOTE: JZ4780_I2C_CTRL_REST can't set when i2c enabled, because 277 * normal read are 2 messages, we cannot disable i2c controller 278 * between these two messages, this means that we must always set 279 * JZ4780_I2C_CTRL_REST when init JZ4780_I2C_CTRL 280 * 281 */ 282 if (i2c_clk <= 100) { 283 tmp = JZ4780_I2C_CTRL_SPDS | JZ4780_I2C_CTRL_REST 284 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD; 285 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 286 287 jz4780_i2c_writew(i2c, JZ4780_I2C_SHCNT, 288 JZ4780_I2CSHCNT_ADJUST(cnt_high)); 289 jz4780_i2c_writew(i2c, JZ4780_I2C_SLCNT, 290 JZ4780_I2CSLCNT_ADJUST(cnt_low)); 291 } else { 292 tmp = JZ4780_I2C_CTRL_SPDF | JZ4780_I2C_CTRL_REST 293 | JZ4780_I2C_CTRL_SLVDIS | JZ4780_I2C_CTRL_MD; 294 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 295 296 jz4780_i2c_writew(i2c, JZ4780_I2C_FHCNT, 297 JZ4780_I2CFHCNT_ADJUST(cnt_high)); 298 jz4780_i2c_writew(i2c, JZ4780_I2C_FLCNT, 299 JZ4780_I2CFLCNT_ADJUST(cnt_low)); 300 } 301 302 /* 303 * a i2c device must internally provide a hold time at least 300ns 304 * tHD:DAT 305 * Standard Mode: min=300ns, max=3450ns 306 * Fast Mode: min=0ns, max=900ns 307 * tSU:DAT 308 * Standard Mode: min=250ns, max=infinite 309 * Fast Mode: min=100(250ns is recommended), max=infinite 310 * 311 * 1i2c_clk = 10^6 / dev_clk_khz 312 * on FPGA, dev_clk_khz = 12000, so 1i2c_clk = 1000/12 = 83ns 313 * on Pisces(1008M), dev_clk_khz=126000, so 1i2c_clk = 1000 / 126 = 8ns 314 * 315 * The actual hold time is (SDAHD + 1) * (i2c_clk period). 316 * 317 * Length of setup time calculated using (SDASU - 1) * (ic_clk_period) 318 * 319 */ 320 if (i2c_clk <= 100) { /* standard mode */ 321 setup_time = 300; 322 hold_time = 400; 323 } else { 324 setup_time = 450; 325 hold_time = 450; 326 } 327 328 hold_time = ((hold_time * dev_clk_khz) / 1000000) - 1; 329 setup_time = ((setup_time * dev_clk_khz) / 1000000) + 1; 330 331 if (setup_time > 255) 332 setup_time = 255; 333 334 if (setup_time <= 0) 335 setup_time = 1; 336 337 jz4780_i2c_writew(i2c, JZ4780_I2C_SDASU, setup_time); 338 339 if (hold_time > 255) 340 hold_time = 255; 341 342 if (hold_time >= 0) { 343 /*i2c hold time enable */ 344 if (i2c->cdata->version >= ID_X1000) { 345 jz4780_i2c_writew(i2c, X1000_I2C_SDAHD, hold_time); 346 } else { 347 hold_time |= JZ4780_I2C_SDAHD_HDENB; 348 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, hold_time); 349 } 350 } else { 351 /* disable hold time */ 352 if (i2c->cdata->version >= ID_X1000) 353 jz4780_i2c_writew(i2c, X1000_I2C_SDAHD, 0); 354 else 355 jz4780_i2c_writew(i2c, JZ4780_I2C_SDAHD, 0); 356 } 357 358 return 0; 359 } 360 361 static int jz4780_i2c_cleanup(struct jz4780_i2c *i2c) 362 { 363 int ret; 364 unsigned long flags; 365 unsigned short tmp; 366 367 spin_lock_irqsave(&i2c->lock, flags); 368 369 /* can send stop now if need */ 370 if (i2c->cdata->version < ID_X1000) { 371 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL); 372 tmp &= ~JZ4780_I2C_CTRL_STPHLD; 373 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 374 } 375 376 /* disable all interrupts first */ 377 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0); 378 379 /* then clear all interrupts */ 380 jz4780_i2c_readw(i2c, JZ4780_I2C_CTXABRT); 381 jz4780_i2c_readw(i2c, JZ4780_I2C_CINTR); 382 383 /* then disable the controller */ 384 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL); 385 tmp &= ~JZ4780_I2C_ENB_I2C; 386 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 387 udelay(10); 388 tmp |= JZ4780_I2C_ENB_I2C; 389 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 390 391 spin_unlock_irqrestore(&i2c->lock, flags); 392 393 ret = jz4780_i2c_disable(i2c); 394 if (ret) 395 dev_err(&i2c->adap.dev, 396 "unable to disable device during cleanup!\n"); 397 398 if (unlikely(jz4780_i2c_readw(i2c, JZ4780_I2C_INTM) 399 & jz4780_i2c_readw(i2c, JZ4780_I2C_INTST))) 400 dev_err(&i2c->adap.dev, 401 "device has interrupts after a complete cleanup!\n"); 402 403 return ret; 404 } 405 406 static int jz4780_i2c_prepare(struct jz4780_i2c *i2c) 407 { 408 jz4780_i2c_set_speed(i2c); 409 return jz4780_i2c_enable(i2c); 410 } 411 412 static void jz4780_i2c_send_rcmd(struct jz4780_i2c *i2c, 413 int cmd_count, 414 int cmd_left) 415 { 416 int i; 417 418 for (i = 0; i < cmd_count - 1; i++) 419 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ); 420 421 if ((cmd_left == 0) && (i2c->cdata->version >= ID_X1000)) 422 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, 423 JZ4780_I2C_DC_READ | X1000_I2C_DC_STOP); 424 else 425 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, JZ4780_I2C_DC_READ); 426 } 427 428 static void jz4780_i2c_trans_done(struct jz4780_i2c *i2c) 429 { 430 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0); 431 complete(&i2c->trans_waitq); 432 } 433 434 static irqreturn_t jz4780_i2c_irq(int irqno, void *dev_id) 435 { 436 unsigned short tmp; 437 unsigned short intst; 438 unsigned short intmsk; 439 struct jz4780_i2c *i2c = dev_id; 440 unsigned long flags; 441 442 spin_lock_irqsave(&i2c->lock, flags); 443 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM); 444 intst = jz4780_i2c_readw(i2c, JZ4780_I2C_INTST); 445 446 intst &= intmsk; 447 448 if (intst & JZ4780_I2C_INTST_TXABT) { 449 jz4780_i2c_trans_done(i2c); 450 goto done; 451 } 452 453 if (intst & JZ4780_I2C_INTST_RXOF) { 454 dev_dbg(&i2c->adap.dev, "received fifo overflow!\n"); 455 jz4780_i2c_trans_done(i2c); 456 goto done; 457 } 458 459 /* 460 * When reading, always drain RX FIFO before we send more Read 461 * Commands to avoid fifo overrun 462 */ 463 if (i2c->is_write == 0) { 464 int rd_left; 465 466 while ((jz4780_i2c_readw(i2c, JZ4780_I2C_STA) 467 & JZ4780_I2C_STA_RFNE)) { 468 *(i2c->rbuf++) = jz4780_i2c_readw(i2c, JZ4780_I2C_DC) 469 & 0xff; 470 i2c->rd_data_xfered++; 471 if (i2c->rd_data_xfered == i2c->rd_total_len) { 472 jz4780_i2c_trans_done(i2c); 473 goto done; 474 } 475 } 476 477 rd_left = i2c->rd_total_len - i2c->rd_data_xfered; 478 479 if (rd_left <= i2c->cdata->fifosize) 480 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, rd_left - 1); 481 } 482 483 if (intst & JZ4780_I2C_INTST_TXEMP) { 484 if (i2c->is_write == 0) { 485 int cmd_left = i2c->rd_total_len - i2c->rd_cmd_xfered; 486 int max_send = (i2c->cdata->fifosize - 1) 487 - (i2c->rd_cmd_xfered 488 - i2c->rd_data_xfered); 489 int cmd_to_send = min(cmd_left, max_send); 490 491 if (i2c->rd_cmd_xfered != 0) 492 cmd_to_send = min(cmd_to_send, 493 i2c->cdata->fifosize 494 - i2c->cdata->tx_level - 1); 495 496 if (cmd_to_send) { 497 i2c->rd_cmd_xfered += cmd_to_send; 498 cmd_left = i2c->rd_total_len - 499 i2c->rd_cmd_xfered; 500 jz4780_i2c_send_rcmd(i2c, 501 cmd_to_send, cmd_left); 502 503 } 504 505 if (cmd_left == 0) { 506 intmsk = jz4780_i2c_readw(i2c, JZ4780_I2C_INTM); 507 intmsk &= ~JZ4780_I2C_INTM_MTXEMP; 508 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, intmsk); 509 510 if (i2c->cdata->version < ID_X1000) { 511 tmp = jz4780_i2c_readw(i2c, 512 JZ4780_I2C_CTRL); 513 tmp &= ~JZ4780_I2C_CTRL_STPHLD; 514 jz4780_i2c_writew(i2c, 515 JZ4780_I2C_CTRL, tmp); 516 } 517 } 518 } else { 519 unsigned short data; 520 unsigned short i2c_sta; 521 522 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA); 523 524 while ((i2c_sta & JZ4780_I2C_STA_TFNF) && 525 (i2c->wt_len > 0)) { 526 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA); 527 data = *i2c->wbuf; 528 data &= ~JZ4780_I2C_DC_READ; 529 if ((!i2c->stop_hold) && (i2c->cdata->version >= 530 ID_X1000)) 531 data |= X1000_I2C_DC_STOP; 532 jz4780_i2c_writew(i2c, JZ4780_I2C_DC, data); 533 i2c->wbuf++; 534 i2c->wt_len--; 535 } 536 537 if (i2c->wt_len == 0) { 538 if ((!i2c->stop_hold) && (i2c->cdata->version < 539 ID_X1000)) { 540 tmp = jz4780_i2c_readw(i2c, 541 JZ4780_I2C_CTRL); 542 tmp &= ~JZ4780_I2C_CTRL_STPHLD; 543 jz4780_i2c_writew(i2c, 544 JZ4780_I2C_CTRL, tmp); 545 } 546 547 jz4780_i2c_trans_done(i2c); 548 goto done; 549 } 550 } 551 } 552 553 done: 554 spin_unlock_irqrestore(&i2c->lock, flags); 555 return IRQ_HANDLED; 556 } 557 558 static void jz4780_i2c_txabrt(struct jz4780_i2c *i2c, int src) 559 { 560 dev_dbg(&i2c->adap.dev, "txabrt: 0x%08x, cmd: %d, send: %d, recv: %d\n", 561 src, i2c->cmd, i2c->cmd_buf[i2c->cmd], i2c->data_buf[i2c->cmd]); 562 } 563 564 static inline int jz4780_i2c_xfer_read(struct jz4780_i2c *i2c, 565 unsigned char *buf, int len, int cnt, 566 int idx) 567 { 568 int ret = 0; 569 long timeout; 570 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5); 571 unsigned short tmp; 572 unsigned long flags; 573 574 memset(buf, 0, len); 575 576 spin_lock_irqsave(&i2c->lock, flags); 577 578 i2c->stop_hold = 0; 579 i2c->is_write = 0; 580 i2c->rbuf = buf; 581 i2c->rd_total_len = len; 582 i2c->rd_data_xfered = 0; 583 i2c->rd_cmd_xfered = 0; 584 585 if (len <= i2c->cdata->fifosize) 586 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, len - 1); 587 else 588 jz4780_i2c_writew(i2c, JZ4780_I2C_RXTL, i2c->cdata->rx_level); 589 590 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, i2c->cdata->tx_level); 591 592 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 593 JZ4780_I2C_INTM_MRXFL | JZ4780_I2C_INTM_MTXEMP 594 | JZ4780_I2C_INTM_MTXABT | JZ4780_I2C_INTM_MRXOF); 595 596 if (i2c->cdata->version < ID_X1000) { 597 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL); 598 tmp |= JZ4780_I2C_CTRL_STPHLD; 599 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 600 } 601 602 spin_unlock_irqrestore(&i2c->lock, flags); 603 604 timeout = wait_for_completion_timeout(&i2c->trans_waitq, 605 msecs_to_jiffies(wait_time)); 606 607 if (!timeout) { 608 dev_err(&i2c->adap.dev, "irq read timeout\n"); 609 dev_dbg(&i2c->adap.dev, "send cmd count:%d %d\n", 610 i2c->cmd, i2c->cmd_buf[i2c->cmd]); 611 dev_dbg(&i2c->adap.dev, "receive data count:%d %d\n", 612 i2c->cmd, i2c->data_buf[i2c->cmd]); 613 ret = -EIO; 614 } 615 616 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT); 617 if (tmp) { 618 jz4780_i2c_txabrt(i2c, tmp); 619 ret = -EIO; 620 } 621 622 return ret; 623 } 624 625 static inline int jz4780_i2c_xfer_write(struct jz4780_i2c *i2c, 626 unsigned char *buf, int len, 627 int cnt, int idx) 628 { 629 int ret = 0; 630 int wait_time = JZ4780_I2C_TIMEOUT * (len + 5); 631 long timeout; 632 unsigned short tmp; 633 unsigned long flags; 634 635 spin_lock_irqsave(&i2c->lock, flags); 636 637 if (idx < (cnt - 1)) 638 i2c->stop_hold = 1; 639 else 640 i2c->stop_hold = 0; 641 642 i2c->is_write = 1; 643 i2c->wbuf = buf; 644 i2c->wt_len = len; 645 646 jz4780_i2c_writew(i2c, JZ4780_I2C_TXTL, i2c->cdata->tx_level); 647 648 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, JZ4780_I2C_INTM_MTXEMP 649 | JZ4780_I2C_INTM_MTXABT); 650 651 if (i2c->cdata->version < ID_X1000) { 652 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL); 653 tmp |= JZ4780_I2C_CTRL_STPHLD; 654 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 655 } 656 657 spin_unlock_irqrestore(&i2c->lock, flags); 658 659 timeout = wait_for_completion_timeout(&i2c->trans_waitq, 660 msecs_to_jiffies(wait_time)); 661 if (timeout && !i2c->stop_hold) { 662 unsigned short i2c_sta; 663 int write_in_process; 664 665 timeout = JZ4780_I2C_TIMEOUT * 100; 666 for (; timeout > 0; timeout--) { 667 i2c_sta = jz4780_i2c_readw(i2c, JZ4780_I2C_STA); 668 669 write_in_process = (i2c_sta & JZ4780_I2C_STA_MSTACT) || 670 !(i2c_sta & JZ4780_I2C_STA_TFE); 671 if (!write_in_process) 672 break; 673 udelay(10); 674 } 675 } 676 677 if (!timeout) { 678 dev_err(&i2c->adap.dev, "write wait timeout\n"); 679 ret = -EIO; 680 } 681 682 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_TXABRT); 683 if (tmp) { 684 jz4780_i2c_txabrt(i2c, tmp); 685 ret = -EIO; 686 } 687 688 return ret; 689 } 690 691 static int jz4780_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, 692 int count) 693 { 694 int i = -EIO; 695 int ret = 0; 696 struct jz4780_i2c *i2c = adap->algo_data; 697 698 ret = jz4780_i2c_prepare(i2c); 699 if (ret) { 700 dev_err(&i2c->adap.dev, "I2C prepare failed\n"); 701 goto out; 702 } 703 704 if (msg->addr != jz4780_i2c_readw(i2c, JZ4780_I2C_TAR)) { 705 ret = jz4780_i2c_set_target(i2c, msg->addr); 706 if (ret) 707 goto out; 708 } 709 for (i = 0; i < count; i++, msg++) { 710 if (msg->flags & I2C_M_RD) 711 ret = jz4780_i2c_xfer_read(i2c, msg->buf, msg->len, 712 count, i); 713 else 714 ret = jz4780_i2c_xfer_write(i2c, msg->buf, msg->len, 715 count, i); 716 717 if (ret) 718 goto out; 719 } 720 721 ret = i; 722 723 out: 724 jz4780_i2c_cleanup(i2c); 725 return ret; 726 } 727 728 static u32 jz4780_i2c_functionality(struct i2c_adapter *adap) 729 { 730 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 731 } 732 733 static const struct i2c_algorithm jz4780_i2c_algorithm = { 734 .master_xfer = jz4780_i2c_xfer, 735 .functionality = jz4780_i2c_functionality, 736 }; 737 738 static const struct ingenic_i2c_config jz4780_i2c_config = { 739 .version = ID_JZ4780, 740 741 .fifosize = JZ4780_I2C_FIFO_LEN, 742 .tx_level = JZ4780_I2C_FIFO_LEN / 2, 743 .rx_level = JZ4780_I2C_FIFO_LEN / 2 - 1, 744 }; 745 746 static const struct ingenic_i2c_config x1000_i2c_config = { 747 .version = ID_X1000, 748 749 .fifosize = X1000_I2C_FIFO_LEN, 750 .tx_level = X1000_I2C_FIFO_LEN / 2, 751 .rx_level = X1000_I2C_FIFO_LEN / 2 - 1, 752 }; 753 754 static const struct of_device_id jz4780_i2c_of_matches[] = { 755 { .compatible = "ingenic,jz4780-i2c", .data = &jz4780_i2c_config }, 756 { .compatible = "ingenic,x1000-i2c", .data = &x1000_i2c_config }, 757 { /* sentinel */ } 758 }; 759 MODULE_DEVICE_TABLE(of, jz4780_i2c_of_matches); 760 761 static int jz4780_i2c_probe(struct platform_device *pdev) 762 { 763 int ret = 0; 764 unsigned int clk_freq = 0; 765 unsigned short tmp; 766 struct resource *r; 767 struct jz4780_i2c *i2c; 768 769 i2c = devm_kzalloc(&pdev->dev, sizeof(struct jz4780_i2c), GFP_KERNEL); 770 if (!i2c) 771 return -ENOMEM; 772 773 i2c->cdata = device_get_match_data(&pdev->dev); 774 if (!i2c->cdata) { 775 dev_err(&pdev->dev, "Error: No device match found\n"); 776 return -ENODEV; 777 } 778 779 i2c->adap.owner = THIS_MODULE; 780 i2c->adap.algo = &jz4780_i2c_algorithm; 781 i2c->adap.algo_data = i2c; 782 i2c->adap.retries = 5; 783 i2c->adap.dev.parent = &pdev->dev; 784 i2c->adap.dev.of_node = pdev->dev.of_node; 785 sprintf(i2c->adap.name, "%s", pdev->name); 786 787 init_completion(&i2c->trans_waitq); 788 spin_lock_init(&i2c->lock); 789 790 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 791 i2c->iomem = devm_ioremap_resource(&pdev->dev, r); 792 if (IS_ERR(i2c->iomem)) 793 return PTR_ERR(i2c->iomem); 794 795 platform_set_drvdata(pdev, i2c); 796 797 i2c->clk = devm_clk_get(&pdev->dev, NULL); 798 if (IS_ERR(i2c->clk)) 799 return PTR_ERR(i2c->clk); 800 801 ret = clk_prepare_enable(i2c->clk); 802 if (ret) 803 return ret; 804 805 ret = of_property_read_u32(pdev->dev.of_node, "clock-frequency", 806 &clk_freq); 807 if (ret) { 808 dev_err(&pdev->dev, "clock-frequency not specified in DT\n"); 809 goto err; 810 } 811 812 i2c->speed = clk_freq / 1000; 813 if (i2c->speed == 0) { 814 ret = -EINVAL; 815 dev_err(&pdev->dev, "clock-frequency minimum is 1000\n"); 816 goto err; 817 } 818 jz4780_i2c_set_speed(i2c); 819 820 dev_info(&pdev->dev, "Bus frequency is %d KHz\n", i2c->speed); 821 822 if (i2c->cdata->version < ID_X1000) { 823 tmp = jz4780_i2c_readw(i2c, JZ4780_I2C_CTRL); 824 tmp &= ~JZ4780_I2C_CTRL_STPHLD; 825 jz4780_i2c_writew(i2c, JZ4780_I2C_CTRL, tmp); 826 } 827 828 jz4780_i2c_writew(i2c, JZ4780_I2C_INTM, 0x0); 829 830 i2c->irq = platform_get_irq(pdev, 0); 831 ret = devm_request_irq(&pdev->dev, i2c->irq, jz4780_i2c_irq, 0, 832 dev_name(&pdev->dev), i2c); 833 if (ret) 834 goto err; 835 836 ret = i2c_add_adapter(&i2c->adap); 837 if (ret < 0) 838 goto err; 839 840 return 0; 841 842 err: 843 clk_disable_unprepare(i2c->clk); 844 return ret; 845 } 846 847 static int jz4780_i2c_remove(struct platform_device *pdev) 848 { 849 struct jz4780_i2c *i2c = platform_get_drvdata(pdev); 850 851 clk_disable_unprepare(i2c->clk); 852 i2c_del_adapter(&i2c->adap); 853 return 0; 854 } 855 856 static struct platform_driver jz4780_i2c_driver = { 857 .probe = jz4780_i2c_probe, 858 .remove = jz4780_i2c_remove, 859 .driver = { 860 .name = "jz4780-i2c", 861 .of_match_table = of_match_ptr(jz4780_i2c_of_matches), 862 }, 863 }; 864 865 module_platform_driver(jz4780_i2c_driver); 866 867 MODULE_LICENSE("GPL"); 868 MODULE_AUTHOR("ztyan<ztyan@ingenic.cn>"); 869 MODULE_DESCRIPTION("i2c driver for JZ4780 SoCs"); 870