1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2018-2019 SiFive, Inc */
3
4#include "fu540-c000.dtsi"
5#include <dt-bindings/gpio/gpio.h>
6
7/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
8#define RTCCLK_FREQ		1000000
9
10/ {
11	#address-cells = <2>;
12	#size-cells = <2>;
13	model = "SiFive HiFive Unleashed A00";
14	compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000";
15
16	chosen {
17		stdout-path = "serial0";
18	};
19
20	cpus {
21		timebase-frequency = <RTCCLK_FREQ>;
22	};
23
24	memory@80000000 {
25		device_type = "memory";
26		reg = <0x0 0x80000000 0x2 0x00000000>;
27	};
28
29	soc {
30	};
31
32	hfclk: hfclk {
33		#clock-cells = <0>;
34		compatible = "fixed-clock";
35		clock-frequency = <33333333>;
36		clock-output-names = "hfclk";
37	};
38
39	rtcclk: rtcclk {
40		#clock-cells = <0>;
41		compatible = "fixed-clock";
42		clock-frequency = <RTCCLK_FREQ>;
43		clock-output-names = "rtcclk";
44	};
45	gpio-restart {
46		compatible = "gpio-restart";
47		gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
48	};
49};
50
51&uart0 {
52	status = "okay";
53};
54
55&uart1 {
56	status = "okay";
57};
58
59&i2c0 {
60	status = "okay";
61};
62
63&qspi0 {
64	status = "okay";
65	flash@0 {
66		compatible = "issi,is25wp256", "jedec,spi-nor";
67		reg = <0>;
68		spi-max-frequency = <50000000>;
69		m25p,fast-read;
70		spi-tx-bus-width = <4>;
71		spi-rx-bus-width = <4>;
72	};
73};
74
75&qspi2 {
76	status = "okay";
77	mmc@0 {
78		compatible = "mmc-spi-slot";
79		reg = <0>;
80		spi-max-frequency = <20000000>;
81		voltage-ranges = <3300 3300>;
82		disable-wp;
83	};
84};
85
86&eth0 {
87	status = "okay";
88	phy-mode = "gmii";
89	phy-handle = <&phy0>;
90	phy0: ethernet-phy@0 {
91		reg = <0>;
92	};
93};
94
95&pwm0 {
96	status = "okay";
97};
98
99&pwm1 {
100	status = "okay";
101};
102
103&gpio {
104	status = "okay";
105};
106