1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "reg_helper.h" 27 #include "dcn30_optc.h" 28 #include "dc.h" 29 #include "dcn_calc_math.h" 30 31 #define REG(reg)\ 32 optc1->tg_regs->reg 33 34 #define CTX \ 35 optc1->base.ctx 36 37 #undef FN 38 #define FN(reg_name, field_name) \ 39 optc1->tg_shift->field_name, optc1->tg_mask->field_name 40 41 void optc3_triplebuffer_lock(struct timing_generator *optc) 42 { 43 struct optc *optc1 = DCN10TG_FROM_TG(optc); 44 45 REG_UPDATE(OTG_GLOBAL_CONTROL2, 46 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 47 48 REG_SET(OTG_VUPDATE_KEEPOUT, 0, 49 OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, 1); 50 51 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 52 OTG_MASTER_UPDATE_LOCK, 1); 53 54 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) 55 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 56 UPDATE_LOCK_STATUS, 1, 57 1, 10); 58 } 59 60 void optc3_lock_doublebuffer_enable(struct timing_generator *optc) 61 { 62 struct optc *optc1 = DCN10TG_FROM_TG(optc); 63 uint32_t v_blank_start = 0; 64 uint32_t v_blank_end = 0; 65 uint32_t h_blank_start = 0; 66 uint32_t h_blank_end = 0; 67 68 REG_GET_2(OTG_V_BLANK_START_END, 69 OTG_V_BLANK_START, &v_blank_start, 70 OTG_V_BLANK_END, &v_blank_end); 71 REG_GET_2(OTG_H_BLANK_START_END, 72 OTG_H_BLANK_START, &h_blank_start, 73 OTG_H_BLANK_END, &h_blank_end); 74 75 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 76 MASTER_UPDATE_LOCK_DB_START_Y, v_blank_start, 77 MASTER_UPDATE_LOCK_DB_END_Y, v_blank_end); 78 REG_UPDATE_2(OTG_GLOBAL_CONTROL4, 79 DIG_UPDATE_POSITION_X, 20, 80 DIG_UPDATE_POSITION_Y, v_blank_start); 81 REG_UPDATE_3(OTG_GLOBAL_CONTROL0, 82 MASTER_UPDATE_LOCK_DB_START_X, h_blank_start - 200 - 1, 83 MASTER_UPDATE_LOCK_DB_END_X, h_blank_end, 84 MASTER_UPDATE_LOCK_DB_EN, 1); 85 REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 1); 86 } 87 88 void optc3_lock_doublebuffer_disable(struct timing_generator *optc) 89 { 90 struct optc *optc1 = DCN10TG_FROM_TG(optc); 91 92 REG_UPDATE_2(OTG_GLOBAL_CONTROL0, 93 MASTER_UPDATE_LOCK_DB_START_X, 0, 94 MASTER_UPDATE_LOCK_DB_END_X, 0); 95 REG_UPDATE_2(OTG_GLOBAL_CONTROL1, 96 MASTER_UPDATE_LOCK_DB_START_Y, 0, 97 MASTER_UPDATE_LOCK_DB_END_Y, 0); 98 99 REG_UPDATE(OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, 0); 100 REG_UPDATE(OTG_GLOBAL_CONTROL0, MASTER_UPDATE_LOCK_DB_EN, 1); 101 } 102 103 void optc3_lock(struct timing_generator *optc) 104 { 105 struct optc *optc1 = DCN10TG_FROM_TG(optc); 106 107 REG_UPDATE(OTG_GLOBAL_CONTROL2, 108 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst); 109 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, 110 OTG_MASTER_UPDATE_LOCK, 1); 111 112 /* Should be fast, status does not update on maximus */ 113 if (optc->ctx->dce_environment != DCE_ENV_FPGA_MAXIMUS) 114 REG_WAIT(OTG_MASTER_UPDATE_LOCK, 115 UPDATE_LOCK_STATUS, 1, 116 1, 10); 117 } 118 119 void optc3_set_out_mux(struct timing_generator *optc, enum otg_out_mux_dest dest) 120 { 121 struct optc *optc1 = DCN10TG_FROM_TG(optc); 122 123 REG_UPDATE(OTG_CONTROL, OTG_OUT_MUX, dest); 124 } 125 126 void optc3_program_blank_color(struct timing_generator *optc, 127 const struct tg_color *blank_color) 128 { 129 struct optc *optc1 = DCN10TG_FROM_TG(optc); 130 131 REG_SET_3(OTG_BLANK_DATA_COLOR, 0, 132 OTG_BLANK_DATA_COLOR_BLUE_CB, blank_color->color_b_cb, 133 OTG_BLANK_DATA_COLOR_GREEN_Y, blank_color->color_g_y, 134 OTG_BLANK_DATA_COLOR_RED_CR, blank_color->color_r_cr); 135 136 REG_SET_3(OTG_BLANK_DATA_COLOR_EXT, 0, 137 OTG_BLANK_DATA_COLOR_BLUE_CB_EXT, blank_color->color_b_cb >> 10, 138 OTG_BLANK_DATA_COLOR_GREEN_Y_EXT, blank_color->color_g_y >> 10, 139 OTG_BLANK_DATA_COLOR_RED_CR_EXT, blank_color->color_r_cr >> 10); 140 } 141 142 void optc3_set_drr_trigger_window(struct timing_generator *optc, 143 uint32_t window_start, uint32_t window_end) 144 { 145 struct optc *optc1 = DCN10TG_FROM_TG(optc); 146 147 REG_SET_2(OTG_DRR_TRIGGER_WINDOW, 0, 148 OTG_DRR_TRIGGER_WINDOW_START_X, window_start, 149 OTG_DRR_TRIGGER_WINDOW_END_X, window_end); 150 } 151 152 void optc3_set_vtotal_change_limit(struct timing_generator *optc, 153 uint32_t limit) 154 { 155 struct optc *optc1 = DCN10TG_FROM_TG(optc); 156 157 158 REG_SET(OTG_DRR_V_TOTAL_CHANGE, 0, 159 OTG_DRR_V_TOTAL_CHANGE_LIMIT, limit); 160 } 161 162 163 /* Set DSC-related configuration. 164 * dsc_mode: 0 disables DSC, other values enable DSC in specified format 165 * sc_bytes_per_pixel: Bytes per pixel in u3.28 format 166 * dsc_slice_width: Slice width in pixels 167 */ 168 void optc3_set_dsc_config(struct timing_generator *optc, 169 enum optc_dsc_mode dsc_mode, 170 uint32_t dsc_bytes_per_pixel, 171 uint32_t dsc_slice_width) 172 { 173 struct optc *optc1 = DCN10TG_FROM_TG(optc); 174 175 optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, 176 dsc_slice_width); 177 178 REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0); 179 180 } 181 182 183 static void optc3_set_odm_bypass(struct timing_generator *optc, 184 const struct dc_crtc_timing *dc_crtc_timing) 185 { 186 struct optc *optc1 = DCN10TG_FROM_TG(optc); 187 enum h_timing_div_mode h_div = H_TIMING_NO_DIV; 188 189 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 190 OPTC_NUM_OF_INPUT_SEGMENT, 0, 191 OPTC_SEG0_SRC_SEL, optc->inst, 192 OPTC_SEG1_SRC_SEL, 0xf, 193 OPTC_SEG2_SRC_SEL, 0xf, 194 OPTC_SEG3_SRC_SEL, 0xf 195 ); 196 197 h_div = optc1_is_two_pixels_per_containter(dc_crtc_timing); 198 REG_SET(OTG_H_TIMING_CNTL, 0, 199 OTG_H_TIMING_DIV_MODE, h_div); 200 201 REG_SET(OPTC_MEMORY_CONFIG, 0, 202 OPTC_MEM_SEL, 0); 203 optc1->opp_count = 1; 204 } 205 206 static void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_cnt, 207 struct dc_crtc_timing *timing) 208 { 209 struct optc *optc1 = DCN10TG_FROM_TG(optc); 210 int mpcc_hactive = (timing->h_addressable + timing->h_border_left + timing->h_border_right) 211 / opp_cnt; 212 uint32_t memory_mask = 0; 213 uint32_t data_fmt = 0; 214 215 /* TODO: In pseudocode but does not affect maximus, delete comment if we dont need on asic 216 * REG_SET(OTG_GLOBAL_CONTROL2, 0, GLOBAL_UPDATE_LOCK_EN, 1); 217 * Program OTG register MASTER_UPDATE_LOCK_DB_X/Y to the position before DP frame start 218 * REG_SET_2(OTG_GLOBAL_CONTROL1, 0, 219 * MASTER_UPDATE_LOCK_DB_X, 160, 220 * MASTER_UPDATE_LOCK_DB_Y, 240); 221 */ 222 223 ASSERT(opp_cnt == 2 || opp_cnt == 4); 224 225 /* 2 pieces of memory required for up to 5120 displays, 4 for up to 8192, 226 * however, for ODM combine we can simplify by always using 4. 227 */ 228 if (opp_cnt == 2) { 229 /* To make sure there's no memory overlap, each instance "reserves" 2 230 * memories and they are uniquely combined here. 231 */ 232 memory_mask = 0x3 << (opp_id[0] * 2) | 0x3 << (opp_id[1] * 2); 233 } else if (opp_cnt == 4) { 234 /* To make sure there's no memory overlap, each instance "reserves" 1 235 * memory and they are uniquely combined here. 236 */ 237 memory_mask = 0x1 << (opp_id[0] * 2) | 0x1 << (opp_id[1] * 2) | 0x1 << (opp_id[2] * 2) | 0x1 << (opp_id[3] * 2); 238 } 239 240 if (REG(OPTC_MEMORY_CONFIG)) 241 REG_SET(OPTC_MEMORY_CONFIG, 0, 242 OPTC_MEM_SEL, memory_mask); 243 244 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) 245 data_fmt = 1; 246 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 247 data_fmt = 2; 248 249 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt); 250 251 if (opp_cnt == 2) { 252 REG_SET_3(OPTC_DATA_SOURCE_SELECT, 0, 253 OPTC_NUM_OF_INPUT_SEGMENT, 1, 254 OPTC_SEG0_SRC_SEL, opp_id[0], 255 OPTC_SEG1_SRC_SEL, opp_id[1]); 256 } else if (opp_cnt == 4) { 257 REG_SET_5(OPTC_DATA_SOURCE_SELECT, 0, 258 OPTC_NUM_OF_INPUT_SEGMENT, 3, 259 OPTC_SEG0_SRC_SEL, opp_id[0], 260 OPTC_SEG1_SRC_SEL, opp_id[1], 261 OPTC_SEG2_SRC_SEL, opp_id[2], 262 OPTC_SEG3_SRC_SEL, opp_id[3]); 263 } 264 265 REG_UPDATE(OPTC_WIDTH_CONTROL, 266 OPTC_SEGMENT_WIDTH, mpcc_hactive); 267 268 REG_SET(OTG_H_TIMING_CNTL, 0, OTG_H_TIMING_DIV_MODE, opp_cnt - 1); 269 optc1->opp_count = opp_cnt; 270 } 271 272 /** 273 * optc3_set_timing_double_buffer() - DRR double buffering control 274 * 275 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN, 276 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers. 277 * 278 * Options: any time, start of frame, dp start of frame (range timing) 279 */ 280 void optc3_set_timing_double_buffer(struct timing_generator *optc, bool enable) 281 { 282 struct optc *optc1 = DCN10TG_FROM_TG(optc); 283 uint32_t mode = enable ? 2 : 0; 284 285 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL, 286 OTG_DRR_TIMING_DBUF_UPDATE_MODE, mode); 287 } 288 289 void optc3_tg_init(struct timing_generator *optc) 290 { 291 optc3_set_timing_double_buffer(optc, true); 292 optc1_clear_optc_underflow(optc); 293 } 294 295 static struct timing_generator_funcs dcn30_tg_funcs = { 296 .validate_timing = optc1_validate_timing, 297 .program_timing = optc1_program_timing, 298 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0, 299 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1, 300 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2, 301 .program_global_sync = optc1_program_global_sync, 302 .enable_crtc = optc2_enable_crtc, 303 .disable_crtc = optc1_disable_crtc, 304 /* used by enable_timing_synchronization. Not need for FPGA */ 305 .is_counter_moving = optc1_is_counter_moving, 306 .get_position = optc1_get_position, 307 .get_frame_count = optc1_get_vblank_counter, 308 .get_scanoutpos = optc1_get_crtc_scanoutpos, 309 .get_otg_active_size = optc1_get_otg_active_size, 310 .set_early_control = optc1_set_early_control, 311 /* used by enable_timing_synchronization. Not need for FPGA */ 312 .wait_for_state = optc1_wait_for_state, 313 .set_blank_color = optc3_program_blank_color, 314 .did_triggered_reset_occur = optc1_did_triggered_reset_occur, 315 .triplebuffer_lock = optc3_triplebuffer_lock, 316 .triplebuffer_unlock = optc2_triplebuffer_unlock, 317 .enable_reset_trigger = optc1_enable_reset_trigger, 318 .enable_crtc_reset = optc1_enable_crtc_reset, 319 .disable_reset_trigger = optc1_disable_reset_trigger, 320 .lock = optc3_lock, 321 .unlock = optc1_unlock, 322 .lock_doublebuffer_enable = optc3_lock_doublebuffer_enable, 323 .lock_doublebuffer_disable = optc3_lock_doublebuffer_disable, 324 .enable_optc_clock = optc1_enable_optc_clock, 325 .set_drr = optc1_set_drr, 326 .set_static_screen_control = optc1_set_static_screen_control, 327 .program_stereo = optc1_program_stereo, 328 .is_stereo_left_eye = optc1_is_stereo_left_eye, 329 .tg_init = optc3_tg_init, 330 .is_tg_enabled = optc1_is_tg_enabled, 331 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred, 332 .clear_optc_underflow = optc1_clear_optc_underflow, 333 .setup_global_swap_lock = NULL, 334 .get_crc = optc1_get_crc, 335 .configure_crc = optc2_configure_crc, 336 .set_dsc_config = optc3_set_dsc_config, 337 .set_dwb_source = NULL, 338 .set_odm_bypass = optc3_set_odm_bypass, 339 .set_odm_combine = optc3_set_odm_combine, 340 .get_optc_source = optc2_get_optc_source, 341 .set_out_mux = optc3_set_out_mux, 342 .set_drr_trigger_window = optc3_set_drr_trigger_window, 343 .set_vtotal_change_limit = optc3_set_vtotal_change_limit, 344 .set_gsl = optc2_set_gsl, 345 .set_gsl_source_select = optc2_set_gsl_source_select, 346 .set_vtg_params = optc1_set_vtg_params, 347 .program_manual_trigger = optc2_program_manual_trigger, 348 .setup_manual_trigger = optc2_setup_manual_trigger, 349 .get_hw_timing = optc1_get_hw_timing, 350 }; 351 352 void dcn30_timing_generator_init(struct optc *optc1) 353 { 354 optc1->base.funcs = &dcn30_tg_funcs; 355 356 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1; 357 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1; 358 359 optc1->min_h_blank = 32; 360 optc1->min_v_blank = 3; 361 optc1->min_v_blank_interlace = 5; 362 optc1->min_h_sync_width = 8; 363 optc1->min_v_sync_width = 1; 364 } 365 366